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Text file src/runtime/internal/atomic/asm_arm.s

Documentation: runtime/internal/atomic

     1	// Copyright 2015 The Go Authors. All rights reserved.
     2	// Use of this source code is governed by a BSD-style
     3	// license that can be found in the LICENSE file.
     4	
     5	#include "textflag.h"
     6	
     7	// bool armcas(int32 *val, int32 old, int32 new)
     8	// Atomically:
     9	//	if(*val == old){
    10	//		*val = new;
    11	//		return 1;
    12	//	}else
    13	//		return 0;
    14	//
    15	// To implement runtime∕internal∕atomic·cas in sys_$GOOS_arm.s
    16	// using the native instructions, use:
    17	//
    18	//	TEXT runtime∕internal∕atomic·cas(SB),NOSPLIT,$0
    19	//		B	runtime∕internal∕atomic·armcas(SB)
    20	//
    21	TEXT runtime∕internal∕atomic·armcas(SB),NOSPLIT,$0-13
    22		MOVW	ptr+0(FP), R1
    23		MOVW	old+4(FP), R2
    24		MOVW	new+8(FP), R3
    25	casl:
    26		LDREX	(R1), R0
    27		CMP	R0, R2
    28		BNE	casfail
    29	
    30		MOVB	runtime·goarm(SB), R8
    31		CMP	$7, R8
    32		BLT	2(PC)
    33		DMB	MB_ISHST
    34	
    35		STREX	R3, (R1), R0
    36		CMP	$0, R0
    37		BNE	casl
    38		MOVW	$1, R0
    39	
    40		CMP	$7, R8
    41		BLT	2(PC)
    42		DMB	MB_ISH
    43	
    44		MOVB	R0, ret+12(FP)
    45		RET
    46	casfail:
    47		MOVW	$0, R0
    48		MOVB	R0, ret+12(FP)
    49		RET
    50	
    51	// stubs
    52	
    53	TEXT runtime∕internal∕atomic·Loadp(SB),NOSPLIT|NOFRAME,$0-8
    54		B runtime∕internal∕atomic·Load(SB)
    55	
    56	TEXT runtime∕internal∕atomic·Casuintptr(SB),NOSPLIT,$0-13
    57		B	runtime∕internal∕atomic·Cas(SB)
    58	
    59	TEXT runtime∕internal∕atomic·Casp1(SB),NOSPLIT,$0-13
    60		B	runtime∕internal∕atomic·Cas(SB)
    61	
    62	TEXT runtime∕internal∕atomic·Loaduintptr(SB),NOSPLIT,$0-8
    63		B	runtime∕internal∕atomic·Load(SB)
    64	
    65	TEXT runtime∕internal∕atomic·Loaduint(SB),NOSPLIT,$0-8
    66		B	runtime∕internal∕atomic·Load(SB)
    67	
    68	TEXT runtime∕internal∕atomic·Storeuintptr(SB),NOSPLIT,$0-8
    69		B	runtime∕internal∕atomic·Store(SB)
    70	
    71	TEXT runtime∕internal∕atomic·StorepNoWB(SB),NOSPLIT,$0-8
    72		B	runtime∕internal∕atomic·Store(SB)
    73	
    74	TEXT runtime∕internal∕atomic·Xadduintptr(SB),NOSPLIT,$0-12
    75		B	runtime∕internal∕atomic·Xadd(SB)
    76	
    77	TEXT runtime∕internal∕atomic·Loadint64(SB),NOSPLIT,$0-12
    78		B	runtime∕internal∕atomic·Load64(SB)
    79	
    80	TEXT runtime∕internal∕atomic·Xaddint64(SB),NOSPLIT,$0-20
    81		B	runtime∕internal∕atomic·Xadd64(SB)
    82	
    83	// 64-bit atomics
    84	// The native ARM implementations use LDREXD/STREXD, which are
    85	// available on ARMv6k or later. We use them only on ARMv7.
    86	// On older ARM, we use Go implementations which simulate 64-bit
    87	// atomics with locks.
    88	
    89	TEXT	armCas64<>(SB),NOSPLIT,$0-21
    90		MOVW	addr+0(FP), R1
    91		// make unaligned atomic access panic
    92		AND.S	$7, R1, R2
    93		BEQ 	2(PC)
    94		MOVW	R2, (R2)	// crash. AND.S above left only low 3 bits in R2.
    95		MOVW	old_lo+4(FP), R2
    96		MOVW	old_hi+8(FP), R3
    97		MOVW	new_lo+12(FP), R4
    98		MOVW	new_hi+16(FP), R5
    99	cas64loop:
   100		LDREXD	(R1), R6	// loads R6 and R7
   101		CMP	R2, R6
   102		BNE	cas64fail
   103		CMP	R3, R7
   104		BNE	cas64fail
   105	
   106		DMB	MB_ISHST
   107	
   108		STREXD	R4, (R1), R0	// stores R4 and R5
   109		CMP	$0, R0
   110		BNE	cas64loop
   111		MOVW	$1, R0
   112	
   113		DMB	MB_ISH
   114	
   115		MOVBU	R0, swapped+20(FP)
   116		RET
   117	cas64fail:
   118		MOVW	$0, R0
   119		MOVBU	R0, swapped+20(FP)
   120		RET
   121	
   122	TEXT	armXadd64<>(SB),NOSPLIT,$0-20
   123		MOVW	addr+0(FP), R1
   124		// make unaligned atomic access panic
   125		AND.S	$7, R1, R2
   126		BEQ 	2(PC)
   127		MOVW	R2, (R2)	// crash. AND.S above left only low 3 bits in R2.
   128		MOVW	delta_lo+4(FP), R2
   129		MOVW	delta_hi+8(FP), R3
   130	
   131	add64loop:
   132		LDREXD	(R1), R4	// loads R4 and R5
   133		ADD.S	R2, R4
   134		ADC	R3, R5
   135	
   136		DMB	MB_ISHST
   137	
   138		STREXD	R4, (R1), R0	// stores R4 and R5
   139		CMP	$0, R0
   140		BNE	add64loop
   141	
   142		DMB	MB_ISH
   143	
   144		MOVW	R4, new_lo+12(FP)
   145		MOVW	R5, new_hi+16(FP)
   146		RET
   147	
   148	TEXT	armXchg64<>(SB),NOSPLIT,$0-20
   149		MOVW	addr+0(FP), R1
   150		// make unaligned atomic access panic
   151		AND.S	$7, R1, R2
   152		BEQ 	2(PC)
   153		MOVW	R2, (R2)	// crash. AND.S above left only low 3 bits in R2.
   154		MOVW	new_lo+4(FP), R2
   155		MOVW	new_hi+8(FP), R3
   156	
   157	swap64loop:
   158		LDREXD	(R1), R4	// loads R4 and R5
   159	
   160		DMB	MB_ISHST
   161	
   162		STREXD	R2, (R1), R0	// stores R2 and R3
   163		CMP	$0, R0
   164		BNE	swap64loop
   165	
   166		DMB	MB_ISH
   167	
   168		MOVW	R4, old_lo+12(FP)
   169		MOVW	R5, old_hi+16(FP)
   170		RET
   171	
   172	TEXT	armLoad64<>(SB),NOSPLIT,$0-12
   173		MOVW	addr+0(FP), R1
   174		// make unaligned atomic access panic
   175		AND.S	$7, R1, R2
   176		BEQ 	2(PC)
   177		MOVW	R2, (R2)	// crash. AND.S above left only low 3 bits in R2.
   178	
   179		LDREXD	(R1), R2	// loads R2 and R3
   180		DMB	MB_ISH
   181	
   182		MOVW	R2, val_lo+4(FP)
   183		MOVW	R3, val_hi+8(FP)
   184		RET
   185	
   186	TEXT	armStore64<>(SB),NOSPLIT,$0-12
   187		MOVW	addr+0(FP), R1
   188		// make unaligned atomic access panic
   189		AND.S	$7, R1, R2
   190		BEQ 	2(PC)
   191		MOVW	R2, (R2)	// crash. AND.S above left only low 3 bits in R2.
   192		MOVW	val_lo+4(FP), R2
   193		MOVW	val_hi+8(FP), R3
   194	
   195	store64loop:
   196		LDREXD	(R1), R4	// loads R4 and R5
   197	
   198		DMB	MB_ISHST
   199	
   200		STREXD	R2, (R1), R0	// stores R2 and R3
   201		CMP	$0, R0
   202		BNE	store64loop
   203	
   204		DMB	MB_ISH
   205		RET
   206	
   207	TEXT	·Cas64(SB),NOSPLIT,$0-21
   208		MOVB	runtime·goarm(SB), R11
   209		CMP	$7, R11
   210		BLT	2(PC)
   211		JMP	armCas64<>(SB)
   212		JMP	·goCas64(SB)
   213	
   214	TEXT	·Xadd64(SB),NOSPLIT,$0-20
   215		MOVB	runtime·goarm(SB), R11
   216		CMP	$7, R11
   217		BLT	2(PC)
   218		JMP	armXadd64<>(SB)
   219		JMP	·goXadd64(SB)
   220	
   221	TEXT	·Xchg64(SB),NOSPLIT,$0-20
   222		MOVB	runtime·goarm(SB), R11
   223		CMP	$7, R11
   224		BLT	2(PC)
   225		JMP	armXchg64<>(SB)
   226		JMP	·goXchg64(SB)
   227	
   228	TEXT	·Load64(SB),NOSPLIT,$0-12
   229		MOVB	runtime·goarm(SB), R11
   230		CMP	$7, R11
   231		BLT	2(PC)
   232		JMP	armLoad64<>(SB)
   233		JMP	·goLoad64(SB)
   234	
   235	TEXT	·Store64(SB),NOSPLIT,$0-12
   236		MOVB	runtime·goarm(SB), R11
   237		CMP	$7, R11
   238		BLT	2(PC)
   239		JMP	armStore64<>(SB)
   240		JMP	·goStore64(SB)

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