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Source file src/internal/cpu/cpu_x86.go

Documentation: internal/cpu

     1  // Copyright 2017 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  // +build 386 amd64
     6  
     7  package cpu
     8  
     9  const CacheLinePadSize = 64
    10  
    11  // cpuid is implemented in cpu_x86.s.
    12  func cpuid(eaxArg, ecxArg uint32) (eax, ebx, ecx, edx uint32)
    13  
    14  // xgetbv with ecx = 0 is implemented in cpu_x86.s.
    15  func xgetbv() (eax, edx uint32)
    16  
    17  const (
    18  	// edx bits
    19  	cpuid_SSE2 = 1 << 26
    20  
    21  	// ecx bits
    22  	cpuid_SSE3      = 1 << 0
    23  	cpuid_PCLMULQDQ = 1 << 1
    24  	cpuid_SSSE3     = 1 << 9
    25  	cpuid_FMA       = 1 << 12
    26  	cpuid_SSE41     = 1 << 19
    27  	cpuid_SSE42     = 1 << 20
    28  	cpuid_POPCNT    = 1 << 23
    29  	cpuid_AES       = 1 << 25
    30  	cpuid_OSXSAVE   = 1 << 27
    31  	cpuid_AVX       = 1 << 28
    32  
    33  	// ebx bits
    34  	cpuid_BMI1 = 1 << 3
    35  	cpuid_AVX2 = 1 << 5
    36  	cpuid_BMI2 = 1 << 8
    37  	cpuid_ERMS = 1 << 9
    38  	cpuid_ADX  = 1 << 19
    39  )
    40  
    41  var maxExtendedFunctionInformation uint32
    42  
    43  func doinit() {
    44  	options = []option{
    45  		{Name: "adx", Feature: &X86.HasADX},
    46  		{Name: "aes", Feature: &X86.HasAES},
    47  		{Name: "avx", Feature: &X86.HasAVX},
    48  		{Name: "avx2", Feature: &X86.HasAVX2},
    49  		{Name: "bmi1", Feature: &X86.HasBMI1},
    50  		{Name: "bmi2", Feature: &X86.HasBMI2},
    51  		{Name: "erms", Feature: &X86.HasERMS},
    52  		{Name: "fma", Feature: &X86.HasFMA},
    53  		{Name: "pclmulqdq", Feature: &X86.HasPCLMULQDQ},
    54  		{Name: "popcnt", Feature: &X86.HasPOPCNT},
    55  		{Name: "sse3", Feature: &X86.HasSSE3},
    56  		{Name: "sse41", Feature: &X86.HasSSE41},
    57  		{Name: "sse42", Feature: &X86.HasSSE42},
    58  		{Name: "ssse3", Feature: &X86.HasSSSE3},
    59  
    60  		// These capabilities should always be enabled on amd64:
    61  		{Name: "sse2", Feature: &X86.HasSSE2, Required: GOARCH == "amd64"},
    62  	}
    63  
    64  	maxID, _, _, _ := cpuid(0, 0)
    65  
    66  	if maxID < 1 {
    67  		return
    68  	}
    69  
    70  	maxExtendedFunctionInformation, _, _, _ = cpuid(0x80000000, 0)
    71  
    72  	_, _, ecx1, edx1 := cpuid(1, 0)
    73  	X86.HasSSE2 = isSet(edx1, cpuid_SSE2)
    74  
    75  	X86.HasSSE3 = isSet(ecx1, cpuid_SSE3)
    76  	X86.HasPCLMULQDQ = isSet(ecx1, cpuid_PCLMULQDQ)
    77  	X86.HasSSSE3 = isSet(ecx1, cpuid_SSSE3)
    78  	X86.HasSSE41 = isSet(ecx1, cpuid_SSE41)
    79  	X86.HasSSE42 = isSet(ecx1, cpuid_SSE42)
    80  	X86.HasPOPCNT = isSet(ecx1, cpuid_POPCNT)
    81  	X86.HasAES = isSet(ecx1, cpuid_AES)
    82  
    83  	// OSXSAVE can be false when using older Operating Systems
    84  	// or when explicitly disabled on newer Operating Systems by
    85  	// e.g. setting the xsavedisable boot option on Windows 10.
    86  	X86.HasOSXSAVE = isSet(ecx1, cpuid_OSXSAVE)
    87  
    88  	// The FMA instruction set extension only has VEX prefixed instructions.
    89  	// VEX prefixed instructions require OSXSAVE to be enabled.
    90  	// See Intel 64 and IA-32 Architecture Software Developer’s Manual Volume 2
    91  	// Section 2.4 "AVX and SSE Instruction Exception Specification"
    92  	X86.HasFMA = isSet(ecx1, cpuid_FMA) && X86.HasOSXSAVE
    93  
    94  	osSupportsAVX := false
    95  	// For XGETBV, OSXSAVE bit is required and sufficient.
    96  	if X86.HasOSXSAVE {
    97  		eax, _ := xgetbv()
    98  		// Check if XMM and YMM registers have OS support.
    99  		osSupportsAVX = isSet(eax, 1<<1) && isSet(eax, 1<<2)
   100  	}
   101  
   102  	X86.HasAVX = isSet(ecx1, cpuid_AVX) && osSupportsAVX
   103  
   104  	if maxID < 7 {
   105  		return
   106  	}
   107  
   108  	_, ebx7, _, _ := cpuid(7, 0)
   109  	X86.HasBMI1 = isSet(ebx7, cpuid_BMI1)
   110  	X86.HasAVX2 = isSet(ebx7, cpuid_AVX2) && osSupportsAVX
   111  	X86.HasBMI2 = isSet(ebx7, cpuid_BMI2)
   112  	X86.HasERMS = isSet(ebx7, cpuid_ERMS)
   113  	X86.HasADX = isSet(ebx7, cpuid_ADX)
   114  }
   115  
   116  func isSet(hwc uint32, value uint32) bool {
   117  	return hwc&value != 0
   118  }
   119  
   120  // Name returns the CPU name given by the vendor.
   121  // If the CPU name can not be determined an
   122  // empty string is returned.
   123  func Name() string {
   124  	if maxExtendedFunctionInformation < 0x80000004 {
   125  		return ""
   126  	}
   127  
   128  	data := make([]byte, 0, 3*4*4)
   129  
   130  	var eax, ebx, ecx, edx uint32
   131  	eax, ebx, ecx, edx = cpuid(0x80000002, 0)
   132  	data = appendBytes(data, eax, ebx, ecx, edx)
   133  	eax, ebx, ecx, edx = cpuid(0x80000003, 0)
   134  	data = appendBytes(data, eax, ebx, ecx, edx)
   135  	eax, ebx, ecx, edx = cpuid(0x80000004, 0)
   136  	data = appendBytes(data, eax, ebx, ecx, edx)
   137  
   138  	// Trim leading spaces.
   139  	for len(data) > 0 && data[0] == ' ' {
   140  		data = data[1:]
   141  	}
   142  
   143  	// Trim tail after and including the first null byte.
   144  	for i, c := range data {
   145  		if c == '\x00' {
   146  			data = data[:i]
   147  			break
   148  		}
   149  	}
   150  
   151  	return string(data)
   152  }
   153  
   154  func appendBytes(b []byte, args ...uint32) []byte {
   155  	for _, arg := range args {
   156  		b = append(b,
   157  			byte((arg >> 0)),
   158  			byte((arg >> 8)),
   159  			byte((arg >> 16)),
   160  			byte((arg >> 24)))
   161  	}
   162  	return b
   163  }
   164  

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