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Text file src/crypto/md5/md5block_386.s

Documentation: crypto/md5

     1	// Original source:
     2	//	http://www.zorinaq.com/papers/md5-amd64.html
     3	//	http://www.zorinaq.com/papers/md5-amd64.tar.bz2
     4	//
     5	// Translated from Perl generating GNU assembly into
     6	// #defines generating 8a assembly, and adjusted for 386,
     7	// by the Go Authors.
     8	
     9	#include "textflag.h"
    10	
    11	// MD5 optimized for AMD64.
    12	//
    13	// Author: Marc Bevand <bevand_m (at) epita.fr>
    14	// Licence: I hereby disclaim the copyright on this code and place it
    15	// in the public domain.
    16	
    17	#define ROUND1(a, b, c, d, index, const, shift) \
    18		XORL	c, BP; \
    19		LEAL	const(a)(DI*1), a; \
    20		ANDL	b, BP; \
    21		XORL d, BP; \
    22		MOVL (index*4)(SI), DI; \
    23		ADDL BP, a; \
    24		ROLL $shift, a; \
    25		MOVL c, BP; \
    26		ADDL b, a
    27	
    28	#define ROUND2(a, b, c, d, index, const, shift) \
    29		LEAL	const(a)(DI*1),a; \
    30		MOVL	d,		DI; \
    31		ANDL	b,		DI; \
    32		MOVL	d,		BP; \
    33		NOTL	BP; \
    34		ANDL	c,		BP; \
    35		ORL	DI,		BP; \
    36		MOVL	(index*4)(SI),DI; \
    37		ADDL	BP,		a; \
    38		ROLL	$shift,	a; \
    39		ADDL	b,		a
    40	
    41	#define ROUND3(a, b, c, d, index, const, shift) \
    42		LEAL	const(a)(DI*1),a; \
    43		MOVL	(index*4)(SI),DI; \
    44		XORL	d,		BP; \
    45		XORL	b,		BP; \
    46		ADDL	BP,		a; \
    47		ROLL	$shift,		a; \
    48		MOVL	b,		BP; \
    49		ADDL	b,		a
    50	
    51	#define ROUND4(a, b, c, d, index, const, shift) \
    52		LEAL	const(a)(DI*1),a; \
    53		ORL	b,		BP; \
    54		XORL	c,		BP; \
    55		ADDL	BP,		a; \
    56		MOVL	(index*4)(SI),DI; \
    57		MOVL	$0xffffffff,	BP; \
    58		ROLL	$shift,		a; \
    59		XORL	c,		BP; \
    60		ADDL	b,		a
    61	
    62	TEXT	·block(SB),NOSPLIT,$24-16
    63		MOVL	dig+0(FP),	BP
    64		MOVL	p+4(FP),	SI
    65		MOVL	p_len+8(FP), DX
    66		SHRL	$6,		DX
    67		SHLL	$6,		DX
    68	
    69		LEAL	(SI)(DX*1),	DI
    70		MOVL	(0*4)(BP),	AX
    71		MOVL	(1*4)(BP),	BX
    72		MOVL	(2*4)(BP),	CX
    73		MOVL	(3*4)(BP),	DX
    74	
    75		CMPL	SI,		DI
    76		JEQ	end
    77	
    78		MOVL	DI,		16(SP)
    79	
    80	loop:
    81		MOVL	AX,		0(SP)
    82		MOVL	BX,		4(SP)
    83		MOVL	CX,		8(SP)
    84		MOVL	DX,		12(SP)
    85	
    86		MOVL	(0*4)(SI),	DI
    87		MOVL	DX,		BP
    88	
    89		ROUND1(AX,BX,CX,DX, 1,0xd76aa478, 7);
    90		ROUND1(DX,AX,BX,CX, 2,0xe8c7b756,12);
    91		ROUND1(CX,DX,AX,BX, 3,0x242070db,17);
    92		ROUND1(BX,CX,DX,AX, 4,0xc1bdceee,22);
    93		ROUND1(AX,BX,CX,DX, 5,0xf57c0faf, 7);
    94		ROUND1(DX,AX,BX,CX, 6,0x4787c62a,12);
    95		ROUND1(CX,DX,AX,BX, 7,0xa8304613,17);
    96		ROUND1(BX,CX,DX,AX, 8,0xfd469501,22);
    97		ROUND1(AX,BX,CX,DX, 9,0x698098d8, 7);
    98		ROUND1(DX,AX,BX,CX,10,0x8b44f7af,12);
    99		ROUND1(CX,DX,AX,BX,11,0xffff5bb1,17);
   100		ROUND1(BX,CX,DX,AX,12,0x895cd7be,22);
   101		ROUND1(AX,BX,CX,DX,13,0x6b901122, 7);
   102		ROUND1(DX,AX,BX,CX,14,0xfd987193,12);
   103		ROUND1(CX,DX,AX,BX,15,0xa679438e,17);
   104		ROUND1(BX,CX,DX,AX, 0,0x49b40821,22);
   105	
   106		MOVL	(1*4)(SI),	DI
   107		MOVL	DX,		BP
   108	
   109		ROUND2(AX,BX,CX,DX, 6,0xf61e2562, 5);
   110		ROUND2(DX,AX,BX,CX,11,0xc040b340, 9);
   111		ROUND2(CX,DX,AX,BX, 0,0x265e5a51,14);
   112		ROUND2(BX,CX,DX,AX, 5,0xe9b6c7aa,20);
   113		ROUND2(AX,BX,CX,DX,10,0xd62f105d, 5);
   114		ROUND2(DX,AX,BX,CX,15, 0x2441453, 9);
   115		ROUND2(CX,DX,AX,BX, 4,0xd8a1e681,14);
   116		ROUND2(BX,CX,DX,AX, 9,0xe7d3fbc8,20);
   117		ROUND2(AX,BX,CX,DX,14,0x21e1cde6, 5);
   118		ROUND2(DX,AX,BX,CX, 3,0xc33707d6, 9);
   119		ROUND2(CX,DX,AX,BX, 8,0xf4d50d87,14);
   120		ROUND2(BX,CX,DX,AX,13,0x455a14ed,20);
   121		ROUND2(AX,BX,CX,DX, 2,0xa9e3e905, 5);
   122		ROUND2(DX,AX,BX,CX, 7,0xfcefa3f8, 9);
   123		ROUND2(CX,DX,AX,BX,12,0x676f02d9,14);
   124		ROUND2(BX,CX,DX,AX, 0,0x8d2a4c8a,20);
   125	 
   126		MOVL	(5*4)(SI),	DI
   127		MOVL	CX,		BP
   128	
   129		ROUND3(AX,BX,CX,DX, 8,0xfffa3942, 4);
   130		ROUND3(DX,AX,BX,CX,11,0x8771f681,11);
   131		ROUND3(CX,DX,AX,BX,14,0x6d9d6122,16);
   132		ROUND3(BX,CX,DX,AX, 1,0xfde5380c,23);
   133		ROUND3(AX,BX,CX,DX, 4,0xa4beea44, 4);
   134		ROUND3(DX,AX,BX,CX, 7,0x4bdecfa9,11);
   135		ROUND3(CX,DX,AX,BX,10,0xf6bb4b60,16);
   136		ROUND3(BX,CX,DX,AX,13,0xbebfbc70,23);
   137		ROUND3(AX,BX,CX,DX, 0,0x289b7ec6, 4);
   138		ROUND3(DX,AX,BX,CX, 3,0xeaa127fa,11);
   139		ROUND3(CX,DX,AX,BX, 6,0xd4ef3085,16);
   140		ROUND3(BX,CX,DX,AX, 9, 0x4881d05,23);
   141		ROUND3(AX,BX,CX,DX,12,0xd9d4d039, 4);
   142		ROUND3(DX,AX,BX,CX,15,0xe6db99e5,11);
   143		ROUND3(CX,DX,AX,BX, 2,0x1fa27cf8,16);
   144		ROUND3(BX,CX,DX,AX, 0,0xc4ac5665,23);
   145	
   146		MOVL	(0*4)(SI),	DI
   147		MOVL	$0xffffffff,	BP
   148		XORL	DX,		BP
   149	
   150		ROUND4(AX,BX,CX,DX, 7,0xf4292244, 6);
   151		ROUND4(DX,AX,BX,CX,14,0x432aff97,10);
   152		ROUND4(CX,DX,AX,BX, 5,0xab9423a7,15);
   153		ROUND4(BX,CX,DX,AX,12,0xfc93a039,21);
   154		ROUND4(AX,BX,CX,DX, 3,0x655b59c3, 6);
   155		ROUND4(DX,AX,BX,CX,10,0x8f0ccc92,10);
   156		ROUND4(CX,DX,AX,BX, 1,0xffeff47d,15);
   157		ROUND4(BX,CX,DX,AX, 8,0x85845dd1,21);
   158		ROUND4(AX,BX,CX,DX,15,0x6fa87e4f, 6);
   159		ROUND4(DX,AX,BX,CX, 6,0xfe2ce6e0,10);
   160		ROUND4(CX,DX,AX,BX,13,0xa3014314,15);
   161		ROUND4(BX,CX,DX,AX, 4,0x4e0811a1,21);
   162		ROUND4(AX,BX,CX,DX,11,0xf7537e82, 6);
   163		ROUND4(DX,AX,BX,CX, 2,0xbd3af235,10);
   164		ROUND4(CX,DX,AX,BX, 9,0x2ad7d2bb,15);
   165		ROUND4(BX,CX,DX,AX, 0,0xeb86d391,21);
   166	
   167		ADDL	0(SP),	AX
   168		ADDL	4(SP),	BX
   169		ADDL	8(SP),	CX
   170		ADDL	12(SP),	DX
   171	
   172		ADDL	$64,		SI
   173		CMPL	SI,		16(SP)
   174		JB	loop
   175	
   176	end:
   177		MOVL	dig+0(FP),	BP
   178		MOVL	AX,		(0*4)(BP)
   179		MOVL	BX,		(1*4)(BP)
   180		MOVL	CX,		(2*4)(BP)
   181		MOVL	DX,		(3*4)(BP)
   182		RET

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