Source file src/cmd/internal/obj/arm64/a.out.go

Documentation: cmd/internal/obj/arm64

     1  // cmd/7c/7.out.h  from Vita Nuova.
     2  // https://code.google.com/p/ken-cc/source/browse/src/cmd/7c/7.out.h
     3  //
     4  // 	Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
     5  // 	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     6  // 	Portions Copyright © 1997-1999 Vita Nuova Limited
     7  // 	Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
     8  // 	Portions Copyright © 2004,2006 Bruce Ellis
     9  // 	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
    10  // 	Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
    11  // 	Portions Copyright © 2009 The Go Authors. All rights reserved.
    12  //
    13  // Permission is hereby granted, free of charge, to any person obtaining a copy
    14  // of this software and associated documentation files (the "Software"), to deal
    15  // in the Software without restriction, including without limitation the rights
    16  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    17  // copies of the Software, and to permit persons to whom the Software is
    18  // furnished to do so, subject to the following conditions:
    19  //
    20  // The above copyright notice and this permission notice shall be included in
    21  // all copies or substantial portions of the Software.
    22  //
    23  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    24  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    25  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    26  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    27  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    28  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    29  // THE SOFTWARE.
    30  
    31  package arm64
    32  
    33  import "cmd/internal/obj"
    34  
    35  const (
    36  	NSNAME = 8
    37  	NSYM   = 50
    38  	NREG   = 32 /* number of general registers */
    39  	NFREG  = 32 /* number of floating point registers */
    40  )
    41  
    42  // General purpose registers, kept in the low bits of Prog.Reg.
    43  const (
    44  	// integer
    45  	REG_R0 = obj.RBaseARM64 + iota
    46  	REG_R1
    47  	REG_R2
    48  	REG_R3
    49  	REG_R4
    50  	REG_R5
    51  	REG_R6
    52  	REG_R7
    53  	REG_R8
    54  	REG_R9
    55  	REG_R10
    56  	REG_R11
    57  	REG_R12
    58  	REG_R13
    59  	REG_R14
    60  	REG_R15
    61  	REG_R16
    62  	REG_R17
    63  	REG_R18
    64  	REG_R19
    65  	REG_R20
    66  	REG_R21
    67  	REG_R22
    68  	REG_R23
    69  	REG_R24
    70  	REG_R25
    71  	REG_R26
    72  	REG_R27
    73  	REG_R28
    74  	REG_R29
    75  	REG_R30
    76  	REG_R31
    77  
    78  	// scalar floating point
    79  	REG_F0
    80  	REG_F1
    81  	REG_F2
    82  	REG_F3
    83  	REG_F4
    84  	REG_F5
    85  	REG_F6
    86  	REG_F7
    87  	REG_F8
    88  	REG_F9
    89  	REG_F10
    90  	REG_F11
    91  	REG_F12
    92  	REG_F13
    93  	REG_F14
    94  	REG_F15
    95  	REG_F16
    96  	REG_F17
    97  	REG_F18
    98  	REG_F19
    99  	REG_F20
   100  	REG_F21
   101  	REG_F22
   102  	REG_F23
   103  	REG_F24
   104  	REG_F25
   105  	REG_F26
   106  	REG_F27
   107  	REG_F28
   108  	REG_F29
   109  	REG_F30
   110  	REG_F31
   111  
   112  	// SIMD
   113  	REG_V0
   114  	REG_V1
   115  	REG_V2
   116  	REG_V3
   117  	REG_V4
   118  	REG_V5
   119  	REG_V6
   120  	REG_V7
   121  	REG_V8
   122  	REG_V9
   123  	REG_V10
   124  	REG_V11
   125  	REG_V12
   126  	REG_V13
   127  	REG_V14
   128  	REG_V15
   129  	REG_V16
   130  	REG_V17
   131  	REG_V18
   132  	REG_V19
   133  	REG_V20
   134  	REG_V21
   135  	REG_V22
   136  	REG_V23
   137  	REG_V24
   138  	REG_V25
   139  	REG_V26
   140  	REG_V27
   141  	REG_V28
   142  	REG_V29
   143  	REG_V30
   144  	REG_V31
   145  
   146  	// The EQ in
   147  	// 	CSET	EQ, R0
   148  	// is encoded as TYPE_REG, even though it's not really a register.
   149  	COND_EQ
   150  	COND_NE
   151  	COND_HS
   152  	COND_LO
   153  	COND_MI
   154  	COND_PL
   155  	COND_VS
   156  	COND_VC
   157  	COND_HI
   158  	COND_LS
   159  	COND_GE
   160  	COND_LT
   161  	COND_GT
   162  	COND_LE
   163  	COND_AL
   164  	COND_NV
   165  
   166  	REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31
   167  )
   168  
   169  // bits 0-4 indicates register: Vn
   170  // bits 5-8 indicates arrangement: <T>
   171  const (
   172  	REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn.<T>
   173  	REG_ELEM                                    // Vn.<T>[index]
   174  	REG_ELEM_END
   175  )
   176  
   177  // Not registers, but flags that can be combined with regular register
   178  // constants to indicate extended register conversion. When checking,
   179  // you should subtract obj.RBaseARM64 first. From this difference, bit 11
   180  // indicates extended register, bits 8-10 select the conversion mode.
   181  // REG_LSL is the index shift specifier, bit 9 indicates shifted offset register.
   182  const REG_LSL = obj.RBaseARM64 + 1<<9
   183  const REG_EXT = obj.RBaseARM64 + 1<<11
   184  
   185  const (
   186  	REG_UXTB = REG_EXT + iota<<8
   187  	REG_UXTH
   188  	REG_UXTW
   189  	REG_UXTX
   190  	REG_SXTB
   191  	REG_SXTH
   192  	REG_SXTW
   193  	REG_SXTX
   194  )
   195  
   196  // Special registers, after subtracting obj.RBaseARM64, bit 12 indicates
   197  // a special register and the low bits select the register.
   198  // SYSREG_END is the last item in the automatically generated system register
   199  // declaration, and it is defined in the sysRegEnc.go file.
   200  const (
   201  	REG_SPECIAL = obj.RBaseARM64 + 1<<12
   202  	REG_DAIFSet = SYSREG_END + iota
   203  	REG_DAIFClr
   204  	REG_PLDL1KEEP
   205  	REG_PLDL1STRM
   206  	REG_PLDL2KEEP
   207  	REG_PLDL2STRM
   208  	REG_PLDL3KEEP
   209  	REG_PLDL3STRM
   210  	REG_PLIL1KEEP
   211  	REG_PLIL1STRM
   212  	REG_PLIL2KEEP
   213  	REG_PLIL2STRM
   214  	REG_PLIL3KEEP
   215  	REG_PLIL3STRM
   216  	REG_PSTL1KEEP
   217  	REG_PSTL1STRM
   218  	REG_PSTL2KEEP
   219  	REG_PSTL2STRM
   220  	REG_PSTL3KEEP
   221  	REG_PSTL3STRM
   222  )
   223  
   224  // Register assignments:
   225  //
   226  // compiler allocates R0 up as temps
   227  // compiler allocates register variables R7-R25
   228  // compiler allocates external registers R26 down
   229  //
   230  // compiler allocates register variables F7-F26
   231  // compiler allocates external registers F26 down
   232  const (
   233  	REGMIN = REG_R7  // register variables allocated from here to REGMAX
   234  	REGRT1 = REG_R16 // ARM64 IP0, external linker may use as a scrach register in trampoline
   235  	REGRT2 = REG_R17 // ARM64 IP1, external linker may use as a scrach register in trampoline
   236  	REGPR  = REG_R18 // ARM64 platform register, unused in the Go toolchain
   237  	REGMAX = REG_R25
   238  
   239  	REGCTXT = REG_R26 // environment for closures
   240  	REGTMP  = REG_R27 // reserved for liblink
   241  	REGG    = REG_R28 // G
   242  	REGFP   = REG_R29 // frame pointer, unused in the Go toolchain
   243  	REGLINK = REG_R30
   244  
   245  	// ARM64 uses R31 as both stack pointer and zero register,
   246  	// depending on the instruction. To differentiate RSP from ZR,
   247  	// we use a different numeric value for REGZERO and REGSP.
   248  	REGZERO = REG_R31
   249  	REGSP   = REG_RSP
   250  
   251  	FREGRET = REG_F0
   252  	FREGMIN = REG_F7  // first register variable
   253  	FREGMAX = REG_F26 // last register variable for 7g only
   254  	FREGEXT = REG_F26 // first external register
   255  )
   256  
   257  // http://infocenter.arm.com/help/topic/com.arm.doc.ecm0665627/abi_sve_aadwarf_100985_0000_00_en.pdf
   258  var ARM64DWARFRegisters = map[int16]int16{
   259  	REG_R0:  0,
   260  	REG_R1:  1,
   261  	REG_R2:  2,
   262  	REG_R3:  3,
   263  	REG_R4:  4,
   264  	REG_R5:  5,
   265  	REG_R6:  6,
   266  	REG_R7:  7,
   267  	REG_R8:  8,
   268  	REG_R9:  9,
   269  	REG_R10: 10,
   270  	REG_R11: 11,
   271  	REG_R12: 12,
   272  	REG_R13: 13,
   273  	REG_R14: 14,
   274  	REG_R15: 15,
   275  	REG_R16: 16,
   276  	REG_R17: 17,
   277  	REG_R18: 18,
   278  	REG_R19: 19,
   279  	REG_R20: 20,
   280  	REG_R21: 21,
   281  	REG_R22: 22,
   282  	REG_R23: 23,
   283  	REG_R24: 24,
   284  	REG_R25: 25,
   285  	REG_R26: 26,
   286  	REG_R27: 27,
   287  	REG_R28: 28,
   288  	REG_R29: 29,
   289  	REG_R30: 30,
   290  
   291  	// floating point
   292  	REG_F0:  64,
   293  	REG_F1:  65,
   294  	REG_F2:  66,
   295  	REG_F3:  67,
   296  	REG_F4:  68,
   297  	REG_F5:  69,
   298  	REG_F6:  70,
   299  	REG_F7:  71,
   300  	REG_F8:  72,
   301  	REG_F9:  73,
   302  	REG_F10: 74,
   303  	REG_F11: 75,
   304  	REG_F12: 76,
   305  	REG_F13: 77,
   306  	REG_F14: 78,
   307  	REG_F15: 79,
   308  	REG_F16: 80,
   309  	REG_F17: 81,
   310  	REG_F18: 82,
   311  	REG_F19: 83,
   312  	REG_F20: 84,
   313  	REG_F21: 85,
   314  	REG_F22: 86,
   315  	REG_F23: 87,
   316  	REG_F24: 88,
   317  	REG_F25: 89,
   318  	REG_F26: 90,
   319  	REG_F27: 91,
   320  	REG_F28: 92,
   321  	REG_F29: 93,
   322  	REG_F30: 94,
   323  	REG_F31: 95,
   324  
   325  	// SIMD
   326  	REG_V0:  64,
   327  	REG_V1:  65,
   328  	REG_V2:  66,
   329  	REG_V3:  67,
   330  	REG_V4:  68,
   331  	REG_V5:  69,
   332  	REG_V6:  70,
   333  	REG_V7:  71,
   334  	REG_V8:  72,
   335  	REG_V9:  73,
   336  	REG_V10: 74,
   337  	REG_V11: 75,
   338  	REG_V12: 76,
   339  	REG_V13: 77,
   340  	REG_V14: 78,
   341  	REG_V15: 79,
   342  	REG_V16: 80,
   343  	REG_V17: 81,
   344  	REG_V18: 82,
   345  	REG_V19: 83,
   346  	REG_V20: 84,
   347  	REG_V21: 85,
   348  	REG_V22: 86,
   349  	REG_V23: 87,
   350  	REG_V24: 88,
   351  	REG_V25: 89,
   352  	REG_V26: 90,
   353  	REG_V27: 91,
   354  	REG_V28: 92,
   355  	REG_V29: 93,
   356  	REG_V30: 94,
   357  	REG_V31: 95,
   358  }
   359  
   360  const (
   361  	BIG = 2048 - 8
   362  )
   363  
   364  const (
   365  	/* mark flags */
   366  	LABEL = 1 << iota
   367  	LEAF
   368  	FLOAT
   369  	BRANCH
   370  	LOAD
   371  	FCMP
   372  	SYNC
   373  	LIST
   374  	FOLL
   375  	NOSCHED
   376  )
   377  
   378  const (
   379  	// optab is sorted based on the order of these constants
   380  	// and the first match is chosen.
   381  	// The more specific class needs to come earlier.
   382  	C_NONE   = iota
   383  	C_REG    // R0..R30
   384  	C_RSP    // R0..R30, RSP
   385  	C_FREG   // F0..F31
   386  	C_VREG   // V0..V31
   387  	C_PAIR   // (Rn, Rm)
   388  	C_SHIFT  // Rn<<2
   389  	C_EXTREG // Rn.UXTB[<<3]
   390  	C_SPR    // REG_NZCV
   391  	C_COND   // EQ, NE, etc
   392  	C_ARNG   // Vn.<T>
   393  	C_ELEM   // Vn.<T>[index]
   394  	C_LIST   // [V1, V2, V3]
   395  
   396  	C_ZCON     // $0 or ZR
   397  	C_ABCON0   // could be C_ADDCON0 or C_BITCON
   398  	C_ADDCON0  // 12-bit unsigned, unshifted
   399  	C_ABCON    // could be C_ADDCON or C_BITCON
   400  	C_AMCON    // could be C_ADDCON or C_MOVCON
   401  	C_ADDCON   // 12-bit unsigned, shifted left by 0 or 12
   402  	C_MBCON    // could be C_MOVCON or C_BITCON
   403  	C_MOVCON   // generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16
   404  	C_BITCON   // bitfield and logical immediate masks
   405  	C_ADDCON2  // 24-bit constant
   406  	C_LCON     // 32-bit constant
   407  	C_MOVCON2  // a constant that can be loaded with one MOVZ/MOVN and one MOVK
   408  	C_MOVCON3  // a constant that can be loaded with one MOVZ/MOVN and two MOVKs
   409  	C_VCON     // 64-bit constant
   410  	C_FCON     // floating-point constant
   411  	C_VCONADDR // 64-bit memory address
   412  
   413  	C_AACON // ADDCON offset in auto constant $a(FP)
   414  	C_LACON // 32-bit offset in auto constant $a(FP)
   415  	C_AECON // ADDCON offset in extern constant $e(SB)
   416  
   417  	// TODO(aram): only one branch class should be enough
   418  	C_SBRA // for TYPE_BRANCH
   419  	C_LBRA
   420  
   421  	C_ZAUTO      // 0(RSP)
   422  	C_NSAUTO_8   // -256 <= x < 0, 0 mod 8
   423  	C_NSAUTO_4   // -256 <= x < 0, 0 mod 4
   424  	C_NSAUTO     // -256 <= x < 0
   425  	C_NPAUTO     // -512 <= x < 0, 0 mod 8
   426  	C_NAUTO4K    // -4095 <= x < 0
   427  	C_PSAUTO_8   // 0 to 255, 0 mod 8
   428  	C_PSAUTO_4   // 0 to 255, 0 mod 4
   429  	C_PSAUTO     // 0 to 255
   430  	C_PPAUTO     // 0 to 504, 0 mod 8
   431  	C_UAUTO4K_8  // 0 to 4095, 0 mod 8
   432  	C_UAUTO4K_4  // 0 to 4095, 0 mod 4
   433  	C_UAUTO4K_2  // 0 to 4095, 0 mod 2
   434  	C_UAUTO4K    // 0 to 4095
   435  	C_UAUTO8K_8  // 0 to 8190, 0 mod 8
   436  	C_UAUTO8K_4  // 0 to 8190, 0 mod 4
   437  	C_UAUTO8K    // 0 to 8190, 0 mod 2
   438  	C_UAUTO16K_8 // 0 to 16380, 0 mod 8
   439  	C_UAUTO16K   // 0 to 16380, 0 mod 4
   440  	C_UAUTO32K   // 0 to 32760, 0 mod 8
   441  	C_LAUTO      // any other 32-bit constant
   442  
   443  	C_SEXT1  // 0 to 4095, direct
   444  	C_SEXT2  // 0 to 8190
   445  	C_SEXT4  // 0 to 16380
   446  	C_SEXT8  // 0 to 32760
   447  	C_SEXT16 // 0 to 65520
   448  	C_LEXT
   449  
   450  	C_ZOREG    // 0(R)
   451  	C_NSOREG_8 // must mirror C_NSAUTO_8, etc
   452  	C_NSOREG_4
   453  	C_NSOREG
   454  	C_NPOREG
   455  	C_NOREG4K
   456  	C_PSOREG_8
   457  	C_PSOREG_4
   458  	C_PSOREG
   459  	C_PPOREG
   460  	C_UOREG4K_8
   461  	C_UOREG4K_4
   462  	C_UOREG4K_2
   463  	C_UOREG4K
   464  	C_UOREG8K_8
   465  	C_UOREG8K_4
   466  	C_UOREG8K
   467  	C_UOREG16K_8
   468  	C_UOREG16K
   469  	C_UOREG32K
   470  	C_LOREG
   471  
   472  	C_ADDR // TODO(aram): explain difference from C_VCONADDR
   473  
   474  	// The GOT slot for a symbol in -dynlink mode.
   475  	C_GOTADDR
   476  
   477  	// TLS "var" in local exec mode: will become a constant offset from
   478  	// thread local base that is ultimately chosen by the program linker.
   479  	C_TLS_LE
   480  
   481  	// TLS "var" in initial exec mode: will become a memory address (chosen
   482  	// by the program linker) that the dynamic linker will fill with the
   483  	// offset from the thread local base.
   484  	C_TLS_IE
   485  
   486  	C_ROFF // register offset (including register extended)
   487  
   488  	C_GOK
   489  	C_TEXTSIZE
   490  	C_NCLASS // must be last
   491  )
   492  
   493  const (
   494  	C_XPRE  = 1 << 6 // match arm.C_WBIT, so Prog.String know how to print it
   495  	C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it
   496  )
   497  
   498  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64
   499  
   500  const (
   501  	AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota
   502  	AADCS
   503  	AADCSW
   504  	AADCW
   505  	AADD
   506  	AADDS
   507  	AADDSW
   508  	AADDW
   509  	AADR
   510  	AADRP
   511  	AAND
   512  	AANDS
   513  	AANDSW
   514  	AANDW
   515  	AASR
   516  	AASRW
   517  	AAT
   518  	ABFI
   519  	ABFIW
   520  	ABFM
   521  	ABFMW
   522  	ABFXIL
   523  	ABFXILW
   524  	ABIC
   525  	ABICS
   526  	ABICSW
   527  	ABICW
   528  	ABRK
   529  	ACBNZ
   530  	ACBNZW
   531  	ACBZ
   532  	ACBZW
   533  	ACCMN
   534  	ACCMNW
   535  	ACCMP
   536  	ACCMPW
   537  	ACINC
   538  	ACINCW
   539  	ACINV
   540  	ACINVW
   541  	ACLREX
   542  	ACLS
   543  	ACLSW
   544  	ACLZ
   545  	ACLZW
   546  	ACMN
   547  	ACMNW
   548  	ACMP
   549  	ACMPW
   550  	ACNEG
   551  	ACNEGW
   552  	ACRC32B
   553  	ACRC32CB
   554  	ACRC32CH
   555  	ACRC32CW
   556  	ACRC32CX
   557  	ACRC32H
   558  	ACRC32W
   559  	ACRC32X
   560  	ACSEL
   561  	ACSELW
   562  	ACSET
   563  	ACSETM
   564  	ACSETMW
   565  	ACSETW
   566  	ACSINC
   567  	ACSINCW
   568  	ACSINV
   569  	ACSINVW
   570  	ACSNEG
   571  	ACSNEGW
   572  	ADC
   573  	ADCPS1
   574  	ADCPS2
   575  	ADCPS3
   576  	ADMB
   577  	ADRPS
   578  	ADSB
   579  	AEON
   580  	AEONW
   581  	AEOR
   582  	AEORW
   583  	AERET
   584  	AEXTR
   585  	AEXTRW
   586  	AHINT
   587  	AHLT
   588  	AHVC
   589  	AIC
   590  	AISB
   591  	ALDADDAB
   592  	ALDADDAD
   593  	ALDADDAH
   594  	ALDADDAW
   595  	ALDADDALB
   596  	ALDADDALD
   597  	ALDADDALH
   598  	ALDADDALW
   599  	ALDADDB
   600  	ALDADDD
   601  	ALDADDH
   602  	ALDADDW
   603  	ALDADDLB
   604  	ALDADDLD
   605  	ALDADDLH
   606  	ALDADDLW
   607  	ALDANDAB
   608  	ALDANDAD
   609  	ALDANDAH
   610  	ALDANDAW
   611  	ALDANDALB
   612  	ALDANDALD
   613  	ALDANDALH
   614  	ALDANDALW
   615  	ALDANDB
   616  	ALDANDD
   617  	ALDANDH
   618  	ALDANDW
   619  	ALDANDLB
   620  	ALDANDLD
   621  	ALDANDLH
   622  	ALDANDLW
   623  	ALDAR
   624  	ALDARB
   625  	ALDARH
   626  	ALDARW
   627  	ALDAXP
   628  	ALDAXPW
   629  	ALDAXR
   630  	ALDAXRB
   631  	ALDAXRH
   632  	ALDAXRW
   633  	ALDEORAB
   634  	ALDEORAD
   635  	ALDEORAH
   636  	ALDEORAW
   637  	ALDEORALB
   638  	ALDEORALD
   639  	ALDEORALH
   640  	ALDEORALW
   641  	ALDEORB
   642  	ALDEORD
   643  	ALDEORH
   644  	ALDEORW
   645  	ALDEORLB
   646  	ALDEORLD
   647  	ALDEORLH
   648  	ALDEORLW
   649  	ALDORAB
   650  	ALDORAD
   651  	ALDORAH
   652  	ALDORAW
   653  	ALDORALB
   654  	ALDORALD
   655  	ALDORALH
   656  	ALDORALW
   657  	ALDORB
   658  	ALDORD
   659  	ALDORH
   660  	ALDORW
   661  	ALDORLB
   662  	ALDORLD
   663  	ALDORLH
   664  	ALDORLW
   665  	ALDP
   666  	ALDPW
   667  	ALDPSW
   668  	ALDXR
   669  	ALDXRB
   670  	ALDXRH
   671  	ALDXRW
   672  	ALDXP
   673  	ALDXPW
   674  	ALSL
   675  	ALSLW
   676  	ALSR
   677  	ALSRW
   678  	AMADD
   679  	AMADDW
   680  	AMNEG
   681  	AMNEGW
   682  	AMOVK
   683  	AMOVKW
   684  	AMOVN
   685  	AMOVNW
   686  	AMOVZ
   687  	AMOVZW
   688  	AMRS
   689  	AMSR
   690  	AMSUB
   691  	AMSUBW
   692  	AMUL
   693  	AMULW
   694  	AMVN
   695  	AMVNW
   696  	ANEG
   697  	ANEGS
   698  	ANEGSW
   699  	ANEGW
   700  	ANGC
   701  	ANGCS
   702  	ANGCSW
   703  	ANGCW
   704  	ANOOP
   705  	AORN
   706  	AORNW
   707  	AORR
   708  	AORRW
   709  	APRFM
   710  	APRFUM
   711  	ARBIT
   712  	ARBITW
   713  	AREM
   714  	AREMW
   715  	AREV
   716  	AREV16
   717  	AREV16W
   718  	AREV32
   719  	AREVW
   720  	AROR
   721  	ARORW
   722  	ASBC
   723  	ASBCS
   724  	ASBCSW
   725  	ASBCW
   726  	ASBFIZ
   727  	ASBFIZW
   728  	ASBFM
   729  	ASBFMW
   730  	ASBFX
   731  	ASBFXW
   732  	ASDIV
   733  	ASDIVW
   734  	ASEV
   735  	ASEVL
   736  	ASMADDL
   737  	ASMC
   738  	ASMNEGL
   739  	ASMSUBL
   740  	ASMULH
   741  	ASMULL
   742  	ASTXR
   743  	ASTXRB
   744  	ASTXRH
   745  	ASTXP
   746  	ASTXPW
   747  	ASTXRW
   748  	ASTLP
   749  	ASTLPW
   750  	ASTLR
   751  	ASTLRB
   752  	ASTLRH
   753  	ASTLRW
   754  	ASTLXP
   755  	ASTLXPW
   756  	ASTLXR
   757  	ASTLXRB
   758  	ASTLXRH
   759  	ASTLXRW
   760  	ASTP
   761  	ASTPW
   762  	ASUB
   763  	ASUBS
   764  	ASUBSW
   765  	ASUBW
   766  	ASVC
   767  	ASXTB
   768  	ASXTBW
   769  	ASXTH
   770  	ASXTHW
   771  	ASXTW
   772  	ASYS
   773  	ASYSL
   774  	ATBNZ
   775  	ATBZ
   776  	ATLBI
   777  	ATST
   778  	ATSTW
   779  	AUBFIZ
   780  	AUBFIZW
   781  	AUBFM
   782  	AUBFMW
   783  	AUBFX
   784  	AUBFXW
   785  	AUDIV
   786  	AUDIVW
   787  	AUMADDL
   788  	AUMNEGL
   789  	AUMSUBL
   790  	AUMULH
   791  	AUMULL
   792  	AUREM
   793  	AUREMW
   794  	AUXTB
   795  	AUXTH
   796  	AUXTW
   797  	AUXTBW
   798  	AUXTHW
   799  	AWFE
   800  	AWFI
   801  	AYIELD
   802  	AMOVB
   803  	AMOVBU
   804  	AMOVH
   805  	AMOVHU
   806  	AMOVW
   807  	AMOVWU
   808  	AMOVD
   809  	AMOVNP
   810  	AMOVNPW
   811  	AMOVP
   812  	AMOVPD
   813  	AMOVPQ
   814  	AMOVPS
   815  	AMOVPSW
   816  	AMOVPW
   817  	ASWPAD
   818  	ASWPAW
   819  	ASWPAH
   820  	ASWPAB
   821  	ASWPALD
   822  	ASWPALW
   823  	ASWPALH
   824  	ASWPALB
   825  	ASWPD
   826  	ASWPW
   827  	ASWPH
   828  	ASWPB
   829  	ASWPLD
   830  	ASWPLW
   831  	ASWPLH
   832  	ASWPLB
   833  	ABEQ
   834  	ABNE
   835  	ABCS
   836  	ABHS
   837  	ABCC
   838  	ABLO
   839  	ABMI
   840  	ABPL
   841  	ABVS
   842  	ABVC
   843  	ABHI
   844  	ABLS
   845  	ABGE
   846  	ABLT
   847  	ABGT
   848  	ABLE
   849  	AFABSD
   850  	AFABSS
   851  	AFADDD
   852  	AFADDS
   853  	AFCCMPD
   854  	AFCCMPED
   855  	AFCCMPS
   856  	AFCCMPES
   857  	AFCMPD
   858  	AFCMPED
   859  	AFCMPES
   860  	AFCMPS
   861  	AFCVTSD
   862  	AFCVTDS
   863  	AFCVTZSD
   864  	AFCVTZSDW
   865  	AFCVTZSS
   866  	AFCVTZSSW
   867  	AFCVTZUD
   868  	AFCVTZUDW
   869  	AFCVTZUS
   870  	AFCVTZUSW
   871  	AFDIVD
   872  	AFDIVS
   873  	AFLDPD
   874  	AFLDPS
   875  	AFMOVD
   876  	AFMOVS
   877  	AFMULD
   878  	AFMULS
   879  	AFNEGD
   880  	AFNEGS
   881  	AFSQRTD
   882  	AFSQRTS
   883  	AFSTPD
   884  	AFSTPS
   885  	AFSUBD
   886  	AFSUBS
   887  	ASCVTFD
   888  	ASCVTFS
   889  	ASCVTFWD
   890  	ASCVTFWS
   891  	AUCVTFD
   892  	AUCVTFS
   893  	AUCVTFWD
   894  	AUCVTFWS
   895  	AWORD
   896  	ADWORD
   897  	AFCSELS
   898  	AFCSELD
   899  	AFMAXS
   900  	AFMINS
   901  	AFMAXD
   902  	AFMIND
   903  	AFMAXNMS
   904  	AFMAXNMD
   905  	AFNMULS
   906  	AFNMULD
   907  	AFRINTNS
   908  	AFRINTND
   909  	AFRINTPS
   910  	AFRINTPD
   911  	AFRINTMS
   912  	AFRINTMD
   913  	AFRINTZS
   914  	AFRINTZD
   915  	AFRINTAS
   916  	AFRINTAD
   917  	AFRINTXS
   918  	AFRINTXD
   919  	AFRINTIS
   920  	AFRINTID
   921  	AFMADDS
   922  	AFMADDD
   923  	AFMSUBS
   924  	AFMSUBD
   925  	AFNMADDS
   926  	AFNMADDD
   927  	AFNMSUBS
   928  	AFNMSUBD
   929  	AFMINNMS
   930  	AFMINNMD
   931  	AFCVTDH
   932  	AFCVTHS
   933  	AFCVTHD
   934  	AFCVTSH
   935  	AAESD
   936  	AAESE
   937  	AAESIMC
   938  	AAESMC
   939  	ASHA1C
   940  	ASHA1H
   941  	ASHA1M
   942  	ASHA1P
   943  	ASHA1SU0
   944  	ASHA1SU1
   945  	ASHA256H
   946  	ASHA256H2
   947  	ASHA256SU0
   948  	ASHA256SU1
   949  	AVADD
   950  	AVADDP
   951  	AVAND
   952  	AVCMEQ
   953  	AVCNT
   954  	AVEOR
   955  	AVMOV
   956  	AVLD1
   957  	AVLD2
   958  	AVLD3
   959  	AVLD4
   960  	AVLD1R
   961  	AVLD2R
   962  	AVLD3R
   963  	AVLD4R
   964  	AVORR
   965  	AVREV32
   966  	AVREV64
   967  	AVST1
   968  	AVST2
   969  	AVST3
   970  	AVST4
   971  	AVDUP
   972  	AVADDV
   973  	AVMOVI
   974  	AVUADDLV
   975  	AVSUB
   976  	AVFMLA
   977  	AVFMLS
   978  	AVPMULL
   979  	AVPMULL2
   980  	AVEXT
   981  	AVRBIT
   982  	AVUSHR
   983  	AVSHL
   984  	AVSRI
   985  	AVTBL
   986  	AVZIP1
   987  	AVZIP2
   988  	ALAST
   989  	AB  = obj.AJMP
   990  	ABL = obj.ACALL
   991  )
   992  
   993  const (
   994  	// shift types
   995  	SHIFT_LL = 0 << 22
   996  	SHIFT_LR = 1 << 22
   997  	SHIFT_AR = 2 << 22
   998  )
   999  
  1000  // Arrangement for ARM64 SIMD instructions
  1001  const (
  1002  	// arrangement types
  1003  	ARNG_8B = iota
  1004  	ARNG_16B
  1005  	ARNG_1D
  1006  	ARNG_4H
  1007  	ARNG_8H
  1008  	ARNG_2S
  1009  	ARNG_4S
  1010  	ARNG_2D
  1011  	ARNG_1Q
  1012  	ARNG_B
  1013  	ARNG_H
  1014  	ARNG_S
  1015  	ARNG_D
  1016  )
  1017  

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