Source file src/cmd/internal/obj/arm64/a.out.go

Documentation: cmd/internal/obj/arm64

     1  // cmd/7c/7.out.h  from Vita Nuova.
     2  // https://code.google.com/p/ken-cc/source/browse/src/cmd/7c/7.out.h
     3  //
     4  // 	Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
     5  // 	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     6  // 	Portions Copyright © 1997-1999 Vita Nuova Limited
     7  // 	Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
     8  // 	Portions Copyright © 2004,2006 Bruce Ellis
     9  // 	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
    10  // 	Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
    11  // 	Portions Copyright © 2009 The Go Authors. All rights reserved.
    12  //
    13  // Permission is hereby granted, free of charge, to any person obtaining a copy
    14  // of this software and associated documentation files (the "Software"), to deal
    15  // in the Software without restriction, including without limitation the rights
    16  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    17  // copies of the Software, and to permit persons to whom the Software is
    18  // furnished to do so, subject to the following conditions:
    19  //
    20  // The above copyright notice and this permission notice shall be included in
    21  // all copies or substantial portions of the Software.
    22  //
    23  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    24  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    25  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    26  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    27  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    28  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    29  // THE SOFTWARE.
    30  
    31  package arm64
    32  
    33  import "cmd/internal/obj"
    34  
    35  const (
    36  	NSNAME = 8
    37  	NSYM   = 50
    38  	NREG   = 32 /* number of general registers */
    39  	NFREG  = 32 /* number of floating point registers */
    40  )
    41  
    42  // General purpose registers, kept in the low bits of Prog.Reg.
    43  const (
    44  	// integer
    45  	REG_R0 = obj.RBaseARM64 + iota
    46  	REG_R1
    47  	REG_R2
    48  	REG_R3
    49  	REG_R4
    50  	REG_R5
    51  	REG_R6
    52  	REG_R7
    53  	REG_R8
    54  	REG_R9
    55  	REG_R10
    56  	REG_R11
    57  	REG_R12
    58  	REG_R13
    59  	REG_R14
    60  	REG_R15
    61  	REG_R16
    62  	REG_R17
    63  	REG_R18
    64  	REG_R19
    65  	REG_R20
    66  	REG_R21
    67  	REG_R22
    68  	REG_R23
    69  	REG_R24
    70  	REG_R25
    71  	REG_R26
    72  	REG_R27
    73  	REG_R28
    74  	REG_R29
    75  	REG_R30
    76  	REG_R31
    77  
    78  	// scalar floating point
    79  	REG_F0
    80  	REG_F1
    81  	REG_F2
    82  	REG_F3
    83  	REG_F4
    84  	REG_F5
    85  	REG_F6
    86  	REG_F7
    87  	REG_F8
    88  	REG_F9
    89  	REG_F10
    90  	REG_F11
    91  	REG_F12
    92  	REG_F13
    93  	REG_F14
    94  	REG_F15
    95  	REG_F16
    96  	REG_F17
    97  	REG_F18
    98  	REG_F19
    99  	REG_F20
   100  	REG_F21
   101  	REG_F22
   102  	REG_F23
   103  	REG_F24
   104  	REG_F25
   105  	REG_F26
   106  	REG_F27
   107  	REG_F28
   108  	REG_F29
   109  	REG_F30
   110  	REG_F31
   111  
   112  	// SIMD
   113  	REG_V0
   114  	REG_V1
   115  	REG_V2
   116  	REG_V3
   117  	REG_V4
   118  	REG_V5
   119  	REG_V6
   120  	REG_V7
   121  	REG_V8
   122  	REG_V9
   123  	REG_V10
   124  	REG_V11
   125  	REG_V12
   126  	REG_V13
   127  	REG_V14
   128  	REG_V15
   129  	REG_V16
   130  	REG_V17
   131  	REG_V18
   132  	REG_V19
   133  	REG_V20
   134  	REG_V21
   135  	REG_V22
   136  	REG_V23
   137  	REG_V24
   138  	REG_V25
   139  	REG_V26
   140  	REG_V27
   141  	REG_V28
   142  	REG_V29
   143  	REG_V30
   144  	REG_V31
   145  
   146  	// The EQ in
   147  	// 	CSET	EQ, R0
   148  	// is encoded as TYPE_REG, even though it's not really a register.
   149  	COND_EQ
   150  	COND_NE
   151  	COND_HS
   152  	COND_LO
   153  	COND_MI
   154  	COND_PL
   155  	COND_VS
   156  	COND_VC
   157  	COND_HI
   158  	COND_LS
   159  	COND_GE
   160  	COND_LT
   161  	COND_GT
   162  	COND_LE
   163  	COND_AL
   164  	COND_NV
   165  
   166  	REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31
   167  )
   168  
   169  // bits 0-4 indicates register: Vn
   170  // bits 5-8 indicates arrangement: <T>
   171  const (
   172  	REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn.<T>
   173  	REG_ELEM                                    // Vn.<T>[index]
   174  	REG_ELEM_END
   175  )
   176  
   177  // Not registers, but flags that can be combined with regular register
   178  // constants to indicate extended register conversion. When checking,
   179  // you should subtract obj.RBaseARM64 first. From this difference, bit 11
   180  // indicates extended register, bits 8-10 select the conversion mode.
   181  // REG_LSL is the index shift specifier, bit 9 indicates shifted offset register.
   182  const REG_LSL = obj.RBaseARM64 + 1<<9
   183  const REG_EXT = obj.RBaseARM64 + 1<<11
   184  
   185  const (
   186  	REG_UXTB = REG_EXT + iota<<8
   187  	REG_UXTH
   188  	REG_UXTW
   189  	REG_UXTX
   190  	REG_SXTB
   191  	REG_SXTH
   192  	REG_SXTW
   193  	REG_SXTX
   194  )
   195  
   196  // Special registers, after subtracting obj.RBaseARM64, bit 12 indicates
   197  // a special register and the low bits select the register.
   198  const (
   199  	REG_SPECIAL = obj.RBaseARM64 + 1<<12 + iota
   200  	REG_DAIF
   201  	REG_NZCV
   202  	REG_FPSR
   203  	REG_FPCR
   204  	REG_SPSR_EL1
   205  	REG_ELR_EL1
   206  	REG_SPSR_EL2
   207  	REG_ELR_EL2
   208  	REG_CurrentEL
   209  	REG_SP_EL0
   210  	REG_SPSel
   211  	REG_DAIFSet
   212  	REG_DAIFClr
   213  	REG_DCZID_EL0
   214  	REG_PLDL1KEEP
   215  	REG_PLDL1STRM
   216  	REG_PLDL2KEEP
   217  	REG_PLDL2STRM
   218  	REG_PLDL3KEEP
   219  	REG_PLDL3STRM
   220  	REG_PLIL1KEEP
   221  	REG_PLIL1STRM
   222  	REG_PLIL2KEEP
   223  	REG_PLIL2STRM
   224  	REG_PLIL3KEEP
   225  	REG_PLIL3STRM
   226  	REG_PSTL1KEEP
   227  	REG_PSTL1STRM
   228  	REG_PSTL2KEEP
   229  	REG_PSTL2STRM
   230  	REG_PSTL3KEEP
   231  	REG_PSTL3STRM
   232  )
   233  
   234  // Register assignments:
   235  //
   236  // compiler allocates R0 up as temps
   237  // compiler allocates register variables R7-R25
   238  // compiler allocates external registers R26 down
   239  //
   240  // compiler allocates register variables F7-F26
   241  // compiler allocates external registers F26 down
   242  const (
   243  	REGMIN = REG_R7  // register variables allocated from here to REGMAX
   244  	REGRT1 = REG_R16 // ARM64 IP0, external linker may use as a scrach register in trampoline
   245  	REGRT2 = REG_R17 // ARM64 IP1, external linker may use as a scrach register in trampoline
   246  	REGPR  = REG_R18 // ARM64 platform register, unused in the Go toolchain
   247  	REGMAX = REG_R25
   248  
   249  	REGCTXT = REG_R26 // environment for closures
   250  	REGTMP  = REG_R27 // reserved for liblink
   251  	REGG    = REG_R28 // G
   252  	REGFP   = REG_R29 // frame pointer, unused in the Go toolchain
   253  	REGLINK = REG_R30
   254  
   255  	// ARM64 uses R31 as both stack pointer and zero register,
   256  	// depending on the instruction. To differentiate RSP from ZR,
   257  	// we use a different numeric value for REGZERO and REGSP.
   258  	REGZERO = REG_R31
   259  	REGSP   = REG_RSP
   260  
   261  	FREGRET = REG_F0
   262  	FREGMIN = REG_F7  // first register variable
   263  	FREGMAX = REG_F26 // last register variable for 7g only
   264  	FREGEXT = REG_F26 // first external register
   265  )
   266  
   267  // http://infocenter.arm.com/help/topic/com.arm.doc.ecm0665627/abi_sve_aadwarf_100985_0000_00_en.pdf
   268  var ARM64DWARFRegisters = map[int16]int16{
   269  	REG_R0:  0,
   270  	REG_R1:  1,
   271  	REG_R2:  2,
   272  	REG_R3:  3,
   273  	REG_R4:  4,
   274  	REG_R5:  5,
   275  	REG_R6:  6,
   276  	REG_R7:  7,
   277  	REG_R8:  8,
   278  	REG_R9:  9,
   279  	REG_R10: 10,
   280  	REG_R11: 11,
   281  	REG_R12: 12,
   282  	REG_R13: 13,
   283  	REG_R14: 14,
   284  	REG_R15: 15,
   285  	REG_R16: 16,
   286  	REG_R17: 17,
   287  	REG_R18: 18,
   288  	REG_R19: 19,
   289  	REG_R20: 20,
   290  	REG_R21: 21,
   291  	REG_R22: 22,
   292  	REG_R23: 23,
   293  	REG_R24: 24,
   294  	REG_R25: 25,
   295  	REG_R26: 26,
   296  	REG_R27: 27,
   297  	REG_R28: 28,
   298  	REG_R29: 29,
   299  	REG_R30: 30,
   300  
   301  	// floating point
   302  	REG_F0:  64,
   303  	REG_F1:  65,
   304  	REG_F2:  66,
   305  	REG_F3:  67,
   306  	REG_F4:  68,
   307  	REG_F5:  69,
   308  	REG_F6:  70,
   309  	REG_F7:  71,
   310  	REG_F8:  72,
   311  	REG_F9:  73,
   312  	REG_F10: 74,
   313  	REG_F11: 75,
   314  	REG_F12: 76,
   315  	REG_F13: 77,
   316  	REG_F14: 78,
   317  	REG_F15: 79,
   318  	REG_F16: 80,
   319  	REG_F17: 81,
   320  	REG_F18: 82,
   321  	REG_F19: 83,
   322  	REG_F20: 84,
   323  	REG_F21: 85,
   324  	REG_F22: 86,
   325  	REG_F23: 87,
   326  	REG_F24: 88,
   327  	REG_F25: 89,
   328  	REG_F26: 90,
   329  	REG_F27: 91,
   330  	REG_F28: 92,
   331  	REG_F29: 93,
   332  	REG_F30: 94,
   333  	REG_F31: 95,
   334  
   335  	// SIMD
   336  	REG_V0:  64,
   337  	REG_V1:  65,
   338  	REG_V2:  66,
   339  	REG_V3:  67,
   340  	REG_V4:  68,
   341  	REG_V5:  69,
   342  	REG_V6:  70,
   343  	REG_V7:  71,
   344  	REG_V8:  72,
   345  	REG_V9:  73,
   346  	REG_V10: 74,
   347  	REG_V11: 75,
   348  	REG_V12: 76,
   349  	REG_V13: 77,
   350  	REG_V14: 78,
   351  	REG_V15: 79,
   352  	REG_V16: 80,
   353  	REG_V17: 81,
   354  	REG_V18: 82,
   355  	REG_V19: 83,
   356  	REG_V20: 84,
   357  	REG_V21: 85,
   358  	REG_V22: 86,
   359  	REG_V23: 87,
   360  	REG_V24: 88,
   361  	REG_V25: 89,
   362  	REG_V26: 90,
   363  	REG_V27: 91,
   364  	REG_V28: 92,
   365  	REG_V29: 93,
   366  	REG_V30: 94,
   367  	REG_V31: 95,
   368  }
   369  
   370  const (
   371  	BIG = 2048 - 8
   372  )
   373  
   374  const (
   375  	/* mark flags */
   376  	LABEL = 1 << iota
   377  	LEAF
   378  	FLOAT
   379  	BRANCH
   380  	LOAD
   381  	FCMP
   382  	SYNC
   383  	LIST
   384  	FOLL
   385  	NOSCHED
   386  )
   387  
   388  const (
   389  	// optab is sorted based on the order of these constants
   390  	// and the first match is chosen.
   391  	// The more specific class needs to come earlier.
   392  	C_NONE   = iota
   393  	C_REG    // R0..R30
   394  	C_RSP    // R0..R30, RSP
   395  	C_FREG   // F0..F31
   396  	C_VREG   // V0..V31
   397  	C_PAIR   // (Rn, Rm)
   398  	C_SHIFT  // Rn<<2
   399  	C_EXTREG // Rn.UXTB[<<3]
   400  	C_SPR    // REG_NZCV
   401  	C_COND   // EQ, NE, etc
   402  	C_ARNG   // Vn.<T>
   403  	C_ELEM   // Vn.<T>[index]
   404  	C_LIST   // [V1, V2, V3]
   405  
   406  	C_ZCON     // $0 or ZR
   407  	C_ABCON0   // could be C_ADDCON0 or C_BITCON
   408  	C_ADDCON0  // 12-bit unsigned, unshifted
   409  	C_ABCON    // could be C_ADDCON or C_BITCON
   410  	C_AMCON    // could be C_ADDCON or C_MOVCON
   411  	C_ADDCON   // 12-bit unsigned, shifted left by 0 or 12
   412  	C_MBCON    // could be C_MOVCON or C_BITCON
   413  	C_MOVCON   // generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16
   414  	C_BITCON   // bitfield and logical immediate masks
   415  	C_ADDCON2  // 24-bit constant
   416  	C_LCON     // 32-bit constant
   417  	C_MOVCON2  // a constant that can be loaded with one MOVZ/MOVN and one MOVK
   418  	C_MOVCON3  // a constant that can be loaded with one MOVZ/MOVN and two MOVKs
   419  	C_VCON     // 64-bit constant
   420  	C_FCON     // floating-point constant
   421  	C_VCONADDR // 64-bit memory address
   422  
   423  	C_AACON // ADDCON offset in auto constant $a(FP)
   424  	C_LACON // 32-bit offset in auto constant $a(FP)
   425  	C_AECON // ADDCON offset in extern constant $e(SB)
   426  
   427  	// TODO(aram): only one branch class should be enough
   428  	C_SBRA // for TYPE_BRANCH
   429  	C_LBRA
   430  
   431  	C_ZAUTO      // 0(RSP)
   432  	C_NSAUTO_8   // -256 <= x < 0, 0 mod 8
   433  	C_NSAUTO_4   // -256 <= x < 0, 0 mod 4
   434  	C_NSAUTO     // -256 <= x < 0
   435  	C_NPAUTO     // -512 <= x < 0, 0 mod 8
   436  	C_NAUTO4K    // -4095 <= x < 0
   437  	C_PSAUTO_8   // 0 to 255, 0 mod 8
   438  	C_PSAUTO_4   // 0 to 255, 0 mod 4
   439  	C_PSAUTO     // 0 to 255
   440  	C_PPAUTO     // 0 to 504, 0 mod 8
   441  	C_UAUTO4K_8  // 0 to 4095, 0 mod 8
   442  	C_UAUTO4K_4  // 0 to 4095, 0 mod 4
   443  	C_UAUTO4K_2  // 0 to 4095, 0 mod 2
   444  	C_UAUTO4K    // 0 to 4095
   445  	C_UAUTO8K_8  // 0 to 8190, 0 mod 8
   446  	C_UAUTO8K_4  // 0 to 8190, 0 mod 4
   447  	C_UAUTO8K    // 0 to 8190, 0 mod 2
   448  	C_UAUTO16K_8 // 0 to 16380, 0 mod 8
   449  	C_UAUTO16K   // 0 to 16380, 0 mod 4
   450  	C_UAUTO32K   // 0 to 32760, 0 mod 8
   451  	C_LAUTO      // any other 32-bit constant
   452  
   453  	C_SEXT1  // 0 to 4095, direct
   454  	C_SEXT2  // 0 to 8190
   455  	C_SEXT4  // 0 to 16380
   456  	C_SEXT8  // 0 to 32760
   457  	C_SEXT16 // 0 to 65520
   458  	C_LEXT
   459  
   460  	C_ZOREG    // 0(R)
   461  	C_NSOREG_8 // must mirror C_NSAUTO_8, etc
   462  	C_NSOREG_4
   463  	C_NSOREG
   464  	C_NPOREG
   465  	C_NOREG4K
   466  	C_PSOREG_8
   467  	C_PSOREG_4
   468  	C_PSOREG
   469  	C_PPOREG
   470  	C_UOREG4K_8
   471  	C_UOREG4K_4
   472  	C_UOREG4K_2
   473  	C_UOREG4K
   474  	C_UOREG8K_8
   475  	C_UOREG8K_4
   476  	C_UOREG8K
   477  	C_UOREG16K_8
   478  	C_UOREG16K
   479  	C_UOREG32K
   480  	C_LOREG
   481  
   482  	C_ADDR // TODO(aram): explain difference from C_VCONADDR
   483  
   484  	// The GOT slot for a symbol in -dynlink mode.
   485  	C_GOTADDR
   486  
   487  	// TLS "var" in local exec mode: will become a constant offset from
   488  	// thread local base that is ultimately chosen by the program linker.
   489  	C_TLS_LE
   490  
   491  	// TLS "var" in initial exec mode: will become a memory address (chosen
   492  	// by the program linker) that the dynamic linker will fill with the
   493  	// offset from the thread local base.
   494  	C_TLS_IE
   495  
   496  	C_ROFF // register offset (including register extended)
   497  
   498  	C_GOK
   499  	C_TEXTSIZE
   500  	C_NCLASS // must be last
   501  )
   502  
   503  const (
   504  	C_XPRE  = 1 << 6 // match arm.C_WBIT, so Prog.String know how to print it
   505  	C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it
   506  )
   507  
   508  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64
   509  
   510  const (
   511  	AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota
   512  	AADCS
   513  	AADCSW
   514  	AADCW
   515  	AADD
   516  	AADDS
   517  	AADDSW
   518  	AADDW
   519  	AADR
   520  	AADRP
   521  	AAND
   522  	AANDS
   523  	AANDSW
   524  	AANDW
   525  	AASR
   526  	AASRW
   527  	AAT
   528  	ABFI
   529  	ABFIW
   530  	ABFM
   531  	ABFMW
   532  	ABFXIL
   533  	ABFXILW
   534  	ABIC
   535  	ABICS
   536  	ABICSW
   537  	ABICW
   538  	ABRK
   539  	ACBNZ
   540  	ACBNZW
   541  	ACBZ
   542  	ACBZW
   543  	ACCMN
   544  	ACCMNW
   545  	ACCMP
   546  	ACCMPW
   547  	ACINC
   548  	ACINCW
   549  	ACINV
   550  	ACINVW
   551  	ACLREX
   552  	ACLS
   553  	ACLSW
   554  	ACLZ
   555  	ACLZW
   556  	ACMN
   557  	ACMNW
   558  	ACMP
   559  	ACMPW
   560  	ACNEG
   561  	ACNEGW
   562  	ACRC32B
   563  	ACRC32CB
   564  	ACRC32CH
   565  	ACRC32CW
   566  	ACRC32CX
   567  	ACRC32H
   568  	ACRC32W
   569  	ACRC32X
   570  	ACSEL
   571  	ACSELW
   572  	ACSET
   573  	ACSETM
   574  	ACSETMW
   575  	ACSETW
   576  	ACSINC
   577  	ACSINCW
   578  	ACSINV
   579  	ACSINVW
   580  	ACSNEG
   581  	ACSNEGW
   582  	ADC
   583  	ADCPS1
   584  	ADCPS2
   585  	ADCPS3
   586  	ADMB
   587  	ADRPS
   588  	ADSB
   589  	AEON
   590  	AEONW
   591  	AEOR
   592  	AEORW
   593  	AERET
   594  	AEXTR
   595  	AEXTRW
   596  	AHINT
   597  	AHLT
   598  	AHVC
   599  	AIC
   600  	AISB
   601  	ALDADDAB
   602  	ALDADDAD
   603  	ALDADDAH
   604  	ALDADDAW
   605  	ALDADDALB
   606  	ALDADDALD
   607  	ALDADDALH
   608  	ALDADDALW
   609  	ALDADDB
   610  	ALDADDD
   611  	ALDADDH
   612  	ALDADDW
   613  	ALDADDLB
   614  	ALDADDLD
   615  	ALDADDLH
   616  	ALDADDLW
   617  	ALDANDAB
   618  	ALDANDAD
   619  	ALDANDAH
   620  	ALDANDAW
   621  	ALDANDALB
   622  	ALDANDALD
   623  	ALDANDALH
   624  	ALDANDALW
   625  	ALDANDB
   626  	ALDANDD
   627  	ALDANDH
   628  	ALDANDW
   629  	ALDANDLB
   630  	ALDANDLD
   631  	ALDANDLH
   632  	ALDANDLW
   633  	ALDAR
   634  	ALDARB
   635  	ALDARH
   636  	ALDARW
   637  	ALDAXP
   638  	ALDAXPW
   639  	ALDAXR
   640  	ALDAXRB
   641  	ALDAXRH
   642  	ALDAXRW
   643  	ALDEORAB
   644  	ALDEORAD
   645  	ALDEORAH
   646  	ALDEORAW
   647  	ALDEORALB
   648  	ALDEORALD
   649  	ALDEORALH
   650  	ALDEORALW
   651  	ALDEORB
   652  	ALDEORD
   653  	ALDEORH
   654  	ALDEORW
   655  	ALDEORLB
   656  	ALDEORLD
   657  	ALDEORLH
   658  	ALDEORLW
   659  	ALDORAB
   660  	ALDORAD
   661  	ALDORAH
   662  	ALDORAW
   663  	ALDORALB
   664  	ALDORALD
   665  	ALDORALH
   666  	ALDORALW
   667  	ALDORB
   668  	ALDORD
   669  	ALDORH
   670  	ALDORW
   671  	ALDORLB
   672  	ALDORLD
   673  	ALDORLH
   674  	ALDORLW
   675  	ALDP
   676  	ALDPW
   677  	ALDPSW
   678  	ALDXR
   679  	ALDXRB
   680  	ALDXRH
   681  	ALDXRW
   682  	ALDXP
   683  	ALDXPW
   684  	ALSL
   685  	ALSLW
   686  	ALSR
   687  	ALSRW
   688  	AMADD
   689  	AMADDW
   690  	AMNEG
   691  	AMNEGW
   692  	AMOVK
   693  	AMOVKW
   694  	AMOVN
   695  	AMOVNW
   696  	AMOVZ
   697  	AMOVZW
   698  	AMRS
   699  	AMSR
   700  	AMSUB
   701  	AMSUBW
   702  	AMUL
   703  	AMULW
   704  	AMVN
   705  	AMVNW
   706  	ANEG
   707  	ANEGS
   708  	ANEGSW
   709  	ANEGW
   710  	ANGC
   711  	ANGCS
   712  	ANGCSW
   713  	ANGCW
   714  	AORN
   715  	AORNW
   716  	AORR
   717  	AORRW
   718  	APRFM
   719  	APRFUM
   720  	ARBIT
   721  	ARBITW
   722  	AREM
   723  	AREMW
   724  	AREV
   725  	AREV16
   726  	AREV16W
   727  	AREV32
   728  	AREVW
   729  	AROR
   730  	ARORW
   731  	ASBC
   732  	ASBCS
   733  	ASBCSW
   734  	ASBCW
   735  	ASBFIZ
   736  	ASBFIZW
   737  	ASBFM
   738  	ASBFMW
   739  	ASBFX
   740  	ASBFXW
   741  	ASDIV
   742  	ASDIVW
   743  	ASEV
   744  	ASEVL
   745  	ASMADDL
   746  	ASMC
   747  	ASMNEGL
   748  	ASMSUBL
   749  	ASMULH
   750  	ASMULL
   751  	ASTXR
   752  	ASTXRB
   753  	ASTXRH
   754  	ASTXP
   755  	ASTXPW
   756  	ASTXRW
   757  	ASTLP
   758  	ASTLPW
   759  	ASTLR
   760  	ASTLRB
   761  	ASTLRH
   762  	ASTLRW
   763  	ASTLXP
   764  	ASTLXPW
   765  	ASTLXR
   766  	ASTLXRB
   767  	ASTLXRH
   768  	ASTLXRW
   769  	ASTP
   770  	ASTPW
   771  	ASUB
   772  	ASUBS
   773  	ASUBSW
   774  	ASUBW
   775  	ASVC
   776  	ASXTB
   777  	ASXTBW
   778  	ASXTH
   779  	ASXTHW
   780  	ASXTW
   781  	ASYS
   782  	ASYSL
   783  	ATBNZ
   784  	ATBZ
   785  	ATLBI
   786  	ATST
   787  	ATSTW
   788  	AUBFIZ
   789  	AUBFIZW
   790  	AUBFM
   791  	AUBFMW
   792  	AUBFX
   793  	AUBFXW
   794  	AUDIV
   795  	AUDIVW
   796  	AUMADDL
   797  	AUMNEGL
   798  	AUMSUBL
   799  	AUMULH
   800  	AUMULL
   801  	AUREM
   802  	AUREMW
   803  	AUXTB
   804  	AUXTH
   805  	AUXTW
   806  	AUXTBW
   807  	AUXTHW
   808  	AWFE
   809  	AWFI
   810  	AYIELD
   811  	AMOVB
   812  	AMOVBU
   813  	AMOVH
   814  	AMOVHU
   815  	AMOVW
   816  	AMOVWU
   817  	AMOVD
   818  	AMOVNP
   819  	AMOVNPW
   820  	AMOVP
   821  	AMOVPD
   822  	AMOVPQ
   823  	AMOVPS
   824  	AMOVPSW
   825  	AMOVPW
   826  	ASWPAD
   827  	ASWPAW
   828  	ASWPAH
   829  	ASWPAB
   830  	ASWPALD
   831  	ASWPALW
   832  	ASWPALH
   833  	ASWPALB
   834  	ASWPD
   835  	ASWPW
   836  	ASWPH
   837  	ASWPB
   838  	ASWPLD
   839  	ASWPLW
   840  	ASWPLH
   841  	ASWPLB
   842  	ABEQ
   843  	ABNE
   844  	ABCS
   845  	ABHS
   846  	ABCC
   847  	ABLO
   848  	ABMI
   849  	ABPL
   850  	ABVS
   851  	ABVC
   852  	ABHI
   853  	ABLS
   854  	ABGE
   855  	ABLT
   856  	ABGT
   857  	ABLE
   858  	AFABSD
   859  	AFABSS
   860  	AFADDD
   861  	AFADDS
   862  	AFCCMPD
   863  	AFCCMPED
   864  	AFCCMPS
   865  	AFCCMPES
   866  	AFCMPD
   867  	AFCMPED
   868  	AFCMPES
   869  	AFCMPS
   870  	AFCVTSD
   871  	AFCVTDS
   872  	AFCVTZSD
   873  	AFCVTZSDW
   874  	AFCVTZSS
   875  	AFCVTZSSW
   876  	AFCVTZUD
   877  	AFCVTZUDW
   878  	AFCVTZUS
   879  	AFCVTZUSW
   880  	AFDIVD
   881  	AFDIVS
   882  	AFLDPD
   883  	AFLDPS
   884  	AFMOVD
   885  	AFMOVS
   886  	AFMULD
   887  	AFMULS
   888  	AFNEGD
   889  	AFNEGS
   890  	AFSQRTD
   891  	AFSQRTS
   892  	AFSTPD
   893  	AFSTPS
   894  	AFSUBD
   895  	AFSUBS
   896  	ASCVTFD
   897  	ASCVTFS
   898  	ASCVTFWD
   899  	ASCVTFWS
   900  	AUCVTFD
   901  	AUCVTFS
   902  	AUCVTFWD
   903  	AUCVTFWS
   904  	AWORD
   905  	ADWORD
   906  	AFCSELS
   907  	AFCSELD
   908  	AFMAXS
   909  	AFMINS
   910  	AFMAXD
   911  	AFMIND
   912  	AFMAXNMS
   913  	AFMAXNMD
   914  	AFNMULS
   915  	AFNMULD
   916  	AFRINTNS
   917  	AFRINTND
   918  	AFRINTPS
   919  	AFRINTPD
   920  	AFRINTMS
   921  	AFRINTMD
   922  	AFRINTZS
   923  	AFRINTZD
   924  	AFRINTAS
   925  	AFRINTAD
   926  	AFRINTXS
   927  	AFRINTXD
   928  	AFRINTIS
   929  	AFRINTID
   930  	AFMADDS
   931  	AFMADDD
   932  	AFMSUBS
   933  	AFMSUBD
   934  	AFNMADDS
   935  	AFNMADDD
   936  	AFNMSUBS
   937  	AFNMSUBD
   938  	AFMINNMS
   939  	AFMINNMD
   940  	AFCVTDH
   941  	AFCVTHS
   942  	AFCVTHD
   943  	AFCVTSH
   944  	AAESD
   945  	AAESE
   946  	AAESIMC
   947  	AAESMC
   948  	ASHA1C
   949  	ASHA1H
   950  	ASHA1M
   951  	ASHA1P
   952  	ASHA1SU0
   953  	ASHA1SU1
   954  	ASHA256H
   955  	ASHA256H2
   956  	ASHA256SU0
   957  	ASHA256SU1
   958  	AVADD
   959  	AVADDP
   960  	AVAND
   961  	AVCMEQ
   962  	AVCNT
   963  	AVEOR
   964  	AVMOV
   965  	AVLD1
   966  	AVORR
   967  	AVREV32
   968  	AVREV64
   969  	AVST1
   970  	AVDUP
   971  	AVADDV
   972  	AVMOVI
   973  	AVUADDLV
   974  	AVSUB
   975  	AVFMLA
   976  	AVFMLS
   977  	AVPMULL
   978  	AVPMULL2
   979  	AVEXT
   980  	AVRBIT
   981  	AVUSHR
   982  	AVSHL
   983  	AVSRI
   984  	AVTBL
   985  	AVZIP1
   986  	AVZIP2
   987  	ALAST
   988  	AB  = obj.AJMP
   989  	ABL = obj.ACALL
   990  )
   991  
   992  const (
   993  	// shift types
   994  	SHIFT_LL = 0 << 22
   995  	SHIFT_LR = 1 << 22
   996  	SHIFT_AR = 2 << 22
   997  )
   998  
   999  // Arrangement for ARM64 SIMD instructions
  1000  const (
  1001  	// arrangement types
  1002  	ARNG_8B = iota
  1003  	ARNG_16B
  1004  	ARNG_1D
  1005  	ARNG_4H
  1006  	ARNG_8H
  1007  	ARNG_2S
  1008  	ARNG_4S
  1009  	ARNG_2D
  1010  	ARNG_1Q
  1011  	ARNG_B
  1012  	ARNG_H
  1013  	ARNG_S
  1014  	ARNG_D
  1015  )
  1016  

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