Source file src/cmd/compile/internal/ssa/rewriteARM64.go

Documentation: cmd/compile/internal/ssa

     1  // Code generated from gen/ARM64.rules; DO NOT EDIT.
     2  // generated with: cd gen; go run *.go
     3  
     4  package ssa
     5  
     6  import "fmt"
     7  import "math"
     8  import "cmd/internal/obj"
     9  import "cmd/internal/objabi"
    10  import "cmd/compile/internal/types"
    11  
    12  var _ = fmt.Println   // in case not otherwise used
    13  var _ = math.MinInt8  // in case not otherwise used
    14  var _ = obj.ANOP      // in case not otherwise used
    15  var _ = objabi.GOROOT // in case not otherwise used
    16  var _ = types.TypeMem // in case not otherwise used
    17  
    18  func rewriteValueARM64(v *Value) bool {
    19  	switch v.Op {
    20  	case OpARM64ADCSflags:
    21  		return rewriteValueARM64_OpARM64ADCSflags_0(v)
    22  	case OpARM64ADD:
    23  		return rewriteValueARM64_OpARM64ADD_0(v) || rewriteValueARM64_OpARM64ADD_10(v) || rewriteValueARM64_OpARM64ADD_20(v)
    24  	case OpARM64ADDconst:
    25  		return rewriteValueARM64_OpARM64ADDconst_0(v)
    26  	case OpARM64ADDshiftLL:
    27  		return rewriteValueARM64_OpARM64ADDshiftLL_0(v)
    28  	case OpARM64ADDshiftRA:
    29  		return rewriteValueARM64_OpARM64ADDshiftRA_0(v)
    30  	case OpARM64ADDshiftRL:
    31  		return rewriteValueARM64_OpARM64ADDshiftRL_0(v)
    32  	case OpARM64AND:
    33  		return rewriteValueARM64_OpARM64AND_0(v) || rewriteValueARM64_OpARM64AND_10(v)
    34  	case OpARM64ANDconst:
    35  		return rewriteValueARM64_OpARM64ANDconst_0(v)
    36  	case OpARM64ANDshiftLL:
    37  		return rewriteValueARM64_OpARM64ANDshiftLL_0(v)
    38  	case OpARM64ANDshiftRA:
    39  		return rewriteValueARM64_OpARM64ANDshiftRA_0(v)
    40  	case OpARM64ANDshiftRL:
    41  		return rewriteValueARM64_OpARM64ANDshiftRL_0(v)
    42  	case OpARM64BIC:
    43  		return rewriteValueARM64_OpARM64BIC_0(v)
    44  	case OpARM64BICshiftLL:
    45  		return rewriteValueARM64_OpARM64BICshiftLL_0(v)
    46  	case OpARM64BICshiftRA:
    47  		return rewriteValueARM64_OpARM64BICshiftRA_0(v)
    48  	case OpARM64BICshiftRL:
    49  		return rewriteValueARM64_OpARM64BICshiftRL_0(v)
    50  	case OpARM64CMN:
    51  		return rewriteValueARM64_OpARM64CMN_0(v)
    52  	case OpARM64CMNW:
    53  		return rewriteValueARM64_OpARM64CMNW_0(v)
    54  	case OpARM64CMNWconst:
    55  		return rewriteValueARM64_OpARM64CMNWconst_0(v)
    56  	case OpARM64CMNconst:
    57  		return rewriteValueARM64_OpARM64CMNconst_0(v)
    58  	case OpARM64CMNshiftLL:
    59  		return rewriteValueARM64_OpARM64CMNshiftLL_0(v)
    60  	case OpARM64CMNshiftRA:
    61  		return rewriteValueARM64_OpARM64CMNshiftRA_0(v)
    62  	case OpARM64CMNshiftRL:
    63  		return rewriteValueARM64_OpARM64CMNshiftRL_0(v)
    64  	case OpARM64CMP:
    65  		return rewriteValueARM64_OpARM64CMP_0(v)
    66  	case OpARM64CMPW:
    67  		return rewriteValueARM64_OpARM64CMPW_0(v)
    68  	case OpARM64CMPWconst:
    69  		return rewriteValueARM64_OpARM64CMPWconst_0(v)
    70  	case OpARM64CMPconst:
    71  		return rewriteValueARM64_OpARM64CMPconst_0(v)
    72  	case OpARM64CMPshiftLL:
    73  		return rewriteValueARM64_OpARM64CMPshiftLL_0(v)
    74  	case OpARM64CMPshiftRA:
    75  		return rewriteValueARM64_OpARM64CMPshiftRA_0(v)
    76  	case OpARM64CMPshiftRL:
    77  		return rewriteValueARM64_OpARM64CMPshiftRL_0(v)
    78  	case OpARM64CSEL:
    79  		return rewriteValueARM64_OpARM64CSEL_0(v)
    80  	case OpARM64CSEL0:
    81  		return rewriteValueARM64_OpARM64CSEL0_0(v)
    82  	case OpARM64DIV:
    83  		return rewriteValueARM64_OpARM64DIV_0(v)
    84  	case OpARM64DIVW:
    85  		return rewriteValueARM64_OpARM64DIVW_0(v)
    86  	case OpARM64EON:
    87  		return rewriteValueARM64_OpARM64EON_0(v)
    88  	case OpARM64EONshiftLL:
    89  		return rewriteValueARM64_OpARM64EONshiftLL_0(v)
    90  	case OpARM64EONshiftRA:
    91  		return rewriteValueARM64_OpARM64EONshiftRA_0(v)
    92  	case OpARM64EONshiftRL:
    93  		return rewriteValueARM64_OpARM64EONshiftRL_0(v)
    94  	case OpARM64Equal:
    95  		return rewriteValueARM64_OpARM64Equal_0(v)
    96  	case OpARM64FADDD:
    97  		return rewriteValueARM64_OpARM64FADDD_0(v)
    98  	case OpARM64FADDS:
    99  		return rewriteValueARM64_OpARM64FADDS_0(v)
   100  	case OpARM64FCMPD:
   101  		return rewriteValueARM64_OpARM64FCMPD_0(v)
   102  	case OpARM64FCMPS:
   103  		return rewriteValueARM64_OpARM64FCMPS_0(v)
   104  	case OpARM64FMOVDfpgp:
   105  		return rewriteValueARM64_OpARM64FMOVDfpgp_0(v)
   106  	case OpARM64FMOVDgpfp:
   107  		return rewriteValueARM64_OpARM64FMOVDgpfp_0(v)
   108  	case OpARM64FMOVDload:
   109  		return rewriteValueARM64_OpARM64FMOVDload_0(v)
   110  	case OpARM64FMOVDloadidx:
   111  		return rewriteValueARM64_OpARM64FMOVDloadidx_0(v)
   112  	case OpARM64FMOVDstore:
   113  		return rewriteValueARM64_OpARM64FMOVDstore_0(v)
   114  	case OpARM64FMOVDstoreidx:
   115  		return rewriteValueARM64_OpARM64FMOVDstoreidx_0(v)
   116  	case OpARM64FMOVSload:
   117  		return rewriteValueARM64_OpARM64FMOVSload_0(v)
   118  	case OpARM64FMOVSloadidx:
   119  		return rewriteValueARM64_OpARM64FMOVSloadidx_0(v)
   120  	case OpARM64FMOVSstore:
   121  		return rewriteValueARM64_OpARM64FMOVSstore_0(v)
   122  	case OpARM64FMOVSstoreidx:
   123  		return rewriteValueARM64_OpARM64FMOVSstoreidx_0(v)
   124  	case OpARM64FMULD:
   125  		return rewriteValueARM64_OpARM64FMULD_0(v)
   126  	case OpARM64FMULS:
   127  		return rewriteValueARM64_OpARM64FMULS_0(v)
   128  	case OpARM64FNEGD:
   129  		return rewriteValueARM64_OpARM64FNEGD_0(v)
   130  	case OpARM64FNEGS:
   131  		return rewriteValueARM64_OpARM64FNEGS_0(v)
   132  	case OpARM64FNMULD:
   133  		return rewriteValueARM64_OpARM64FNMULD_0(v)
   134  	case OpARM64FNMULS:
   135  		return rewriteValueARM64_OpARM64FNMULS_0(v)
   136  	case OpARM64FSUBD:
   137  		return rewriteValueARM64_OpARM64FSUBD_0(v)
   138  	case OpARM64FSUBS:
   139  		return rewriteValueARM64_OpARM64FSUBS_0(v)
   140  	case OpARM64GreaterEqual:
   141  		return rewriteValueARM64_OpARM64GreaterEqual_0(v)
   142  	case OpARM64GreaterEqualF:
   143  		return rewriteValueARM64_OpARM64GreaterEqualF_0(v)
   144  	case OpARM64GreaterEqualU:
   145  		return rewriteValueARM64_OpARM64GreaterEqualU_0(v)
   146  	case OpARM64GreaterThan:
   147  		return rewriteValueARM64_OpARM64GreaterThan_0(v)
   148  	case OpARM64GreaterThanF:
   149  		return rewriteValueARM64_OpARM64GreaterThanF_0(v)
   150  	case OpARM64GreaterThanU:
   151  		return rewriteValueARM64_OpARM64GreaterThanU_0(v)
   152  	case OpARM64LessEqual:
   153  		return rewriteValueARM64_OpARM64LessEqual_0(v)
   154  	case OpARM64LessEqualF:
   155  		return rewriteValueARM64_OpARM64LessEqualF_0(v)
   156  	case OpARM64LessEqualU:
   157  		return rewriteValueARM64_OpARM64LessEqualU_0(v)
   158  	case OpARM64LessThan:
   159  		return rewriteValueARM64_OpARM64LessThan_0(v)
   160  	case OpARM64LessThanF:
   161  		return rewriteValueARM64_OpARM64LessThanF_0(v)
   162  	case OpARM64LessThanU:
   163  		return rewriteValueARM64_OpARM64LessThanU_0(v)
   164  	case OpARM64MADD:
   165  		return rewriteValueARM64_OpARM64MADD_0(v) || rewriteValueARM64_OpARM64MADD_10(v) || rewriteValueARM64_OpARM64MADD_20(v)
   166  	case OpARM64MADDW:
   167  		return rewriteValueARM64_OpARM64MADDW_0(v) || rewriteValueARM64_OpARM64MADDW_10(v) || rewriteValueARM64_OpARM64MADDW_20(v)
   168  	case OpARM64MNEG:
   169  		return rewriteValueARM64_OpARM64MNEG_0(v) || rewriteValueARM64_OpARM64MNEG_10(v) || rewriteValueARM64_OpARM64MNEG_20(v)
   170  	case OpARM64MNEGW:
   171  		return rewriteValueARM64_OpARM64MNEGW_0(v) || rewriteValueARM64_OpARM64MNEGW_10(v) || rewriteValueARM64_OpARM64MNEGW_20(v)
   172  	case OpARM64MOD:
   173  		return rewriteValueARM64_OpARM64MOD_0(v)
   174  	case OpARM64MODW:
   175  		return rewriteValueARM64_OpARM64MODW_0(v)
   176  	case OpARM64MOVBUload:
   177  		return rewriteValueARM64_OpARM64MOVBUload_0(v)
   178  	case OpARM64MOVBUloadidx:
   179  		return rewriteValueARM64_OpARM64MOVBUloadidx_0(v)
   180  	case OpARM64MOVBUreg:
   181  		return rewriteValueARM64_OpARM64MOVBUreg_0(v)
   182  	case OpARM64MOVBload:
   183  		return rewriteValueARM64_OpARM64MOVBload_0(v)
   184  	case OpARM64MOVBloadidx:
   185  		return rewriteValueARM64_OpARM64MOVBloadidx_0(v)
   186  	case OpARM64MOVBreg:
   187  		return rewriteValueARM64_OpARM64MOVBreg_0(v)
   188  	case OpARM64MOVBstore:
   189  		return rewriteValueARM64_OpARM64MOVBstore_0(v) || rewriteValueARM64_OpARM64MOVBstore_10(v) || rewriteValueARM64_OpARM64MOVBstore_20(v) || rewriteValueARM64_OpARM64MOVBstore_30(v) || rewriteValueARM64_OpARM64MOVBstore_40(v)
   190  	case OpARM64MOVBstoreidx:
   191  		return rewriteValueARM64_OpARM64MOVBstoreidx_0(v) || rewriteValueARM64_OpARM64MOVBstoreidx_10(v)
   192  	case OpARM64MOVBstorezero:
   193  		return rewriteValueARM64_OpARM64MOVBstorezero_0(v)
   194  	case OpARM64MOVBstorezeroidx:
   195  		return rewriteValueARM64_OpARM64MOVBstorezeroidx_0(v)
   196  	case OpARM64MOVDload:
   197  		return rewriteValueARM64_OpARM64MOVDload_0(v)
   198  	case OpARM64MOVDloadidx:
   199  		return rewriteValueARM64_OpARM64MOVDloadidx_0(v)
   200  	case OpARM64MOVDloadidx8:
   201  		return rewriteValueARM64_OpARM64MOVDloadidx8_0(v)
   202  	case OpARM64MOVDreg:
   203  		return rewriteValueARM64_OpARM64MOVDreg_0(v)
   204  	case OpARM64MOVDstore:
   205  		return rewriteValueARM64_OpARM64MOVDstore_0(v)
   206  	case OpARM64MOVDstoreidx:
   207  		return rewriteValueARM64_OpARM64MOVDstoreidx_0(v)
   208  	case OpARM64MOVDstoreidx8:
   209  		return rewriteValueARM64_OpARM64MOVDstoreidx8_0(v)
   210  	case OpARM64MOVDstorezero:
   211  		return rewriteValueARM64_OpARM64MOVDstorezero_0(v)
   212  	case OpARM64MOVDstorezeroidx:
   213  		return rewriteValueARM64_OpARM64MOVDstorezeroidx_0(v)
   214  	case OpARM64MOVDstorezeroidx8:
   215  		return rewriteValueARM64_OpARM64MOVDstorezeroidx8_0(v)
   216  	case OpARM64MOVHUload:
   217  		return rewriteValueARM64_OpARM64MOVHUload_0(v)
   218  	case OpARM64MOVHUloadidx:
   219  		return rewriteValueARM64_OpARM64MOVHUloadidx_0(v)
   220  	case OpARM64MOVHUloadidx2:
   221  		return rewriteValueARM64_OpARM64MOVHUloadidx2_0(v)
   222  	case OpARM64MOVHUreg:
   223  		return rewriteValueARM64_OpARM64MOVHUreg_0(v) || rewriteValueARM64_OpARM64MOVHUreg_10(v)
   224  	case OpARM64MOVHload:
   225  		return rewriteValueARM64_OpARM64MOVHload_0(v)
   226  	case OpARM64MOVHloadidx:
   227  		return rewriteValueARM64_OpARM64MOVHloadidx_0(v)
   228  	case OpARM64MOVHloadidx2:
   229  		return rewriteValueARM64_OpARM64MOVHloadidx2_0(v)
   230  	case OpARM64MOVHreg:
   231  		return rewriteValueARM64_OpARM64MOVHreg_0(v) || rewriteValueARM64_OpARM64MOVHreg_10(v)
   232  	case OpARM64MOVHstore:
   233  		return rewriteValueARM64_OpARM64MOVHstore_0(v) || rewriteValueARM64_OpARM64MOVHstore_10(v) || rewriteValueARM64_OpARM64MOVHstore_20(v)
   234  	case OpARM64MOVHstoreidx:
   235  		return rewriteValueARM64_OpARM64MOVHstoreidx_0(v) || rewriteValueARM64_OpARM64MOVHstoreidx_10(v)
   236  	case OpARM64MOVHstoreidx2:
   237  		return rewriteValueARM64_OpARM64MOVHstoreidx2_0(v)
   238  	case OpARM64MOVHstorezero:
   239  		return rewriteValueARM64_OpARM64MOVHstorezero_0(v)
   240  	case OpARM64MOVHstorezeroidx:
   241  		return rewriteValueARM64_OpARM64MOVHstorezeroidx_0(v)
   242  	case OpARM64MOVHstorezeroidx2:
   243  		return rewriteValueARM64_OpARM64MOVHstorezeroidx2_0(v)
   244  	case OpARM64MOVQstorezero:
   245  		return rewriteValueARM64_OpARM64MOVQstorezero_0(v)
   246  	case OpARM64MOVWUload:
   247  		return rewriteValueARM64_OpARM64MOVWUload_0(v)
   248  	case OpARM64MOVWUloadidx:
   249  		return rewriteValueARM64_OpARM64MOVWUloadidx_0(v)
   250  	case OpARM64MOVWUloadidx4:
   251  		return rewriteValueARM64_OpARM64MOVWUloadidx4_0(v)
   252  	case OpARM64MOVWUreg:
   253  		return rewriteValueARM64_OpARM64MOVWUreg_0(v) || rewriteValueARM64_OpARM64MOVWUreg_10(v)
   254  	case OpARM64MOVWload:
   255  		return rewriteValueARM64_OpARM64MOVWload_0(v)
   256  	case OpARM64MOVWloadidx:
   257  		return rewriteValueARM64_OpARM64MOVWloadidx_0(v)
   258  	case OpARM64MOVWloadidx4:
   259  		return rewriteValueARM64_OpARM64MOVWloadidx4_0(v)
   260  	case OpARM64MOVWreg:
   261  		return rewriteValueARM64_OpARM64MOVWreg_0(v) || rewriteValueARM64_OpARM64MOVWreg_10(v)
   262  	case OpARM64MOVWstore:
   263  		return rewriteValueARM64_OpARM64MOVWstore_0(v) || rewriteValueARM64_OpARM64MOVWstore_10(v)
   264  	case OpARM64MOVWstoreidx:
   265  		return rewriteValueARM64_OpARM64MOVWstoreidx_0(v)
   266  	case OpARM64MOVWstoreidx4:
   267  		return rewriteValueARM64_OpARM64MOVWstoreidx4_0(v)
   268  	case OpARM64MOVWstorezero:
   269  		return rewriteValueARM64_OpARM64MOVWstorezero_0(v)
   270  	case OpARM64MOVWstorezeroidx:
   271  		return rewriteValueARM64_OpARM64MOVWstorezeroidx_0(v)
   272  	case OpARM64MOVWstorezeroidx4:
   273  		return rewriteValueARM64_OpARM64MOVWstorezeroidx4_0(v)
   274  	case OpARM64MSUB:
   275  		return rewriteValueARM64_OpARM64MSUB_0(v) || rewriteValueARM64_OpARM64MSUB_10(v) || rewriteValueARM64_OpARM64MSUB_20(v)
   276  	case OpARM64MSUBW:
   277  		return rewriteValueARM64_OpARM64MSUBW_0(v) || rewriteValueARM64_OpARM64MSUBW_10(v) || rewriteValueARM64_OpARM64MSUBW_20(v)
   278  	case OpARM64MUL:
   279  		return rewriteValueARM64_OpARM64MUL_0(v) || rewriteValueARM64_OpARM64MUL_10(v) || rewriteValueARM64_OpARM64MUL_20(v)
   280  	case OpARM64MULW:
   281  		return rewriteValueARM64_OpARM64MULW_0(v) || rewriteValueARM64_OpARM64MULW_10(v) || rewriteValueARM64_OpARM64MULW_20(v)
   282  	case OpARM64MVN:
   283  		return rewriteValueARM64_OpARM64MVN_0(v)
   284  	case OpARM64MVNshiftLL:
   285  		return rewriteValueARM64_OpARM64MVNshiftLL_0(v)
   286  	case OpARM64MVNshiftRA:
   287  		return rewriteValueARM64_OpARM64MVNshiftRA_0(v)
   288  	case OpARM64MVNshiftRL:
   289  		return rewriteValueARM64_OpARM64MVNshiftRL_0(v)
   290  	case OpARM64NEG:
   291  		return rewriteValueARM64_OpARM64NEG_0(v)
   292  	case OpARM64NEGshiftLL:
   293  		return rewriteValueARM64_OpARM64NEGshiftLL_0(v)
   294  	case OpARM64NEGshiftRA:
   295  		return rewriteValueARM64_OpARM64NEGshiftRA_0(v)
   296  	case OpARM64NEGshiftRL:
   297  		return rewriteValueARM64_OpARM64NEGshiftRL_0(v)
   298  	case OpARM64NotEqual:
   299  		return rewriteValueARM64_OpARM64NotEqual_0(v)
   300  	case OpARM64OR:
   301  		return rewriteValueARM64_OpARM64OR_0(v) || rewriteValueARM64_OpARM64OR_10(v) || rewriteValueARM64_OpARM64OR_20(v) || rewriteValueARM64_OpARM64OR_30(v) || rewriteValueARM64_OpARM64OR_40(v)
   302  	case OpARM64ORN:
   303  		return rewriteValueARM64_OpARM64ORN_0(v)
   304  	case OpARM64ORNshiftLL:
   305  		return rewriteValueARM64_OpARM64ORNshiftLL_0(v)
   306  	case OpARM64ORNshiftRA:
   307  		return rewriteValueARM64_OpARM64ORNshiftRA_0(v)
   308  	case OpARM64ORNshiftRL:
   309  		return rewriteValueARM64_OpARM64ORNshiftRL_0(v)
   310  	case OpARM64ORconst:
   311  		return rewriteValueARM64_OpARM64ORconst_0(v)
   312  	case OpARM64ORshiftLL:
   313  		return rewriteValueARM64_OpARM64ORshiftLL_0(v) || rewriteValueARM64_OpARM64ORshiftLL_10(v) || rewriteValueARM64_OpARM64ORshiftLL_20(v)
   314  	case OpARM64ORshiftRA:
   315  		return rewriteValueARM64_OpARM64ORshiftRA_0(v)
   316  	case OpARM64ORshiftRL:
   317  		return rewriteValueARM64_OpARM64ORshiftRL_0(v)
   318  	case OpARM64RORWconst:
   319  		return rewriteValueARM64_OpARM64RORWconst_0(v)
   320  	case OpARM64RORconst:
   321  		return rewriteValueARM64_OpARM64RORconst_0(v)
   322  	case OpARM64SBCSflags:
   323  		return rewriteValueARM64_OpARM64SBCSflags_0(v)
   324  	case OpARM64SLL:
   325  		return rewriteValueARM64_OpARM64SLL_0(v)
   326  	case OpARM64SLLconst:
   327  		return rewriteValueARM64_OpARM64SLLconst_0(v)
   328  	case OpARM64SRA:
   329  		return rewriteValueARM64_OpARM64SRA_0(v)
   330  	case OpARM64SRAconst:
   331  		return rewriteValueARM64_OpARM64SRAconst_0(v)
   332  	case OpARM64SRL:
   333  		return rewriteValueARM64_OpARM64SRL_0(v)
   334  	case OpARM64SRLconst:
   335  		return rewriteValueARM64_OpARM64SRLconst_0(v) || rewriteValueARM64_OpARM64SRLconst_10(v)
   336  	case OpARM64STP:
   337  		return rewriteValueARM64_OpARM64STP_0(v)
   338  	case OpARM64SUB:
   339  		return rewriteValueARM64_OpARM64SUB_0(v) || rewriteValueARM64_OpARM64SUB_10(v)
   340  	case OpARM64SUBconst:
   341  		return rewriteValueARM64_OpARM64SUBconst_0(v)
   342  	case OpARM64SUBshiftLL:
   343  		return rewriteValueARM64_OpARM64SUBshiftLL_0(v)
   344  	case OpARM64SUBshiftRA:
   345  		return rewriteValueARM64_OpARM64SUBshiftRA_0(v)
   346  	case OpARM64SUBshiftRL:
   347  		return rewriteValueARM64_OpARM64SUBshiftRL_0(v)
   348  	case OpARM64TST:
   349  		return rewriteValueARM64_OpARM64TST_0(v)
   350  	case OpARM64TSTW:
   351  		return rewriteValueARM64_OpARM64TSTW_0(v)
   352  	case OpARM64TSTWconst:
   353  		return rewriteValueARM64_OpARM64TSTWconst_0(v)
   354  	case OpARM64TSTconst:
   355  		return rewriteValueARM64_OpARM64TSTconst_0(v)
   356  	case OpARM64TSTshiftLL:
   357  		return rewriteValueARM64_OpARM64TSTshiftLL_0(v)
   358  	case OpARM64TSTshiftRA:
   359  		return rewriteValueARM64_OpARM64TSTshiftRA_0(v)
   360  	case OpARM64TSTshiftRL:
   361  		return rewriteValueARM64_OpARM64TSTshiftRL_0(v)
   362  	case OpARM64UBFIZ:
   363  		return rewriteValueARM64_OpARM64UBFIZ_0(v)
   364  	case OpARM64UBFX:
   365  		return rewriteValueARM64_OpARM64UBFX_0(v)
   366  	case OpARM64UDIV:
   367  		return rewriteValueARM64_OpARM64UDIV_0(v)
   368  	case OpARM64UDIVW:
   369  		return rewriteValueARM64_OpARM64UDIVW_0(v)
   370  	case OpARM64UMOD:
   371  		return rewriteValueARM64_OpARM64UMOD_0(v)
   372  	case OpARM64UMODW:
   373  		return rewriteValueARM64_OpARM64UMODW_0(v)
   374  	case OpARM64XOR:
   375  		return rewriteValueARM64_OpARM64XOR_0(v) || rewriteValueARM64_OpARM64XOR_10(v)
   376  	case OpARM64XORconst:
   377  		return rewriteValueARM64_OpARM64XORconst_0(v)
   378  	case OpARM64XORshiftLL:
   379  		return rewriteValueARM64_OpARM64XORshiftLL_0(v)
   380  	case OpARM64XORshiftRA:
   381  		return rewriteValueARM64_OpARM64XORshiftRA_0(v)
   382  	case OpARM64XORshiftRL:
   383  		return rewriteValueARM64_OpARM64XORshiftRL_0(v)
   384  	case OpAbs:
   385  		return rewriteValueARM64_OpAbs_0(v)
   386  	case OpAdd16:
   387  		return rewriteValueARM64_OpAdd16_0(v)
   388  	case OpAdd32:
   389  		return rewriteValueARM64_OpAdd32_0(v)
   390  	case OpAdd32F:
   391  		return rewriteValueARM64_OpAdd32F_0(v)
   392  	case OpAdd64:
   393  		return rewriteValueARM64_OpAdd64_0(v)
   394  	case OpAdd64F:
   395  		return rewriteValueARM64_OpAdd64F_0(v)
   396  	case OpAdd8:
   397  		return rewriteValueARM64_OpAdd8_0(v)
   398  	case OpAddPtr:
   399  		return rewriteValueARM64_OpAddPtr_0(v)
   400  	case OpAddr:
   401  		return rewriteValueARM64_OpAddr_0(v)
   402  	case OpAnd16:
   403  		return rewriteValueARM64_OpAnd16_0(v)
   404  	case OpAnd32:
   405  		return rewriteValueARM64_OpAnd32_0(v)
   406  	case OpAnd64:
   407  		return rewriteValueARM64_OpAnd64_0(v)
   408  	case OpAnd8:
   409  		return rewriteValueARM64_OpAnd8_0(v)
   410  	case OpAndB:
   411  		return rewriteValueARM64_OpAndB_0(v)
   412  	case OpAtomicAdd32:
   413  		return rewriteValueARM64_OpAtomicAdd32_0(v)
   414  	case OpAtomicAdd32Variant:
   415  		return rewriteValueARM64_OpAtomicAdd32Variant_0(v)
   416  	case OpAtomicAdd64:
   417  		return rewriteValueARM64_OpAtomicAdd64_0(v)
   418  	case OpAtomicAdd64Variant:
   419  		return rewriteValueARM64_OpAtomicAdd64Variant_0(v)
   420  	case OpAtomicAnd8:
   421  		return rewriteValueARM64_OpAtomicAnd8_0(v)
   422  	case OpAtomicCompareAndSwap32:
   423  		return rewriteValueARM64_OpAtomicCompareAndSwap32_0(v)
   424  	case OpAtomicCompareAndSwap64:
   425  		return rewriteValueARM64_OpAtomicCompareAndSwap64_0(v)
   426  	case OpAtomicExchange32:
   427  		return rewriteValueARM64_OpAtomicExchange32_0(v)
   428  	case OpAtomicExchange64:
   429  		return rewriteValueARM64_OpAtomicExchange64_0(v)
   430  	case OpAtomicLoad32:
   431  		return rewriteValueARM64_OpAtomicLoad32_0(v)
   432  	case OpAtomicLoad64:
   433  		return rewriteValueARM64_OpAtomicLoad64_0(v)
   434  	case OpAtomicLoad8:
   435  		return rewriteValueARM64_OpAtomicLoad8_0(v)
   436  	case OpAtomicLoadPtr:
   437  		return rewriteValueARM64_OpAtomicLoadPtr_0(v)
   438  	case OpAtomicOr8:
   439  		return rewriteValueARM64_OpAtomicOr8_0(v)
   440  	case OpAtomicStore32:
   441  		return rewriteValueARM64_OpAtomicStore32_0(v)
   442  	case OpAtomicStore64:
   443  		return rewriteValueARM64_OpAtomicStore64_0(v)
   444  	case OpAtomicStorePtrNoWB:
   445  		return rewriteValueARM64_OpAtomicStorePtrNoWB_0(v)
   446  	case OpAvg64u:
   447  		return rewriteValueARM64_OpAvg64u_0(v)
   448  	case OpBitLen32:
   449  		return rewriteValueARM64_OpBitLen32_0(v)
   450  	case OpBitLen64:
   451  		return rewriteValueARM64_OpBitLen64_0(v)
   452  	case OpBitRev16:
   453  		return rewriteValueARM64_OpBitRev16_0(v)
   454  	case OpBitRev32:
   455  		return rewriteValueARM64_OpBitRev32_0(v)
   456  	case OpBitRev64:
   457  		return rewriteValueARM64_OpBitRev64_0(v)
   458  	case OpBitRev8:
   459  		return rewriteValueARM64_OpBitRev8_0(v)
   460  	case OpBswap32:
   461  		return rewriteValueARM64_OpBswap32_0(v)
   462  	case OpBswap64:
   463  		return rewriteValueARM64_OpBswap64_0(v)
   464  	case OpCeil:
   465  		return rewriteValueARM64_OpCeil_0(v)
   466  	case OpClosureCall:
   467  		return rewriteValueARM64_OpClosureCall_0(v)
   468  	case OpCom16:
   469  		return rewriteValueARM64_OpCom16_0(v)
   470  	case OpCom32:
   471  		return rewriteValueARM64_OpCom32_0(v)
   472  	case OpCom64:
   473  		return rewriteValueARM64_OpCom64_0(v)
   474  	case OpCom8:
   475  		return rewriteValueARM64_OpCom8_0(v)
   476  	case OpCondSelect:
   477  		return rewriteValueARM64_OpCondSelect_0(v)
   478  	case OpConst16:
   479  		return rewriteValueARM64_OpConst16_0(v)
   480  	case OpConst32:
   481  		return rewriteValueARM64_OpConst32_0(v)
   482  	case OpConst32F:
   483  		return rewriteValueARM64_OpConst32F_0(v)
   484  	case OpConst64:
   485  		return rewriteValueARM64_OpConst64_0(v)
   486  	case OpConst64F:
   487  		return rewriteValueARM64_OpConst64F_0(v)
   488  	case OpConst8:
   489  		return rewriteValueARM64_OpConst8_0(v)
   490  	case OpConstBool:
   491  		return rewriteValueARM64_OpConstBool_0(v)
   492  	case OpConstNil:
   493  		return rewriteValueARM64_OpConstNil_0(v)
   494  	case OpCtz16:
   495  		return rewriteValueARM64_OpCtz16_0(v)
   496  	case OpCtz16NonZero:
   497  		return rewriteValueARM64_OpCtz16NonZero_0(v)
   498  	case OpCtz32:
   499  		return rewriteValueARM64_OpCtz32_0(v)
   500  	case OpCtz32NonZero:
   501  		return rewriteValueARM64_OpCtz32NonZero_0(v)
   502  	case OpCtz64:
   503  		return rewriteValueARM64_OpCtz64_0(v)
   504  	case OpCtz64NonZero:
   505  		return rewriteValueARM64_OpCtz64NonZero_0(v)
   506  	case OpCtz8:
   507  		return rewriteValueARM64_OpCtz8_0(v)
   508  	case OpCtz8NonZero:
   509  		return rewriteValueARM64_OpCtz8NonZero_0(v)
   510  	case OpCvt32Fto32:
   511  		return rewriteValueARM64_OpCvt32Fto32_0(v)
   512  	case OpCvt32Fto32U:
   513  		return rewriteValueARM64_OpCvt32Fto32U_0(v)
   514  	case OpCvt32Fto64:
   515  		return rewriteValueARM64_OpCvt32Fto64_0(v)
   516  	case OpCvt32Fto64F:
   517  		return rewriteValueARM64_OpCvt32Fto64F_0(v)
   518  	case OpCvt32Fto64U:
   519  		return rewriteValueARM64_OpCvt32Fto64U_0(v)
   520  	case OpCvt32Uto32F:
   521  		return rewriteValueARM64_OpCvt32Uto32F_0(v)
   522  	case OpCvt32Uto64F:
   523  		return rewriteValueARM64_OpCvt32Uto64F_0(v)
   524  	case OpCvt32to32F:
   525  		return rewriteValueARM64_OpCvt32to32F_0(v)
   526  	case OpCvt32to64F:
   527  		return rewriteValueARM64_OpCvt32to64F_0(v)
   528  	case OpCvt64Fto32:
   529  		return rewriteValueARM64_OpCvt64Fto32_0(v)
   530  	case OpCvt64Fto32F:
   531  		return rewriteValueARM64_OpCvt64Fto32F_0(v)
   532  	case OpCvt64Fto32U:
   533  		return rewriteValueARM64_OpCvt64Fto32U_0(v)
   534  	case OpCvt64Fto64:
   535  		return rewriteValueARM64_OpCvt64Fto64_0(v)
   536  	case OpCvt64Fto64U:
   537  		return rewriteValueARM64_OpCvt64Fto64U_0(v)
   538  	case OpCvt64Uto32F:
   539  		return rewriteValueARM64_OpCvt64Uto32F_0(v)
   540  	case OpCvt64Uto64F:
   541  		return rewriteValueARM64_OpCvt64Uto64F_0(v)
   542  	case OpCvt64to32F:
   543  		return rewriteValueARM64_OpCvt64to32F_0(v)
   544  	case OpCvt64to64F:
   545  		return rewriteValueARM64_OpCvt64to64F_0(v)
   546  	case OpDiv16:
   547  		return rewriteValueARM64_OpDiv16_0(v)
   548  	case OpDiv16u:
   549  		return rewriteValueARM64_OpDiv16u_0(v)
   550  	case OpDiv32:
   551  		return rewriteValueARM64_OpDiv32_0(v)
   552  	case OpDiv32F:
   553  		return rewriteValueARM64_OpDiv32F_0(v)
   554  	case OpDiv32u:
   555  		return rewriteValueARM64_OpDiv32u_0(v)
   556  	case OpDiv64:
   557  		return rewriteValueARM64_OpDiv64_0(v)
   558  	case OpDiv64F:
   559  		return rewriteValueARM64_OpDiv64F_0(v)
   560  	case OpDiv64u:
   561  		return rewriteValueARM64_OpDiv64u_0(v)
   562  	case OpDiv8:
   563  		return rewriteValueARM64_OpDiv8_0(v)
   564  	case OpDiv8u:
   565  		return rewriteValueARM64_OpDiv8u_0(v)
   566  	case OpEq16:
   567  		return rewriteValueARM64_OpEq16_0(v)
   568  	case OpEq32:
   569  		return rewriteValueARM64_OpEq32_0(v)
   570  	case OpEq32F:
   571  		return rewriteValueARM64_OpEq32F_0(v)
   572  	case OpEq64:
   573  		return rewriteValueARM64_OpEq64_0(v)
   574  	case OpEq64F:
   575  		return rewriteValueARM64_OpEq64F_0(v)
   576  	case OpEq8:
   577  		return rewriteValueARM64_OpEq8_0(v)
   578  	case OpEqB:
   579  		return rewriteValueARM64_OpEqB_0(v)
   580  	case OpEqPtr:
   581  		return rewriteValueARM64_OpEqPtr_0(v)
   582  	case OpFloor:
   583  		return rewriteValueARM64_OpFloor_0(v)
   584  	case OpGeq16:
   585  		return rewriteValueARM64_OpGeq16_0(v)
   586  	case OpGeq16U:
   587  		return rewriteValueARM64_OpGeq16U_0(v)
   588  	case OpGeq32:
   589  		return rewriteValueARM64_OpGeq32_0(v)
   590  	case OpGeq32F:
   591  		return rewriteValueARM64_OpGeq32F_0(v)
   592  	case OpGeq32U:
   593  		return rewriteValueARM64_OpGeq32U_0(v)
   594  	case OpGeq64:
   595  		return rewriteValueARM64_OpGeq64_0(v)
   596  	case OpGeq64F:
   597  		return rewriteValueARM64_OpGeq64F_0(v)
   598  	case OpGeq64U:
   599  		return rewriteValueARM64_OpGeq64U_0(v)
   600  	case OpGeq8:
   601  		return rewriteValueARM64_OpGeq8_0(v)
   602  	case OpGeq8U:
   603  		return rewriteValueARM64_OpGeq8U_0(v)
   604  	case OpGetCallerPC:
   605  		return rewriteValueARM64_OpGetCallerPC_0(v)
   606  	case OpGetCallerSP:
   607  		return rewriteValueARM64_OpGetCallerSP_0(v)
   608  	case OpGetClosurePtr:
   609  		return rewriteValueARM64_OpGetClosurePtr_0(v)
   610  	case OpGreater16:
   611  		return rewriteValueARM64_OpGreater16_0(v)
   612  	case OpGreater16U:
   613  		return rewriteValueARM64_OpGreater16U_0(v)
   614  	case OpGreater32:
   615  		return rewriteValueARM64_OpGreater32_0(v)
   616  	case OpGreater32F:
   617  		return rewriteValueARM64_OpGreater32F_0(v)
   618  	case OpGreater32U:
   619  		return rewriteValueARM64_OpGreater32U_0(v)
   620  	case OpGreater64:
   621  		return rewriteValueARM64_OpGreater64_0(v)
   622  	case OpGreater64F:
   623  		return rewriteValueARM64_OpGreater64F_0(v)
   624  	case OpGreater64U:
   625  		return rewriteValueARM64_OpGreater64U_0(v)
   626  	case OpGreater8:
   627  		return rewriteValueARM64_OpGreater8_0(v)
   628  	case OpGreater8U:
   629  		return rewriteValueARM64_OpGreater8U_0(v)
   630  	case OpHmul32:
   631  		return rewriteValueARM64_OpHmul32_0(v)
   632  	case OpHmul32u:
   633  		return rewriteValueARM64_OpHmul32u_0(v)
   634  	case OpHmul64:
   635  		return rewriteValueARM64_OpHmul64_0(v)
   636  	case OpHmul64u:
   637  		return rewriteValueARM64_OpHmul64u_0(v)
   638  	case OpInterCall:
   639  		return rewriteValueARM64_OpInterCall_0(v)
   640  	case OpIsInBounds:
   641  		return rewriteValueARM64_OpIsInBounds_0(v)
   642  	case OpIsNonNil:
   643  		return rewriteValueARM64_OpIsNonNil_0(v)
   644  	case OpIsSliceInBounds:
   645  		return rewriteValueARM64_OpIsSliceInBounds_0(v)
   646  	case OpLeq16:
   647  		return rewriteValueARM64_OpLeq16_0(v)
   648  	case OpLeq16U:
   649  		return rewriteValueARM64_OpLeq16U_0(v)
   650  	case OpLeq32:
   651  		return rewriteValueARM64_OpLeq32_0(v)
   652  	case OpLeq32F:
   653  		return rewriteValueARM64_OpLeq32F_0(v)
   654  	case OpLeq32U:
   655  		return rewriteValueARM64_OpLeq32U_0(v)
   656  	case OpLeq64:
   657  		return rewriteValueARM64_OpLeq64_0(v)
   658  	case OpLeq64F:
   659  		return rewriteValueARM64_OpLeq64F_0(v)
   660  	case OpLeq64U:
   661  		return rewriteValueARM64_OpLeq64U_0(v)
   662  	case OpLeq8:
   663  		return rewriteValueARM64_OpLeq8_0(v)
   664  	case OpLeq8U:
   665  		return rewriteValueARM64_OpLeq8U_0(v)
   666  	case OpLess16:
   667  		return rewriteValueARM64_OpLess16_0(v)
   668  	case OpLess16U:
   669  		return rewriteValueARM64_OpLess16U_0(v)
   670  	case OpLess32:
   671  		return rewriteValueARM64_OpLess32_0(v)
   672  	case OpLess32F:
   673  		return rewriteValueARM64_OpLess32F_0(v)
   674  	case OpLess32U:
   675  		return rewriteValueARM64_OpLess32U_0(v)
   676  	case OpLess64:
   677  		return rewriteValueARM64_OpLess64_0(v)
   678  	case OpLess64F:
   679  		return rewriteValueARM64_OpLess64F_0(v)
   680  	case OpLess64U:
   681  		return rewriteValueARM64_OpLess64U_0(v)
   682  	case OpLess8:
   683  		return rewriteValueARM64_OpLess8_0(v)
   684  	case OpLess8U:
   685  		return rewriteValueARM64_OpLess8U_0(v)
   686  	case OpLoad:
   687  		return rewriteValueARM64_OpLoad_0(v)
   688  	case OpLocalAddr:
   689  		return rewriteValueARM64_OpLocalAddr_0(v)
   690  	case OpLsh16x16:
   691  		return rewriteValueARM64_OpLsh16x16_0(v)
   692  	case OpLsh16x32:
   693  		return rewriteValueARM64_OpLsh16x32_0(v)
   694  	case OpLsh16x64:
   695  		return rewriteValueARM64_OpLsh16x64_0(v)
   696  	case OpLsh16x8:
   697  		return rewriteValueARM64_OpLsh16x8_0(v)
   698  	case OpLsh32x16:
   699  		return rewriteValueARM64_OpLsh32x16_0(v)
   700  	case OpLsh32x32:
   701  		return rewriteValueARM64_OpLsh32x32_0(v)
   702  	case OpLsh32x64:
   703  		return rewriteValueARM64_OpLsh32x64_0(v)
   704  	case OpLsh32x8:
   705  		return rewriteValueARM64_OpLsh32x8_0(v)
   706  	case OpLsh64x16:
   707  		return rewriteValueARM64_OpLsh64x16_0(v)
   708  	case OpLsh64x32:
   709  		return rewriteValueARM64_OpLsh64x32_0(v)
   710  	case OpLsh64x64:
   711  		return rewriteValueARM64_OpLsh64x64_0(v)
   712  	case OpLsh64x8:
   713  		return rewriteValueARM64_OpLsh64x8_0(v)
   714  	case OpLsh8x16:
   715  		return rewriteValueARM64_OpLsh8x16_0(v)
   716  	case OpLsh8x32:
   717  		return rewriteValueARM64_OpLsh8x32_0(v)
   718  	case OpLsh8x64:
   719  		return rewriteValueARM64_OpLsh8x64_0(v)
   720  	case OpLsh8x8:
   721  		return rewriteValueARM64_OpLsh8x8_0(v)
   722  	case OpMod16:
   723  		return rewriteValueARM64_OpMod16_0(v)
   724  	case OpMod16u:
   725  		return rewriteValueARM64_OpMod16u_0(v)
   726  	case OpMod32:
   727  		return rewriteValueARM64_OpMod32_0(v)
   728  	case OpMod32u:
   729  		return rewriteValueARM64_OpMod32u_0(v)
   730  	case OpMod64:
   731  		return rewriteValueARM64_OpMod64_0(v)
   732  	case OpMod64u:
   733  		return rewriteValueARM64_OpMod64u_0(v)
   734  	case OpMod8:
   735  		return rewriteValueARM64_OpMod8_0(v)
   736  	case OpMod8u:
   737  		return rewriteValueARM64_OpMod8u_0(v)
   738  	case OpMove:
   739  		return rewriteValueARM64_OpMove_0(v) || rewriteValueARM64_OpMove_10(v)
   740  	case OpMul16:
   741  		return rewriteValueARM64_OpMul16_0(v)
   742  	case OpMul32:
   743  		return rewriteValueARM64_OpMul32_0(v)
   744  	case OpMul32F:
   745  		return rewriteValueARM64_OpMul32F_0(v)
   746  	case OpMul64:
   747  		return rewriteValueARM64_OpMul64_0(v)
   748  	case OpMul64F:
   749  		return rewriteValueARM64_OpMul64F_0(v)
   750  	case OpMul64uhilo:
   751  		return rewriteValueARM64_OpMul64uhilo_0(v)
   752  	case OpMul8:
   753  		return rewriteValueARM64_OpMul8_0(v)
   754  	case OpNeg16:
   755  		return rewriteValueARM64_OpNeg16_0(v)
   756  	case OpNeg32:
   757  		return rewriteValueARM64_OpNeg32_0(v)
   758  	case OpNeg32F:
   759  		return rewriteValueARM64_OpNeg32F_0(v)
   760  	case OpNeg64:
   761  		return rewriteValueARM64_OpNeg64_0(v)
   762  	case OpNeg64F:
   763  		return rewriteValueARM64_OpNeg64F_0(v)
   764  	case OpNeg8:
   765  		return rewriteValueARM64_OpNeg8_0(v)
   766  	case OpNeq16:
   767  		return rewriteValueARM64_OpNeq16_0(v)
   768  	case OpNeq32:
   769  		return rewriteValueARM64_OpNeq32_0(v)
   770  	case OpNeq32F:
   771  		return rewriteValueARM64_OpNeq32F_0(v)
   772  	case OpNeq64:
   773  		return rewriteValueARM64_OpNeq64_0(v)
   774  	case OpNeq64F:
   775  		return rewriteValueARM64_OpNeq64F_0(v)
   776  	case OpNeq8:
   777  		return rewriteValueARM64_OpNeq8_0(v)
   778  	case OpNeqB:
   779  		return rewriteValueARM64_OpNeqB_0(v)
   780  	case OpNeqPtr:
   781  		return rewriteValueARM64_OpNeqPtr_0(v)
   782  	case OpNilCheck:
   783  		return rewriteValueARM64_OpNilCheck_0(v)
   784  	case OpNot:
   785  		return rewriteValueARM64_OpNot_0(v)
   786  	case OpOffPtr:
   787  		return rewriteValueARM64_OpOffPtr_0(v)
   788  	case OpOr16:
   789  		return rewriteValueARM64_OpOr16_0(v)
   790  	case OpOr32:
   791  		return rewriteValueARM64_OpOr32_0(v)
   792  	case OpOr64:
   793  		return rewriteValueARM64_OpOr64_0(v)
   794  	case OpOr8:
   795  		return rewriteValueARM64_OpOr8_0(v)
   796  	case OpOrB:
   797  		return rewriteValueARM64_OpOrB_0(v)
   798  	case OpPanicBounds:
   799  		return rewriteValueARM64_OpPanicBounds_0(v)
   800  	case OpPopCount16:
   801  		return rewriteValueARM64_OpPopCount16_0(v)
   802  	case OpPopCount32:
   803  		return rewriteValueARM64_OpPopCount32_0(v)
   804  	case OpPopCount64:
   805  		return rewriteValueARM64_OpPopCount64_0(v)
   806  	case OpRotateLeft16:
   807  		return rewriteValueARM64_OpRotateLeft16_0(v)
   808  	case OpRotateLeft32:
   809  		return rewriteValueARM64_OpRotateLeft32_0(v)
   810  	case OpRotateLeft64:
   811  		return rewriteValueARM64_OpRotateLeft64_0(v)
   812  	case OpRotateLeft8:
   813  		return rewriteValueARM64_OpRotateLeft8_0(v)
   814  	case OpRound:
   815  		return rewriteValueARM64_OpRound_0(v)
   816  	case OpRound32F:
   817  		return rewriteValueARM64_OpRound32F_0(v)
   818  	case OpRound64F:
   819  		return rewriteValueARM64_OpRound64F_0(v)
   820  	case OpRoundToEven:
   821  		return rewriteValueARM64_OpRoundToEven_0(v)
   822  	case OpRsh16Ux16:
   823  		return rewriteValueARM64_OpRsh16Ux16_0(v)
   824  	case OpRsh16Ux32:
   825  		return rewriteValueARM64_OpRsh16Ux32_0(v)
   826  	case OpRsh16Ux64:
   827  		return rewriteValueARM64_OpRsh16Ux64_0(v)
   828  	case OpRsh16Ux8:
   829  		return rewriteValueARM64_OpRsh16Ux8_0(v)
   830  	case OpRsh16x16:
   831  		return rewriteValueARM64_OpRsh16x16_0(v)
   832  	case OpRsh16x32:
   833  		return rewriteValueARM64_OpRsh16x32_0(v)
   834  	case OpRsh16x64:
   835  		return rewriteValueARM64_OpRsh16x64_0(v)
   836  	case OpRsh16x8:
   837  		return rewriteValueARM64_OpRsh16x8_0(v)
   838  	case OpRsh32Ux16:
   839  		return rewriteValueARM64_OpRsh32Ux16_0(v)
   840  	case OpRsh32Ux32:
   841  		return rewriteValueARM64_OpRsh32Ux32_0(v)
   842  	case OpRsh32Ux64:
   843  		return rewriteValueARM64_OpRsh32Ux64_0(v)
   844  	case OpRsh32Ux8:
   845  		return rewriteValueARM64_OpRsh32Ux8_0(v)
   846  	case OpRsh32x16:
   847  		return rewriteValueARM64_OpRsh32x16_0(v)
   848  	case OpRsh32x32:
   849  		return rewriteValueARM64_OpRsh32x32_0(v)
   850  	case OpRsh32x64:
   851  		return rewriteValueARM64_OpRsh32x64_0(v)
   852  	case OpRsh32x8:
   853  		return rewriteValueARM64_OpRsh32x8_0(v)
   854  	case OpRsh64Ux16:
   855  		return rewriteValueARM64_OpRsh64Ux16_0(v)
   856  	case OpRsh64Ux32:
   857  		return rewriteValueARM64_OpRsh64Ux32_0(v)
   858  	case OpRsh64Ux64:
   859  		return rewriteValueARM64_OpRsh64Ux64_0(v)
   860  	case OpRsh64Ux8:
   861  		return rewriteValueARM64_OpRsh64Ux8_0(v)
   862  	case OpRsh64x16:
   863  		return rewriteValueARM64_OpRsh64x16_0(v)
   864  	case OpRsh64x32:
   865  		return rewriteValueARM64_OpRsh64x32_0(v)
   866  	case OpRsh64x64:
   867  		return rewriteValueARM64_OpRsh64x64_0(v)
   868  	case OpRsh64x8:
   869  		return rewriteValueARM64_OpRsh64x8_0(v)
   870  	case OpRsh8Ux16:
   871  		return rewriteValueARM64_OpRsh8Ux16_0(v)
   872  	case OpRsh8Ux32:
   873  		return rewriteValueARM64_OpRsh8Ux32_0(v)
   874  	case OpRsh8Ux64:
   875  		return rewriteValueARM64_OpRsh8Ux64_0(v)
   876  	case OpRsh8Ux8:
   877  		return rewriteValueARM64_OpRsh8Ux8_0(v)
   878  	case OpRsh8x16:
   879  		return rewriteValueARM64_OpRsh8x16_0(v)
   880  	case OpRsh8x32:
   881  		return rewriteValueARM64_OpRsh8x32_0(v)
   882  	case OpRsh8x64:
   883  		return rewriteValueARM64_OpRsh8x64_0(v)
   884  	case OpRsh8x8:
   885  		return rewriteValueARM64_OpRsh8x8_0(v)
   886  	case OpSelect0:
   887  		return rewriteValueARM64_OpSelect0_0(v)
   888  	case OpSelect1:
   889  		return rewriteValueARM64_OpSelect1_0(v)
   890  	case OpSignExt16to32:
   891  		return rewriteValueARM64_OpSignExt16to32_0(v)
   892  	case OpSignExt16to64:
   893  		return rewriteValueARM64_OpSignExt16to64_0(v)
   894  	case OpSignExt32to64:
   895  		return rewriteValueARM64_OpSignExt32to64_0(v)
   896  	case OpSignExt8to16:
   897  		return rewriteValueARM64_OpSignExt8to16_0(v)
   898  	case OpSignExt8to32:
   899  		return rewriteValueARM64_OpSignExt8to32_0(v)
   900  	case OpSignExt8to64:
   901  		return rewriteValueARM64_OpSignExt8to64_0(v)
   902  	case OpSlicemask:
   903  		return rewriteValueARM64_OpSlicemask_0(v)
   904  	case OpSqrt:
   905  		return rewriteValueARM64_OpSqrt_0(v)
   906  	case OpStaticCall:
   907  		return rewriteValueARM64_OpStaticCall_0(v)
   908  	case OpStore:
   909  		return rewriteValueARM64_OpStore_0(v)
   910  	case OpSub16:
   911  		return rewriteValueARM64_OpSub16_0(v)
   912  	case OpSub32:
   913  		return rewriteValueARM64_OpSub32_0(v)
   914  	case OpSub32F:
   915  		return rewriteValueARM64_OpSub32F_0(v)
   916  	case OpSub64:
   917  		return rewriteValueARM64_OpSub64_0(v)
   918  	case OpSub64F:
   919  		return rewriteValueARM64_OpSub64F_0(v)
   920  	case OpSub8:
   921  		return rewriteValueARM64_OpSub8_0(v)
   922  	case OpSubPtr:
   923  		return rewriteValueARM64_OpSubPtr_0(v)
   924  	case OpTrunc:
   925  		return rewriteValueARM64_OpTrunc_0(v)
   926  	case OpTrunc16to8:
   927  		return rewriteValueARM64_OpTrunc16to8_0(v)
   928  	case OpTrunc32to16:
   929  		return rewriteValueARM64_OpTrunc32to16_0(v)
   930  	case OpTrunc32to8:
   931  		return rewriteValueARM64_OpTrunc32to8_0(v)
   932  	case OpTrunc64to16:
   933  		return rewriteValueARM64_OpTrunc64to16_0(v)
   934  	case OpTrunc64to32:
   935  		return rewriteValueARM64_OpTrunc64to32_0(v)
   936  	case OpTrunc64to8:
   937  		return rewriteValueARM64_OpTrunc64to8_0(v)
   938  	case OpWB:
   939  		return rewriteValueARM64_OpWB_0(v)
   940  	case OpXor16:
   941  		return rewriteValueARM64_OpXor16_0(v)
   942  	case OpXor32:
   943  		return rewriteValueARM64_OpXor32_0(v)
   944  	case OpXor64:
   945  		return rewriteValueARM64_OpXor64_0(v)
   946  	case OpXor8:
   947  		return rewriteValueARM64_OpXor8_0(v)
   948  	case OpZero:
   949  		return rewriteValueARM64_OpZero_0(v) || rewriteValueARM64_OpZero_10(v) || rewriteValueARM64_OpZero_20(v)
   950  	case OpZeroExt16to32:
   951  		return rewriteValueARM64_OpZeroExt16to32_0(v)
   952  	case OpZeroExt16to64:
   953  		return rewriteValueARM64_OpZeroExt16to64_0(v)
   954  	case OpZeroExt32to64:
   955  		return rewriteValueARM64_OpZeroExt32to64_0(v)
   956  	case OpZeroExt8to16:
   957  		return rewriteValueARM64_OpZeroExt8to16_0(v)
   958  	case OpZeroExt8to32:
   959  		return rewriteValueARM64_OpZeroExt8to32_0(v)
   960  	case OpZeroExt8to64:
   961  		return rewriteValueARM64_OpZeroExt8to64_0(v)
   962  	}
   963  	return false
   964  }
   965  func rewriteValueARM64_OpARM64ADCSflags_0(v *Value) bool {
   966  	b := v.Block
   967  	typ := &b.Func.Config.Types
   968  	// match: (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] (ADCzerocarry <typ.UInt64> c))))
   969  	// cond:
   970  	// result: (ADCSflags x y c)
   971  	for {
   972  		_ = v.Args[2]
   973  		x := v.Args[0]
   974  		y := v.Args[1]
   975  		v_2 := v.Args[2]
   976  		if v_2.Op != OpSelect1 {
   977  			break
   978  		}
   979  		if v_2.Type != types.TypeFlags {
   980  			break
   981  		}
   982  		v_2_0 := v_2.Args[0]
   983  		if v_2_0.Op != OpARM64ADDSconstflags {
   984  			break
   985  		}
   986  		if v_2_0.AuxInt != -1 {
   987  			break
   988  		}
   989  		v_2_0_0 := v_2_0.Args[0]
   990  		if v_2_0_0.Op != OpARM64ADCzerocarry {
   991  			break
   992  		}
   993  		if v_2_0_0.Type != typ.UInt64 {
   994  			break
   995  		}
   996  		c := v_2_0_0.Args[0]
   997  		v.reset(OpARM64ADCSflags)
   998  		v.AddArg(x)
   999  		v.AddArg(y)
  1000  		v.AddArg(c)
  1001  		return true
  1002  	}
  1003  	// match: (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] (MOVDconst [0]))))
  1004  	// cond:
  1005  	// result: (ADDSflags x y)
  1006  	for {
  1007  		_ = v.Args[2]
  1008  		x := v.Args[0]
  1009  		y := v.Args[1]
  1010  		v_2 := v.Args[2]
  1011  		if v_2.Op != OpSelect1 {
  1012  			break
  1013  		}
  1014  		if v_2.Type != types.TypeFlags {
  1015  			break
  1016  		}
  1017  		v_2_0 := v_2.Args[0]
  1018  		if v_2_0.Op != OpARM64ADDSconstflags {
  1019  			break
  1020  		}
  1021  		if v_2_0.AuxInt != -1 {
  1022  			break
  1023  		}
  1024  		v_2_0_0 := v_2_0.Args[0]
  1025  		if v_2_0_0.Op != OpARM64MOVDconst {
  1026  			break
  1027  		}
  1028  		if v_2_0_0.AuxInt != 0 {
  1029  			break
  1030  		}
  1031  		v.reset(OpARM64ADDSflags)
  1032  		v.AddArg(x)
  1033  		v.AddArg(y)
  1034  		return true
  1035  	}
  1036  	return false
  1037  }
  1038  func rewriteValueARM64_OpARM64ADD_0(v *Value) bool {
  1039  	// match: (ADD x (MOVDconst [c]))
  1040  	// cond:
  1041  	// result: (ADDconst [c] x)
  1042  	for {
  1043  		_ = v.Args[1]
  1044  		x := v.Args[0]
  1045  		v_1 := v.Args[1]
  1046  		if v_1.Op != OpARM64MOVDconst {
  1047  			break
  1048  		}
  1049  		c := v_1.AuxInt
  1050  		v.reset(OpARM64ADDconst)
  1051  		v.AuxInt = c
  1052  		v.AddArg(x)
  1053  		return true
  1054  	}
  1055  	// match: (ADD (MOVDconst [c]) x)
  1056  	// cond:
  1057  	// result: (ADDconst [c] x)
  1058  	for {
  1059  		x := v.Args[1]
  1060  		v_0 := v.Args[0]
  1061  		if v_0.Op != OpARM64MOVDconst {
  1062  			break
  1063  		}
  1064  		c := v_0.AuxInt
  1065  		v.reset(OpARM64ADDconst)
  1066  		v.AuxInt = c
  1067  		v.AddArg(x)
  1068  		return true
  1069  	}
  1070  	// match: (ADD a l:(MUL x y))
  1071  	// cond: l.Uses==1 && clobber(l)
  1072  	// result: (MADD a x y)
  1073  	for {
  1074  		_ = v.Args[1]
  1075  		a := v.Args[0]
  1076  		l := v.Args[1]
  1077  		if l.Op != OpARM64MUL {
  1078  			break
  1079  		}
  1080  		y := l.Args[1]
  1081  		x := l.Args[0]
  1082  		if !(l.Uses == 1 && clobber(l)) {
  1083  			break
  1084  		}
  1085  		v.reset(OpARM64MADD)
  1086  		v.AddArg(a)
  1087  		v.AddArg(x)
  1088  		v.AddArg(y)
  1089  		return true
  1090  	}
  1091  	// match: (ADD l:(MUL x y) a)
  1092  	// cond: l.Uses==1 && clobber(l)
  1093  	// result: (MADD a x y)
  1094  	for {
  1095  		a := v.Args[1]
  1096  		l := v.Args[0]
  1097  		if l.Op != OpARM64MUL {
  1098  			break
  1099  		}
  1100  		y := l.Args[1]
  1101  		x := l.Args[0]
  1102  		if !(l.Uses == 1 && clobber(l)) {
  1103  			break
  1104  		}
  1105  		v.reset(OpARM64MADD)
  1106  		v.AddArg(a)
  1107  		v.AddArg(x)
  1108  		v.AddArg(y)
  1109  		return true
  1110  	}
  1111  	// match: (ADD a l:(MNEG x y))
  1112  	// cond: l.Uses==1 && clobber(l)
  1113  	// result: (MSUB a x y)
  1114  	for {
  1115  		_ = v.Args[1]
  1116  		a := v.Args[0]
  1117  		l := v.Args[1]
  1118  		if l.Op != OpARM64MNEG {
  1119  			break
  1120  		}
  1121  		y := l.Args[1]
  1122  		x := l.Args[0]
  1123  		if !(l.Uses == 1 && clobber(l)) {
  1124  			break
  1125  		}
  1126  		v.reset(OpARM64MSUB)
  1127  		v.AddArg(a)
  1128  		v.AddArg(x)
  1129  		v.AddArg(y)
  1130  		return true
  1131  	}
  1132  	// match: (ADD l:(MNEG x y) a)
  1133  	// cond: l.Uses==1 && clobber(l)
  1134  	// result: (MSUB a x y)
  1135  	for {
  1136  		a := v.Args[1]
  1137  		l := v.Args[0]
  1138  		if l.Op != OpARM64MNEG {
  1139  			break
  1140  		}
  1141  		y := l.Args[1]
  1142  		x := l.Args[0]
  1143  		if !(l.Uses == 1 && clobber(l)) {
  1144  			break
  1145  		}
  1146  		v.reset(OpARM64MSUB)
  1147  		v.AddArg(a)
  1148  		v.AddArg(x)
  1149  		v.AddArg(y)
  1150  		return true
  1151  	}
  1152  	// match: (ADD a l:(MULW x y))
  1153  	// cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l)
  1154  	// result: (MADDW a x y)
  1155  	for {
  1156  		_ = v.Args[1]
  1157  		a := v.Args[0]
  1158  		l := v.Args[1]
  1159  		if l.Op != OpARM64MULW {
  1160  			break
  1161  		}
  1162  		y := l.Args[1]
  1163  		x := l.Args[0]
  1164  		if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) {
  1165  			break
  1166  		}
  1167  		v.reset(OpARM64MADDW)
  1168  		v.AddArg(a)
  1169  		v.AddArg(x)
  1170  		v.AddArg(y)
  1171  		return true
  1172  	}
  1173  	// match: (ADD l:(MULW x y) a)
  1174  	// cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l)
  1175  	// result: (MADDW a x y)
  1176  	for {
  1177  		a := v.Args[1]
  1178  		l := v.Args[0]
  1179  		if l.Op != OpARM64MULW {
  1180  			break
  1181  		}
  1182  		y := l.Args[1]
  1183  		x := l.Args[0]
  1184  		if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) {
  1185  			break
  1186  		}
  1187  		v.reset(OpARM64MADDW)
  1188  		v.AddArg(a)
  1189  		v.AddArg(x)
  1190  		v.AddArg(y)
  1191  		return true
  1192  	}
  1193  	// match: (ADD a l:(MNEGW x y))
  1194  	// cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l)
  1195  	// result: (MSUBW a x y)
  1196  	for {
  1197  		_ = v.Args[1]
  1198  		a := v.Args[0]
  1199  		l := v.Args[1]
  1200  		if l.Op != OpARM64MNEGW {
  1201  			break
  1202  		}
  1203  		y := l.Args[1]
  1204  		x := l.Args[0]
  1205  		if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) {
  1206  			break
  1207  		}
  1208  		v.reset(OpARM64MSUBW)
  1209  		v.AddArg(a)
  1210  		v.AddArg(x)
  1211  		v.AddArg(y)
  1212  		return true
  1213  	}
  1214  	// match: (ADD l:(MNEGW x y) a)
  1215  	// cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l)
  1216  	// result: (MSUBW a x y)
  1217  	for {
  1218  		a := v.Args[1]
  1219  		l := v.Args[0]
  1220  		if l.Op != OpARM64MNEGW {
  1221  			break
  1222  		}
  1223  		y := l.Args[1]
  1224  		x := l.Args[0]
  1225  		if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) {
  1226  			break
  1227  		}
  1228  		v.reset(OpARM64MSUBW)
  1229  		v.AddArg(a)
  1230  		v.AddArg(x)
  1231  		v.AddArg(y)
  1232  		return true
  1233  	}
  1234  	return false
  1235  }
  1236  func rewriteValueARM64_OpARM64ADD_10(v *Value) bool {
  1237  	b := v.Block
  1238  	typ := &b.Func.Config.Types
  1239  	// match: (ADD x (NEG y))
  1240  	// cond:
  1241  	// result: (SUB x y)
  1242  	for {
  1243  		_ = v.Args[1]
  1244  		x := v.Args[0]
  1245  		v_1 := v.Args[1]
  1246  		if v_1.Op != OpARM64NEG {
  1247  			break
  1248  		}
  1249  		y := v_1.Args[0]
  1250  		v.reset(OpARM64SUB)
  1251  		v.AddArg(x)
  1252  		v.AddArg(y)
  1253  		return true
  1254  	}
  1255  	// match: (ADD (NEG y) x)
  1256  	// cond:
  1257  	// result: (SUB x y)
  1258  	for {
  1259  		x := v.Args[1]
  1260  		v_0 := v.Args[0]
  1261  		if v_0.Op != OpARM64NEG {
  1262  			break
  1263  		}
  1264  		y := v_0.Args[0]
  1265  		v.reset(OpARM64SUB)
  1266  		v.AddArg(x)
  1267  		v.AddArg(y)
  1268  		return true
  1269  	}
  1270  	// match: (ADD x0 x1:(SLLconst [c] y))
  1271  	// cond: clobberIfDead(x1)
  1272  	// result: (ADDshiftLL x0 y [c])
  1273  	for {
  1274  		_ = v.Args[1]
  1275  		x0 := v.Args[0]
  1276  		x1 := v.Args[1]
  1277  		if x1.Op != OpARM64SLLconst {
  1278  			break
  1279  		}
  1280  		c := x1.AuxInt
  1281  		y := x1.Args[0]
  1282  		if !(clobberIfDead(x1)) {
  1283  			break
  1284  		}
  1285  		v.reset(OpARM64ADDshiftLL)
  1286  		v.AuxInt = c
  1287  		v.AddArg(x0)
  1288  		v.AddArg(y)
  1289  		return true
  1290  	}
  1291  	// match: (ADD x1:(SLLconst [c] y) x0)
  1292  	// cond: clobberIfDead(x1)
  1293  	// result: (ADDshiftLL x0 y [c])
  1294  	for {
  1295  		x0 := v.Args[1]
  1296  		x1 := v.Args[0]
  1297  		if x1.Op != OpARM64SLLconst {
  1298  			break
  1299  		}
  1300  		c := x1.AuxInt
  1301  		y := x1.Args[0]
  1302  		if !(clobberIfDead(x1)) {
  1303  			break
  1304  		}
  1305  		v.reset(OpARM64ADDshiftLL)
  1306  		v.AuxInt = c
  1307  		v.AddArg(x0)
  1308  		v.AddArg(y)
  1309  		return true
  1310  	}
  1311  	// match: (ADD x0 x1:(SRLconst [c] y))
  1312  	// cond: clobberIfDead(x1)
  1313  	// result: (ADDshiftRL x0 y [c])
  1314  	for {
  1315  		_ = v.Args[1]
  1316  		x0 := v.Args[0]
  1317  		x1 := v.Args[1]
  1318  		if x1.Op != OpARM64SRLconst {
  1319  			break
  1320  		}
  1321  		c := x1.AuxInt
  1322  		y := x1.Args[0]
  1323  		if !(clobberIfDead(x1)) {
  1324  			break
  1325  		}
  1326  		v.reset(OpARM64ADDshiftRL)
  1327  		v.AuxInt = c
  1328  		v.AddArg(x0)
  1329  		v.AddArg(y)
  1330  		return true
  1331  	}
  1332  	// match: (ADD x1:(SRLconst [c] y) x0)
  1333  	// cond: clobberIfDead(x1)
  1334  	// result: (ADDshiftRL x0 y [c])
  1335  	for {
  1336  		x0 := v.Args[1]
  1337  		x1 := v.Args[0]
  1338  		if x1.Op != OpARM64SRLconst {
  1339  			break
  1340  		}
  1341  		c := x1.AuxInt
  1342  		y := x1.Args[0]
  1343  		if !(clobberIfDead(x1)) {
  1344  			break
  1345  		}
  1346  		v.reset(OpARM64ADDshiftRL)
  1347  		v.AuxInt = c
  1348  		v.AddArg(x0)
  1349  		v.AddArg(y)
  1350  		return true
  1351  	}
  1352  	// match: (ADD x0 x1:(SRAconst [c] y))
  1353  	// cond: clobberIfDead(x1)
  1354  	// result: (ADDshiftRA x0 y [c])
  1355  	for {
  1356  		_ = v.Args[1]
  1357  		x0 := v.Args[0]
  1358  		x1 := v.Args[1]
  1359  		if x1.Op != OpARM64SRAconst {
  1360  			break
  1361  		}
  1362  		c := x1.AuxInt
  1363  		y := x1.Args[0]
  1364  		if !(clobberIfDead(x1)) {
  1365  			break
  1366  		}
  1367  		v.reset(OpARM64ADDshiftRA)
  1368  		v.AuxInt = c
  1369  		v.AddArg(x0)
  1370  		v.AddArg(y)
  1371  		return true
  1372  	}
  1373  	// match: (ADD x1:(SRAconst [c] y) x0)
  1374  	// cond: clobberIfDead(x1)
  1375  	// result: (ADDshiftRA x0 y [c])
  1376  	for {
  1377  		x0 := v.Args[1]
  1378  		x1 := v.Args[0]
  1379  		if x1.Op != OpARM64SRAconst {
  1380  			break
  1381  		}
  1382  		c := x1.AuxInt
  1383  		y := x1.Args[0]
  1384  		if !(clobberIfDead(x1)) {
  1385  			break
  1386  		}
  1387  		v.reset(OpARM64ADDshiftRA)
  1388  		v.AuxInt = c
  1389  		v.AddArg(x0)
  1390  		v.AddArg(y)
  1391  		return true
  1392  	}
  1393  	// match: (ADD (SLL x (ANDconst <t> [63] y)) (CSEL0 <typ.UInt64> {cc} (SRL <typ.UInt64> x (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y))) (CMPconst [64] (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y)))))
  1394  	// cond: cc.(Op) == OpARM64LessThanU
  1395  	// result: (ROR x (NEG <t> y))
  1396  	for {
  1397  		_ = v.Args[1]
  1398  		v_0 := v.Args[0]
  1399  		if v_0.Op != OpARM64SLL {
  1400  			break
  1401  		}
  1402  		_ = v_0.Args[1]
  1403  		x := v_0.Args[0]
  1404  		v_0_1 := v_0.Args[1]
  1405  		if v_0_1.Op != OpARM64ANDconst {
  1406  			break
  1407  		}
  1408  		t := v_0_1.Type
  1409  		if v_0_1.AuxInt != 63 {
  1410  			break
  1411  		}
  1412  		y := v_0_1.Args[0]
  1413  		v_1 := v.Args[1]
  1414  		if v_1.Op != OpARM64CSEL0 {
  1415  			break
  1416  		}
  1417  		if v_1.Type != typ.UInt64 {
  1418  			break
  1419  		}
  1420  		cc := v_1.Aux
  1421  		_ = v_1.Args[1]
  1422  		v_1_0 := v_1.Args[0]
  1423  		if v_1_0.Op != OpARM64SRL {
  1424  			break
  1425  		}
  1426  		if v_1_0.Type != typ.UInt64 {
  1427  			break
  1428  		}
  1429  		_ = v_1_0.Args[1]
  1430  		if x != v_1_0.Args[0] {
  1431  			break
  1432  		}
  1433  		v_1_0_1 := v_1_0.Args[1]
  1434  		if v_1_0_1.Op != OpARM64SUB {
  1435  			break
  1436  		}
  1437  		if v_1_0_1.Type != t {
  1438  			break
  1439  		}
  1440  		_ = v_1_0_1.Args[1]
  1441  		v_1_0_1_0 := v_1_0_1.Args[0]
  1442  		if v_1_0_1_0.Op != OpARM64MOVDconst {
  1443  			break
  1444  		}
  1445  		if v_1_0_1_0.AuxInt != 64 {
  1446  			break
  1447  		}
  1448  		v_1_0_1_1 := v_1_0_1.Args[1]
  1449  		if v_1_0_1_1.Op != OpARM64ANDconst {
  1450  			break
  1451  		}
  1452  		if v_1_0_1_1.Type != t {
  1453  			break
  1454  		}
  1455  		if v_1_0_1_1.AuxInt != 63 {
  1456  			break
  1457  		}
  1458  		if y != v_1_0_1_1.Args[0] {
  1459  			break
  1460  		}
  1461  		v_1_1 := v_1.Args[1]
  1462  		if v_1_1.Op != OpARM64CMPconst {
  1463  			break
  1464  		}
  1465  		if v_1_1.AuxInt != 64 {
  1466  			break
  1467  		}
  1468  		v_1_1_0 := v_1_1.Args[0]
  1469  		if v_1_1_0.Op != OpARM64SUB {
  1470  			break
  1471  		}
  1472  		if v_1_1_0.Type != t {
  1473  			break
  1474  		}
  1475  		_ = v_1_1_0.Args[1]
  1476  		v_1_1_0_0 := v_1_1_0.Args[0]
  1477  		if v_1_1_0_0.Op != OpARM64MOVDconst {
  1478  			break
  1479  		}
  1480  		if v_1_1_0_0.AuxInt != 64 {
  1481  			break
  1482  		}
  1483  		v_1_1_0_1 := v_1_1_0.Args[1]
  1484  		if v_1_1_0_1.Op != OpARM64ANDconst {
  1485  			break
  1486  		}
  1487  		if v_1_1_0_1.Type != t {
  1488  			break
  1489  		}
  1490  		if v_1_1_0_1.AuxInt != 63 {
  1491  			break
  1492  		}
  1493  		if y != v_1_1_0_1.Args[0] {
  1494  			break
  1495  		}
  1496  		if !(cc.(Op) == OpARM64LessThanU) {
  1497  			break
  1498  		}
  1499  		v.reset(OpARM64ROR)
  1500  		v.AddArg(x)
  1501  		v0 := b.NewValue0(v.Pos, OpARM64NEG, t)
  1502  		v0.AddArg(y)
  1503  		v.AddArg(v0)
  1504  		return true
  1505  	}
  1506  	// match: (ADD (CSEL0 <typ.UInt64> {cc} (SRL <typ.UInt64> x (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y))) (CMPconst [64] (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y)))) (SLL x (ANDconst <t> [63] y)))
  1507  	// cond: cc.(Op) == OpARM64LessThanU
  1508  	// result: (ROR x (NEG <t> y))
  1509  	for {
  1510  		_ = v.Args[1]
  1511  		v_0 := v.Args[0]
  1512  		if v_0.Op != OpARM64CSEL0 {
  1513  			break
  1514  		}
  1515  		if v_0.Type != typ.UInt64 {
  1516  			break
  1517  		}
  1518  		cc := v_0.Aux
  1519  		_ = v_0.Args[1]
  1520  		v_0_0 := v_0.Args[0]
  1521  		if v_0_0.Op != OpARM64SRL {
  1522  			break
  1523  		}
  1524  		if v_0_0.Type != typ.UInt64 {
  1525  			break
  1526  		}
  1527  		_ = v_0_0.Args[1]
  1528  		x := v_0_0.Args[0]
  1529  		v_0_0_1 := v_0_0.Args[1]
  1530  		if v_0_0_1.Op != OpARM64SUB {
  1531  			break
  1532  		}
  1533  		t := v_0_0_1.Type
  1534  		_ = v_0_0_1.Args[1]
  1535  		v_0_0_1_0 := v_0_0_1.Args[0]
  1536  		if v_0_0_1_0.Op != OpARM64MOVDconst {
  1537  			break
  1538  		}
  1539  		if v_0_0_1_0.AuxInt != 64 {
  1540  			break
  1541  		}
  1542  		v_0_0_1_1 := v_0_0_1.Args[1]
  1543  		if v_0_0_1_1.Op != OpARM64ANDconst {
  1544  			break
  1545  		}
  1546  		if v_0_0_1_1.Type != t {
  1547  			break
  1548  		}
  1549  		if v_0_0_1_1.AuxInt != 63 {
  1550  			break
  1551  		}
  1552  		y := v_0_0_1_1.Args[0]
  1553  		v_0_1 := v_0.Args[1]
  1554  		if v_0_1.Op != OpARM64CMPconst {
  1555  			break
  1556  		}
  1557  		if v_0_1.AuxInt != 64 {
  1558  			break
  1559  		}
  1560  		v_0_1_0 := v_0_1.Args[0]
  1561  		if v_0_1_0.Op != OpARM64SUB {
  1562  			break
  1563  		}
  1564  		if v_0_1_0.Type != t {
  1565  			break
  1566  		}
  1567  		_ = v_0_1_0.Args[1]
  1568  		v_0_1_0_0 := v_0_1_0.Args[0]
  1569  		if v_0_1_0_0.Op != OpARM64MOVDconst {
  1570  			break
  1571  		}
  1572  		if v_0_1_0_0.AuxInt != 64 {
  1573  			break
  1574  		}
  1575  		v_0_1_0_1 := v_0_1_0.Args[1]
  1576  		if v_0_1_0_1.Op != OpARM64ANDconst {
  1577  			break
  1578  		}
  1579  		if v_0_1_0_1.Type != t {
  1580  			break
  1581  		}
  1582  		if v_0_1_0_1.AuxInt != 63 {
  1583  			break
  1584  		}
  1585  		if y != v_0_1_0_1.Args[0] {
  1586  			break
  1587  		}
  1588  		v_1 := v.Args[1]
  1589  		if v_1.Op != OpARM64SLL {
  1590  			break
  1591  		}
  1592  		_ = v_1.Args[1]
  1593  		if x != v_1.Args[0] {
  1594  			break
  1595  		}
  1596  		v_1_1 := v_1.Args[1]
  1597  		if v_1_1.Op != OpARM64ANDconst {
  1598  			break
  1599  		}
  1600  		if v_1_1.Type != t {
  1601  			break
  1602  		}
  1603  		if v_1_1.AuxInt != 63 {
  1604  			break
  1605  		}
  1606  		if y != v_1_1.Args[0] {
  1607  			break
  1608  		}
  1609  		if !(cc.(Op) == OpARM64LessThanU) {
  1610  			break
  1611  		}
  1612  		v.reset(OpARM64ROR)
  1613  		v.AddArg(x)
  1614  		v0 := b.NewValue0(v.Pos, OpARM64NEG, t)
  1615  		v0.AddArg(y)
  1616  		v.AddArg(v0)
  1617  		return true
  1618  	}
  1619  	return false
  1620  }
  1621  func rewriteValueARM64_OpARM64ADD_20(v *Value) bool {
  1622  	b := v.Block
  1623  	typ := &b.Func.Config.Types
  1624  	// match: (ADD (SRL <typ.UInt64> x (ANDconst <t> [63] y)) (CSEL0 <typ.UInt64> {cc} (SLL x (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y))) (CMPconst [64] (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y)))))
  1625  	// cond: cc.(Op) == OpARM64LessThanU
  1626  	// result: (ROR x y)
  1627  	for {
  1628  		_ = v.Args[1]
  1629  		v_0 := v.Args[0]
  1630  		if v_0.Op != OpARM64SRL {
  1631  			break
  1632  		}
  1633  		if v_0.Type != typ.UInt64 {
  1634  			break
  1635  		}
  1636  		_ = v_0.Args[1]
  1637  		x := v_0.Args[0]
  1638  		v_0_1 := v_0.Args[1]
  1639  		if v_0_1.Op != OpARM64ANDconst {
  1640  			break
  1641  		}
  1642  		t := v_0_1.Type
  1643  		if v_0_1.AuxInt != 63 {
  1644  			break
  1645  		}
  1646  		y := v_0_1.Args[0]
  1647  		v_1 := v.Args[1]
  1648  		if v_1.Op != OpARM64CSEL0 {
  1649  			break
  1650  		}
  1651  		if v_1.Type != typ.UInt64 {
  1652  			break
  1653  		}
  1654  		cc := v_1.Aux
  1655  		_ = v_1.Args[1]
  1656  		v_1_0 := v_1.Args[0]
  1657  		if v_1_0.Op != OpARM64SLL {
  1658  			break
  1659  		}
  1660  		_ = v_1_0.Args[1]
  1661  		if x != v_1_0.Args[0] {
  1662  			break
  1663  		}
  1664  		v_1_0_1 := v_1_0.Args[1]
  1665  		if v_1_0_1.Op != OpARM64SUB {
  1666  			break
  1667  		}
  1668  		if v_1_0_1.Type != t {
  1669  			break
  1670  		}
  1671  		_ = v_1_0_1.Args[1]
  1672  		v_1_0_1_0 := v_1_0_1.Args[0]
  1673  		if v_1_0_1_0.Op != OpARM64MOVDconst {
  1674  			break
  1675  		}
  1676  		if v_1_0_1_0.AuxInt != 64 {
  1677  			break
  1678  		}
  1679  		v_1_0_1_1 := v_1_0_1.Args[1]
  1680  		if v_1_0_1_1.Op != OpARM64ANDconst {
  1681  			break
  1682  		}
  1683  		if v_1_0_1_1.Type != t {
  1684  			break
  1685  		}
  1686  		if v_1_0_1_1.AuxInt != 63 {
  1687  			break
  1688  		}
  1689  		if y != v_1_0_1_1.Args[0] {
  1690  			break
  1691  		}
  1692  		v_1_1 := v_1.Args[1]
  1693  		if v_1_1.Op != OpARM64CMPconst {
  1694  			break
  1695  		}
  1696  		if v_1_1.AuxInt != 64 {
  1697  			break
  1698  		}
  1699  		v_1_1_0 := v_1_1.Args[0]
  1700  		if v_1_1_0.Op != OpARM64SUB {
  1701  			break
  1702  		}
  1703  		if v_1_1_0.Type != t {
  1704  			break
  1705  		}
  1706  		_ = v_1_1_0.Args[1]
  1707  		v_1_1_0_0 := v_1_1_0.Args[0]
  1708  		if v_1_1_0_0.Op != OpARM64MOVDconst {
  1709  			break
  1710  		}
  1711  		if v_1_1_0_0.AuxInt != 64 {
  1712  			break
  1713  		}
  1714  		v_1_1_0_1 := v_1_1_0.Args[1]
  1715  		if v_1_1_0_1.Op != OpARM64ANDconst {
  1716  			break
  1717  		}
  1718  		if v_1_1_0_1.Type != t {
  1719  			break
  1720  		}
  1721  		if v_1_1_0_1.AuxInt != 63 {
  1722  			break
  1723  		}
  1724  		if y != v_1_1_0_1.Args[0] {
  1725  			break
  1726  		}
  1727  		if !(cc.(Op) == OpARM64LessThanU) {
  1728  			break
  1729  		}
  1730  		v.reset(OpARM64ROR)
  1731  		v.AddArg(x)
  1732  		v.AddArg(y)
  1733  		return true
  1734  	}
  1735  	// match: (ADD (CSEL0 <typ.UInt64> {cc} (SLL x (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y))) (CMPconst [64] (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y)))) (SRL <typ.UInt64> x (ANDconst <t> [63] y)))
  1736  	// cond: cc.(Op) == OpARM64LessThanU
  1737  	// result: (ROR x y)
  1738  	for {
  1739  		_ = v.Args[1]
  1740  		v_0 := v.Args[0]
  1741  		if v_0.Op != OpARM64CSEL0 {
  1742  			break
  1743  		}
  1744  		if v_0.Type != typ.UInt64 {
  1745  			break
  1746  		}
  1747  		cc := v_0.Aux
  1748  		_ = v_0.Args[1]
  1749  		v_0_0 := v_0.Args[0]
  1750  		if v_0_0.Op != OpARM64SLL {
  1751  			break
  1752  		}
  1753  		_ = v_0_0.Args[1]
  1754  		x := v_0_0.Args[0]
  1755  		v_0_0_1 := v_0_0.Args[1]
  1756  		if v_0_0_1.Op != OpARM64SUB {
  1757  			break
  1758  		}
  1759  		t := v_0_0_1.Type
  1760  		_ = v_0_0_1.Args[1]
  1761  		v_0_0_1_0 := v_0_0_1.Args[0]
  1762  		if v_0_0_1_0.Op != OpARM64MOVDconst {
  1763  			break
  1764  		}
  1765  		if v_0_0_1_0.AuxInt != 64 {
  1766  			break
  1767  		}
  1768  		v_0_0_1_1 := v_0_0_1.Args[1]
  1769  		if v_0_0_1_1.Op != OpARM64ANDconst {
  1770  			break
  1771  		}
  1772  		if v_0_0_1_1.Type != t {
  1773  			break
  1774  		}
  1775  		if v_0_0_1_1.AuxInt != 63 {
  1776  			break
  1777  		}
  1778  		y := v_0_0_1_1.Args[0]
  1779  		v_0_1 := v_0.Args[1]
  1780  		if v_0_1.Op != OpARM64CMPconst {
  1781  			break
  1782  		}
  1783  		if v_0_1.AuxInt != 64 {
  1784  			break
  1785  		}
  1786  		v_0_1_0 := v_0_1.Args[0]
  1787  		if v_0_1_0.Op != OpARM64SUB {
  1788  			break
  1789  		}
  1790  		if v_0_1_0.Type != t {
  1791  			break
  1792  		}
  1793  		_ = v_0_1_0.Args[1]
  1794  		v_0_1_0_0 := v_0_1_0.Args[0]
  1795  		if v_0_1_0_0.Op != OpARM64MOVDconst {
  1796  			break
  1797  		}
  1798  		if v_0_1_0_0.AuxInt != 64 {
  1799  			break
  1800  		}
  1801  		v_0_1_0_1 := v_0_1_0.Args[1]
  1802  		if v_0_1_0_1.Op != OpARM64ANDconst {
  1803  			break
  1804  		}
  1805  		if v_0_1_0_1.Type != t {
  1806  			break
  1807  		}
  1808  		if v_0_1_0_1.AuxInt != 63 {
  1809  			break
  1810  		}
  1811  		if y != v_0_1_0_1.Args[0] {
  1812  			break
  1813  		}
  1814  		v_1 := v.Args[1]
  1815  		if v_1.Op != OpARM64SRL {
  1816  			break
  1817  		}
  1818  		if v_1.Type != typ.UInt64 {
  1819  			break
  1820  		}
  1821  		_ = v_1.Args[1]
  1822  		if x != v_1.Args[0] {
  1823  			break
  1824  		}
  1825  		v_1_1 := v_1.Args[1]
  1826  		if v_1_1.Op != OpARM64ANDconst {
  1827  			break
  1828  		}
  1829  		if v_1_1.Type != t {
  1830  			break
  1831  		}
  1832  		if v_1_1.AuxInt != 63 {
  1833  			break
  1834  		}
  1835  		if y != v_1_1.Args[0] {
  1836  			break
  1837  		}
  1838  		if !(cc.(Op) == OpARM64LessThanU) {
  1839  			break
  1840  		}
  1841  		v.reset(OpARM64ROR)
  1842  		v.AddArg(x)
  1843  		v.AddArg(y)
  1844  		return true
  1845  	}
  1846  	// match: (ADD (SLL x (ANDconst <t> [31] y)) (CSEL0 <typ.UInt32> {cc} (SRL <typ.UInt32> (MOVWUreg x) (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y))) (CMPconst [64] (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y)))))
  1847  	// cond: cc.(Op) == OpARM64LessThanU
  1848  	// result: (RORW x (NEG <t> y))
  1849  	for {
  1850  		_ = v.Args[1]
  1851  		v_0 := v.Args[0]
  1852  		if v_0.Op != OpARM64SLL {
  1853  			break
  1854  		}
  1855  		_ = v_0.Args[1]
  1856  		x := v_0.Args[0]
  1857  		v_0_1 := v_0.Args[1]
  1858  		if v_0_1.Op != OpARM64ANDconst {
  1859  			break
  1860  		}
  1861  		t := v_0_1.Type
  1862  		if v_0_1.AuxInt != 31 {
  1863  			break
  1864  		}
  1865  		y := v_0_1.Args[0]
  1866  		v_1 := v.Args[1]
  1867  		if v_1.Op != OpARM64CSEL0 {
  1868  			break
  1869  		}
  1870  		if v_1.Type != typ.UInt32 {
  1871  			break
  1872  		}
  1873  		cc := v_1.Aux
  1874  		_ = v_1.Args[1]
  1875  		v_1_0 := v_1.Args[0]
  1876  		if v_1_0.Op != OpARM64SRL {
  1877  			break
  1878  		}
  1879  		if v_1_0.Type != typ.UInt32 {
  1880  			break
  1881  		}
  1882  		_ = v_1_0.Args[1]
  1883  		v_1_0_0 := v_1_0.Args[0]
  1884  		if v_1_0_0.Op != OpARM64MOVWUreg {
  1885  			break
  1886  		}
  1887  		if x != v_1_0_0.Args[0] {
  1888  			break
  1889  		}
  1890  		v_1_0_1 := v_1_0.Args[1]
  1891  		if v_1_0_1.Op != OpARM64SUB {
  1892  			break
  1893  		}
  1894  		if v_1_0_1.Type != t {
  1895  			break
  1896  		}
  1897  		_ = v_1_0_1.Args[1]
  1898  		v_1_0_1_0 := v_1_0_1.Args[0]
  1899  		if v_1_0_1_0.Op != OpARM64MOVDconst {
  1900  			break
  1901  		}
  1902  		if v_1_0_1_0.AuxInt != 32 {
  1903  			break
  1904  		}
  1905  		v_1_0_1_1 := v_1_0_1.Args[1]
  1906  		if v_1_0_1_1.Op != OpARM64ANDconst {
  1907  			break
  1908  		}
  1909  		if v_1_0_1_1.Type != t {
  1910  			break
  1911  		}
  1912  		if v_1_0_1_1.AuxInt != 31 {
  1913  			break
  1914  		}
  1915  		if y != v_1_0_1_1.Args[0] {
  1916  			break
  1917  		}
  1918  		v_1_1 := v_1.Args[1]
  1919  		if v_1_1.Op != OpARM64CMPconst {
  1920  			break
  1921  		}
  1922  		if v_1_1.AuxInt != 64 {
  1923  			break
  1924  		}
  1925  		v_1_1_0 := v_1_1.Args[0]
  1926  		if v_1_1_0.Op != OpARM64SUB {
  1927  			break
  1928  		}
  1929  		if v_1_1_0.Type != t {
  1930  			break
  1931  		}
  1932  		_ = v_1_1_0.Args[1]
  1933  		v_1_1_0_0 := v_1_1_0.Args[0]
  1934  		if v_1_1_0_0.Op != OpARM64MOVDconst {
  1935  			break
  1936  		}
  1937  		if v_1_1_0_0.AuxInt != 32 {
  1938  			break
  1939  		}
  1940  		v_1_1_0_1 := v_1_1_0.Args[1]
  1941  		if v_1_1_0_1.Op != OpARM64ANDconst {
  1942  			break
  1943  		}
  1944  		if v_1_1_0_1.Type != t {
  1945  			break
  1946  		}
  1947  		if v_1_1_0_1.AuxInt != 31 {
  1948  			break
  1949  		}
  1950  		if y != v_1_1_0_1.Args[0] {
  1951  			break
  1952  		}
  1953  		if !(cc.(Op) == OpARM64LessThanU) {
  1954  			break
  1955  		}
  1956  		v.reset(OpARM64RORW)
  1957  		v.AddArg(x)
  1958  		v0 := b.NewValue0(v.Pos, OpARM64NEG, t)
  1959  		v0.AddArg(y)
  1960  		v.AddArg(v0)
  1961  		return true
  1962  	}
  1963  	// match: (ADD (CSEL0 <typ.UInt32> {cc} (SRL <typ.UInt32> (MOVWUreg x) (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y))) (CMPconst [64] (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y)))) (SLL x (ANDconst <t> [31] y)))
  1964  	// cond: cc.(Op) == OpARM64LessThanU
  1965  	// result: (RORW x (NEG <t> y))
  1966  	for {
  1967  		_ = v.Args[1]
  1968  		v_0 := v.Args[0]
  1969  		if v_0.Op != OpARM64CSEL0 {
  1970  			break
  1971  		}
  1972  		if v_0.Type != typ.UInt32 {
  1973  			break
  1974  		}
  1975  		cc := v_0.Aux
  1976  		_ = v_0.Args[1]
  1977  		v_0_0 := v_0.Args[0]
  1978  		if v_0_0.Op != OpARM64SRL {
  1979  			break
  1980  		}
  1981  		if v_0_0.Type != typ.UInt32 {
  1982  			break
  1983  		}
  1984  		_ = v_0_0.Args[1]
  1985  		v_0_0_0 := v_0_0.Args[0]
  1986  		if v_0_0_0.Op != OpARM64MOVWUreg {
  1987  			break
  1988  		}
  1989  		x := v_0_0_0.Args[0]
  1990  		v_0_0_1 := v_0_0.Args[1]
  1991  		if v_0_0_1.Op != OpARM64SUB {
  1992  			break
  1993  		}
  1994  		t := v_0_0_1.Type
  1995  		_ = v_0_0_1.Args[1]
  1996  		v_0_0_1_0 := v_0_0_1.Args[0]
  1997  		if v_0_0_1_0.Op != OpARM64MOVDconst {
  1998  			break
  1999  		}
  2000  		if v_0_0_1_0.AuxInt != 32 {
  2001  			break
  2002  		}
  2003  		v_0_0_1_1 := v_0_0_1.Args[1]
  2004  		if v_0_0_1_1.Op != OpARM64ANDconst {
  2005  			break
  2006  		}
  2007  		if v_0_0_1_1.Type != t {
  2008  			break
  2009  		}
  2010  		if v_0_0_1_1.AuxInt != 31 {
  2011  			break
  2012  		}
  2013  		y := v_0_0_1_1.Args[0]
  2014  		v_0_1 := v_0.Args[1]
  2015  		if v_0_1.Op != OpARM64CMPconst {
  2016  			break
  2017  		}
  2018  		if v_0_1.AuxInt != 64 {
  2019  			break
  2020  		}
  2021  		v_0_1_0 := v_0_1.Args[0]
  2022  		if v_0_1_0.Op != OpARM64SUB {
  2023  			break
  2024  		}
  2025  		if v_0_1_0.Type != t {
  2026  			break
  2027  		}
  2028  		_ = v_0_1_0.Args[1]
  2029  		v_0_1_0_0 := v_0_1_0.Args[0]
  2030  		if v_0_1_0_0.Op != OpARM64MOVDconst {
  2031  			break
  2032  		}
  2033  		if v_0_1_0_0.AuxInt != 32 {
  2034  			break
  2035  		}
  2036  		v_0_1_0_1 := v_0_1_0.Args[1]
  2037  		if v_0_1_0_1.Op != OpARM64ANDconst {
  2038  			break
  2039  		}
  2040  		if v_0_1_0_1.Type != t {
  2041  			break
  2042  		}
  2043  		if v_0_1_0_1.AuxInt != 31 {
  2044  			break
  2045  		}
  2046  		if y != v_0_1_0_1.Args[0] {
  2047  			break
  2048  		}
  2049  		v_1 := v.Args[1]
  2050  		if v_1.Op != OpARM64SLL {
  2051  			break
  2052  		}
  2053  		_ = v_1.Args[1]
  2054  		if x != v_1.Args[0] {
  2055  			break
  2056  		}
  2057  		v_1_1 := v_1.Args[1]
  2058  		if v_1_1.Op != OpARM64ANDconst {
  2059  			break
  2060  		}
  2061  		if v_1_1.Type != t {
  2062  			break
  2063  		}
  2064  		if v_1_1.AuxInt != 31 {
  2065  			break
  2066  		}
  2067  		if y != v_1_1.Args[0] {
  2068  			break
  2069  		}
  2070  		if !(cc.(Op) == OpARM64LessThanU) {
  2071  			break
  2072  		}
  2073  		v.reset(OpARM64RORW)
  2074  		v.AddArg(x)
  2075  		v0 := b.NewValue0(v.Pos, OpARM64NEG, t)
  2076  		v0.AddArg(y)
  2077  		v.AddArg(v0)
  2078  		return true
  2079  	}
  2080  	// match: (ADD (SRL <typ.UInt32> (MOVWUreg x) (ANDconst <t> [31] y)) (CSEL0 <typ.UInt32> {cc} (SLL x (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y))) (CMPconst [64] (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y)))))
  2081  	// cond: cc.(Op) == OpARM64LessThanU
  2082  	// result: (RORW x y)
  2083  	for {
  2084  		_ = v.Args[1]
  2085  		v_0 := v.Args[0]
  2086  		if v_0.Op != OpARM64SRL {
  2087  			break
  2088  		}
  2089  		if v_0.Type != typ.UInt32 {
  2090  			break
  2091  		}
  2092  		_ = v_0.Args[1]
  2093  		v_0_0 := v_0.Args[0]
  2094  		if v_0_0.Op != OpARM64MOVWUreg {
  2095  			break
  2096  		}
  2097  		x := v_0_0.Args[0]
  2098  		v_0_1 := v_0.Args[1]
  2099  		if v_0_1.Op != OpARM64ANDconst {
  2100  			break
  2101  		}
  2102  		t := v_0_1.Type
  2103  		if v_0_1.AuxInt != 31 {
  2104  			break
  2105  		}
  2106  		y := v_0_1.Args[0]
  2107  		v_1 := v.Args[1]
  2108  		if v_1.Op != OpARM64CSEL0 {
  2109  			break
  2110  		}
  2111  		if v_1.Type != typ.UInt32 {
  2112  			break
  2113  		}
  2114  		cc := v_1.Aux
  2115  		_ = v_1.Args[1]
  2116  		v_1_0 := v_1.Args[0]
  2117  		if v_1_0.Op != OpARM64SLL {
  2118  			break
  2119  		}
  2120  		_ = v_1_0.Args[1]
  2121  		if x != v_1_0.Args[0] {
  2122  			break
  2123  		}
  2124  		v_1_0_1 := v_1_0.Args[1]
  2125  		if v_1_0_1.Op != OpARM64SUB {
  2126  			break
  2127  		}
  2128  		if v_1_0_1.Type != t {
  2129  			break
  2130  		}
  2131  		_ = v_1_0_1.Args[1]
  2132  		v_1_0_1_0 := v_1_0_1.Args[0]
  2133  		if v_1_0_1_0.Op != OpARM64MOVDconst {
  2134  			break
  2135  		}
  2136  		if v_1_0_1_0.AuxInt != 32 {
  2137  			break
  2138  		}
  2139  		v_1_0_1_1 := v_1_0_1.Args[1]
  2140  		if v_1_0_1_1.Op != OpARM64ANDconst {
  2141  			break
  2142  		}
  2143  		if v_1_0_1_1.Type != t {
  2144  			break
  2145  		}
  2146  		if v_1_0_1_1.AuxInt != 31 {
  2147  			break
  2148  		}
  2149  		if y != v_1_0_1_1.Args[0] {
  2150  			break
  2151  		}
  2152  		v_1_1 := v_1.Args[1]
  2153  		if v_1_1.Op != OpARM64CMPconst {
  2154  			break
  2155  		}
  2156  		if v_1_1.AuxInt != 64 {
  2157  			break
  2158  		}
  2159  		v_1_1_0 := v_1_1.Args[0]
  2160  		if v_1_1_0.Op != OpARM64SUB {
  2161  			break
  2162  		}
  2163  		if v_1_1_0.Type != t {
  2164  			break
  2165  		}
  2166  		_ = v_1_1_0.Args[1]
  2167  		v_1_1_0_0 := v_1_1_0.Args[0]
  2168  		if v_1_1_0_0.Op != OpARM64MOVDconst {
  2169  			break
  2170  		}
  2171  		if v_1_1_0_0.AuxInt != 32 {
  2172  			break
  2173  		}
  2174  		v_1_1_0_1 := v_1_1_0.Args[1]
  2175  		if v_1_1_0_1.Op != OpARM64ANDconst {
  2176  			break
  2177  		}
  2178  		if v_1_1_0_1.Type != t {
  2179  			break
  2180  		}
  2181  		if v_1_1_0_1.AuxInt != 31 {
  2182  			break
  2183  		}
  2184  		if y != v_1_1_0_1.Args[0] {
  2185  			break
  2186  		}
  2187  		if !(cc.(Op) == OpARM64LessThanU) {
  2188  			break
  2189  		}
  2190  		v.reset(OpARM64RORW)
  2191  		v.AddArg(x)
  2192  		v.AddArg(y)
  2193  		return true
  2194  	}
  2195  	// match: (ADD (CSEL0 <typ.UInt32> {cc} (SLL x (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y))) (CMPconst [64] (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y)))) (SRL <typ.UInt32> (MOVWUreg x) (ANDconst <t> [31] y)))
  2196  	// cond: cc.(Op) == OpARM64LessThanU
  2197  	// result: (RORW x y)
  2198  	for {
  2199  		_ = v.Args[1]
  2200  		v_0 := v.Args[0]
  2201  		if v_0.Op != OpARM64CSEL0 {
  2202  			break
  2203  		}
  2204  		if v_0.Type != typ.UInt32 {
  2205  			break
  2206  		}
  2207  		cc := v_0.Aux
  2208  		_ = v_0.Args[1]
  2209  		v_0_0 := v_0.Args[0]
  2210  		if v_0_0.Op != OpARM64SLL {
  2211  			break
  2212  		}
  2213  		_ = v_0_0.Args[1]
  2214  		x := v_0_0.Args[0]
  2215  		v_0_0_1 := v_0_0.Args[1]
  2216  		if v_0_0_1.Op != OpARM64SUB {
  2217  			break
  2218  		}
  2219  		t := v_0_0_1.Type
  2220  		_ = v_0_0_1.Args[1]
  2221  		v_0_0_1_0 := v_0_0_1.Args[0]
  2222  		if v_0_0_1_0.Op != OpARM64MOVDconst {
  2223  			break
  2224  		}
  2225  		if v_0_0_1_0.AuxInt != 32 {
  2226  			break
  2227  		}
  2228  		v_0_0_1_1 := v_0_0_1.Args[1]
  2229  		if v_0_0_1_1.Op != OpARM64ANDconst {
  2230  			break
  2231  		}
  2232  		if v_0_0_1_1.Type != t {
  2233  			break
  2234  		}
  2235  		if v_0_0_1_1.AuxInt != 31 {
  2236  			break
  2237  		}
  2238  		y := v_0_0_1_1.Args[0]
  2239  		v_0_1 := v_0.Args[1]
  2240  		if v_0_1.Op != OpARM64CMPconst {
  2241  			break
  2242  		}
  2243  		if v_0_1.AuxInt != 64 {
  2244  			break
  2245  		}
  2246  		v_0_1_0 := v_0_1.Args[0]
  2247  		if v_0_1_0.Op != OpARM64SUB {
  2248  			break
  2249  		}
  2250  		if v_0_1_0.Type != t {
  2251  			break
  2252  		}
  2253  		_ = v_0_1_0.Args[1]
  2254  		v_0_1_0_0 := v_0_1_0.Args[0]
  2255  		if v_0_1_0_0.Op != OpARM64MOVDconst {
  2256  			break
  2257  		}
  2258  		if v_0_1_0_0.AuxInt != 32 {
  2259  			break
  2260  		}
  2261  		v_0_1_0_1 := v_0_1_0.Args[1]
  2262  		if v_0_1_0_1.Op != OpARM64ANDconst {
  2263  			break
  2264  		}
  2265  		if v_0_1_0_1.Type != t {
  2266  			break
  2267  		}
  2268  		if v_0_1_0_1.AuxInt != 31 {
  2269  			break
  2270  		}
  2271  		if y != v_0_1_0_1.Args[0] {
  2272  			break
  2273  		}
  2274  		v_1 := v.Args[1]
  2275  		if v_1.Op != OpARM64SRL {
  2276  			break
  2277  		}
  2278  		if v_1.Type != typ.UInt32 {
  2279  			break
  2280  		}
  2281  		_ = v_1.Args[1]
  2282  		v_1_0 := v_1.Args[0]
  2283  		if v_1_0.Op != OpARM64MOVWUreg {
  2284  			break
  2285  		}
  2286  		if x != v_1_0.Args[0] {
  2287  			break
  2288  		}
  2289  		v_1_1 := v_1.Args[1]
  2290  		if v_1_1.Op != OpARM64ANDconst {
  2291  			break
  2292  		}
  2293  		if v_1_1.Type != t {
  2294  			break
  2295  		}
  2296  		if v_1_1.AuxInt != 31 {
  2297  			break
  2298  		}
  2299  		if y != v_1_1.Args[0] {
  2300  			break
  2301  		}
  2302  		if !(cc.(Op) == OpARM64LessThanU) {
  2303  			break
  2304  		}
  2305  		v.reset(OpARM64RORW)
  2306  		v.AddArg(x)
  2307  		v.AddArg(y)
  2308  		return true
  2309  	}
  2310  	return false
  2311  }
  2312  func rewriteValueARM64_OpARM64ADDconst_0(v *Value) bool {
  2313  	// match: (ADDconst [off1] (MOVDaddr [off2] {sym} ptr))
  2314  	// cond:
  2315  	// result: (MOVDaddr [off1+off2] {sym} ptr)
  2316  	for {
  2317  		off1 := v.AuxInt
  2318  		v_0 := v.Args[0]
  2319  		if v_0.Op != OpARM64MOVDaddr {
  2320  			break
  2321  		}
  2322  		off2 := v_0.AuxInt
  2323  		sym := v_0.Aux
  2324  		ptr := v_0.Args[0]
  2325  		v.reset(OpARM64MOVDaddr)
  2326  		v.AuxInt = off1 + off2
  2327  		v.Aux = sym
  2328  		v.AddArg(ptr)
  2329  		return true
  2330  	}
  2331  	// match: (ADDconst [0] x)
  2332  	// cond:
  2333  	// result: x
  2334  	for {
  2335  		if v.AuxInt != 0 {
  2336  			break
  2337  		}
  2338  		x := v.Args[0]
  2339  		v.reset(OpCopy)
  2340  		v.Type = x.Type
  2341  		v.AddArg(x)
  2342  		return true
  2343  	}
  2344  	// match: (ADDconst [c] (MOVDconst [d]))
  2345  	// cond:
  2346  	// result: (MOVDconst [c+d])
  2347  	for {
  2348  		c := v.AuxInt
  2349  		v_0 := v.Args[0]
  2350  		if v_0.Op != OpARM64MOVDconst {
  2351  			break
  2352  		}
  2353  		d := v_0.AuxInt
  2354  		v.reset(OpARM64MOVDconst)
  2355  		v.AuxInt = c + d
  2356  		return true
  2357  	}
  2358  	// match: (ADDconst [c] (ADDconst [d] x))
  2359  	// cond:
  2360  	// result: (ADDconst [c+d] x)
  2361  	for {
  2362  		c := v.AuxInt
  2363  		v_0 := v.Args[0]
  2364  		if v_0.Op != OpARM64ADDconst {
  2365  			break
  2366  		}
  2367  		d := v_0.AuxInt
  2368  		x := v_0.Args[0]
  2369  		v.reset(OpARM64ADDconst)
  2370  		v.AuxInt = c + d
  2371  		v.AddArg(x)
  2372  		return true
  2373  	}
  2374  	// match: (ADDconst [c] (SUBconst [d] x))
  2375  	// cond:
  2376  	// result: (ADDconst [c-d] x)
  2377  	for {
  2378  		c := v.AuxInt
  2379  		v_0 := v.Args[0]
  2380  		if v_0.Op != OpARM64SUBconst {
  2381  			break
  2382  		}
  2383  		d := v_0.AuxInt
  2384  		x := v_0.Args[0]
  2385  		v.reset(OpARM64ADDconst)
  2386  		v.AuxInt = c - d
  2387  		v.AddArg(x)
  2388  		return true
  2389  	}
  2390  	return false
  2391  }
  2392  func rewriteValueARM64_OpARM64ADDshiftLL_0(v *Value) bool {
  2393  	b := v.Block
  2394  	typ := &b.Func.Config.Types
  2395  	// match: (ADDshiftLL (MOVDconst [c]) x [d])
  2396  	// cond:
  2397  	// result: (ADDconst [c] (SLLconst <x.Type> x [d]))
  2398  	for {
  2399  		d := v.AuxInt
  2400  		x := v.Args[1]
  2401  		v_0 := v.Args[0]
  2402  		if v_0.Op != OpARM64MOVDconst {
  2403  			break
  2404  		}
  2405  		c := v_0.AuxInt
  2406  		v.reset(OpARM64ADDconst)
  2407  		v.AuxInt = c
  2408  		v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
  2409  		v0.AuxInt = d
  2410  		v0.AddArg(x)
  2411  		v.AddArg(v0)
  2412  		return true
  2413  	}
  2414  	// match: (ADDshiftLL x (MOVDconst [c]) [d])
  2415  	// cond:
  2416  	// result: (ADDconst x [int64(uint64(c)<<uint64(d))])
  2417  	for {
  2418  		d := v.AuxInt
  2419  		_ = v.Args[1]
  2420  		x := v.Args[0]
  2421  		v_1 := v.Args[1]
  2422  		if v_1.Op != OpARM64MOVDconst {
  2423  			break
  2424  		}
  2425  		c := v_1.AuxInt
  2426  		v.reset(OpARM64ADDconst)
  2427  		v.AuxInt = int64(uint64(c) << uint64(d))
  2428  		v.AddArg(x)
  2429  		return true
  2430  	}
  2431  	// match: (ADDshiftLL [c] (SRLconst x [64-c]) x)
  2432  	// cond:
  2433  	// result: (RORconst [64-c] x)
  2434  	for {
  2435  		c := v.AuxInt
  2436  		x := v.Args[1]
  2437  		v_0 := v.Args[0]
  2438  		if v_0.Op != OpARM64SRLconst {
  2439  			break
  2440  		}
  2441  		if v_0.AuxInt != 64-c {
  2442  			break
  2443  		}
  2444  		if x != v_0.Args[0] {
  2445  			break
  2446  		}
  2447  		v.reset(OpARM64RORconst)
  2448  		v.AuxInt = 64 - c
  2449  		v.AddArg(x)
  2450  		return true
  2451  	}
  2452  	// match: (ADDshiftLL <t> [c] (UBFX [bfc] x) x)
  2453  	// cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)
  2454  	// result: (RORWconst [32-c] x)
  2455  	for {
  2456  		t := v.Type
  2457  		c := v.AuxInt
  2458  		x := v.Args[1]
  2459  		v_0 := v.Args[0]
  2460  		if v_0.Op != OpARM64UBFX {
  2461  			break
  2462  		}
  2463  		bfc := v_0.AuxInt
  2464  		if x != v_0.Args[0] {
  2465  			break
  2466  		}
  2467  		if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) {
  2468  			break
  2469  		}
  2470  		v.reset(OpARM64RORWconst)
  2471  		v.AuxInt = 32 - c
  2472  		v.AddArg(x)
  2473  		return true
  2474  	}
  2475  	// match: (ADDshiftLL <typ.UInt16> [8] (UBFX <typ.UInt16> [armBFAuxInt(8, 8)] x) x)
  2476  	// cond:
  2477  	// result: (REV16W x)
  2478  	for {
  2479  		if v.Type != typ.UInt16 {
  2480  			break
  2481  		}
  2482  		if v.AuxInt != 8 {
  2483  			break
  2484  		}
  2485  		x := v.Args[1]
  2486  		v_0 := v.Args[0]
  2487  		if v_0.Op != OpARM64UBFX {
  2488  			break
  2489  		}
  2490  		if v_0.Type != typ.UInt16 {
  2491  			break
  2492  		}
  2493  		if v_0.AuxInt != armBFAuxInt(8, 8) {
  2494  			break
  2495  		}
  2496  		if x != v_0.Args[0] {
  2497  			break
  2498  		}
  2499  		v.reset(OpARM64REV16W)
  2500  		v.AddArg(x)
  2501  		return true
  2502  	}
  2503  	// match: (ADDshiftLL [c] (SRLconst x [64-c]) x2)
  2504  	// cond:
  2505  	// result: (EXTRconst [64-c] x2 x)
  2506  	for {
  2507  		c := v.AuxInt
  2508  		x2 := v.Args[1]
  2509  		v_0 := v.Args[0]
  2510  		if v_0.Op != OpARM64SRLconst {
  2511  			break
  2512  		}
  2513  		if v_0.AuxInt != 64-c {
  2514  			break
  2515  		}
  2516  		x := v_0.Args[0]
  2517  		v.reset(OpARM64EXTRconst)
  2518  		v.AuxInt = 64 - c
  2519  		v.AddArg(x2)
  2520  		v.AddArg(x)
  2521  		return true
  2522  	}
  2523  	// match: (ADDshiftLL <t> [c] (UBFX [bfc] x) x2)
  2524  	// cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)
  2525  	// result: (EXTRWconst [32-c] x2 x)
  2526  	for {
  2527  		t := v.Type
  2528  		c := v.AuxInt
  2529  		x2 := v.Args[1]
  2530  		v_0 := v.Args[0]
  2531  		if v_0.Op != OpARM64UBFX {
  2532  			break
  2533  		}
  2534  		bfc := v_0.AuxInt
  2535  		x := v_0.Args[0]
  2536  		if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) {
  2537  			break
  2538  		}
  2539  		v.reset(OpARM64EXTRWconst)
  2540  		v.AuxInt = 32 - c
  2541  		v.AddArg(x2)
  2542  		v.AddArg(x)
  2543  		return true
  2544  	}
  2545  	return false
  2546  }
  2547  func rewriteValueARM64_OpARM64ADDshiftRA_0(v *Value) bool {
  2548  	b := v.Block
  2549  	// match: (ADDshiftRA (MOVDconst [c]) x [d])
  2550  	// cond:
  2551  	// result: (ADDconst [c] (SRAconst <x.Type> x [d]))
  2552  	for {
  2553  		d := v.AuxInt
  2554  		x := v.Args[1]
  2555  		v_0 := v.Args[0]
  2556  		if v_0.Op != OpARM64MOVDconst {
  2557  			break
  2558  		}
  2559  		c := v_0.AuxInt
  2560  		v.reset(OpARM64ADDconst)
  2561  		v.AuxInt = c
  2562  		v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type)
  2563  		v0.AuxInt = d
  2564  		v0.AddArg(x)
  2565  		v.AddArg(v0)
  2566  		return true
  2567  	}
  2568  	// match: (ADDshiftRA x (MOVDconst [c]) [d])
  2569  	// cond:
  2570  	// result: (ADDconst x [c>>uint64(d)])
  2571  	for {
  2572  		d := v.AuxInt
  2573  		_ = v.Args[1]
  2574  		x := v.Args[0]
  2575  		v_1 := v.Args[1]
  2576  		if v_1.Op != OpARM64MOVDconst {
  2577  			break
  2578  		}
  2579  		c := v_1.AuxInt
  2580  		v.reset(OpARM64ADDconst)
  2581  		v.AuxInt = c >> uint64(d)
  2582  		v.AddArg(x)
  2583  		return true
  2584  	}
  2585  	return false
  2586  }
  2587  func rewriteValueARM64_OpARM64ADDshiftRL_0(v *Value) bool {
  2588  	b := v.Block
  2589  	// match: (ADDshiftRL (MOVDconst [c]) x [d])
  2590  	// cond:
  2591  	// result: (ADDconst [c] (SRLconst <x.Type> x [d]))
  2592  	for {
  2593  		d := v.AuxInt
  2594  		x := v.Args[1]
  2595  		v_0 := v.Args[0]
  2596  		if v_0.Op != OpARM64MOVDconst {
  2597  			break
  2598  		}
  2599  		c := v_0.AuxInt
  2600  		v.reset(OpARM64ADDconst)
  2601  		v.AuxInt = c
  2602  		v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type)
  2603  		v0.AuxInt = d
  2604  		v0.AddArg(x)
  2605  		v.AddArg(v0)
  2606  		return true
  2607  	}
  2608  	// match: (ADDshiftRL x (MOVDconst [c]) [d])
  2609  	// cond:
  2610  	// result: (ADDconst x [int64(uint64(c)>>uint64(d))])
  2611  	for {
  2612  		d := v.AuxInt
  2613  		_ = v.Args[1]
  2614  		x := v.Args[0]
  2615  		v_1 := v.Args[1]
  2616  		if v_1.Op != OpARM64MOVDconst {
  2617  			break
  2618  		}
  2619  		c := v_1.AuxInt
  2620  		v.reset(OpARM64ADDconst)
  2621  		v.AuxInt = int64(uint64(c) >> uint64(d))
  2622  		v.AddArg(x)
  2623  		return true
  2624  	}
  2625  	// match: (ADDshiftRL [c] (SLLconst x [64-c]) x)
  2626  	// cond:
  2627  	// result: (RORconst [ c] x)
  2628  	for {
  2629  		c := v.AuxInt
  2630  		x := v.Args[1]
  2631  		v_0 := v.Args[0]
  2632  		if v_0.Op != OpARM64SLLconst {
  2633  			break
  2634  		}
  2635  		if v_0.AuxInt != 64-c {
  2636  			break
  2637  		}
  2638  		if x != v_0.Args[0] {
  2639  			break
  2640  		}
  2641  		v.reset(OpARM64RORconst)
  2642  		v.AuxInt = c
  2643  		v.AddArg(x)
  2644  		return true
  2645  	}
  2646  	// match: (ADDshiftRL <t> [c] (SLLconst x [32-c]) (MOVWUreg x))
  2647  	// cond: c < 32 && t.Size() == 4
  2648  	// result: (RORWconst [c] x)
  2649  	for {
  2650  		t := v.Type
  2651  		c := v.AuxInt
  2652  		_ = v.Args[1]
  2653  		v_0 := v.Args[0]
  2654  		if v_0.Op != OpARM64SLLconst {
  2655  			break
  2656  		}
  2657  		if v_0.AuxInt != 32-c {
  2658  			break
  2659  		}
  2660  		x := v_0.Args[0]
  2661  		v_1 := v.Args[1]
  2662  		if v_1.Op != OpARM64MOVWUreg {
  2663  			break
  2664  		}
  2665  		if x != v_1.Args[0] {
  2666  			break
  2667  		}
  2668  		if !(c < 32 && t.Size() == 4) {
  2669  			break
  2670  		}
  2671  		v.reset(OpARM64RORWconst)
  2672  		v.AuxInt = c
  2673  		v.AddArg(x)
  2674  		return true
  2675  	}
  2676  	return false
  2677  }
  2678  func rewriteValueARM64_OpARM64AND_0(v *Value) bool {
  2679  	// match: (AND x (MOVDconst [c]))
  2680  	// cond:
  2681  	// result: (ANDconst [c] x)
  2682  	for {
  2683  		_ = v.Args[1]
  2684  		x := v.Args[0]
  2685  		v_1 := v.Args[1]
  2686  		if v_1.Op != OpARM64MOVDconst {
  2687  			break
  2688  		}
  2689  		c := v_1.AuxInt
  2690  		v.reset(OpARM64ANDconst)
  2691  		v.AuxInt = c
  2692  		v.AddArg(x)
  2693  		return true
  2694  	}
  2695  	// match: (AND (MOVDconst [c]) x)
  2696  	// cond:
  2697  	// result: (ANDconst [c] x)
  2698  	for {
  2699  		x := v.Args[1]
  2700  		v_0 := v.Args[0]
  2701  		if v_0.Op != OpARM64MOVDconst {
  2702  			break
  2703  		}
  2704  		c := v_0.AuxInt
  2705  		v.reset(OpARM64ANDconst)
  2706  		v.AuxInt = c
  2707  		v.AddArg(x)
  2708  		return true
  2709  	}
  2710  	// match: (AND x x)
  2711  	// cond:
  2712  	// result: x
  2713  	for {
  2714  		x := v.Args[1]
  2715  		if x != v.Args[0] {
  2716  			break
  2717  		}
  2718  		v.reset(OpCopy)
  2719  		v.Type = x.Type
  2720  		v.AddArg(x)
  2721  		return true
  2722  	}
  2723  	// match: (AND x (MVN y))
  2724  	// cond:
  2725  	// result: (BIC x y)
  2726  	for {
  2727  		_ = v.Args[1]
  2728  		x := v.Args[0]
  2729  		v_1 := v.Args[1]
  2730  		if v_1.Op != OpARM64MVN {
  2731  			break
  2732  		}
  2733  		y := v_1.Args[0]
  2734  		v.reset(OpARM64BIC)
  2735  		v.AddArg(x)
  2736  		v.AddArg(y)
  2737  		return true
  2738  	}
  2739  	// match: (AND (MVN y) x)
  2740  	// cond:
  2741  	// result: (BIC x y)
  2742  	for {
  2743  		x := v.Args[1]
  2744  		v_0 := v.Args[0]
  2745  		if v_0.Op != OpARM64MVN {
  2746  			break
  2747  		}
  2748  		y := v_0.Args[0]
  2749  		v.reset(OpARM64BIC)
  2750  		v.AddArg(x)
  2751  		v.AddArg(y)
  2752  		return true
  2753  	}
  2754  	// match: (AND x0 x1:(SLLconst [c] y))
  2755  	// cond: clobberIfDead(x1)
  2756  	// result: (ANDshiftLL x0 y [c])
  2757  	for {
  2758  		_ = v.Args[1]
  2759  		x0 := v.Args[0]
  2760  		x1 := v.Args[1]
  2761  		if x1.Op != OpARM64SLLconst {
  2762  			break
  2763  		}
  2764  		c := x1.AuxInt
  2765  		y := x1.Args[0]
  2766  		if !(clobberIfDead(x1)) {
  2767  			break
  2768  		}
  2769  		v.reset(OpARM64ANDshiftLL)
  2770  		v.AuxInt = c
  2771  		v.AddArg(x0)
  2772  		v.AddArg(y)
  2773  		return true
  2774  	}
  2775  	// match: (AND x1:(SLLconst [c] y) x0)
  2776  	// cond: clobberIfDead(x1)
  2777  	// result: (ANDshiftLL x0 y [c])
  2778  	for {
  2779  		x0 := v.Args[1]
  2780  		x1 := v.Args[0]
  2781  		if x1.Op != OpARM64SLLconst {
  2782  			break
  2783  		}
  2784  		c := x1.AuxInt
  2785  		y := x1.Args[0]
  2786  		if !(clobberIfDead(x1)) {
  2787  			break
  2788  		}
  2789  		v.reset(OpARM64ANDshiftLL)
  2790  		v.AuxInt = c
  2791  		v.AddArg(x0)
  2792  		v.AddArg(y)
  2793  		return true
  2794  	}
  2795  	// match: (AND x0 x1:(SRLconst [c] y))
  2796  	// cond: clobberIfDead(x1)
  2797  	// result: (ANDshiftRL x0 y [c])
  2798  	for {
  2799  		_ = v.Args[1]
  2800  		x0 := v.Args[0]
  2801  		x1 := v.Args[1]
  2802  		if x1.Op != OpARM64SRLconst {
  2803  			break
  2804  		}
  2805  		c := x1.AuxInt
  2806  		y := x1.Args[0]
  2807  		if !(clobberIfDead(x1)) {
  2808  			break
  2809  		}
  2810  		v.reset(OpARM64ANDshiftRL)
  2811  		v.AuxInt = c
  2812  		v.AddArg(x0)
  2813  		v.AddArg(y)
  2814  		return true
  2815  	}
  2816  	// match: (AND x1:(SRLconst [c] y) x0)
  2817  	// cond: clobberIfDead(x1)
  2818  	// result: (ANDshiftRL x0 y [c])
  2819  	for {
  2820  		x0 := v.Args[1]
  2821  		x1 := v.Args[0]
  2822  		if x1.Op != OpARM64SRLconst {
  2823  			break
  2824  		}
  2825  		c := x1.AuxInt
  2826  		y := x1.Args[0]
  2827  		if !(clobberIfDead(x1)) {
  2828  			break
  2829  		}
  2830  		v.reset(OpARM64ANDshiftRL)
  2831  		v.AuxInt = c
  2832  		v.AddArg(x0)
  2833  		v.AddArg(y)
  2834  		return true
  2835  	}
  2836  	// match: (AND x0 x1:(SRAconst [c] y))
  2837  	// cond: clobberIfDead(x1)
  2838  	// result: (ANDshiftRA x0 y [c])
  2839  	for {
  2840  		_ = v.Args[1]
  2841  		x0 := v.Args[0]
  2842  		x1 := v.Args[1]
  2843  		if x1.Op != OpARM64SRAconst {
  2844  			break
  2845  		}
  2846  		c := x1.AuxInt
  2847  		y := x1.Args[0]
  2848  		if !(clobberIfDead(x1)) {
  2849  			break
  2850  		}
  2851  		v.reset(OpARM64ANDshiftRA)
  2852  		v.AuxInt = c
  2853  		v.AddArg(x0)
  2854  		v.AddArg(y)
  2855  		return true
  2856  	}
  2857  	return false
  2858  }
  2859  func rewriteValueARM64_OpARM64AND_10(v *Value) bool {
  2860  	// match: (AND x1:(SRAconst [c] y) x0)
  2861  	// cond: clobberIfDead(x1)
  2862  	// result: (ANDshiftRA x0 y [c])
  2863  	for {
  2864  		x0 := v.Args[1]
  2865  		x1 := v.Args[0]
  2866  		if x1.Op != OpARM64SRAconst {
  2867  			break
  2868  		}
  2869  		c := x1.AuxInt
  2870  		y := x1.Args[0]
  2871  		if !(clobberIfDead(x1)) {
  2872  			break
  2873  		}
  2874  		v.reset(OpARM64ANDshiftRA)
  2875  		v.AuxInt = c
  2876  		v.AddArg(x0)
  2877  		v.AddArg(y)
  2878  		return true
  2879  	}
  2880  	return false
  2881  }
  2882  func rewriteValueARM64_OpARM64ANDconst_0(v *Value) bool {
  2883  	// match: (ANDconst [0] _)
  2884  	// cond:
  2885  	// result: (MOVDconst [0])
  2886  	for {
  2887  		if v.AuxInt != 0 {
  2888  			break
  2889  		}
  2890  		v.reset(OpARM64MOVDconst)
  2891  		v.AuxInt = 0
  2892  		return true
  2893  	}
  2894  	// match: (ANDconst [-1] x)
  2895  	// cond:
  2896  	// result: x
  2897  	for {
  2898  		if v.AuxInt != -1 {
  2899  			break
  2900  		}
  2901  		x := v.Args[0]
  2902  		v.reset(OpCopy)
  2903  		v.Type = x.Type
  2904  		v.AddArg(x)
  2905  		return true
  2906  	}
  2907  	// match: (ANDconst [c] (MOVDconst [d]))
  2908  	// cond:
  2909  	// result: (MOVDconst [c&d])
  2910  	for {
  2911  		c := v.AuxInt
  2912  		v_0 := v.Args[0]
  2913  		if v_0.Op != OpARM64MOVDconst {
  2914  			break
  2915  		}
  2916  		d := v_0.AuxInt
  2917  		v.reset(OpARM64MOVDconst)
  2918  		v.AuxInt = c & d
  2919  		return true
  2920  	}
  2921  	// match: (ANDconst [c] (ANDconst [d] x))
  2922  	// cond:
  2923  	// result: (ANDconst [c&d] x)
  2924  	for {
  2925  		c := v.AuxInt
  2926  		v_0 := v.Args[0]
  2927  		if v_0.Op != OpARM64ANDconst {
  2928  			break
  2929  		}
  2930  		d := v_0.AuxInt
  2931  		x := v_0.Args[0]
  2932  		v.reset(OpARM64ANDconst)
  2933  		v.AuxInt = c & d
  2934  		v.AddArg(x)
  2935  		return true
  2936  	}
  2937  	// match: (ANDconst [c] (MOVWUreg x))
  2938  	// cond:
  2939  	// result: (ANDconst [c&(1<<32-1)] x)
  2940  	for {
  2941  		c := v.AuxInt
  2942  		v_0 := v.Args[0]
  2943  		if v_0.Op != OpARM64MOVWUreg {
  2944  			break
  2945  		}
  2946  		x := v_0.Args[0]
  2947  		v.reset(OpARM64ANDconst)
  2948  		v.AuxInt = c & (1<<32 - 1)
  2949  		v.AddArg(x)
  2950  		return true
  2951  	}
  2952  	// match: (ANDconst [c] (MOVHUreg x))
  2953  	// cond:
  2954  	// result: (ANDconst [c&(1<<16-1)] x)
  2955  	for {
  2956  		c := v.AuxInt
  2957  		v_0 := v.Args[0]
  2958  		if v_0.Op != OpARM64MOVHUreg {
  2959  			break
  2960  		}
  2961  		x := v_0.Args[0]
  2962  		v.reset(OpARM64ANDconst)
  2963  		v.AuxInt = c & (1<<16 - 1)
  2964  		v.AddArg(x)
  2965  		return true
  2966  	}
  2967  	// match: (ANDconst [c] (MOVBUreg x))
  2968  	// cond:
  2969  	// result: (ANDconst [c&(1<<8-1)] x)
  2970  	for {
  2971  		c := v.AuxInt
  2972  		v_0 := v.Args[0]
  2973  		if v_0.Op != OpARM64MOVBUreg {
  2974  			break
  2975  		}
  2976  		x := v_0.Args[0]
  2977  		v.reset(OpARM64ANDconst)
  2978  		v.AuxInt = c & (1<<8 - 1)
  2979  		v.AddArg(x)
  2980  		return true
  2981  	}
  2982  	// match: (ANDconst [ac] (SLLconst [sc] x))
  2983  	// cond: isARM64BFMask(sc, ac, sc)
  2984  	// result: (UBFIZ [armBFAuxInt(sc, arm64BFWidth(ac, sc))] x)
  2985  	for {
  2986  		ac := v.AuxInt
  2987  		v_0 := v.Args[0]
  2988  		if v_0.Op != OpARM64SLLconst {
  2989  			break
  2990  		}
  2991  		sc := v_0.AuxInt
  2992  		x := v_0.Args[0]
  2993  		if !(isARM64BFMask(sc, ac, sc)) {
  2994  			break
  2995  		}
  2996  		v.reset(OpARM64UBFIZ)
  2997  		v.AuxInt = armBFAuxInt(sc, arm64BFWidth(ac, sc))
  2998  		v.AddArg(x)
  2999  		return true
  3000  	}
  3001  	// match: (ANDconst [ac] (SRLconst [sc] x))
  3002  	// cond: isARM64BFMask(sc, ac, 0)
  3003  	// result: (UBFX [armBFAuxInt(sc, arm64BFWidth(ac, 0))] x)
  3004  	for {
  3005  		ac := v.AuxInt
  3006  		v_0 := v.Args[0]
  3007  		if v_0.Op != OpARM64SRLconst {
  3008  			break
  3009  		}
  3010  		sc := v_0.AuxInt
  3011  		x := v_0.Args[0]
  3012  		if !(isARM64BFMask(sc, ac, 0)) {
  3013  			break
  3014  		}
  3015  		v.reset(OpARM64UBFX)
  3016  		v.AuxInt = armBFAuxInt(sc, arm64BFWidth(ac, 0))
  3017  		v.AddArg(x)
  3018  		return true
  3019  	}
  3020  	return false
  3021  }
  3022  func rewriteValueARM64_OpARM64ANDshiftLL_0(v *Value) bool {
  3023  	b := v.Block
  3024  	// match: (ANDshiftLL (MOVDconst [c]) x [d])
  3025  	// cond:
  3026  	// result: (ANDconst [c] (SLLconst <x.Type> x [d]))
  3027  	for {
  3028  		d := v.AuxInt
  3029  		x := v.Args[1]
  3030  		v_0 := v.Args[0]
  3031  		if v_0.Op != OpARM64MOVDconst {
  3032  			break
  3033  		}
  3034  		c := v_0.AuxInt
  3035  		v.reset(OpARM64ANDconst)
  3036  		v.AuxInt = c
  3037  		v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
  3038  		v0.AuxInt = d
  3039  		v0.AddArg(x)
  3040  		v.AddArg(v0)
  3041  		return true
  3042  	}
  3043  	// match: (ANDshiftLL x (MOVDconst [c]) [d])
  3044  	// cond:
  3045  	// result: (ANDconst x [int64(uint64(c)<<uint64(d))])
  3046  	for {
  3047  		d := v.AuxInt
  3048  		_ = v.Args[1]
  3049  		x := v.Args[0]
  3050  		v_1 := v.Args[1]
  3051  		if v_1.Op != OpARM64MOVDconst {
  3052  			break
  3053  		}
  3054  		c := v_1.AuxInt
  3055  		v.reset(OpARM64ANDconst)
  3056  		v.AuxInt = int64(uint64(c) << uint64(d))
  3057  		v.AddArg(x)
  3058  		return true
  3059  	}
  3060  	// match: (ANDshiftLL x y:(SLLconst x [c]) [d])
  3061  	// cond: c==d
  3062  	// result: y
  3063  	for {
  3064  		d := v.AuxInt
  3065  		_ = v.Args[1]
  3066  		x := v.Args[0]
  3067  		y := v.Args[1]
  3068  		if y.Op != OpARM64SLLconst {
  3069  			break
  3070  		}
  3071  		c := y.AuxInt
  3072  		if x != y.Args[0] {
  3073  			break
  3074  		}
  3075  		if !(c == d) {
  3076  			break
  3077  		}
  3078  		v.reset(OpCopy)
  3079  		v.Type = y.Type
  3080  		v.AddArg(y)
  3081  		return true
  3082  	}
  3083  	return false
  3084  }
  3085  func rewriteValueARM64_OpARM64ANDshiftRA_0(v *Value) bool {
  3086  	b := v.Block
  3087  	// match: (ANDshiftRA (MOVDconst [c]) x [d])
  3088  	// cond:
  3089  	// result: (ANDconst [c] (SRAconst <x.Type> x [d]))
  3090  	for {
  3091  		d := v.AuxInt
  3092  		x := v.Args[1]
  3093  		v_0 := v.Args[0]
  3094  		if v_0.Op != OpARM64MOVDconst {
  3095  			break
  3096  		}
  3097  		c := v_0.AuxInt
  3098  		v.reset(OpARM64ANDconst)
  3099  		v.AuxInt = c
  3100  		v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type)
  3101  		v0.AuxInt = d
  3102  		v0.AddArg(x)
  3103  		v.AddArg(v0)
  3104  		return true
  3105  	}
  3106  	// match: (ANDshiftRA x (MOVDconst [c]) [d])
  3107  	// cond:
  3108  	// result: (ANDconst x [c>>uint64(d)])
  3109  	for {
  3110  		d := v.AuxInt
  3111  		_ = v.Args[1]
  3112  		x := v.Args[0]
  3113  		v_1 := v.Args[1]
  3114  		if v_1.Op != OpARM64MOVDconst {
  3115  			break
  3116  		}
  3117  		c := v_1.AuxInt
  3118  		v.reset(OpARM64ANDconst)
  3119  		v.AuxInt = c >> uint64(d)
  3120  		v.AddArg(x)
  3121  		return true
  3122  	}
  3123  	// match: (ANDshiftRA x y:(SRAconst x [c]) [d])
  3124  	// cond: c==d
  3125  	// result: y
  3126  	for {
  3127  		d := v.AuxInt
  3128  		_ = v.Args[1]
  3129  		x := v.Args[0]
  3130  		y := v.Args[1]
  3131  		if y.Op != OpARM64SRAconst {
  3132  			break
  3133  		}
  3134  		c := y.AuxInt
  3135  		if x != y.Args[0] {
  3136  			break
  3137  		}
  3138  		if !(c == d) {
  3139  			break
  3140  		}
  3141  		v.reset(OpCopy)
  3142  		v.Type = y.Type
  3143  		v.AddArg(y)
  3144  		return true
  3145  	}
  3146  	return false
  3147  }
  3148  func rewriteValueARM64_OpARM64ANDshiftRL_0(v *Value) bool {
  3149  	b := v.Block
  3150  	// match: (ANDshiftRL (MOVDconst [c]) x [d])
  3151  	// cond:
  3152  	// result: (ANDconst [c] (SRLconst <x.Type> x [d]))
  3153  	for {
  3154  		d := v.AuxInt
  3155  		x := v.Args[1]
  3156  		v_0 := v.Args[0]
  3157  		if v_0.Op != OpARM64MOVDconst {
  3158  			break
  3159  		}
  3160  		c := v_0.AuxInt
  3161  		v.reset(OpARM64ANDconst)
  3162  		v.AuxInt = c
  3163  		v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type)
  3164  		v0.AuxInt = d
  3165  		v0.AddArg(x)
  3166  		v.AddArg(v0)
  3167  		return true
  3168  	}
  3169  	// match: (ANDshiftRL x (MOVDconst [c]) [d])
  3170  	// cond:
  3171  	// result: (ANDconst x [int64(uint64(c)>>uint64(d))])
  3172  	for {
  3173  		d := v.AuxInt
  3174  		_ = v.Args[1]
  3175  		x := v.Args[0]
  3176  		v_1 := v.Args[1]
  3177  		if v_1.Op != OpARM64MOVDconst {
  3178  			break
  3179  		}
  3180  		c := v_1.AuxInt
  3181  		v.reset(OpARM64ANDconst)
  3182  		v.AuxInt = int64(uint64(c) >> uint64(d))
  3183  		v.AddArg(x)
  3184  		return true
  3185  	}
  3186  	// match: (ANDshiftRL x y:(SRLconst x [c]) [d])
  3187  	// cond: c==d
  3188  	// result: y
  3189  	for {
  3190  		d := v.AuxInt
  3191  		_ = v.Args[1]
  3192  		x := v.Args[0]
  3193  		y := v.Args[1]
  3194  		if y.Op != OpARM64SRLconst {
  3195  			break
  3196  		}
  3197  		c := y.AuxInt
  3198  		if x != y.Args[0] {
  3199  			break
  3200  		}
  3201  		if !(c == d) {
  3202  			break
  3203  		}
  3204  		v.reset(OpCopy)
  3205  		v.Type = y.Type
  3206  		v.AddArg(y)
  3207  		return true
  3208  	}
  3209  	return false
  3210  }
  3211  func rewriteValueARM64_OpARM64BIC_0(v *Value) bool {
  3212  	// match: (BIC x (MOVDconst [c]))
  3213  	// cond:
  3214  	// result: (ANDconst [^c] x)
  3215  	for {
  3216  		_ = v.Args[1]
  3217  		x := v.Args[0]
  3218  		v_1 := v.Args[1]
  3219  		if v_1.Op != OpARM64MOVDconst {
  3220  			break
  3221  		}
  3222  		c := v_1.AuxInt
  3223  		v.reset(OpARM64ANDconst)
  3224  		v.AuxInt = ^c
  3225  		v.AddArg(x)
  3226  		return true
  3227  	}
  3228  	// match: (BIC x x)
  3229  	// cond:
  3230  	// result: (MOVDconst [0])
  3231  	for {
  3232  		x := v.Args[1]
  3233  		if x != v.Args[0] {
  3234  			break
  3235  		}
  3236  		v.reset(OpARM64MOVDconst)
  3237  		v.AuxInt = 0
  3238  		return true
  3239  	}
  3240  	// match: (BIC x0 x1:(SLLconst [c] y))
  3241  	// cond: clobberIfDead(x1)
  3242  	// result: (BICshiftLL x0 y [c])
  3243  	for {
  3244  		_ = v.Args[1]
  3245  		x0 := v.Args[0]
  3246  		x1 := v.Args[1]
  3247  		if x1.Op != OpARM64SLLconst {
  3248  			break
  3249  		}
  3250  		c := x1.AuxInt
  3251  		y := x1.Args[0]
  3252  		if !(clobberIfDead(x1)) {
  3253  			break
  3254  		}
  3255  		v.reset(OpARM64BICshiftLL)
  3256  		v.AuxInt = c
  3257  		v.AddArg(x0)
  3258  		v.AddArg(y)
  3259  		return true
  3260  	}
  3261  	// match: (BIC x0 x1:(SRLconst [c] y))
  3262  	// cond: clobberIfDead(x1)
  3263  	// result: (BICshiftRL x0 y [c])
  3264  	for {
  3265  		_ = v.Args[1]
  3266  		x0 := v.Args[0]
  3267  		x1 := v.Args[1]
  3268  		if x1.Op != OpARM64SRLconst {
  3269  			break
  3270  		}
  3271  		c := x1.AuxInt
  3272  		y := x1.Args[0]
  3273  		if !(clobberIfDead(x1)) {
  3274  			break
  3275  		}
  3276  		v.reset(OpARM64BICshiftRL)
  3277  		v.AuxInt = c
  3278  		v.AddArg(x0)
  3279  		v.AddArg(y)
  3280  		return true
  3281  	}
  3282  	// match: (BIC x0 x1:(SRAconst [c] y))
  3283  	// cond: clobberIfDead(x1)
  3284  	// result: (BICshiftRA x0 y [c])
  3285  	for {
  3286  		_ = v.Args[1]
  3287  		x0 := v.Args[0]
  3288  		x1 := v.Args[1]
  3289  		if x1.Op != OpARM64SRAconst {
  3290  			break
  3291  		}
  3292  		c := x1.AuxInt
  3293  		y := x1.Args[0]
  3294  		if !(clobberIfDead(x1)) {
  3295  			break
  3296  		}
  3297  		v.reset(OpARM64BICshiftRA)
  3298  		v.AuxInt = c
  3299  		v.AddArg(x0)
  3300  		v.AddArg(y)
  3301  		return true
  3302  	}
  3303  	return false
  3304  }
  3305  func rewriteValueARM64_OpARM64BICshiftLL_0(v *Value) bool {
  3306  	// match: (BICshiftLL x (MOVDconst [c]) [d])
  3307  	// cond:
  3308  	// result: (ANDconst x [^int64(uint64(c)<<uint64(d))])
  3309  	for {
  3310  		d := v.AuxInt
  3311  		_ = v.Args[1]
  3312  		x := v.Args[0]
  3313  		v_1 := v.Args[1]
  3314  		if v_1.Op != OpARM64MOVDconst {
  3315  			break
  3316  		}
  3317  		c := v_1.AuxInt
  3318  		v.reset(OpARM64ANDconst)
  3319  		v.AuxInt = ^int64(uint64(c) << uint64(d))
  3320  		v.AddArg(x)
  3321  		return true
  3322  	}
  3323  	// match: (BICshiftLL x (SLLconst x [c]) [d])
  3324  	// cond: c==d
  3325  	// result: (MOVDconst [0])
  3326  	for {
  3327  		d := v.AuxInt
  3328  		_ = v.Args[1]
  3329  		x := v.Args[0]
  3330  		v_1 := v.Args[1]
  3331  		if v_1.Op != OpARM64SLLconst {
  3332  			break
  3333  		}
  3334  		c := v_1.AuxInt
  3335  		if x != v_1.Args[0] {
  3336  			break
  3337  		}
  3338  		if !(c == d) {
  3339  			break
  3340  		}
  3341  		v.reset(OpARM64MOVDconst)
  3342  		v.AuxInt = 0
  3343  		return true
  3344  	}
  3345  	return false
  3346  }
  3347  func rewriteValueARM64_OpARM64BICshiftRA_0(v *Value) bool {
  3348  	// match: (BICshiftRA x (MOVDconst [c]) [d])
  3349  	// cond:
  3350  	// result: (ANDconst x [^(c>>uint64(d))])
  3351  	for {
  3352  		d := v.AuxInt
  3353  		_ = v.Args[1]
  3354  		x := v.Args[0]
  3355  		v_1 := v.Args[1]
  3356  		if v_1.Op != OpARM64MOVDconst {
  3357  			break
  3358  		}
  3359  		c := v_1.AuxInt
  3360  		v.reset(OpARM64ANDconst)
  3361  		v.AuxInt = ^(c >> uint64(d))
  3362  		v.AddArg(x)
  3363  		return true
  3364  	}
  3365  	// match: (BICshiftRA x (SRAconst x [c]) [d])
  3366  	// cond: c==d
  3367  	// result: (MOVDconst [0])
  3368  	for {
  3369  		d := v.AuxInt
  3370  		_ = v.Args[1]
  3371  		x := v.Args[0]
  3372  		v_1 := v.Args[1]
  3373  		if v_1.Op != OpARM64SRAconst {
  3374  			break
  3375  		}
  3376  		c := v_1.AuxInt
  3377  		if x != v_1.Args[0] {
  3378  			break
  3379  		}
  3380  		if !(c == d) {
  3381  			break
  3382  		}
  3383  		v.reset(OpARM64MOVDconst)
  3384  		v.AuxInt = 0
  3385  		return true
  3386  	}
  3387  	return false
  3388  }
  3389  func rewriteValueARM64_OpARM64BICshiftRL_0(v *Value) bool {
  3390  	// match: (BICshiftRL x (MOVDconst [c]) [d])
  3391  	// cond:
  3392  	// result: (ANDconst x [^int64(uint64(c)>>uint64(d))])
  3393  	for {
  3394  		d := v.AuxInt
  3395  		_ = v.Args[1]
  3396  		x := v.Args[0]
  3397  		v_1 := v.Args[1]
  3398  		if v_1.Op != OpARM64MOVDconst {
  3399  			break
  3400  		}
  3401  		c := v_1.AuxInt
  3402  		v.reset(OpARM64ANDconst)
  3403  		v.AuxInt = ^int64(uint64(c) >> uint64(d))
  3404  		v.AddArg(x)
  3405  		return true
  3406  	}
  3407  	// match: (BICshiftRL x (SRLconst x [c]) [d])
  3408  	// cond: c==d
  3409  	// result: (MOVDconst [0])
  3410  	for {
  3411  		d := v.AuxInt
  3412  		_ = v.Args[1]
  3413  		x := v.Args[0]
  3414  		v_1 := v.Args[1]
  3415  		if v_1.Op != OpARM64SRLconst {
  3416  			break
  3417  		}
  3418  		c := v_1.AuxInt
  3419  		if x != v_1.Args[0] {
  3420  			break
  3421  		}
  3422  		if !(c == d) {
  3423  			break
  3424  		}
  3425  		v.reset(OpARM64MOVDconst)
  3426  		v.AuxInt = 0
  3427  		return true
  3428  	}
  3429  	return false
  3430  }
  3431  func rewriteValueARM64_OpARM64CMN_0(v *Value) bool {
  3432  	// match: (CMN x (MOVDconst [c]))
  3433  	// cond:
  3434  	// result: (CMNconst [c] x)
  3435  	for {
  3436  		_ = v.Args[1]
  3437  		x := v.Args[0]
  3438  		v_1 := v.Args[1]
  3439  		if v_1.Op != OpARM64MOVDconst {
  3440  			break
  3441  		}
  3442  		c := v_1.AuxInt
  3443  		v.reset(OpARM64CMNconst)
  3444  		v.AuxInt = c
  3445  		v.AddArg(x)
  3446  		return true
  3447  	}
  3448  	// match: (CMN (MOVDconst [c]) x)
  3449  	// cond:
  3450  	// result: (CMNconst [c] x)
  3451  	for {
  3452  		x := v.Args[1]
  3453  		v_0 := v.Args[0]
  3454  		if v_0.Op != OpARM64MOVDconst {
  3455  			break
  3456  		}
  3457  		c := v_0.AuxInt
  3458  		v.reset(OpARM64CMNconst)
  3459  		v.AuxInt = c
  3460  		v.AddArg(x)
  3461  		return true
  3462  	}
  3463  	// match: (CMN x0 x1:(SLLconst [c] y))
  3464  	// cond: clobberIfDead(x1)
  3465  	// result: (CMNshiftLL x0 y [c])
  3466  	for {
  3467  		_ = v.Args[1]
  3468  		x0 := v.Args[0]
  3469  		x1 := v.Args[1]
  3470  		if x1.Op != OpARM64SLLconst {
  3471  			break
  3472  		}
  3473  		c := x1.AuxInt
  3474  		y := x1.Args[0]
  3475  		if !(clobberIfDead(x1)) {
  3476  			break
  3477  		}
  3478  		v.reset(OpARM64CMNshiftLL)
  3479  		v.AuxInt = c
  3480  		v.AddArg(x0)
  3481  		v.AddArg(y)
  3482  		return true
  3483  	}
  3484  	// match: (CMN x1:(SLLconst [c] y) x0)
  3485  	// cond: clobberIfDead(x1)
  3486  	// result: (CMNshiftLL x0 y [c])
  3487  	for {
  3488  		x0 := v.Args[1]
  3489  		x1 := v.Args[0]
  3490  		if x1.Op != OpARM64SLLconst {
  3491  			break
  3492  		}
  3493  		c := x1.AuxInt
  3494  		y := x1.Args[0]
  3495  		if !(clobberIfDead(x1)) {
  3496  			break
  3497  		}
  3498  		v.reset(OpARM64CMNshiftLL)
  3499  		v.AuxInt = c
  3500  		v.AddArg(x0)
  3501  		v.AddArg(y)
  3502  		return true
  3503  	}
  3504  	// match: (CMN x0 x1:(SRLconst [c] y))
  3505  	// cond: clobberIfDead(x1)
  3506  	// result: (CMNshiftRL x0 y [c])
  3507  	for {
  3508  		_ = v.Args[1]
  3509  		x0 := v.Args[0]
  3510  		x1 := v.Args[1]
  3511  		if x1.Op != OpARM64SRLconst {
  3512  			break
  3513  		}
  3514  		c := x1.AuxInt
  3515  		y := x1.Args[0]
  3516  		if !(clobberIfDead(x1)) {
  3517  			break
  3518  		}
  3519  		v.reset(OpARM64CMNshiftRL)
  3520  		v.AuxInt = c
  3521  		v.AddArg(x0)
  3522  		v.AddArg(y)
  3523  		return true
  3524  	}
  3525  	// match: (CMN x1:(SRLconst [c] y) x0)
  3526  	// cond: clobberIfDead(x1)
  3527  	// result: (CMNshiftRL x0 y [c])
  3528  	for {
  3529  		x0 := v.Args[1]
  3530  		x1 := v.Args[0]
  3531  		if x1.Op != OpARM64SRLconst {
  3532  			break
  3533  		}
  3534  		c := x1.AuxInt
  3535  		y := x1.Args[0]
  3536  		if !(clobberIfDead(x1)) {
  3537  			break
  3538  		}
  3539  		v.reset(OpARM64CMNshiftRL)
  3540  		v.AuxInt = c
  3541  		v.AddArg(x0)
  3542  		v.AddArg(y)
  3543  		return true
  3544  	}
  3545  	// match: (CMN x0 x1:(SRAconst [c] y))
  3546  	// cond: clobberIfDead(x1)
  3547  	// result: (CMNshiftRA x0 y [c])
  3548  	for {
  3549  		_ = v.Args[1]
  3550  		x0 := v.Args[0]
  3551  		x1 := v.Args[1]
  3552  		if x1.Op != OpARM64SRAconst {
  3553  			break
  3554  		}
  3555  		c := x1.AuxInt
  3556  		y := x1.Args[0]
  3557  		if !(clobberIfDead(x1)) {
  3558  			break
  3559  		}
  3560  		v.reset(OpARM64CMNshiftRA)
  3561  		v.AuxInt = c
  3562  		v.AddArg(x0)
  3563  		v.AddArg(y)
  3564  		return true
  3565  	}
  3566  	// match: (CMN x1:(SRAconst [c] y) x0)
  3567  	// cond: clobberIfDead(x1)
  3568  	// result: (CMNshiftRA x0 y [c])
  3569  	for {
  3570  		x0 := v.Args[1]
  3571  		x1 := v.Args[0]
  3572  		if x1.Op != OpARM64SRAconst {
  3573  			break
  3574  		}
  3575  		c := x1.AuxInt
  3576  		y := x1.Args[0]
  3577  		if !(clobberIfDead(x1)) {
  3578  			break
  3579  		}
  3580  		v.reset(OpARM64CMNshiftRA)
  3581  		v.AuxInt = c
  3582  		v.AddArg(x0)
  3583  		v.AddArg(y)
  3584  		return true
  3585  	}
  3586  	return false
  3587  }
  3588  func rewriteValueARM64_OpARM64CMNW_0(v *Value) bool {
  3589  	// match: (CMNW x (MOVDconst [c]))
  3590  	// cond:
  3591  	// result: (CMNWconst [c] x)
  3592  	for {
  3593  		_ = v.Args[1]
  3594  		x := v.Args[0]
  3595  		v_1 := v.Args[1]
  3596  		if v_1.Op != OpARM64MOVDconst {
  3597  			break
  3598  		}
  3599  		c := v_1.AuxInt
  3600  		v.reset(OpARM64CMNWconst)
  3601  		v.AuxInt = c
  3602  		v.AddArg(x)
  3603  		return true
  3604  	}
  3605  	// match: (CMNW (MOVDconst [c]) x)
  3606  	// cond:
  3607  	// result: (CMNWconst [c] x)
  3608  	for {
  3609  		x := v.Args[1]
  3610  		v_0 := v.Args[0]
  3611  		if v_0.Op != OpARM64MOVDconst {
  3612  			break
  3613  		}
  3614  		c := v_0.AuxInt
  3615  		v.reset(OpARM64CMNWconst)
  3616  		v.AuxInt = c
  3617  		v.AddArg(x)
  3618  		return true
  3619  	}
  3620  	return false
  3621  }
  3622  func rewriteValueARM64_OpARM64CMNWconst_0(v *Value) bool {
  3623  	// match: (CMNWconst (MOVDconst [x]) [y])
  3624  	// cond: int32(x)==int32(-y)
  3625  	// result: (FlagEQ)
  3626  	for {
  3627  		y := v.AuxInt
  3628  		v_0 := v.Args[0]
  3629  		if v_0.Op != OpARM64MOVDconst {
  3630  			break
  3631  		}
  3632  		x := v_0.AuxInt
  3633  		if !(int32(x) == int32(-y)) {
  3634  			break
  3635  		}
  3636  		v.reset(OpARM64FlagEQ)
  3637  		return true
  3638  	}
  3639  	// match: (CMNWconst (MOVDconst [x]) [y])
  3640  	// cond: int32(x)<int32(-y) && uint32(x)<uint32(-y)
  3641  	// result: (FlagLT_ULT)
  3642  	for {
  3643  		y := v.AuxInt
  3644  		v_0 := v.Args[0]
  3645  		if v_0.Op != OpARM64MOVDconst {
  3646  			break
  3647  		}
  3648  		x := v_0.AuxInt
  3649  		if !(int32(x) < int32(-y) && uint32(x) < uint32(-y)) {
  3650  			break
  3651  		}
  3652  		v.reset(OpARM64FlagLT_ULT)
  3653  		return true
  3654  	}
  3655  	// match: (CMNWconst (MOVDconst [x]) [y])
  3656  	// cond: int32(x)<int32(-y) && uint32(x)>uint32(-y)
  3657  	// result: (FlagLT_UGT)
  3658  	for {
  3659  		y := v.AuxInt
  3660  		v_0 := v.Args[0]
  3661  		if v_0.Op != OpARM64MOVDconst {
  3662  			break
  3663  		}
  3664  		x := v_0.AuxInt
  3665  		if !(int32(x) < int32(-y) && uint32(x) > uint32(-y)) {
  3666  			break
  3667  		}
  3668  		v.reset(OpARM64FlagLT_UGT)
  3669  		return true
  3670  	}
  3671  	// match: (CMNWconst (MOVDconst [x]) [y])
  3672  	// cond: int32(x)>int32(-y) && uint32(x)<uint32(-y)
  3673  	// result: (FlagGT_ULT)
  3674  	for {
  3675  		y := v.AuxInt
  3676  		v_0 := v.Args[0]
  3677  		if v_0.Op != OpARM64MOVDconst {
  3678  			break
  3679  		}
  3680  		x := v_0.AuxInt
  3681  		if !(int32(x) > int32(-y) && uint32(x) < uint32(-y)) {
  3682  			break
  3683  		}
  3684  		v.reset(OpARM64FlagGT_ULT)
  3685  		return true
  3686  	}
  3687  	// match: (CMNWconst (MOVDconst [x]) [y])
  3688  	// cond: int32(x)>int32(-y) && uint32(x)>uint32(-y)
  3689  	// result: (FlagGT_UGT)
  3690  	for {
  3691  		y := v.AuxInt
  3692  		v_0 := v.Args[0]
  3693  		if v_0.Op != OpARM64MOVDconst {
  3694  			break
  3695  		}
  3696  		x := v_0.AuxInt
  3697  		if !(int32(x) > int32(-y) && uint32(x) > uint32(-y)) {
  3698  			break
  3699  		}
  3700  		v.reset(OpARM64FlagGT_UGT)
  3701  		return true
  3702  	}
  3703  	return false
  3704  }
  3705  func rewriteValueARM64_OpARM64CMNconst_0(v *Value) bool {
  3706  	// match: (CMNconst (MOVDconst [x]) [y])
  3707  	// cond: int64(x)==int64(-y)
  3708  	// result: (FlagEQ)
  3709  	for {
  3710  		y := v.AuxInt
  3711  		v_0 := v.Args[0]
  3712  		if v_0.Op != OpARM64MOVDconst {
  3713  			break
  3714  		}
  3715  		x := v_0.AuxInt
  3716  		if !(int64(x) == int64(-y)) {
  3717  			break
  3718  		}
  3719  		v.reset(OpARM64FlagEQ)
  3720  		return true
  3721  	}
  3722  	// match: (CMNconst (MOVDconst [x]) [y])
  3723  	// cond: int64(x)<int64(-y) && uint64(x)<uint64(-y)
  3724  	// result: (FlagLT_ULT)
  3725  	for {
  3726  		y := v.AuxInt
  3727  		v_0 := v.Args[0]
  3728  		if v_0.Op != OpARM64MOVDconst {
  3729  			break
  3730  		}
  3731  		x := v_0.AuxInt
  3732  		if !(int64(x) < int64(-y) && uint64(x) < uint64(-y)) {
  3733  			break
  3734  		}
  3735  		v.reset(OpARM64FlagLT_ULT)
  3736  		return true
  3737  	}
  3738  	// match: (CMNconst (MOVDconst [x]) [y])
  3739  	// cond: int64(x)<int64(-y) && uint64(x)>uint64(-y)
  3740  	// result: (FlagLT_UGT)
  3741  	for {
  3742  		y := v.AuxInt
  3743  		v_0 := v.Args[0]
  3744  		if v_0.Op != OpARM64MOVDconst {
  3745  			break
  3746  		}
  3747  		x := v_0.AuxInt
  3748  		if !(int64(x) < int64(-y) && uint64(x) > uint64(-y)) {
  3749  			break
  3750  		}
  3751  		v.reset(OpARM64FlagLT_UGT)
  3752  		return true
  3753  	}
  3754  	// match: (CMNconst (MOVDconst [x]) [y])
  3755  	// cond: int64(x)>int64(-y) && uint64(x)<uint64(-y)
  3756  	// result: (FlagGT_ULT)
  3757  	for {
  3758  		y := v.AuxInt
  3759  		v_0 := v.Args[0]
  3760  		if v_0.Op != OpARM64MOVDconst {
  3761  			break
  3762  		}
  3763  		x := v_0.AuxInt
  3764  		if !(int64(x) > int64(-y) && uint64(x) < uint64(-y)) {
  3765  			break
  3766  		}
  3767  		v.reset(OpARM64FlagGT_ULT)
  3768  		return true
  3769  	}
  3770  	// match: (CMNconst (MOVDconst [x]) [y])
  3771  	// cond: int64(x)>int64(-y) && uint64(x)>uint64(-y)
  3772  	// result: (FlagGT_UGT)
  3773  	for {
  3774  		y := v.AuxInt
  3775  		v_0 := v.Args[0]
  3776  		if v_0.Op != OpARM64MOVDconst {
  3777  			break
  3778  		}
  3779  		x := v_0.AuxInt
  3780  		if !(int64(x) > int64(-y) && uint64(x) > uint64(-y)) {
  3781  			break
  3782  		}
  3783  		v.reset(OpARM64FlagGT_UGT)
  3784  		return true
  3785  	}
  3786  	return false
  3787  }
  3788  func rewriteValueARM64_OpARM64CMNshiftLL_0(v *Value) bool {
  3789  	b := v.Block
  3790  	// match: (CMNshiftLL (MOVDconst [c]) x [d])
  3791  	// cond:
  3792  	// result: (CMNconst [c] (SLLconst <x.Type> x [d]))
  3793  	for {
  3794  		d := v.AuxInt
  3795  		x := v.Args[1]
  3796  		v_0 := v.Args[0]
  3797  		if v_0.Op != OpARM64MOVDconst {
  3798  			break
  3799  		}
  3800  		c := v_0.AuxInt
  3801  		v.reset(OpARM64CMNconst)
  3802  		v.AuxInt = c
  3803  		v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
  3804  		v0.AuxInt = d
  3805  		v0.AddArg(x)
  3806  		v.AddArg(v0)
  3807  		return true
  3808  	}
  3809  	// match: (CMNshiftLL x (MOVDconst [c]) [d])
  3810  	// cond:
  3811  	// result: (CMNconst x [int64(uint64(c)<<uint64(d))])
  3812  	for {
  3813  		d := v.AuxInt
  3814  		_ = v.Args[1]
  3815  		x := v.Args[0]
  3816  		v_1 := v.Args[1]
  3817  		if v_1.Op != OpARM64MOVDconst {
  3818  			break
  3819  		}
  3820  		c := v_1.AuxInt
  3821  		v.reset(OpARM64CMNconst)
  3822  		v.AuxInt = int64(uint64(c) << uint64(d))
  3823  		v.AddArg(x)
  3824  		return true
  3825  	}
  3826  	return false
  3827  }
  3828  func rewriteValueARM64_OpARM64CMNshiftRA_0(v *Value) bool {
  3829  	b := v.Block
  3830  	// match: (CMNshiftRA (MOVDconst [c]) x [d])
  3831  	// cond:
  3832  	// result: (CMNconst [c] (SRAconst <x.Type> x [d]))
  3833  	for {
  3834  		d := v.AuxInt
  3835  		x := v.Args[1]
  3836  		v_0 := v.Args[0]
  3837  		if v_0.Op != OpARM64MOVDconst {
  3838  			break
  3839  		}
  3840  		c := v_0.AuxInt
  3841  		v.reset(OpARM64CMNconst)
  3842  		v.AuxInt = c
  3843  		v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type)
  3844  		v0.AuxInt = d
  3845  		v0.AddArg(x)
  3846  		v.AddArg(v0)
  3847  		return true
  3848  	}
  3849  	// match: (CMNshiftRA x (MOVDconst [c]) [d])
  3850  	// cond:
  3851  	// result: (CMNconst x [c>>uint64(d)])
  3852  	for {
  3853  		d := v.AuxInt
  3854  		_ = v.Args[1]
  3855  		x := v.Args[0]
  3856  		v_1 := v.Args[1]
  3857  		if v_1.Op != OpARM64MOVDconst {
  3858  			break
  3859  		}
  3860  		c := v_1.AuxInt
  3861  		v.reset(OpARM64CMNconst)
  3862  		v.AuxInt = c >> uint64(d)
  3863  		v.AddArg(x)
  3864  		return true
  3865  	}
  3866  	return false
  3867  }
  3868  func rewriteValueARM64_OpARM64CMNshiftRL_0(v *Value) bool {
  3869  	b := v.Block
  3870  	// match: (CMNshiftRL (MOVDconst [c]) x [d])
  3871  	// cond:
  3872  	// result: (CMNconst [c] (SRLconst <x.Type> x [d]))
  3873  	for {
  3874  		d := v.AuxInt
  3875  		x := v.Args[1]
  3876  		v_0 := v.Args[0]
  3877  		if v_0.Op != OpARM64MOVDconst {
  3878  			break
  3879  		}
  3880  		c := v_0.AuxInt
  3881  		v.reset(OpARM64CMNconst)
  3882  		v.AuxInt = c
  3883  		v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type)
  3884  		v0.AuxInt = d
  3885  		v0.AddArg(x)
  3886  		v.AddArg(v0)
  3887  		return true
  3888  	}
  3889  	// match: (CMNshiftRL x (MOVDconst [c]) [d])
  3890  	// cond:
  3891  	// result: (CMNconst x [int64(uint64(c)>>uint64(d))])
  3892  	for {
  3893  		d := v.AuxInt
  3894  		_ = v.Args[1]
  3895  		x := v.Args[0]
  3896  		v_1 := v.Args[1]
  3897  		if v_1.Op != OpARM64MOVDconst {
  3898  			break
  3899  		}
  3900  		c := v_1.AuxInt
  3901  		v.reset(OpARM64CMNconst)
  3902  		v.AuxInt = int64(uint64(c) >> uint64(d))
  3903  		v.AddArg(x)
  3904  		return true
  3905  	}
  3906  	return false
  3907  }
  3908  func rewriteValueARM64_OpARM64CMP_0(v *Value) bool {
  3909  	b := v.Block
  3910  	// match: (CMP x (MOVDconst [c]))
  3911  	// cond:
  3912  	// result: (CMPconst [c] x)
  3913  	for {
  3914  		_ = v.Args[1]
  3915  		x := v.Args[0]
  3916  		v_1 := v.Args[1]
  3917  		if v_1.Op != OpARM64MOVDconst {
  3918  			break
  3919  		}
  3920  		c := v_1.AuxInt
  3921  		v.reset(OpARM64CMPconst)
  3922  		v.AuxInt = c
  3923  		v.AddArg(x)
  3924  		return true
  3925  	}
  3926  	// match: (CMP (MOVDconst [c]) x)
  3927  	// cond:
  3928  	// result: (InvertFlags (CMPconst [c] x))
  3929  	for {
  3930  		x := v.Args[1]
  3931  		v_0 := v.Args[0]
  3932  		if v_0.Op != OpARM64MOVDconst {
  3933  			break
  3934  		}
  3935  		c := v_0.AuxInt
  3936  		v.reset(OpARM64InvertFlags)
  3937  		v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
  3938  		v0.AuxInt = c
  3939  		v0.AddArg(x)
  3940  		v.AddArg(v0)
  3941  		return true
  3942  	}
  3943  	// match: (CMP x0 x1:(SLLconst [c] y))
  3944  	// cond: clobberIfDead(x1)
  3945  	// result: (CMPshiftLL x0 y [c])
  3946  	for {
  3947  		_ = v.Args[1]
  3948  		x0 := v.Args[0]
  3949  		x1 := v.Args[1]
  3950  		if x1.Op != OpARM64SLLconst {
  3951  			break
  3952  		}
  3953  		c := x1.AuxInt
  3954  		y := x1.Args[0]
  3955  		if !(clobberIfDead(x1)) {
  3956  			break
  3957  		}
  3958  		v.reset(OpARM64CMPshiftLL)
  3959  		v.AuxInt = c
  3960  		v.AddArg(x0)
  3961  		v.AddArg(y)
  3962  		return true
  3963  	}
  3964  	// match: (CMP x0:(SLLconst [c] y) x1)
  3965  	// cond: clobberIfDead(x0)
  3966  	// result: (InvertFlags (CMPshiftLL x1 y [c]))
  3967  	for {
  3968  		x1 := v.Args[1]
  3969  		x0 := v.Args[0]
  3970  		if x0.Op != OpARM64SLLconst {
  3971  			break
  3972  		}
  3973  		c := x0.AuxInt
  3974  		y := x0.Args[0]
  3975  		if !(clobberIfDead(x0)) {
  3976  			break
  3977  		}
  3978  		v.reset(OpARM64InvertFlags)
  3979  		v0 := b.NewValue0(v.Pos, OpARM64CMPshiftLL, types.TypeFlags)
  3980  		v0.AuxInt = c
  3981  		v0.AddArg(x1)
  3982  		v0.AddArg(y)
  3983  		v.AddArg(v0)
  3984  		return true
  3985  	}
  3986  	// match: (CMP x0 x1:(SRLconst [c] y))
  3987  	// cond: clobberIfDead(x1)
  3988  	// result: (CMPshiftRL x0 y [c])
  3989  	for {
  3990  		_ = v.Args[1]
  3991  		x0 := v.Args[0]
  3992  		x1 := v.Args[1]
  3993  		if x1.Op != OpARM64SRLconst {
  3994  			break
  3995  		}
  3996  		c := x1.AuxInt
  3997  		y := x1.Args[0]
  3998  		if !(clobberIfDead(x1)) {
  3999  			break
  4000  		}
  4001  		v.reset(OpARM64CMPshiftRL)
  4002  		v.AuxInt = c
  4003  		v.AddArg(x0)
  4004  		v.AddArg(y)
  4005  		return true
  4006  	}
  4007  	// match: (CMP x0:(SRLconst [c] y) x1)
  4008  	// cond: clobberIfDead(x0)
  4009  	// result: (InvertFlags (CMPshiftRL x1 y [c]))
  4010  	for {
  4011  		x1 := v.Args[1]
  4012  		x0 := v.Args[0]
  4013  		if x0.Op != OpARM64SRLconst {
  4014  			break
  4015  		}
  4016  		c := x0.AuxInt
  4017  		y := x0.Args[0]
  4018  		if !(clobberIfDead(x0)) {
  4019  			break
  4020  		}
  4021  		v.reset(OpARM64InvertFlags)
  4022  		v0 := b.NewValue0(v.Pos, OpARM64CMPshiftRL, types.TypeFlags)
  4023  		v0.AuxInt = c
  4024  		v0.AddArg(x1)
  4025  		v0.AddArg(y)
  4026  		v.AddArg(v0)
  4027  		return true
  4028  	}
  4029  	// match: (CMP x0 x1:(SRAconst [c] y))
  4030  	// cond: clobberIfDead(x1)
  4031  	// result: (CMPshiftRA x0 y [c])
  4032  	for {
  4033  		_ = v.Args[1]
  4034  		x0 := v.Args[0]
  4035  		x1 := v.Args[1]
  4036  		if x1.Op != OpARM64SRAconst {
  4037  			break
  4038  		}
  4039  		c := x1.AuxInt
  4040  		y := x1.Args[0]
  4041  		if !(clobberIfDead(x1)) {
  4042  			break
  4043  		}
  4044  		v.reset(OpARM64CMPshiftRA)
  4045  		v.AuxInt = c
  4046  		v.AddArg(x0)
  4047  		v.AddArg(y)
  4048  		return true
  4049  	}
  4050  	// match: (CMP x0:(SRAconst [c] y) x1)
  4051  	// cond: clobberIfDead(x0)
  4052  	// result: (InvertFlags (CMPshiftRA x1 y [c]))
  4053  	for {
  4054  		x1 := v.Args[1]
  4055  		x0 := v.Args[0]
  4056  		if x0.Op != OpARM64SRAconst {
  4057  			break
  4058  		}
  4059  		c := x0.AuxInt
  4060  		y := x0.Args[0]
  4061  		if !(clobberIfDead(x0)) {
  4062  			break
  4063  		}
  4064  		v.reset(OpARM64InvertFlags)
  4065  		v0 := b.NewValue0(v.Pos, OpARM64CMPshiftRA, types.TypeFlags)
  4066  		v0.AuxInt = c
  4067  		v0.AddArg(x1)
  4068  		v0.AddArg(y)
  4069  		v.AddArg(v0)
  4070  		return true
  4071  	}
  4072  	return false
  4073  }
  4074  func rewriteValueARM64_OpARM64CMPW_0(v *Value) bool {
  4075  	b := v.Block
  4076  	// match: (CMPW x (MOVDconst [c]))
  4077  	// cond:
  4078  	// result: (CMPWconst [int64(int32(c))] x)
  4079  	for {
  4080  		_ = v.Args[1]
  4081  		x := v.Args[0]
  4082  		v_1 := v.Args[1]
  4083  		if v_1.Op != OpARM64MOVDconst {
  4084  			break
  4085  		}
  4086  		c := v_1.AuxInt
  4087  		v.reset(OpARM64CMPWconst)
  4088  		v.AuxInt = int64(int32(c))
  4089  		v.AddArg(x)
  4090  		return true
  4091  	}
  4092  	// match: (CMPW (MOVDconst [c]) x)
  4093  	// cond:
  4094  	// result: (InvertFlags (CMPWconst [int64(int32(c))] x))
  4095  	for {
  4096  		x := v.Args[1]
  4097  		v_0 := v.Args[0]
  4098  		if v_0.Op != OpARM64MOVDconst {
  4099  			break
  4100  		}
  4101  		c := v_0.AuxInt
  4102  		v.reset(OpARM64InvertFlags)
  4103  		v0 := b.NewValue0(v.Pos, OpARM64CMPWconst, types.TypeFlags)
  4104  		v0.AuxInt = int64(int32(c))
  4105  		v0.AddArg(x)
  4106  		v.AddArg(v0)
  4107  		return true
  4108  	}
  4109  	return false
  4110  }
  4111  func rewriteValueARM64_OpARM64CMPWconst_0(v *Value) bool {
  4112  	// match: (CMPWconst (MOVDconst [x]) [y])
  4113  	// cond: int32(x)==int32(y)
  4114  	// result: (FlagEQ)
  4115  	for {
  4116  		y := v.AuxInt
  4117  		v_0 := v.Args[0]
  4118  		if v_0.Op != OpARM64MOVDconst {
  4119  			break
  4120  		}
  4121  		x := v_0.AuxInt
  4122  		if !(int32(x) == int32(y)) {
  4123  			break
  4124  		}
  4125  		v.reset(OpARM64FlagEQ)
  4126  		return true
  4127  	}
  4128  	// match: (CMPWconst (MOVDconst [x]) [y])
  4129  	// cond: int32(x)<int32(y) && uint32(x)<uint32(y)
  4130  	// result: (FlagLT_ULT)
  4131  	for {
  4132  		y := v.AuxInt
  4133  		v_0 := v.Args[0]
  4134  		if v_0.Op != OpARM64MOVDconst {
  4135  			break
  4136  		}
  4137  		x := v_0.AuxInt
  4138  		if !(int32(x) < int32(y) && uint32(x) < uint32(y)) {
  4139  			break
  4140  		}
  4141  		v.reset(OpARM64FlagLT_ULT)
  4142  		return true
  4143  	}
  4144  	// match: (CMPWconst (MOVDconst [x]) [y])
  4145  	// cond: int32(x)<int32(y) && uint32(x)>uint32(y)
  4146  	// result: (FlagLT_UGT)
  4147  	for {
  4148  		y := v.AuxInt
  4149  		v_0 := v.Args[0]
  4150  		if v_0.Op != OpARM64MOVDconst {
  4151  			break
  4152  		}
  4153  		x := v_0.AuxInt
  4154  		if !(int32(x) < int32(y) && uint32(x) > uint32(y)) {
  4155  			break
  4156  		}
  4157  		v.reset(OpARM64FlagLT_UGT)
  4158  		return true
  4159  	}
  4160  	// match: (CMPWconst (MOVDconst [x]) [y])
  4161  	// cond: int32(x)>int32(y) && uint32(x)<uint32(y)
  4162  	// result: (FlagGT_ULT)
  4163  	for {
  4164  		y := v.AuxInt
  4165  		v_0 := v.Args[0]
  4166  		if v_0.Op != OpARM64MOVDconst {
  4167  			break
  4168  		}
  4169  		x := v_0.AuxInt
  4170  		if !(int32(x) > int32(y) && uint32(x) < uint32(y)) {
  4171  			break
  4172  		}
  4173  		v.reset(OpARM64FlagGT_ULT)
  4174  		return true
  4175  	}
  4176  	// match: (CMPWconst (MOVDconst [x]) [y])
  4177  	// cond: int32(x)>int32(y) && uint32(x)>uint32(y)
  4178  	// result: (FlagGT_UGT)
  4179  	for {
  4180  		y := v.AuxInt
  4181  		v_0 := v.Args[0]
  4182  		if v_0.Op != OpARM64MOVDconst {
  4183  			break
  4184  		}
  4185  		x := v_0.AuxInt
  4186  		if !(int32(x) > int32(y) && uint32(x) > uint32(y)) {
  4187  			break
  4188  		}
  4189  		v.reset(OpARM64FlagGT_UGT)
  4190  		return true
  4191  	}
  4192  	// match: (CMPWconst (MOVBUreg _) [c])
  4193  	// cond: 0xff < int32(c)
  4194  	// result: (FlagLT_ULT)
  4195  	for {
  4196  		c := v.AuxInt
  4197  		v_0 := v.Args[0]
  4198  		if v_0.Op != OpARM64MOVBUreg {
  4199  			break
  4200  		}
  4201  		if !(0xff < int32(c)) {
  4202  			break
  4203  		}
  4204  		v.reset(OpARM64FlagLT_ULT)
  4205  		return true
  4206  	}
  4207  	// match: (CMPWconst (MOVHUreg _) [c])
  4208  	// cond: 0xffff < int32(c)
  4209  	// result: (FlagLT_ULT)
  4210  	for {
  4211  		c := v.AuxInt
  4212  		v_0 := v.Args[0]
  4213  		if v_0.Op != OpARM64MOVHUreg {
  4214  			break
  4215  		}
  4216  		if !(0xffff < int32(c)) {
  4217  			break
  4218  		}
  4219  		v.reset(OpARM64FlagLT_ULT)
  4220  		return true
  4221  	}
  4222  	return false
  4223  }
  4224  func rewriteValueARM64_OpARM64CMPconst_0(v *Value) bool {
  4225  	// match: (CMPconst (MOVDconst [x]) [y])
  4226  	// cond: x==y
  4227  	// result: (FlagEQ)
  4228  	for {
  4229  		y := v.AuxInt
  4230  		v_0 := v.Args[0]
  4231  		if v_0.Op != OpARM64MOVDconst {
  4232  			break
  4233  		}
  4234  		x := v_0.AuxInt
  4235  		if !(x == y) {
  4236  			break
  4237  		}
  4238  		v.reset(OpARM64FlagEQ)
  4239  		return true
  4240  	}
  4241  	// match: (CMPconst (MOVDconst [x]) [y])
  4242  	// cond: x<y && uint64(x)<uint64(y)
  4243  	// result: (FlagLT_ULT)
  4244  	for {
  4245  		y := v.AuxInt
  4246  		v_0 := v.Args[0]
  4247  		if v_0.Op != OpARM64MOVDconst {
  4248  			break
  4249  		}
  4250  		x := v_0.AuxInt
  4251  		if !(x < y && uint64(x) < uint64(y)) {
  4252  			break
  4253  		}
  4254  		v.reset(OpARM64FlagLT_ULT)
  4255  		return true
  4256  	}
  4257  	// match: (CMPconst (MOVDconst [x]) [y])
  4258  	// cond: x<y && uint64(x)>uint64(y)
  4259  	// result: (FlagLT_UGT)
  4260  	for {
  4261  		y := v.AuxInt
  4262  		v_0 := v.Args[0]
  4263  		if v_0.Op != OpARM64MOVDconst {
  4264  			break
  4265  		}
  4266  		x := v_0.AuxInt
  4267  		if !(x < y && uint64(x) > uint64(y)) {
  4268  			break
  4269  		}
  4270  		v.reset(OpARM64FlagLT_UGT)
  4271  		return true
  4272  	}
  4273  	// match: (CMPconst (MOVDconst [x]) [y])
  4274  	// cond: x>y && uint64(x)<uint64(y)
  4275  	// result: (FlagGT_ULT)
  4276  	for {
  4277  		y := v.AuxInt
  4278  		v_0 := v.Args[0]
  4279  		if v_0.Op != OpARM64MOVDconst {
  4280  			break
  4281  		}
  4282  		x := v_0.AuxInt
  4283  		if !(x > y && uint64(x) < uint64(y)) {
  4284  			break
  4285  		}
  4286  		v.reset(OpARM64FlagGT_ULT)
  4287  		return true
  4288  	}
  4289  	// match: (CMPconst (MOVDconst [x]) [y])
  4290  	// cond: x>y && uint64(x)>uint64(y)
  4291  	// result: (FlagGT_UGT)
  4292  	for {
  4293  		y := v.AuxInt
  4294  		v_0 := v.Args[0]
  4295  		if v_0.Op != OpARM64MOVDconst {
  4296  			break
  4297  		}
  4298  		x := v_0.AuxInt
  4299  		if !(x > y && uint64(x) > uint64(y)) {
  4300  			break
  4301  		}
  4302  		v.reset(OpARM64FlagGT_UGT)
  4303  		return true
  4304  	}
  4305  	// match: (CMPconst (MOVBUreg _) [c])
  4306  	// cond: 0xff < c
  4307  	// result: (FlagLT_ULT)
  4308  	for {
  4309  		c := v.AuxInt
  4310  		v_0 := v.Args[0]
  4311  		if v_0.Op != OpARM64MOVBUreg {
  4312  			break
  4313  		}
  4314  		if !(0xff < c) {
  4315  			break
  4316  		}
  4317  		v.reset(OpARM64FlagLT_ULT)
  4318  		return true
  4319  	}
  4320  	// match: (CMPconst (MOVHUreg _) [c])
  4321  	// cond: 0xffff < c
  4322  	// result: (FlagLT_ULT)
  4323  	for {
  4324  		c := v.AuxInt
  4325  		v_0 := v.Args[0]
  4326  		if v_0.Op != OpARM64MOVHUreg {
  4327  			break
  4328  		}
  4329  		if !(0xffff < c) {
  4330  			break
  4331  		}
  4332  		v.reset(OpARM64FlagLT_ULT)
  4333  		return true
  4334  	}
  4335  	// match: (CMPconst (MOVWUreg _) [c])
  4336  	// cond: 0xffffffff < c
  4337  	// result: (FlagLT_ULT)
  4338  	for {
  4339  		c := v.AuxInt
  4340  		v_0 := v.Args[0]
  4341  		if v_0.Op != OpARM64MOVWUreg {
  4342  			break
  4343  		}
  4344  		if !(0xffffffff < c) {
  4345  			break
  4346  		}
  4347  		v.reset(OpARM64FlagLT_ULT)
  4348  		return true
  4349  	}
  4350  	// match: (CMPconst (ANDconst _ [m]) [n])
  4351  	// cond: 0 <= m && m < n
  4352  	// result: (FlagLT_ULT)
  4353  	for {
  4354  		n := v.AuxInt
  4355  		v_0 := v.Args[0]
  4356  		if v_0.Op != OpARM64ANDconst {
  4357  			break
  4358  		}
  4359  		m := v_0.AuxInt
  4360  		if !(0 <= m && m < n) {
  4361  			break
  4362  		}
  4363  		v.reset(OpARM64FlagLT_ULT)
  4364  		return true
  4365  	}
  4366  	// match: (CMPconst (SRLconst _ [c]) [n])
  4367  	// cond: 0 <= n && 0 < c && c <= 63 && (1<<uint64(64-c)) <= uint64(n)
  4368  	// result: (FlagLT_ULT)
  4369  	for {
  4370  		n := v.AuxInt
  4371  		v_0 := v.Args[0]
  4372  		if v_0.Op != OpARM64SRLconst {
  4373  			break
  4374  		}
  4375  		c := v_0.AuxInt
  4376  		if !(0 <= n && 0 < c && c <= 63 && (1<<uint64(64-c)) <= uint64(n)) {
  4377  			break
  4378  		}
  4379  		v.reset(OpARM64FlagLT_ULT)
  4380  		return true
  4381  	}
  4382  	return false
  4383  }
  4384  func rewriteValueARM64_OpARM64CMPshiftLL_0(v *Value) bool {
  4385  	b := v.Block
  4386  	// match: (CMPshiftLL (MOVDconst [c]) x [d])
  4387  	// cond:
  4388  	// result: (InvertFlags (CMPconst [c] (SLLconst <x.Type> x [d])))
  4389  	for {
  4390  		d := v.AuxInt
  4391  		x := v.Args[1]
  4392  		v_0 := v.Args[0]
  4393  		if v_0.Op != OpARM64MOVDconst {
  4394  			break
  4395  		}
  4396  		c := v_0.AuxInt
  4397  		v.reset(OpARM64InvertFlags)
  4398  		v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
  4399  		v0.AuxInt = c
  4400  		v1 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
  4401  		v1.AuxInt = d
  4402  		v1.AddArg(x)
  4403  		v0.AddArg(v1)
  4404  		v.AddArg(v0)
  4405  		return true
  4406  	}
  4407  	// match: (CMPshiftLL x (MOVDconst [c]) [d])
  4408  	// cond:
  4409  	// result: (CMPconst x [int64(uint64(c)<<uint64(d))])
  4410  	for {
  4411  		d := v.AuxInt
  4412  		_ = v.Args[1]
  4413  		x := v.Args[0]
  4414  		v_1 := v.Args[1]
  4415  		if v_1.Op != OpARM64MOVDconst {
  4416  			break
  4417  		}
  4418  		c := v_1.AuxInt
  4419  		v.reset(OpARM64CMPconst)
  4420  		v.AuxInt = int64(uint64(c) << uint64(d))
  4421  		v.AddArg(x)
  4422  		return true
  4423  	}
  4424  	return false
  4425  }
  4426  func rewriteValueARM64_OpARM64CMPshiftRA_0(v *Value) bool {
  4427  	b := v.Block
  4428  	// match: (CMPshiftRA (MOVDconst [c]) x [d])
  4429  	// cond:
  4430  	// result: (InvertFlags (CMPconst [c] (SRAconst <x.Type> x [d])))
  4431  	for {
  4432  		d := v.AuxInt
  4433  		x := v.Args[1]
  4434  		v_0 := v.Args[0]
  4435  		if v_0.Op != OpARM64MOVDconst {
  4436  			break
  4437  		}
  4438  		c := v_0.AuxInt
  4439  		v.reset(OpARM64InvertFlags)
  4440  		v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
  4441  		v0.AuxInt = c
  4442  		v1 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type)
  4443  		v1.AuxInt = d
  4444  		v1.AddArg(x)
  4445  		v0.AddArg(v1)
  4446  		v.AddArg(v0)
  4447  		return true
  4448  	}
  4449  	// match: (CMPshiftRA x (MOVDconst [c]) [d])
  4450  	// cond:
  4451  	// result: (CMPconst x [c>>uint64(d)])
  4452  	for {
  4453  		d := v.AuxInt
  4454  		_ = v.Args[1]
  4455  		x := v.Args[0]
  4456  		v_1 := v.Args[1]
  4457  		if v_1.Op != OpARM64MOVDconst {
  4458  			break
  4459  		}
  4460  		c := v_1.AuxInt
  4461  		v.reset(OpARM64CMPconst)
  4462  		v.AuxInt = c >> uint64(d)
  4463  		v.AddArg(x)
  4464  		return true
  4465  	}
  4466  	return false
  4467  }
  4468  func rewriteValueARM64_OpARM64CMPshiftRL_0(v *Value) bool {
  4469  	b := v.Block
  4470  	// match: (CMPshiftRL (MOVDconst [c]) x [d])
  4471  	// cond:
  4472  	// result: (InvertFlags (CMPconst [c] (SRLconst <x.Type> x [d])))
  4473  	for {
  4474  		d := v.AuxInt
  4475  		x := v.Args[1]
  4476  		v_0 := v.Args[0]
  4477  		if v_0.Op != OpARM64MOVDconst {
  4478  			break
  4479  		}
  4480  		c := v_0.AuxInt
  4481  		v.reset(OpARM64InvertFlags)
  4482  		v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
  4483  		v0.AuxInt = c
  4484  		v1 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type)
  4485  		v1.AuxInt = d
  4486  		v1.AddArg(x)
  4487  		v0.AddArg(v1)
  4488  		v.AddArg(v0)
  4489  		return true
  4490  	}
  4491  	// match: (CMPshiftRL x (MOVDconst [c]) [d])
  4492  	// cond:
  4493  	// result: (CMPconst x [int64(uint64(c)>>uint64(d))])
  4494  	for {
  4495  		d := v.AuxInt
  4496  		_ = v.Args[1]
  4497  		x := v.Args[0]
  4498  		v_1 := v.Args[1]
  4499  		if v_1.Op != OpARM64MOVDconst {
  4500  			break
  4501  		}
  4502  		c := v_1.AuxInt
  4503  		v.reset(OpARM64CMPconst)
  4504  		v.AuxInt = int64(uint64(c) >> uint64(d))
  4505  		v.AddArg(x)
  4506  		return true
  4507  	}
  4508  	return false
  4509  }
  4510  func rewriteValueARM64_OpARM64CSEL_0(v *Value) bool {
  4511  	// match: (CSEL {cc} x (MOVDconst [0]) flag)
  4512  	// cond:
  4513  	// result: (CSEL0 {cc} x flag)
  4514  	for {
  4515  		cc := v.Aux
  4516  		flag := v.Args[2]
  4517  		x := v.Args[0]
  4518  		v_1 := v.Args[1]
  4519  		if v_1.Op != OpARM64MOVDconst {
  4520  			break
  4521  		}
  4522  		if v_1.AuxInt != 0 {
  4523  			break
  4524  		}
  4525  		v.reset(OpARM64CSEL0)
  4526  		v.Aux = cc
  4527  		v.AddArg(x)
  4528  		v.AddArg(flag)
  4529  		return true
  4530  	}
  4531  	// match: (CSEL {cc} (MOVDconst [0]) y flag)
  4532  	// cond:
  4533  	// result: (CSEL0 {arm64Negate(cc.(Op))} y flag)
  4534  	for {
  4535  		cc := v.Aux
  4536  		flag := v.Args[2]
  4537  		v_0 := v.Args[0]
  4538  		if v_0.Op != OpARM64MOVDconst {
  4539  			break
  4540  		}
  4541  		if v_0.AuxInt != 0 {
  4542  			break
  4543  		}
  4544  		y := v.Args[1]
  4545  		v.reset(OpARM64CSEL0)
  4546  		v.Aux = arm64Negate(cc.(Op))
  4547  		v.AddArg(y)
  4548  		v.AddArg(flag)
  4549  		return true
  4550  	}
  4551  	// match: (CSEL {cc} x y (InvertFlags cmp))
  4552  	// cond:
  4553  	// result: (CSEL {arm64Invert(cc.(Op))} x y cmp)
  4554  	for {
  4555  		cc := v.Aux
  4556  		_ = v.Args[2]
  4557  		x := v.Args[0]
  4558  		y := v.Args[1]
  4559  		v_2 := v.Args[2]
  4560  		if v_2.Op != OpARM64InvertFlags {
  4561  			break
  4562  		}
  4563  		cmp := v_2.Args[0]
  4564  		v.reset(OpARM64CSEL)
  4565  		v.Aux = arm64Invert(cc.(Op))
  4566  		v.AddArg(x)
  4567  		v.AddArg(y)
  4568  		v.AddArg(cmp)
  4569  		return true
  4570  	}
  4571  	// match: (CSEL {cc} x _ flag)
  4572  	// cond: ccARM64Eval(cc, flag) > 0
  4573  	// result: x
  4574  	for {
  4575  		cc := v.Aux
  4576  		flag := v.Args[2]
  4577  		x := v.Args[0]
  4578  		if !(ccARM64Eval(cc, flag) > 0) {
  4579  			break
  4580  		}
  4581  		v.reset(OpCopy)
  4582  		v.Type = x.Type
  4583  		v.AddArg(x)
  4584  		return true
  4585  	}
  4586  	// match: (CSEL {cc} _ y flag)
  4587  	// cond: ccARM64Eval(cc, flag) < 0
  4588  	// result: y
  4589  	for {
  4590  		cc := v.Aux
  4591  		flag := v.Args[2]
  4592  		y := v.Args[1]
  4593  		if !(ccARM64Eval(cc, flag) < 0) {
  4594  			break
  4595  		}
  4596  		v.reset(OpCopy)
  4597  		v.Type = y.Type
  4598  		v.AddArg(y)
  4599  		return true
  4600  	}
  4601  	// match: (CSEL {cc} x y (CMPWconst [0] boolval))
  4602  	// cond: cc.(Op) == OpARM64NotEqual && flagArg(boolval) != nil
  4603  	// result: (CSEL {boolval.Op} x y flagArg(boolval))
  4604  	for {
  4605  		cc := v.Aux
  4606  		_ = v.Args[2]
  4607  		x := v.Args[0]
  4608  		y := v.Args[1]
  4609  		v_2 := v.Args[2]
  4610  		if v_2.Op != OpARM64CMPWconst {
  4611  			break
  4612  		}
  4613  		if v_2.AuxInt != 0 {
  4614  			break
  4615  		}
  4616  		boolval := v_2.Args[0]
  4617  		if !(cc.(Op) == OpARM64NotEqual && flagArg(boolval) != nil) {
  4618  			break
  4619  		}
  4620  		v.reset(OpARM64CSEL)
  4621  		v.Aux = boolval.Op
  4622  		v.AddArg(x)
  4623  		v.AddArg(y)
  4624  		v.AddArg(flagArg(boolval))
  4625  		return true
  4626  	}
  4627  	// match: (CSEL {cc} x y (CMPWconst [0] boolval))
  4628  	// cond: cc.(Op) == OpARM64Equal && flagArg(boolval) != nil
  4629  	// result: (CSEL {arm64Negate(boolval.Op)} x y flagArg(boolval))
  4630  	for {
  4631  		cc := v.Aux
  4632  		_ = v.Args[2]
  4633  		x := v.Args[0]
  4634  		y := v.Args[1]
  4635  		v_2 := v.Args[2]
  4636  		if v_2.Op != OpARM64CMPWconst {
  4637  			break
  4638  		}
  4639  		if v_2.AuxInt != 0 {
  4640  			break
  4641  		}
  4642  		boolval := v_2.Args[0]
  4643  		if !(cc.(Op) == OpARM64Equal && flagArg(boolval) != nil) {
  4644  			break
  4645  		}
  4646  		v.reset(OpARM64CSEL)
  4647  		v.Aux = arm64Negate(boolval.Op)
  4648  		v.AddArg(x)
  4649  		v.AddArg(y)
  4650  		v.AddArg(flagArg(boolval))
  4651  		return true
  4652  	}
  4653  	return false
  4654  }
  4655  func rewriteValueARM64_OpARM64CSEL0_0(v *Value) bool {
  4656  	// match: (CSEL0 {cc} x (InvertFlags cmp))
  4657  	// cond:
  4658  	// result: (CSEL0 {arm64Invert(cc.(Op))} x cmp)
  4659  	for {
  4660  		cc := v.Aux
  4661  		_ = v.Args[1]
  4662  		x := v.Args[0]
  4663  		v_1 := v.Args[1]
  4664  		if v_1.Op != OpARM64InvertFlags {
  4665  			break
  4666  		}
  4667  		cmp := v_1.Args[0]
  4668  		v.reset(OpARM64CSEL0)
  4669  		v.Aux = arm64Invert(cc.(Op))
  4670  		v.AddArg(x)
  4671  		v.AddArg(cmp)
  4672  		return true
  4673  	}
  4674  	// match: (CSEL0 {cc} x flag)
  4675  	// cond: ccARM64Eval(cc, flag) > 0
  4676  	// result: x
  4677  	for {
  4678  		cc := v.Aux
  4679  		flag := v.Args[1]
  4680  		x := v.Args[0]
  4681  		if !(ccARM64Eval(cc, flag) > 0) {
  4682  			break
  4683  		}
  4684  		v.reset(OpCopy)
  4685  		v.Type = x.Type
  4686  		v.AddArg(x)
  4687  		return true
  4688  	}
  4689  	// match: (CSEL0 {cc} _ flag)
  4690  	// cond: ccARM64Eval(cc, flag) < 0
  4691  	// result: (MOVDconst [0])
  4692  	for {
  4693  		cc := v.Aux
  4694  		flag := v.Args[1]
  4695  		if !(ccARM64Eval(cc, flag) < 0) {
  4696  			break
  4697  		}
  4698  		v.reset(OpARM64MOVDconst)
  4699  		v.AuxInt = 0
  4700  		return true
  4701  	}
  4702  	// match: (CSEL0 {cc} x (CMPWconst [0] boolval))
  4703  	// cond: cc.(Op) == OpARM64NotEqual && flagArg(boolval) != nil
  4704  	// result: (CSEL0 {boolval.Op} x flagArg(boolval))
  4705  	for {
  4706  		cc := v.Aux
  4707  		_ = v.Args[1]
  4708  		x := v.Args[0]
  4709  		v_1 := v.Args[1]
  4710  		if v_1.Op != OpARM64CMPWconst {
  4711  			break
  4712  		}
  4713  		if v_1.AuxInt != 0 {
  4714  			break
  4715  		}
  4716  		boolval := v_1.Args[0]
  4717  		if !(cc.(Op) == OpARM64NotEqual && flagArg(boolval) != nil) {
  4718  			break
  4719  		}
  4720  		v.reset(OpARM64CSEL0)
  4721  		v.Aux = boolval.Op
  4722  		v.AddArg(x)
  4723  		v.AddArg(flagArg(boolval))
  4724  		return true
  4725  	}
  4726  	// match: (CSEL0 {cc} x (CMPWconst [0] boolval))
  4727  	// cond: cc.(Op) == OpARM64Equal && flagArg(boolval) != nil
  4728  	// result: (CSEL0 {arm64Negate(boolval.Op)} x flagArg(boolval))
  4729  	for {
  4730  		cc := v.Aux
  4731  		_ = v.Args[1]
  4732  		x := v.Args[0]
  4733  		v_1 := v.Args[1]
  4734  		if v_1.Op != OpARM64CMPWconst {
  4735  			break
  4736  		}
  4737  		if v_1.AuxInt != 0 {
  4738  			break
  4739  		}
  4740  		boolval := v_1.Args[0]
  4741  		if !(cc.(Op) == OpARM64Equal && flagArg(boolval) != nil) {
  4742  			break
  4743  		}
  4744  		v.reset(OpARM64CSEL0)
  4745  		v.Aux = arm64Negate(boolval.Op)
  4746  		v.AddArg(x)
  4747  		v.AddArg(flagArg(boolval))
  4748  		return true
  4749  	}
  4750  	return false
  4751  }
  4752  func rewriteValueARM64_OpARM64DIV_0(v *Value) bool {
  4753  	// match: (DIV (MOVDconst [c]) (MOVDconst [d]))
  4754  	// cond:
  4755  	// result: (MOVDconst [c/d])
  4756  	for {
  4757  		_ = v.Args[1]
  4758  		v_0 := v.Args[0]
  4759  		if v_0.Op != OpARM64MOVDconst {
  4760  			break
  4761  		}
  4762  		c := v_0.AuxInt
  4763  		v_1 := v.Args[1]
  4764  		if v_1.Op != OpARM64MOVDconst {
  4765  			break
  4766  		}
  4767  		d := v_1.AuxInt
  4768  		v.reset(OpARM64MOVDconst)
  4769  		v.AuxInt = c / d
  4770  		return true
  4771  	}
  4772  	return false
  4773  }
  4774  func rewriteValueARM64_OpARM64DIVW_0(v *Value) bool {
  4775  	// match: (DIVW (MOVDconst [c]) (MOVDconst [d]))
  4776  	// cond:
  4777  	// result: (MOVDconst [int64(int32(c)/int32(d))])
  4778  	for {
  4779  		_ = v.Args[1]
  4780  		v_0 := v.Args[0]
  4781  		if v_0.Op != OpARM64MOVDconst {
  4782  			break
  4783  		}
  4784  		c := v_0.AuxInt
  4785  		v_1 := v.Args[1]
  4786  		if v_1.Op != OpARM64MOVDconst {
  4787  			break
  4788  		}
  4789  		d := v_1.AuxInt
  4790  		v.reset(OpARM64MOVDconst)
  4791  		v.AuxInt = int64(int32(c) / int32(d))
  4792  		return true
  4793  	}
  4794  	return false
  4795  }
  4796  func rewriteValueARM64_OpARM64EON_0(v *Value) bool {
  4797  	// match: (EON x (MOVDconst [c]))
  4798  	// cond:
  4799  	// result: (XORconst [^c] x)
  4800  	for {
  4801  		_ = v.Args[1]
  4802  		x := v.Args[0]
  4803  		v_1 := v.Args[1]
  4804  		if v_1.Op != OpARM64MOVDconst {
  4805  			break
  4806  		}
  4807  		c := v_1.AuxInt
  4808  		v.reset(OpARM64XORconst)
  4809  		v.AuxInt = ^c
  4810  		v.AddArg(x)
  4811  		return true
  4812  	}
  4813  	// match: (EON x x)
  4814  	// cond:
  4815  	// result: (MOVDconst [-1])
  4816  	for {
  4817  		x := v.Args[1]
  4818  		if x != v.Args[0] {
  4819  			break
  4820  		}
  4821  		v.reset(OpARM64MOVDconst)
  4822  		v.AuxInt = -1
  4823  		return true
  4824  	}
  4825  	// match: (EON x0 x1:(SLLconst [c] y))
  4826  	// cond: clobberIfDead(x1)
  4827  	// result: (EONshiftLL x0 y [c])
  4828  	for {
  4829  		_ = v.Args[1]
  4830  		x0 := v.Args[0]
  4831  		x1 := v.Args[1]
  4832  		if x1.Op != OpARM64SLLconst {
  4833  			break
  4834  		}
  4835  		c := x1.AuxInt
  4836  		y := x1.Args[0]
  4837  		if !(clobberIfDead(x1)) {
  4838  			break
  4839  		}
  4840  		v.reset(OpARM64EONshiftLL)
  4841  		v.AuxInt = c
  4842  		v.AddArg(x0)
  4843  		v.AddArg(y)
  4844  		return true
  4845  	}
  4846  	// match: (EON x0 x1:(SRLconst [c] y))
  4847  	// cond: clobberIfDead(x1)
  4848  	// result: (EONshiftRL x0 y [c])
  4849  	for {
  4850  		_ = v.Args[1]
  4851  		x0 := v.Args[0]
  4852  		x1 := v.Args[1]
  4853  		if x1.Op != OpARM64SRLconst {
  4854  			break
  4855  		}
  4856  		c := x1.AuxInt
  4857  		y := x1.Args[0]
  4858  		if !(clobberIfDead(x1)) {
  4859  			break
  4860  		}
  4861  		v.reset(OpARM64EONshiftRL)
  4862  		v.AuxInt = c
  4863  		v.AddArg(x0)
  4864  		v.AddArg(y)
  4865  		return true
  4866  	}
  4867  	// match: (EON x0 x1:(SRAconst [c] y))
  4868  	// cond: clobberIfDead(x1)
  4869  	// result: (EONshiftRA x0 y [c])
  4870  	for {
  4871  		_ = v.Args[1]
  4872  		x0 := v.Args[0]
  4873  		x1 := v.Args[1]
  4874  		if x1.Op != OpARM64SRAconst {
  4875  			break
  4876  		}
  4877  		c := x1.AuxInt
  4878  		y := x1.Args[0]
  4879  		if !(clobberIfDead(x1)) {
  4880  			break
  4881  		}
  4882  		v.reset(OpARM64EONshiftRA)
  4883  		v.AuxInt = c
  4884  		v.AddArg(x0)
  4885  		v.AddArg(y)
  4886  		return true
  4887  	}
  4888  	return false
  4889  }
  4890  func rewriteValueARM64_OpARM64EONshiftLL_0(v *Value) bool {
  4891  	// match: (EONshiftLL x (MOVDconst [c]) [d])
  4892  	// cond:
  4893  	// result: (XORconst x [^int64(uint64(c)<<uint64(d))])
  4894  	for {
  4895  		d := v.AuxInt
  4896  		_ = v.Args[1]
  4897  		x := v.Args[0]
  4898  		v_1 := v.Args[1]
  4899  		if v_1.Op != OpARM64MOVDconst {
  4900  			break
  4901  		}
  4902  		c := v_1.AuxInt
  4903  		v.reset(OpARM64XORconst)
  4904  		v.AuxInt = ^int64(uint64(c) << uint64(d))
  4905  		v.AddArg(x)
  4906  		return true
  4907  	}
  4908  	// match: (EONshiftLL x (SLLconst x [c]) [d])
  4909  	// cond: c==d
  4910  	// result: (MOVDconst [-1])
  4911  	for {
  4912  		d := v.AuxInt
  4913  		_ = v.Args[1]
  4914  		x := v.Args[0]
  4915  		v_1 := v.Args[1]
  4916  		if v_1.Op != OpARM64SLLconst {
  4917  			break
  4918  		}
  4919  		c := v_1.AuxInt
  4920  		if x != v_1.Args[0] {
  4921  			break
  4922  		}
  4923  		if !(c == d) {
  4924  			break
  4925  		}
  4926  		v.reset(OpARM64MOVDconst)
  4927  		v.AuxInt = -1
  4928  		return true
  4929  	}
  4930  	return false
  4931  }
  4932  func rewriteValueARM64_OpARM64EONshiftRA_0(v *Value) bool {
  4933  	// match: (EONshiftRA x (MOVDconst [c]) [d])
  4934  	// cond:
  4935  	// result: (XORconst x [^(c>>uint64(d))])
  4936  	for {
  4937  		d := v.AuxInt
  4938  		_ = v.Args[1]
  4939  		x := v.Args[0]
  4940  		v_1 := v.Args[1]
  4941  		if v_1.Op != OpARM64MOVDconst {
  4942  			break
  4943  		}
  4944  		c := v_1.AuxInt
  4945  		v.reset(OpARM64XORconst)
  4946  		v.AuxInt = ^(c >> uint64(d))
  4947  		v.AddArg(x)
  4948  		return true
  4949  	}
  4950  	// match: (EONshiftRA x (SRAconst x [c]) [d])
  4951  	// cond: c==d
  4952  	// result: (MOVDconst [-1])
  4953  	for {
  4954  		d := v.AuxInt
  4955  		_ = v.Args[1]
  4956  		x := v.Args[0]
  4957  		v_1 := v.Args[1]
  4958  		if v_1.Op != OpARM64SRAconst {
  4959  			break
  4960  		}
  4961  		c := v_1.AuxInt
  4962  		if x != v_1.Args[0] {
  4963  			break
  4964  		}
  4965  		if !(c == d) {
  4966  			break
  4967  		}
  4968  		v.reset(OpARM64MOVDconst)
  4969  		v.AuxInt = -1
  4970  		return true
  4971  	}
  4972  	return false
  4973  }
  4974  func rewriteValueARM64_OpARM64EONshiftRL_0(v *Value) bool {
  4975  	// match: (EONshiftRL x (MOVDconst [c]) [d])
  4976  	// cond:
  4977  	// result: (XORconst x [^int64(uint64(c)>>uint64(d))])
  4978  	for {
  4979  		d := v.AuxInt
  4980  		_ = v.Args[1]
  4981  		x := v.Args[0]
  4982  		v_1 := v.Args[1]
  4983  		if v_1.Op != OpARM64MOVDconst {
  4984  			break
  4985  		}
  4986  		c := v_1.AuxInt
  4987  		v.reset(OpARM64XORconst)
  4988  		v.AuxInt = ^int64(uint64(c) >> uint64(d))
  4989  		v.AddArg(x)
  4990  		return true
  4991  	}
  4992  	// match: (EONshiftRL x (SRLconst x [c]) [d])
  4993  	// cond: c==d
  4994  	// result: (MOVDconst [-1])
  4995  	for {
  4996  		d := v.AuxInt
  4997  		_ = v.Args[1]
  4998  		x := v.Args[0]
  4999  		v_1 := v.Args[1]
  5000  		if v_1.Op != OpARM64SRLconst {
  5001  			break
  5002  		}
  5003  		c := v_1.AuxInt
  5004  		if x != v_1.Args[0] {
  5005  			break
  5006  		}
  5007  		if !(c == d) {
  5008  			break
  5009  		}
  5010  		v.reset(OpARM64MOVDconst)
  5011  		v.AuxInt = -1
  5012  		return true
  5013  	}
  5014  	return false
  5015  }
  5016  func rewriteValueARM64_OpARM64Equal_0(v *Value) bool {
  5017  	// match: (Equal (FlagEQ))
  5018  	// cond:
  5019  	// result: (MOVDconst [1])
  5020  	for {
  5021  		v_0 := v.Args[0]
  5022  		if v_0.Op != OpARM64FlagEQ {
  5023  			break
  5024  		}
  5025  		v.reset(OpARM64MOVDconst)
  5026  		v.AuxInt = 1
  5027  		return true
  5028  	}
  5029  	// match: (Equal (FlagLT_ULT))
  5030  	// cond:
  5031  	// result: (MOVDconst [0])
  5032  	for {
  5033  		v_0 := v.Args[0]
  5034  		if v_0.Op != OpARM64FlagLT_ULT {
  5035  			break
  5036  		}
  5037  		v.reset(OpARM64MOVDconst)
  5038  		v.AuxInt = 0
  5039  		return true
  5040  	}
  5041  	// match: (Equal (FlagLT_UGT))
  5042  	// cond:
  5043  	// result: (MOVDconst [0])
  5044  	for {
  5045  		v_0 := v.Args[0]
  5046  		if v_0.Op != OpARM64FlagLT_UGT {
  5047  			break
  5048  		}
  5049  		v.reset(OpARM64MOVDconst)
  5050  		v.AuxInt = 0
  5051  		return true
  5052  	}
  5053  	// match: (Equal (FlagGT_ULT))
  5054  	// cond:
  5055  	// result: (MOVDconst [0])
  5056  	for {
  5057  		v_0 := v.Args[0]
  5058  		if v_0.Op != OpARM64FlagGT_ULT {
  5059  			break
  5060  		}
  5061  		v.reset(OpARM64MOVDconst)
  5062  		v.AuxInt = 0
  5063  		return true
  5064  	}
  5065  	// match: (Equal (FlagGT_UGT))
  5066  	// cond:
  5067  	// result: (MOVDconst [0])
  5068  	for {
  5069  		v_0 := v.Args[0]
  5070  		if v_0.Op != OpARM64FlagGT_UGT {
  5071  			break
  5072  		}
  5073  		v.reset(OpARM64MOVDconst)
  5074  		v.AuxInt = 0
  5075  		return true
  5076  	}
  5077  	// match: (Equal (InvertFlags x))
  5078  	// cond:
  5079  	// result: (Equal x)
  5080  	for {
  5081  		v_0 := v.Args[0]
  5082  		if v_0.Op != OpARM64InvertFlags {
  5083  			break
  5084  		}
  5085  		x := v_0.Args[0]
  5086  		v.reset(OpARM64Equal)
  5087  		v.AddArg(x)
  5088  		return true
  5089  	}
  5090  	return false
  5091  }
  5092  func rewriteValueARM64_OpARM64FADDD_0(v *Value) bool {
  5093  	// match: (FADDD a (FMULD x y))
  5094  	// cond:
  5095  	// result: (FMADDD a x y)
  5096  	for {
  5097  		_ = v.Args[1]
  5098  		a := v.Args[0]
  5099  		v_1 := v.Args[1]
  5100  		if v_1.Op != OpARM64FMULD {
  5101  			break
  5102  		}
  5103  		y := v_1.Args[1]
  5104  		x := v_1.Args[0]
  5105  		v.reset(OpARM64FMADDD)
  5106  		v.AddArg(a)
  5107  		v.AddArg(x)
  5108  		v.AddArg(y)
  5109  		return true
  5110  	}
  5111  	// match: (FADDD (FMULD x y) a)
  5112  	// cond:
  5113  	// result: (FMADDD a x y)
  5114  	for {
  5115  		a := v.Args[1]
  5116  		v_0 := v.Args[0]
  5117  		if v_0.Op != OpARM64FMULD {
  5118  			break
  5119  		}
  5120  		y := v_0.Args[1]
  5121  		x := v_0.Args[0]
  5122  		v.reset(OpARM64FMADDD)
  5123  		v.AddArg(a)
  5124  		v.AddArg(x)
  5125  		v.AddArg(y)
  5126  		return true
  5127  	}
  5128  	// match: (FADDD a (FNMULD x y))
  5129  	// cond:
  5130  	// result: (FMSUBD a x y)
  5131  	for {
  5132  		_ = v.Args[1]
  5133  		a := v.Args[0]
  5134  		v_1 := v.Args[1]
  5135  		if v_1.Op != OpARM64FNMULD {
  5136  			break
  5137  		}
  5138  		y := v_1.Args[1]
  5139  		x := v_1.Args[0]
  5140  		v.reset(OpARM64FMSUBD)
  5141  		v.AddArg(a)
  5142  		v.AddArg(x)
  5143  		v.AddArg(y)
  5144  		return true
  5145  	}
  5146  	// match: (FADDD (FNMULD x y) a)
  5147  	// cond:
  5148  	// result: (FMSUBD a x y)
  5149  	for {
  5150  		a := v.Args[1]
  5151  		v_0 := v.Args[0]
  5152  		if v_0.Op != OpARM64FNMULD {
  5153  			break
  5154  		}
  5155  		y := v_0.Args[1]
  5156  		x := v_0.Args[0]
  5157  		v.reset(OpARM64FMSUBD)
  5158  		v.AddArg(a)
  5159  		v.AddArg(x)
  5160  		v.AddArg(y)
  5161  		return true
  5162  	}
  5163  	return false
  5164  }
  5165  func rewriteValueARM64_OpARM64FADDS_0(v *Value) bool {
  5166  	// match: (FADDS a (FMULS x y))
  5167  	// cond:
  5168  	// result: (FMADDS a x y)
  5169  	for {
  5170  		_ = v.Args[1]
  5171  		a := v.Args[0]
  5172  		v_1 := v.Args[1]
  5173  		if v_1.Op != OpARM64FMULS {
  5174  			break
  5175  		}
  5176  		y := v_1.Args[1]
  5177  		x := v_1.Args[0]
  5178  		v.reset(OpARM64FMADDS)
  5179  		v.AddArg(a)
  5180  		v.AddArg(x)
  5181  		v.AddArg(y)
  5182  		return true
  5183  	}
  5184  	// match: (FADDS (FMULS x y) a)
  5185  	// cond:
  5186  	// result: (FMADDS a x y)
  5187  	for {
  5188  		a := v.Args[1]
  5189  		v_0 := v.Args[0]
  5190  		if v_0.Op != OpARM64FMULS {
  5191  			break
  5192  		}
  5193  		y := v_0.Args[1]
  5194  		x := v_0.Args[0]
  5195  		v.reset(OpARM64FMADDS)
  5196  		v.AddArg(a)
  5197  		v.AddArg(x)
  5198  		v.AddArg(y)
  5199  		return true
  5200  	}
  5201  	// match: (FADDS a (FNMULS x y))
  5202  	// cond:
  5203  	// result: (FMSUBS a x y)
  5204  	for {
  5205  		_ = v.Args[1]
  5206  		a := v.Args[0]
  5207  		v_1 := v.Args[1]
  5208  		if v_1.Op != OpARM64FNMULS {
  5209  			break
  5210  		}
  5211  		y := v_1.Args[1]
  5212  		x := v_1.Args[0]
  5213  		v.reset(OpARM64FMSUBS)
  5214  		v.AddArg(a)
  5215  		v.AddArg(x)
  5216  		v.AddArg(y)
  5217  		return true
  5218  	}
  5219  	// match: (FADDS (FNMULS x y) a)
  5220  	// cond:
  5221  	// result: (FMSUBS a x y)
  5222  	for {
  5223  		a := v.Args[1]
  5224  		v_0 := v.Args[0]
  5225  		if v_0.Op != OpARM64FNMULS {
  5226  			break
  5227  		}
  5228  		y := v_0.Args[1]
  5229  		x := v_0.Args[0]
  5230  		v.reset(OpARM64FMSUBS)
  5231  		v.AddArg(a)
  5232  		v.AddArg(x)
  5233  		v.AddArg(y)
  5234  		return true
  5235  	}
  5236  	return false
  5237  }
  5238  func rewriteValueARM64_OpARM64FCMPD_0(v *Value) bool {
  5239  	b := v.Block
  5240  	// match: (FCMPD x (FMOVDconst [0]))
  5241  	// cond:
  5242  	// result: (FCMPD0 x)
  5243  	for {
  5244  		_ = v.Args[1]
  5245  		x := v.Args[0]
  5246  		v_1 := v.Args[1]
  5247  		if v_1.Op != OpARM64FMOVDconst {
  5248  			break
  5249  		}
  5250  		if v_1.AuxInt != 0 {
  5251  			break
  5252  		}
  5253  		v.reset(OpARM64FCMPD0)
  5254  		v.AddArg(x)
  5255  		return true
  5256  	}
  5257  	// match: (FCMPD (FMOVDconst [0]) x)
  5258  	// cond:
  5259  	// result: (InvertFlags (FCMPD0 x))
  5260  	for {
  5261  		x := v.Args[1]
  5262  		v_0 := v.Args[0]
  5263  		if v_0.Op != OpARM64FMOVDconst {
  5264  			break
  5265  		}
  5266  		if v_0.AuxInt != 0 {
  5267  			break
  5268  		}
  5269  		v.reset(OpARM64InvertFlags)
  5270  		v0 := b.NewValue0(v.Pos, OpARM64FCMPD0, types.TypeFlags)
  5271  		v0.AddArg(x)
  5272  		v.AddArg(v0)
  5273  		return true
  5274  	}
  5275  	return false
  5276  }
  5277  func rewriteValueARM64_OpARM64FCMPS_0(v *Value) bool {
  5278  	b := v.Block
  5279  	// match: (FCMPS x (FMOVSconst [0]))
  5280  	// cond:
  5281  	// result: (FCMPS0 x)
  5282  	for {
  5283  		_ = v.Args[1]
  5284  		x := v.Args[0]
  5285  		v_1 := v.Args[1]
  5286  		if v_1.Op != OpARM64FMOVSconst {
  5287  			break
  5288  		}
  5289  		if v_1.AuxInt != 0 {
  5290  			break
  5291  		}
  5292  		v.reset(OpARM64FCMPS0)
  5293  		v.AddArg(x)
  5294  		return true
  5295  	}
  5296  	// match: (FCMPS (FMOVSconst [0]) x)
  5297  	// cond:
  5298  	// result: (InvertFlags (FCMPS0 x))
  5299  	for {
  5300  		x := v.Args[1]
  5301  		v_0 := v.Args[0]
  5302  		if v_0.Op != OpARM64FMOVSconst {
  5303  			break
  5304  		}
  5305  		if v_0.AuxInt != 0 {
  5306  			break
  5307  		}
  5308  		v.reset(OpARM64InvertFlags)
  5309  		v0 := b.NewValue0(v.Pos, OpARM64FCMPS0, types.TypeFlags)
  5310  		v0.AddArg(x)
  5311  		v.AddArg(v0)
  5312  		return true
  5313  	}
  5314  	return false
  5315  }
  5316  func rewriteValueARM64_OpARM64FMOVDfpgp_0(v *Value) bool {
  5317  	b := v.Block
  5318  	// match: (FMOVDfpgp <t> (Arg [off] {sym}))
  5319  	// cond:
  5320  	// result: @b.Func.Entry (Arg <t> [off] {sym})
  5321  	for {
  5322  		t := v.Type
  5323  		v_0 := v.Args[0]
  5324  		if v_0.Op != OpArg {
  5325  			break
  5326  		}
  5327  		off := v_0.AuxInt
  5328  		sym := v_0.Aux
  5329  		b = b.Func.Entry
  5330  		v0 := b.NewValue0(v.Pos, OpArg, t)
  5331  		v.reset(OpCopy)
  5332  		v.AddArg(v0)
  5333  		v0.AuxInt = off
  5334  		v0.Aux = sym
  5335  		return true
  5336  	}
  5337  	return false
  5338  }
  5339  func rewriteValueARM64_OpARM64FMOVDgpfp_0(v *Value) bool {
  5340  	b := v.Block
  5341  	// match: (FMOVDgpfp <t> (Arg [off] {sym}))
  5342  	// cond:
  5343  	// result: @b.Func.Entry (Arg <t> [off] {sym})
  5344  	for {
  5345  		t := v.Type
  5346  		v_0 := v.Args[0]
  5347  		if v_0.Op != OpArg {
  5348  			break
  5349  		}
  5350  		off := v_0.AuxInt
  5351  		sym := v_0.Aux
  5352  		b = b.Func.Entry
  5353  		v0 := b.NewValue0(v.Pos, OpArg, t)
  5354  		v.reset(OpCopy)
  5355  		v.AddArg(v0)
  5356  		v0.AuxInt = off
  5357  		v0.Aux = sym
  5358  		return true
  5359  	}
  5360  	return false
  5361  }
  5362  func rewriteValueARM64_OpARM64FMOVDload_0(v *Value) bool {
  5363  	b := v.Block
  5364  	config := b.Func.Config
  5365  	// match: (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr val _))
  5366  	// cond:
  5367  	// result: (FMOVDgpfp val)
  5368  	for {
  5369  		off := v.AuxInt
  5370  		sym := v.Aux
  5371  		_ = v.Args[1]
  5372  		ptr := v.Args[0]
  5373  		v_1 := v.Args[1]
  5374  		if v_1.Op != OpARM64MOVDstore {
  5375  			break
  5376  		}
  5377  		if v_1.AuxInt != off {
  5378  			break
  5379  		}
  5380  		if v_1.Aux != sym {
  5381  			break
  5382  		}
  5383  		_ = v_1.Args[2]
  5384  		if ptr != v_1.Args[0] {
  5385  			break
  5386  		}
  5387  		val := v_1.Args[1]
  5388  		v.reset(OpARM64FMOVDgpfp)
  5389  		v.AddArg(val)
  5390  		return true
  5391  	}
  5392  	// match: (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem)
  5393  	// cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  5394  	// result: (FMOVDload [off1+off2] {sym} ptr mem)
  5395  	for {
  5396  		off1 := v.AuxInt
  5397  		sym := v.Aux
  5398  		mem := v.Args[1]
  5399  		v_0 := v.Args[0]
  5400  		if v_0.Op != OpARM64ADDconst {
  5401  			break
  5402  		}
  5403  		off2 := v_0.AuxInt
  5404  		ptr := v_0.Args[0]
  5405  		if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  5406  			break
  5407  		}
  5408  		v.reset(OpARM64FMOVDload)
  5409  		v.AuxInt = off1 + off2
  5410  		v.Aux = sym
  5411  		v.AddArg(ptr)
  5412  		v.AddArg(mem)
  5413  		return true
  5414  	}
  5415  	// match: (FMOVDload [off] {sym} (ADD ptr idx) mem)
  5416  	// cond: off == 0 && sym == nil
  5417  	// result: (FMOVDloadidx ptr idx mem)
  5418  	for {
  5419  		off := v.AuxInt
  5420  		sym := v.Aux
  5421  		mem := v.Args[1]
  5422  		v_0 := v.Args[0]
  5423  		if v_0.Op != OpARM64ADD {
  5424  			break
  5425  		}
  5426  		idx := v_0.Args[1]
  5427  		ptr := v_0.Args[0]
  5428  		if !(off == 0 && sym == nil) {
  5429  			break
  5430  		}
  5431  		v.reset(OpARM64FMOVDloadidx)
  5432  		v.AddArg(ptr)
  5433  		v.AddArg(idx)
  5434  		v.AddArg(mem)
  5435  		return true
  5436  	}
  5437  	// match: (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
  5438  	// cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  5439  	// result: (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
  5440  	for {
  5441  		off1 := v.AuxInt
  5442  		sym1 := v.Aux
  5443  		mem := v.Args[1]
  5444  		v_0 := v.Args[0]
  5445  		if v_0.Op != OpARM64MOVDaddr {
  5446  			break
  5447  		}
  5448  		off2 := v_0.AuxInt
  5449  		sym2 := v_0.Aux
  5450  		ptr := v_0.Args[0]
  5451  		if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  5452  			break
  5453  		}
  5454  		v.reset(OpARM64FMOVDload)
  5455  		v.AuxInt = off1 + off2
  5456  		v.Aux = mergeSym(sym1, sym2)
  5457  		v.AddArg(ptr)
  5458  		v.AddArg(mem)
  5459  		return true
  5460  	}
  5461  	return false
  5462  }
  5463  func rewriteValueARM64_OpARM64FMOVDloadidx_0(v *Value) bool {
  5464  	// match: (FMOVDloadidx ptr (MOVDconst [c]) mem)
  5465  	// cond:
  5466  	// result: (FMOVDload [c] ptr mem)
  5467  	for {
  5468  		mem := v.Args[2]
  5469  		ptr := v.Args[0]
  5470  		v_1 := v.Args[1]
  5471  		if v_1.Op != OpARM64MOVDconst {
  5472  			break
  5473  		}
  5474  		c := v_1.AuxInt
  5475  		v.reset(OpARM64FMOVDload)
  5476  		v.AuxInt = c
  5477  		v.AddArg(ptr)
  5478  		v.AddArg(mem)
  5479  		return true
  5480  	}
  5481  	// match: (FMOVDloadidx (MOVDconst [c]) ptr mem)
  5482  	// cond:
  5483  	// result: (FMOVDload [c] ptr mem)
  5484  	for {
  5485  		mem := v.Args[2]
  5486  		v_0 := v.Args[0]
  5487  		if v_0.Op != OpARM64MOVDconst {
  5488  			break
  5489  		}
  5490  		c := v_0.AuxInt
  5491  		ptr := v.Args[1]
  5492  		v.reset(OpARM64FMOVDload)
  5493  		v.AuxInt = c
  5494  		v.AddArg(ptr)
  5495  		v.AddArg(mem)
  5496  		return true
  5497  	}
  5498  	return false
  5499  }
  5500  func rewriteValueARM64_OpARM64FMOVDstore_0(v *Value) bool {
  5501  	b := v.Block
  5502  	config := b.Func.Config
  5503  	// match: (FMOVDstore [off] {sym} ptr (FMOVDgpfp val) mem)
  5504  	// cond:
  5505  	// result: (MOVDstore [off] {sym} ptr val mem)
  5506  	for {
  5507  		off := v.AuxInt
  5508  		sym := v.Aux
  5509  		mem := v.Args[2]
  5510  		ptr := v.Args[0]
  5511  		v_1 := v.Args[1]
  5512  		if v_1.Op != OpARM64FMOVDgpfp {
  5513  			break
  5514  		}
  5515  		val := v_1.Args[0]
  5516  		v.reset(OpARM64MOVDstore)
  5517  		v.AuxInt = off
  5518  		v.Aux = sym
  5519  		v.AddArg(ptr)
  5520  		v.AddArg(val)
  5521  		v.AddArg(mem)
  5522  		return true
  5523  	}
  5524  	// match: (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem)
  5525  	// cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  5526  	// result: (FMOVDstore [off1+off2] {sym} ptr val mem)
  5527  	for {
  5528  		off1 := v.AuxInt
  5529  		sym := v.Aux
  5530  		mem := v.Args[2]
  5531  		v_0 := v.Args[0]
  5532  		if v_0.Op != OpARM64ADDconst {
  5533  			break
  5534  		}
  5535  		off2 := v_0.AuxInt
  5536  		ptr := v_0.Args[0]
  5537  		val := v.Args[1]
  5538  		if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  5539  			break
  5540  		}
  5541  		v.reset(OpARM64FMOVDstore)
  5542  		v.AuxInt = off1 + off2
  5543  		v.Aux = sym
  5544  		v.AddArg(ptr)
  5545  		v.AddArg(val)
  5546  		v.AddArg(mem)
  5547  		return true
  5548  	}
  5549  	// match: (FMOVDstore [off] {sym} (ADD ptr idx) val mem)
  5550  	// cond: off == 0 && sym == nil
  5551  	// result: (FMOVDstoreidx ptr idx val mem)
  5552  	for {
  5553  		off := v.AuxInt
  5554  		sym := v.Aux
  5555  		mem := v.Args[2]
  5556  		v_0 := v.Args[0]
  5557  		if v_0.Op != OpARM64ADD {
  5558  			break
  5559  		}
  5560  		idx := v_0.Args[1]
  5561  		ptr := v_0.Args[0]
  5562  		val := v.Args[1]
  5563  		if !(off == 0 && sym == nil) {
  5564  			break
  5565  		}
  5566  		v.reset(OpARM64FMOVDstoreidx)
  5567  		v.AddArg(ptr)
  5568  		v.AddArg(idx)
  5569  		v.AddArg(val)
  5570  		v.AddArg(mem)
  5571  		return true
  5572  	}
  5573  	// match: (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
  5574  	// cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  5575  	// result: (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
  5576  	for {
  5577  		off1 := v.AuxInt
  5578  		sym1 := v.Aux
  5579  		mem := v.Args[2]
  5580  		v_0 := v.Args[0]
  5581  		if v_0.Op != OpARM64MOVDaddr {
  5582  			break
  5583  		}
  5584  		off2 := v_0.AuxInt
  5585  		sym2 := v_0.Aux
  5586  		ptr := v_0.Args[0]
  5587  		val := v.Args[1]
  5588  		if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  5589  			break
  5590  		}
  5591  		v.reset(OpARM64FMOVDstore)
  5592  		v.AuxInt = off1 + off2
  5593  		v.Aux = mergeSym(sym1, sym2)
  5594  		v.AddArg(ptr)
  5595  		v.AddArg(val)
  5596  		v.AddArg(mem)
  5597  		return true
  5598  	}
  5599  	return false
  5600  }
  5601  func rewriteValueARM64_OpARM64FMOVDstoreidx_0(v *Value) bool {
  5602  	// match: (FMOVDstoreidx ptr (MOVDconst [c]) val mem)
  5603  	// cond:
  5604  	// result: (FMOVDstore [c] ptr val mem)
  5605  	for {
  5606  		mem := v.Args[3]
  5607  		ptr := v.Args[0]
  5608  		v_1 := v.Args[1]
  5609  		if v_1.Op != OpARM64MOVDconst {
  5610  			break
  5611  		}
  5612  		c := v_1.AuxInt
  5613  		val := v.Args[2]
  5614  		v.reset(OpARM64FMOVDstore)
  5615  		v.AuxInt = c
  5616  		v.AddArg(ptr)
  5617  		v.AddArg(val)
  5618  		v.AddArg(mem)
  5619  		return true
  5620  	}
  5621  	// match: (FMOVDstoreidx (MOVDconst [c]) idx val mem)
  5622  	// cond:
  5623  	// result: (FMOVDstore [c] idx val mem)
  5624  	for {
  5625  		mem := v.Args[3]
  5626  		v_0 := v.Args[0]
  5627  		if v_0.Op != OpARM64MOVDconst {
  5628  			break
  5629  		}
  5630  		c := v_0.AuxInt
  5631  		idx := v.Args[1]
  5632  		val := v.Args[2]
  5633  		v.reset(OpARM64FMOVDstore)
  5634  		v.AuxInt = c
  5635  		v.AddArg(idx)
  5636  		v.AddArg(val)
  5637  		v.AddArg(mem)
  5638  		return true
  5639  	}
  5640  	return false
  5641  }
  5642  func rewriteValueARM64_OpARM64FMOVSload_0(v *Value) bool {
  5643  	b := v.Block
  5644  	config := b.Func.Config
  5645  	// match: (FMOVSload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _))
  5646  	// cond:
  5647  	// result: (FMOVSgpfp val)
  5648  	for {
  5649  		off := v.AuxInt
  5650  		sym := v.Aux
  5651  		_ = v.Args[1]
  5652  		ptr := v.Args[0]
  5653  		v_1 := v.Args[1]
  5654  		if v_1.Op != OpARM64MOVWstore {
  5655  			break
  5656  		}
  5657  		if v_1.AuxInt != off {
  5658  			break
  5659  		}
  5660  		if v_1.Aux != sym {
  5661  			break
  5662  		}
  5663  		_ = v_1.Args[2]
  5664  		if ptr != v_1.Args[0] {
  5665  			break
  5666  		}
  5667  		val := v_1.Args[1]
  5668  		v.reset(OpARM64FMOVSgpfp)
  5669  		v.AddArg(val)
  5670  		return true
  5671  	}
  5672  	// match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem)
  5673  	// cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  5674  	// result: (FMOVSload [off1+off2] {sym} ptr mem)
  5675  	for {
  5676  		off1 := v.AuxInt
  5677  		sym := v.Aux
  5678  		mem := v.Args[1]
  5679  		v_0 := v.Args[0]
  5680  		if v_0.Op != OpARM64ADDconst {
  5681  			break
  5682  		}
  5683  		off2 := v_0.AuxInt
  5684  		ptr := v_0.Args[0]
  5685  		if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  5686  			break
  5687  		}
  5688  		v.reset(OpARM64FMOVSload)
  5689  		v.AuxInt = off1 + off2
  5690  		v.Aux = sym
  5691  		v.AddArg(ptr)
  5692  		v.AddArg(mem)
  5693  		return true
  5694  	}
  5695  	// match: (FMOVSload [off] {sym} (ADD ptr idx) mem)
  5696  	// cond: off == 0 && sym == nil
  5697  	// result: (FMOVSloadidx ptr idx mem)
  5698  	for {
  5699  		off := v.AuxInt
  5700  		sym := v.Aux
  5701  		mem := v.Args[1]
  5702  		v_0 := v.Args[0]
  5703  		if v_0.Op != OpARM64ADD {
  5704  			break
  5705  		}
  5706  		idx := v_0.Args[1]
  5707  		ptr := v_0.Args[0]
  5708  		if !(off == 0 && sym == nil) {
  5709  			break
  5710  		}
  5711  		v.reset(OpARM64FMOVSloadidx)
  5712  		v.AddArg(ptr)
  5713  		v.AddArg(idx)
  5714  		v.AddArg(mem)
  5715  		return true
  5716  	}
  5717  	// match: (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
  5718  	// cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  5719  	// result: (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
  5720  	for {
  5721  		off1 := v.AuxInt
  5722  		sym1 := v.Aux
  5723  		mem := v.Args[1]
  5724  		v_0 := v.Args[0]
  5725  		if v_0.Op != OpARM64MOVDaddr {
  5726  			break
  5727  		}
  5728  		off2 := v_0.AuxInt
  5729  		sym2 := v_0.Aux
  5730  		ptr := v_0.Args[0]
  5731  		if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  5732  			break
  5733  		}
  5734  		v.reset(OpARM64FMOVSload)
  5735  		v.AuxInt = off1 + off2
  5736  		v.Aux = mergeSym(sym1, sym2)
  5737  		v.AddArg(ptr)
  5738  		v.AddArg(mem)
  5739  		return true
  5740  	}
  5741  	return false
  5742  }
  5743  func rewriteValueARM64_OpARM64FMOVSloadidx_0(v *Value) bool {
  5744  	// match: (FMOVSloadidx ptr (MOVDconst [c]) mem)
  5745  	// cond:
  5746  	// result: (FMOVSload [c] ptr mem)
  5747  	for {
  5748  		mem := v.Args[2]
  5749  		ptr := v.Args[0]
  5750  		v_1 := v.Args[1]
  5751  		if v_1.Op != OpARM64MOVDconst {
  5752  			break
  5753  		}
  5754  		c := v_1.AuxInt
  5755  		v.reset(OpARM64FMOVSload)
  5756  		v.AuxInt = c
  5757  		v.AddArg(ptr)
  5758  		v.AddArg(mem)
  5759  		return true
  5760  	}
  5761  	// match: (FMOVSloadidx (MOVDconst [c]) ptr mem)
  5762  	// cond:
  5763  	// result: (FMOVSload [c] ptr mem)
  5764  	for {
  5765  		mem := v.Args[2]
  5766  		v_0 := v.Args[0]
  5767  		if v_0.Op != OpARM64MOVDconst {
  5768  			break
  5769  		}
  5770  		c := v_0.AuxInt
  5771  		ptr := v.Args[1]
  5772  		v.reset(OpARM64FMOVSload)
  5773  		v.AuxInt = c
  5774  		v.AddArg(ptr)
  5775  		v.AddArg(mem)
  5776  		return true
  5777  	}
  5778  	return false
  5779  }
  5780  func rewriteValueARM64_OpARM64FMOVSstore_0(v *Value) bool {
  5781  	b := v.Block
  5782  	config := b.Func.Config
  5783  	// match: (FMOVSstore [off] {sym} ptr (FMOVSgpfp val) mem)
  5784  	// cond:
  5785  	// result: (MOVWstore [off] {sym} ptr val mem)
  5786  	for {
  5787  		off := v.AuxInt
  5788  		sym := v.Aux
  5789  		mem := v.Args[2]
  5790  		ptr := v.Args[0]
  5791  		v_1 := v.Args[1]
  5792  		if v_1.Op != OpARM64FMOVSgpfp {
  5793  			break
  5794  		}
  5795  		val := v_1.Args[0]
  5796  		v.reset(OpARM64MOVWstore)
  5797  		v.AuxInt = off
  5798  		v.Aux = sym
  5799  		v.AddArg(ptr)
  5800  		v.AddArg(val)
  5801  		v.AddArg(mem)
  5802  		return true
  5803  	}
  5804  	// match: (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem)
  5805  	// cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  5806  	// result: (FMOVSstore [off1+off2] {sym} ptr val mem)
  5807  	for {
  5808  		off1 := v.AuxInt
  5809  		sym := v.Aux
  5810  		mem := v.Args[2]
  5811  		v_0 := v.Args[0]
  5812  		if v_0.Op != OpARM64ADDconst {
  5813  			break
  5814  		}
  5815  		off2 := v_0.AuxInt
  5816  		ptr := v_0.Args[0]
  5817  		val := v.Args[1]
  5818  		if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  5819  			break
  5820  		}
  5821  		v.reset(OpARM64FMOVSstore)
  5822  		v.AuxInt = off1 + off2
  5823  		v.Aux = sym
  5824  		v.AddArg(ptr)
  5825  		v.AddArg(val)
  5826  		v.AddArg(mem)
  5827  		return true
  5828  	}
  5829  	// match: (FMOVSstore [off] {sym} (ADD ptr idx) val mem)
  5830  	// cond: off == 0 && sym == nil
  5831  	// result: (FMOVSstoreidx ptr idx val mem)
  5832  	for {
  5833  		off := v.AuxInt
  5834  		sym := v.Aux
  5835  		mem := v.Args[2]
  5836  		v_0 := v.Args[0]
  5837  		if v_0.Op != OpARM64ADD {
  5838  			break
  5839  		}
  5840  		idx := v_0.Args[1]
  5841  		ptr := v_0.Args[0]
  5842  		val := v.Args[1]
  5843  		if !(off == 0 && sym == nil) {
  5844  			break
  5845  		}
  5846  		v.reset(OpARM64FMOVSstoreidx)
  5847  		v.AddArg(ptr)
  5848  		v.AddArg(idx)
  5849  		v.AddArg(val)
  5850  		v.AddArg(mem)
  5851  		return true
  5852  	}
  5853  	// match: (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
  5854  	// cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  5855  	// result: (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
  5856  	for {
  5857  		off1 := v.AuxInt
  5858  		sym1 := v.Aux
  5859  		mem := v.Args[2]
  5860  		v_0 := v.Args[0]
  5861  		if v_0.Op != OpARM64MOVDaddr {
  5862  			break
  5863  		}
  5864  		off2 := v_0.AuxInt
  5865  		sym2 := v_0.Aux
  5866  		ptr := v_0.Args[0]
  5867  		val := v.Args[1]
  5868  		if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  5869  			break
  5870  		}
  5871  		v.reset(OpARM64FMOVSstore)
  5872  		v.AuxInt = off1 + off2
  5873  		v.Aux = mergeSym(sym1, sym2)
  5874  		v.AddArg(ptr)
  5875  		v.AddArg(val)
  5876  		v.AddArg(mem)
  5877  		return true
  5878  	}
  5879  	return false
  5880  }
  5881  func rewriteValueARM64_OpARM64FMOVSstoreidx_0(v *Value) bool {
  5882  	// match: (FMOVSstoreidx ptr (MOVDconst [c]) val mem)
  5883  	// cond:
  5884  	// result: (FMOVSstore [c] ptr val mem)
  5885  	for {
  5886  		mem := v.Args[3]
  5887  		ptr := v.Args[0]
  5888  		v_1 := v.Args[1]
  5889  		if v_1.Op != OpARM64MOVDconst {
  5890  			break
  5891  		}
  5892  		c := v_1.AuxInt
  5893  		val := v.Args[2]
  5894  		v.reset(OpARM64FMOVSstore)
  5895  		v.AuxInt = c
  5896  		v.AddArg(ptr)
  5897  		v.AddArg(val)
  5898  		v.AddArg(mem)
  5899  		return true
  5900  	}
  5901  	// match: (FMOVSstoreidx (MOVDconst [c]) idx val mem)
  5902  	// cond:
  5903  	// result: (FMOVSstore [c] idx val mem)
  5904  	for {
  5905  		mem := v.Args[3]
  5906  		v_0 := v.Args[0]
  5907  		if v_0.Op != OpARM64MOVDconst {
  5908  			break
  5909  		}
  5910  		c := v_0.AuxInt
  5911  		idx := v.Args[1]
  5912  		val := v.Args[2]
  5913  		v.reset(OpARM64FMOVSstore)
  5914  		v.AuxInt = c
  5915  		v.AddArg(idx)
  5916  		v.AddArg(val)
  5917  		v.AddArg(mem)
  5918  		return true
  5919  	}
  5920  	return false
  5921  }
  5922  func rewriteValueARM64_OpARM64FMULD_0(v *Value) bool {
  5923  	// match: (FMULD (FNEGD x) y)
  5924  	// cond:
  5925  	// result: (FNMULD x y)
  5926  	for {
  5927  		y := v.Args[1]
  5928  		v_0 := v.Args[0]
  5929  		if v_0.Op != OpARM64FNEGD {
  5930  			break
  5931  		}
  5932  		x := v_0.Args[0]
  5933  		v.reset(OpARM64FNMULD)
  5934  		v.AddArg(x)
  5935  		v.AddArg(y)
  5936  		return true
  5937  	}
  5938  	// match: (FMULD y (FNEGD x))
  5939  	// cond:
  5940  	// result: (FNMULD x y)
  5941  	for {
  5942  		_ = v.Args[1]
  5943  		y := v.Args[0]
  5944  		v_1 := v.Args[1]
  5945  		if v_1.Op != OpARM64FNEGD {
  5946  			break
  5947  		}
  5948  		x := v_1.Args[0]
  5949  		v.reset(OpARM64FNMULD)
  5950  		v.AddArg(x)
  5951  		v.AddArg(y)
  5952  		return true
  5953  	}
  5954  	return false
  5955  }
  5956  func rewriteValueARM64_OpARM64FMULS_0(v *Value) bool {
  5957  	// match: (FMULS (FNEGS x) y)
  5958  	// cond:
  5959  	// result: (FNMULS x y)
  5960  	for {
  5961  		y := v.Args[1]
  5962  		v_0 := v.Args[0]
  5963  		if v_0.Op != OpARM64FNEGS {
  5964  			break
  5965  		}
  5966  		x := v_0.Args[0]
  5967  		v.reset(OpARM64FNMULS)
  5968  		v.AddArg(x)
  5969  		v.AddArg(y)
  5970  		return true
  5971  	}
  5972  	// match: (FMULS y (FNEGS x))
  5973  	// cond:
  5974  	// result: (FNMULS x y)
  5975  	for {
  5976  		_ = v.Args[1]
  5977  		y := v.Args[0]
  5978  		v_1 := v.Args[1]
  5979  		if v_1.Op != OpARM64FNEGS {
  5980  			break
  5981  		}
  5982  		x := v_1.Args[0]
  5983  		v.reset(OpARM64FNMULS)
  5984  		v.AddArg(x)
  5985  		v.AddArg(y)
  5986  		return true
  5987  	}
  5988  	return false
  5989  }
  5990  func rewriteValueARM64_OpARM64FNEGD_0(v *Value) bool {
  5991  	// match: (FNEGD (FMULD x y))
  5992  	// cond:
  5993  	// result: (FNMULD x y)
  5994  	for {
  5995  		v_0 := v.Args[0]
  5996  		if v_0.Op != OpARM64FMULD {
  5997  			break
  5998  		}
  5999  		y := v_0.Args[1]
  6000  		x := v_0.Args[0]
  6001  		v.reset(OpARM64FNMULD)
  6002  		v.AddArg(x)
  6003  		v.AddArg(y)
  6004  		return true
  6005  	}
  6006  	// match: (FNEGD (FNMULD x y))
  6007  	// cond:
  6008  	// result: (FMULD x y)
  6009  	for {
  6010  		v_0 := v.Args[0]
  6011  		if v_0.Op != OpARM64FNMULD {
  6012  			break
  6013  		}
  6014  		y := v_0.Args[1]
  6015  		x := v_0.Args[0]
  6016  		v.reset(OpARM64FMULD)
  6017  		v.AddArg(x)
  6018  		v.AddArg(y)
  6019  		return true
  6020  	}
  6021  	return false
  6022  }
  6023  func rewriteValueARM64_OpARM64FNEGS_0(v *Value) bool {
  6024  	// match: (FNEGS (FMULS x y))
  6025  	// cond:
  6026  	// result: (FNMULS x y)
  6027  	for {
  6028  		v_0 := v.Args[0]
  6029  		if v_0.Op != OpARM64FMULS {
  6030  			break
  6031  		}
  6032  		y := v_0.Args[1]
  6033  		x := v_0.Args[0]
  6034  		v.reset(OpARM64FNMULS)
  6035  		v.AddArg(x)
  6036  		v.AddArg(y)
  6037  		return true
  6038  	}
  6039  	// match: (FNEGS (FNMULS x y))
  6040  	// cond:
  6041  	// result: (FMULS x y)
  6042  	for {
  6043  		v_0 := v.Args[0]
  6044  		if v_0.Op != OpARM64FNMULS {
  6045  			break
  6046  		}
  6047  		y := v_0.Args[1]
  6048  		x := v_0.Args[0]
  6049  		v.reset(OpARM64FMULS)
  6050  		v.AddArg(x)
  6051  		v.AddArg(y)
  6052  		return true
  6053  	}
  6054  	return false
  6055  }
  6056  func rewriteValueARM64_OpARM64FNMULD_0(v *Value) bool {
  6057  	// match: (FNMULD (FNEGD x) y)
  6058  	// cond:
  6059  	// result: (FMULD x y)
  6060  	for {
  6061  		y := v.Args[1]
  6062  		v_0 := v.Args[0]
  6063  		if v_0.Op != OpARM64FNEGD {
  6064  			break
  6065  		}
  6066  		x := v_0.Args[0]
  6067  		v.reset(OpARM64FMULD)
  6068  		v.AddArg(x)
  6069  		v.AddArg(y)
  6070  		return true
  6071  	}
  6072  	// match: (FNMULD y (FNEGD x))
  6073  	// cond:
  6074  	// result: (FMULD x y)
  6075  	for {
  6076  		_ = v.Args[1]
  6077  		y := v.Args[0]
  6078  		v_1 := v.Args[1]
  6079  		if v_1.Op != OpARM64FNEGD {
  6080  			break
  6081  		}
  6082  		x := v_1.Args[0]
  6083  		v.reset(OpARM64FMULD)
  6084  		v.AddArg(x)
  6085  		v.AddArg(y)
  6086  		return true
  6087  	}
  6088  	return false
  6089  }
  6090  func rewriteValueARM64_OpARM64FNMULS_0(v *Value) bool {
  6091  	// match: (FNMULS (FNEGS x) y)
  6092  	// cond:
  6093  	// result: (FMULS x y)
  6094  	for {
  6095  		y := v.Args[1]
  6096  		v_0 := v.Args[0]
  6097  		if v_0.Op != OpARM64FNEGS {
  6098  			break
  6099  		}
  6100  		x := v_0.Args[0]
  6101  		v.reset(OpARM64FMULS)
  6102  		v.AddArg(x)
  6103  		v.AddArg(y)
  6104  		return true
  6105  	}
  6106  	// match: (FNMULS y (FNEGS x))
  6107  	// cond:
  6108  	// result: (FMULS x y)
  6109  	for {
  6110  		_ = v.Args[1]
  6111  		y := v.Args[0]
  6112  		v_1 := v.Args[1]
  6113  		if v_1.Op != OpARM64FNEGS {
  6114  			break
  6115  		}
  6116  		x := v_1.Args[0]
  6117  		v.reset(OpARM64FMULS)
  6118  		v.AddArg(x)
  6119  		v.AddArg(y)
  6120  		return true
  6121  	}
  6122  	return false
  6123  }
  6124  func rewriteValueARM64_OpARM64FSUBD_0(v *Value) bool {
  6125  	// match: (FSUBD a (FMULD x y))
  6126  	// cond:
  6127  	// result: (FMSUBD a x y)
  6128  	for {
  6129  		_ = v.Args[1]
  6130  		a := v.Args[0]
  6131  		v_1 := v.Args[1]
  6132  		if v_1.Op != OpARM64FMULD {
  6133  			break
  6134  		}
  6135  		y := v_1.Args[1]
  6136  		x := v_1.Args[0]
  6137  		v.reset(OpARM64FMSUBD)
  6138  		v.AddArg(a)
  6139  		v.AddArg(x)
  6140  		v.AddArg(y)
  6141  		return true
  6142  	}
  6143  	// match: (FSUBD (FMULD x y) a)
  6144  	// cond:
  6145  	// result: (FNMSUBD a x y)
  6146  	for {
  6147  		a := v.Args[1]
  6148  		v_0 := v.Args[0]
  6149  		if v_0.Op != OpARM64FMULD {
  6150  			break
  6151  		}
  6152  		y := v_0.Args[1]
  6153  		x := v_0.Args[0]
  6154  		v.reset(OpARM64FNMSUBD)
  6155  		v.AddArg(a)
  6156  		v.AddArg(x)
  6157  		v.AddArg(y)
  6158  		return true
  6159  	}
  6160  	// match: (FSUBD a (FNMULD x y))
  6161  	// cond:
  6162  	// result: (FMADDD a x y)
  6163  	for {
  6164  		_ = v.Args[1]
  6165  		a := v.Args[0]
  6166  		v_1 := v.Args[1]
  6167  		if v_1.Op != OpARM64FNMULD {
  6168  			break
  6169  		}
  6170  		y := v_1.Args[1]
  6171  		x := v_1.Args[0]
  6172  		v.reset(OpARM64FMADDD)
  6173  		v.AddArg(a)
  6174  		v.AddArg(x)
  6175  		v.AddArg(y)
  6176  		return true
  6177  	}
  6178  	// match: (FSUBD (FNMULD x y) a)
  6179  	// cond:
  6180  	// result: (FNMADDD a x y)
  6181  	for {
  6182  		a := v.Args[1]
  6183  		v_0 := v.Args[0]
  6184  		if v_0.Op != OpARM64FNMULD {
  6185  			break
  6186  		}
  6187  		y := v_0.Args[1]
  6188  		x := v_0.Args[0]
  6189  		v.reset(OpARM64FNMADDD)
  6190  		v.AddArg(a)
  6191  		v.AddArg(x)
  6192  		v.AddArg(y)
  6193  		return true
  6194  	}
  6195  	return false
  6196  }
  6197  func rewriteValueARM64_OpARM64FSUBS_0(v *Value) bool {
  6198  	// match: (FSUBS a (FMULS x y))
  6199  	// cond:
  6200  	// result: (FMSUBS a x y)
  6201  	for {
  6202  		_ = v.Args[1]
  6203  		a := v.Args[0]
  6204  		v_1 := v.Args[1]
  6205  		if v_1.Op != OpARM64FMULS {
  6206  			break
  6207  		}
  6208  		y := v_1.Args[1]
  6209  		x := v_1.Args[0]
  6210  		v.reset(OpARM64FMSUBS)
  6211  		v.AddArg(a)
  6212  		v.AddArg(x)
  6213  		v.AddArg(y)
  6214  		return true
  6215  	}
  6216  	// match: (FSUBS (FMULS x y) a)
  6217  	// cond:
  6218  	// result: (FNMSUBS a x y)
  6219  	for {
  6220  		a := v.Args[1]
  6221  		v_0 := v.Args[0]
  6222  		if v_0.Op != OpARM64FMULS {
  6223  			break
  6224  		}
  6225  		y := v_0.Args[1]
  6226  		x := v_0.Args[0]
  6227  		v.reset(OpARM64FNMSUBS)
  6228  		v.AddArg(a)
  6229  		v.AddArg(x)
  6230  		v.AddArg(y)
  6231  		return true
  6232  	}
  6233  	// match: (FSUBS a (FNMULS x y))
  6234  	// cond:
  6235  	// result: (FMADDS a x y)
  6236  	for {
  6237  		_ = v.Args[1]
  6238  		a := v.Args[0]
  6239  		v_1 := v.Args[1]
  6240  		if v_1.Op != OpARM64FNMULS {
  6241  			break
  6242  		}
  6243  		y := v_1.Args[1]
  6244  		x := v_1.Args[0]
  6245  		v.reset(OpARM64FMADDS)
  6246  		v.AddArg(a)
  6247  		v.AddArg(x)
  6248  		v.AddArg(y)
  6249  		return true
  6250  	}
  6251  	// match: (FSUBS (FNMULS x y) a)
  6252  	// cond:
  6253  	// result: (FNMADDS a x y)
  6254  	for {
  6255  		a := v.Args[1]
  6256  		v_0 := v.Args[0]
  6257  		if v_0.Op != OpARM64FNMULS {
  6258  			break
  6259  		}
  6260  		y := v_0.Args[1]
  6261  		x := v_0.Args[0]
  6262  		v.reset(OpARM64FNMADDS)
  6263  		v.AddArg(a)
  6264  		v.AddArg(x)
  6265  		v.AddArg(y)
  6266  		return true
  6267  	}
  6268  	return false
  6269  }
  6270  func rewriteValueARM64_OpARM64GreaterEqual_0(v *Value) bool {
  6271  	// match: (GreaterEqual (FlagEQ))
  6272  	// cond:
  6273  	// result: (MOVDconst [1])
  6274  	for {
  6275  		v_0 := v.Args[0]
  6276  		if v_0.Op != OpARM64FlagEQ {
  6277  			break
  6278  		}
  6279  		v.reset(OpARM64MOVDconst)
  6280  		v.AuxInt = 1
  6281  		return true
  6282  	}
  6283  	// match: (GreaterEqual (FlagLT_ULT))
  6284  	// cond:
  6285  	// result: (MOVDconst [0])
  6286  	for {
  6287  		v_0 := v.Args[0]
  6288  		if v_0.Op != OpARM64FlagLT_ULT {
  6289  			break
  6290  		}
  6291  		v.reset(OpARM64MOVDconst)
  6292  		v.AuxInt = 0
  6293  		return true
  6294  	}
  6295  	// match: (GreaterEqual (FlagLT_UGT))
  6296  	// cond:
  6297  	// result: (MOVDconst [0])
  6298  	for {
  6299  		v_0 := v.Args[0]
  6300  		if v_0.Op != OpARM64FlagLT_UGT {
  6301  			break
  6302  		}
  6303  		v.reset(OpARM64MOVDconst)
  6304  		v.AuxInt = 0
  6305  		return true
  6306  	}
  6307  	// match: (GreaterEqual (FlagGT_ULT))
  6308  	// cond:
  6309  	// result: (MOVDconst [1])
  6310  	for {
  6311  		v_0 := v.Args[0]
  6312  		if v_0.Op != OpARM64FlagGT_ULT {
  6313  			break
  6314  		}
  6315  		v.reset(OpARM64MOVDconst)
  6316  		v.AuxInt = 1
  6317  		return true
  6318  	}
  6319  	// match: (GreaterEqual (FlagGT_UGT))
  6320  	// cond:
  6321  	// result: (MOVDconst [1])
  6322  	for {
  6323  		v_0 := v.Args[0]
  6324  		if v_0.Op != OpARM64FlagGT_UGT {
  6325  			break
  6326  		}
  6327  		v.reset(OpARM64MOVDconst)
  6328  		v.AuxInt = 1
  6329  		return true
  6330  	}
  6331  	// match: (GreaterEqual (InvertFlags x))
  6332  	// cond:
  6333  	// result: (LessEqual x)
  6334  	for {
  6335  		v_0 := v.Args[0]
  6336  		if v_0.Op != OpARM64InvertFlags {
  6337  			break
  6338  		}
  6339  		x := v_0.Args[0]
  6340  		v.reset(OpARM64LessEqual)
  6341  		v.AddArg(x)
  6342  		return true
  6343  	}
  6344  	return false
  6345  }
  6346  func rewriteValueARM64_OpARM64GreaterEqualF_0(v *Value) bool {
  6347  	// match: (GreaterEqualF (InvertFlags x))
  6348  	// cond:
  6349  	// result: (LessEqualF x)
  6350  	for {
  6351  		v_0 := v.Args[0]
  6352  		if v_0.Op != OpARM64InvertFlags {
  6353  			break
  6354  		}
  6355  		x := v_0.Args[0]
  6356  		v.reset(OpARM64LessEqualF)
  6357  		v.AddArg(x)
  6358  		return true
  6359  	}
  6360  	return false
  6361  }
  6362  func rewriteValueARM64_OpARM64GreaterEqualU_0(v *Value) bool {
  6363  	// match: (GreaterEqualU (FlagEQ))
  6364  	// cond:
  6365  	// result: (MOVDconst [1])
  6366  	for {
  6367  		v_0 := v.Args[0]
  6368  		if v_0.Op != OpARM64FlagEQ {
  6369  			break
  6370  		}
  6371  		v.reset(OpARM64MOVDconst)
  6372  		v.AuxInt = 1
  6373  		return true
  6374  	}
  6375  	// match: (GreaterEqualU (FlagLT_ULT))
  6376  	// cond:
  6377  	// result: (MOVDconst [0])
  6378  	for {
  6379  		v_0 := v.Args[0]
  6380  		if v_0.Op != OpARM64FlagLT_ULT {
  6381  			break
  6382  		}
  6383  		v.reset(OpARM64MOVDconst)
  6384  		v.AuxInt = 0
  6385  		return true
  6386  	}
  6387  	// match: (GreaterEqualU (FlagLT_UGT))
  6388  	// cond:
  6389  	// result: (MOVDconst [1])
  6390  	for {
  6391  		v_0 := v.Args[0]
  6392  		if v_0.Op != OpARM64FlagLT_UGT {
  6393  			break
  6394  		}
  6395  		v.reset(OpARM64MOVDconst)
  6396  		v.AuxInt = 1
  6397  		return true
  6398  	}
  6399  	// match: (GreaterEqualU (FlagGT_ULT))
  6400  	// cond:
  6401  	// result: (MOVDconst [0])
  6402  	for {
  6403  		v_0 := v.Args[0]
  6404  		if v_0.Op != OpARM64FlagGT_ULT {
  6405  			break
  6406  		}
  6407  		v.reset(OpARM64MOVDconst)
  6408  		v.AuxInt = 0
  6409  		return true
  6410  	}
  6411  	// match: (GreaterEqualU (FlagGT_UGT))
  6412  	// cond:
  6413  	// result: (MOVDconst [1])
  6414  	for {
  6415  		v_0 := v.Args[0]
  6416  		if v_0.Op != OpARM64FlagGT_UGT {
  6417  			break
  6418  		}
  6419  		v.reset(OpARM64MOVDconst)
  6420  		v.AuxInt = 1
  6421  		return true
  6422  	}
  6423  	// match: (GreaterEqualU (InvertFlags x))
  6424  	// cond:
  6425  	// result: (LessEqualU x)
  6426  	for {
  6427  		v_0 := v.Args[0]
  6428  		if v_0.Op != OpARM64InvertFlags {
  6429  			break
  6430  		}
  6431  		x := v_0.Args[0]
  6432  		v.reset(OpARM64LessEqualU)
  6433  		v.AddArg(x)
  6434  		return true
  6435  	}
  6436  	return false
  6437  }
  6438  func rewriteValueARM64_OpARM64GreaterThan_0(v *Value) bool {
  6439  	// match: (GreaterThan (FlagEQ))
  6440  	// cond:
  6441  	// result: (MOVDconst [0])
  6442  	for {
  6443  		v_0 := v.Args[0]
  6444  		if v_0.Op != OpARM64FlagEQ {
  6445  			break
  6446  		}
  6447  		v.reset(OpARM64MOVDconst)
  6448  		v.AuxInt = 0
  6449  		return true
  6450  	}
  6451  	// match: (GreaterThan (FlagLT_ULT))
  6452  	// cond:
  6453  	// result: (MOVDconst [0])
  6454  	for {
  6455  		v_0 := v.Args[0]
  6456  		if v_0.Op != OpARM64FlagLT_ULT {
  6457  			break
  6458  		}
  6459  		v.reset(OpARM64MOVDconst)
  6460  		v.AuxInt = 0
  6461  		return true
  6462  	}
  6463  	// match: (GreaterThan (FlagLT_UGT))
  6464  	// cond:
  6465  	// result: (MOVDconst [0])
  6466  	for {
  6467  		v_0 := v.Args[0]
  6468  		if v_0.Op != OpARM64FlagLT_UGT {
  6469  			break
  6470  		}
  6471  		v.reset(OpARM64MOVDconst)
  6472  		v.AuxInt = 0
  6473  		return true
  6474  	}
  6475  	// match: (GreaterThan (FlagGT_ULT))
  6476  	// cond:
  6477  	// result: (MOVDconst [1])
  6478  	for {
  6479  		v_0 := v.Args[0]
  6480  		if v_0.Op != OpARM64FlagGT_ULT {
  6481  			break
  6482  		}
  6483  		v.reset(OpARM64MOVDconst)
  6484  		v.AuxInt = 1
  6485  		return true
  6486  	}
  6487  	// match: (GreaterThan (FlagGT_UGT))
  6488  	// cond:
  6489  	// result: (MOVDconst [1])
  6490  	for {
  6491  		v_0 := v.Args[0]
  6492  		if v_0.Op != OpARM64FlagGT_UGT {
  6493  			break
  6494  		}
  6495  		v.reset(OpARM64MOVDconst)
  6496  		v.AuxInt = 1
  6497  		return true
  6498  	}
  6499  	// match: (GreaterThan (InvertFlags x))
  6500  	// cond:
  6501  	// result: (LessThan x)
  6502  	for {
  6503  		v_0 := v.Args[0]
  6504  		if v_0.Op != OpARM64InvertFlags {
  6505  			break
  6506  		}
  6507  		x := v_0.Args[0]
  6508  		v.reset(OpARM64LessThan)
  6509  		v.AddArg(x)
  6510  		return true
  6511  	}
  6512  	return false
  6513  }
  6514  func rewriteValueARM64_OpARM64GreaterThanF_0(v *Value) bool {
  6515  	// match: (GreaterThanF (InvertFlags x))
  6516  	// cond:
  6517  	// result: (LessThanF x)
  6518  	for {
  6519  		v_0 := v.Args[0]
  6520  		if v_0.Op != OpARM64InvertFlags {
  6521  			break
  6522  		}
  6523  		x := v_0.Args[0]
  6524  		v.reset(OpARM64LessThanF)
  6525  		v.AddArg(x)
  6526  		return true
  6527  	}
  6528  	return false
  6529  }
  6530  func rewriteValueARM64_OpARM64GreaterThanU_0(v *Value) bool {
  6531  	// match: (GreaterThanU (FlagEQ))
  6532  	// cond:
  6533  	// result: (MOVDconst [0])
  6534  	for {
  6535  		v_0 := v.Args[0]
  6536  		if v_0.Op != OpARM64FlagEQ {
  6537  			break
  6538  		}
  6539  		v.reset(OpARM64MOVDconst)
  6540  		v.AuxInt = 0
  6541  		return true
  6542  	}
  6543  	// match: (GreaterThanU (FlagLT_ULT))
  6544  	// cond:
  6545  	// result: (MOVDconst [0])
  6546  	for {
  6547  		v_0 := v.Args[0]
  6548  		if v_0.Op != OpARM64FlagLT_ULT {
  6549  			break
  6550  		}
  6551  		v.reset(OpARM64MOVDconst)
  6552  		v.AuxInt = 0
  6553  		return true
  6554  	}
  6555  	// match: (GreaterThanU (FlagLT_UGT))
  6556  	// cond:
  6557  	// result: (MOVDconst [1])
  6558  	for {
  6559  		v_0 := v.Args[0]
  6560  		if v_0.Op != OpARM64FlagLT_UGT {
  6561  			break
  6562  		}
  6563  		v.reset(OpARM64MOVDconst)
  6564  		v.AuxInt = 1
  6565  		return true
  6566  	}
  6567  	// match: (GreaterThanU (FlagGT_ULT))
  6568  	// cond:
  6569  	// result: (MOVDconst [0])
  6570  	for {
  6571  		v_0 := v.Args[0]
  6572  		if v_0.Op != OpARM64FlagGT_ULT {
  6573  			break
  6574  		}
  6575  		v.reset(OpARM64MOVDconst)
  6576  		v.AuxInt = 0
  6577  		return true
  6578  	}
  6579  	// match: (GreaterThanU (FlagGT_UGT))
  6580  	// cond:
  6581  	// result: (MOVDconst [1])
  6582  	for {
  6583  		v_0 := v.Args[0]
  6584  		if v_0.Op != OpARM64FlagGT_UGT {
  6585  			break
  6586  		}
  6587  		v.reset(OpARM64MOVDconst)
  6588  		v.AuxInt = 1
  6589  		return true
  6590  	}
  6591  	// match: (GreaterThanU (InvertFlags x))
  6592  	// cond:
  6593  	// result: (LessThanU x)
  6594  	for {
  6595  		v_0 := v.Args[0]
  6596  		if v_0.Op != OpARM64InvertFlags {
  6597  			break
  6598  		}
  6599  		x := v_0.Args[0]
  6600  		v.reset(OpARM64LessThanU)
  6601  		v.AddArg(x)
  6602  		return true
  6603  	}
  6604  	return false
  6605  }
  6606  func rewriteValueARM64_OpARM64LessEqual_0(v *Value) bool {
  6607  	// match: (LessEqual (FlagEQ))
  6608  	// cond:
  6609  	// result: (MOVDconst [1])
  6610  	for {
  6611  		v_0 := v.Args[0]
  6612  		if v_0.Op != OpARM64FlagEQ {
  6613  			break
  6614  		}
  6615  		v.reset(OpARM64MOVDconst)
  6616  		v.AuxInt = 1
  6617  		return true
  6618  	}
  6619  	// match: (LessEqual (FlagLT_ULT))
  6620  	// cond:
  6621  	// result: (MOVDconst [1])
  6622  	for {
  6623  		v_0 := v.Args[0]
  6624  		if v_0.Op != OpARM64FlagLT_ULT {
  6625  			break
  6626  		}
  6627  		v.reset(OpARM64MOVDconst)
  6628  		v.AuxInt = 1
  6629  		return true
  6630  	}
  6631  	// match: (LessEqual (FlagLT_UGT))
  6632  	// cond:
  6633  	// result: (MOVDconst [1])
  6634  	for {
  6635  		v_0 := v.Args[0]
  6636  		if v_0.Op != OpARM64FlagLT_UGT {
  6637  			break
  6638  		}
  6639  		v.reset(OpARM64MOVDconst)
  6640  		v.AuxInt = 1
  6641  		return true
  6642  	}
  6643  	// match: (LessEqual (FlagGT_ULT))
  6644  	// cond:
  6645  	// result: (MOVDconst [0])
  6646  	for {
  6647  		v_0 := v.Args[0]
  6648  		if v_0.Op != OpARM64FlagGT_ULT {
  6649  			break
  6650  		}
  6651  		v.reset(OpARM64MOVDconst)
  6652  		v.AuxInt = 0
  6653  		return true
  6654  	}
  6655  	// match: (LessEqual (FlagGT_UGT))
  6656  	// cond:
  6657  	// result: (MOVDconst [0])
  6658  	for {
  6659  		v_0 := v.Args[0]
  6660  		if v_0.Op != OpARM64FlagGT_UGT {
  6661  			break
  6662  		}
  6663  		v.reset(OpARM64MOVDconst)
  6664  		v.AuxInt = 0
  6665  		return true
  6666  	}
  6667  	// match: (LessEqual (InvertFlags x))
  6668  	// cond:
  6669  	// result: (GreaterEqual x)
  6670  	for {
  6671  		v_0 := v.Args[0]
  6672  		if v_0.Op != OpARM64InvertFlags {
  6673  			break
  6674  		}
  6675  		x := v_0.Args[0]
  6676  		v.reset(OpARM64GreaterEqual)
  6677  		v.AddArg(x)
  6678  		return true
  6679  	}
  6680  	return false
  6681  }
  6682  func rewriteValueARM64_OpARM64LessEqualF_0(v *Value) bool {
  6683  	// match: (LessEqualF (InvertFlags x))
  6684  	// cond:
  6685  	// result: (GreaterEqualF x)
  6686  	for {
  6687  		v_0 := v.Args[0]
  6688  		if v_0.Op != OpARM64InvertFlags {
  6689  			break
  6690  		}
  6691  		x := v_0.Args[0]
  6692  		v.reset(OpARM64GreaterEqualF)
  6693  		v.AddArg(x)
  6694  		return true
  6695  	}
  6696  	return false
  6697  }
  6698  func rewriteValueARM64_OpARM64LessEqualU_0(v *Value) bool {
  6699  	// match: (LessEqualU (FlagEQ))
  6700  	// cond:
  6701  	// result: (MOVDconst [1])
  6702  	for {
  6703  		v_0 := v.Args[0]
  6704  		if v_0.Op != OpARM64FlagEQ {
  6705  			break
  6706  		}
  6707  		v.reset(OpARM64MOVDconst)
  6708  		v.AuxInt = 1
  6709  		return true
  6710  	}
  6711  	// match: (LessEqualU (FlagLT_ULT))
  6712  	// cond:
  6713  	// result: (MOVDconst [1])
  6714  	for {
  6715  		v_0 := v.Args[0]
  6716  		if v_0.Op != OpARM64FlagLT_ULT {
  6717  			break
  6718  		}
  6719  		v.reset(OpARM64MOVDconst)
  6720  		v.AuxInt = 1
  6721  		return true
  6722  	}
  6723  	// match: (LessEqualU (FlagLT_UGT))
  6724  	// cond:
  6725  	// result: (MOVDconst [0])
  6726  	for {
  6727  		v_0 := v.Args[0]
  6728  		if v_0.Op != OpARM64FlagLT_UGT {
  6729  			break
  6730  		}
  6731  		v.reset(OpARM64MOVDconst)
  6732  		v.AuxInt = 0
  6733  		return true
  6734  	}
  6735  	// match: (LessEqualU (FlagGT_ULT))
  6736  	// cond:
  6737  	// result: (MOVDconst [1])
  6738  	for {
  6739  		v_0 := v.Args[0]
  6740  		if v_0.Op != OpARM64FlagGT_ULT {
  6741  			break
  6742  		}
  6743  		v.reset(OpARM64MOVDconst)
  6744  		v.AuxInt = 1
  6745  		return true
  6746  	}
  6747  	// match: (LessEqualU (FlagGT_UGT))
  6748  	// cond:
  6749  	// result: (MOVDconst [0])
  6750  	for {
  6751  		v_0 := v.Args[0]
  6752  		if v_0.Op != OpARM64FlagGT_UGT {
  6753  			break
  6754  		}
  6755  		v.reset(OpARM64MOVDconst)
  6756  		v.AuxInt = 0
  6757  		return true
  6758  	}
  6759  	// match: (LessEqualU (InvertFlags x))
  6760  	// cond:
  6761  	// result: (GreaterEqualU x)
  6762  	for {
  6763  		v_0 := v.Args[0]
  6764  		if v_0.Op != OpARM64InvertFlags {
  6765  			break
  6766  		}
  6767  		x := v_0.Args[0]
  6768  		v.reset(OpARM64GreaterEqualU)
  6769  		v.AddArg(x)
  6770  		return true
  6771  	}
  6772  	return false
  6773  }
  6774  func rewriteValueARM64_OpARM64LessThan_0(v *Value) bool {
  6775  	// match: (LessThan (FlagEQ))
  6776  	// cond:
  6777  	// result: (MOVDconst [0])
  6778  	for {
  6779  		v_0 := v.Args[0]
  6780  		if v_0.Op != OpARM64FlagEQ {
  6781  			break
  6782  		}
  6783  		v.reset(OpARM64MOVDconst)
  6784  		v.AuxInt = 0
  6785  		return true
  6786  	}
  6787  	// match: (LessThan (FlagLT_ULT))
  6788  	// cond:
  6789  	// result: (MOVDconst [1])
  6790  	for {
  6791  		v_0 := v.Args[0]
  6792  		if v_0.Op != OpARM64FlagLT_ULT {
  6793  			break
  6794  		}
  6795  		v.reset(OpARM64MOVDconst)
  6796  		v.AuxInt = 1
  6797  		return true
  6798  	}
  6799  	// match: (LessThan (FlagLT_UGT))
  6800  	// cond:
  6801  	// result: (MOVDconst [1])
  6802  	for {
  6803  		v_0 := v.Args[0]
  6804  		if v_0.Op != OpARM64FlagLT_UGT {
  6805  			break
  6806  		}
  6807  		v.reset(OpARM64MOVDconst)
  6808  		v.AuxInt = 1
  6809  		return true
  6810  	}
  6811  	// match: (LessThan (FlagGT_ULT))
  6812  	// cond:
  6813  	// result: (MOVDconst [0])
  6814  	for {
  6815  		v_0 := v.Args[0]
  6816  		if v_0.Op != OpARM64FlagGT_ULT {
  6817  			break
  6818  		}
  6819  		v.reset(OpARM64MOVDconst)
  6820  		v.AuxInt = 0
  6821  		return true
  6822  	}
  6823  	// match: (LessThan (FlagGT_UGT))
  6824  	// cond:
  6825  	// result: (MOVDconst [0])
  6826  	for {
  6827  		v_0 := v.Args[0]
  6828  		if v_0.Op != OpARM64FlagGT_UGT {
  6829  			break
  6830  		}
  6831  		v.reset(OpARM64MOVDconst)
  6832  		v.AuxInt = 0
  6833  		return true
  6834  	}
  6835  	// match: (LessThan (InvertFlags x))
  6836  	// cond:
  6837  	// result: (GreaterThan x)
  6838  	for {
  6839  		v_0 := v.Args[0]
  6840  		if v_0.Op != OpARM64InvertFlags {
  6841  			break
  6842  		}
  6843  		x := v_0.Args[0]
  6844  		v.reset(OpARM64GreaterThan)
  6845  		v.AddArg(x)
  6846  		return true
  6847  	}
  6848  	return false
  6849  }
  6850  func rewriteValueARM64_OpARM64LessThanF_0(v *Value) bool {
  6851  	// match: (LessThanF (InvertFlags x))
  6852  	// cond:
  6853  	// result: (GreaterThanF x)
  6854  	for {
  6855  		v_0 := v.Args[0]
  6856  		if v_0.Op != OpARM64InvertFlags {
  6857  			break
  6858  		}
  6859  		x := v_0.Args[0]
  6860  		v.reset(OpARM64GreaterThanF)
  6861  		v.AddArg(x)
  6862  		return true
  6863  	}
  6864  	return false
  6865  }
  6866  func rewriteValueARM64_OpARM64LessThanU_0(v *Value) bool {
  6867  	// match: (LessThanU (FlagEQ))
  6868  	// cond:
  6869  	// result: (MOVDconst [0])
  6870  	for {
  6871  		v_0 := v.Args[0]
  6872  		if v_0.Op != OpARM64FlagEQ {
  6873  			break
  6874  		}
  6875  		v.reset(OpARM64MOVDconst)
  6876  		v.AuxInt = 0
  6877  		return true
  6878  	}
  6879  	// match: (LessThanU (FlagLT_ULT))
  6880  	// cond:
  6881  	// result: (MOVDconst [1])
  6882  	for {
  6883  		v_0 := v.Args[0]
  6884  		if v_0.Op != OpARM64FlagLT_ULT {
  6885  			break
  6886  		}
  6887  		v.reset(OpARM64MOVDconst)
  6888  		v.AuxInt = 1
  6889  		return true
  6890  	}
  6891  	// match: (LessThanU (FlagLT_UGT))
  6892  	// cond:
  6893  	// result: (MOVDconst [0])
  6894  	for {
  6895  		v_0 := v.Args[0]
  6896  		if v_0.Op != OpARM64FlagLT_UGT {
  6897  			break
  6898  		}
  6899  		v.reset(OpARM64MOVDconst)
  6900  		v.AuxInt = 0
  6901  		return true
  6902  	}
  6903  	// match: (LessThanU (FlagGT_ULT))
  6904  	// cond:
  6905  	// result: (MOVDconst [1])
  6906  	for {
  6907  		v_0 := v.Args[0]
  6908  		if v_0.Op != OpARM64FlagGT_ULT {
  6909  			break
  6910  		}
  6911  		v.reset(OpARM64MOVDconst)
  6912  		v.AuxInt = 1
  6913  		return true
  6914  	}
  6915  	// match: (LessThanU (FlagGT_UGT))
  6916  	// cond:
  6917  	// result: (MOVDconst [0])
  6918  	for {
  6919  		v_0 := v.Args[0]
  6920  		if v_0.Op != OpARM64FlagGT_UGT {
  6921  			break
  6922  		}
  6923  		v.reset(OpARM64MOVDconst)
  6924  		v.AuxInt = 0
  6925  		return true
  6926  	}
  6927  	// match: (LessThanU (InvertFlags x))
  6928  	// cond:
  6929  	// result: (GreaterThanU x)
  6930  	for {
  6931  		v_0 := v.Args[0]
  6932  		if v_0.Op != OpARM64InvertFlags {
  6933  			break
  6934  		}
  6935  		x := v_0.Args[0]
  6936  		v.reset(OpARM64GreaterThanU)
  6937  		v.AddArg(x)
  6938  		return true
  6939  	}
  6940  	return false
  6941  }
  6942  func rewriteValueARM64_OpARM64MADD_0(v *Value) bool {
  6943  	b := v.Block
  6944  	// match: (MADD a x (MOVDconst [-1]))
  6945  	// cond:
  6946  	// result: (SUB a x)
  6947  	for {
  6948  		_ = v.Args[2]
  6949  		a := v.Args[0]
  6950  		x := v.Args[1]
  6951  		v_2 := v.Args[2]
  6952  		if v_2.Op != OpARM64MOVDconst {
  6953  			break
  6954  		}
  6955  		if v_2.AuxInt != -1 {
  6956  			break
  6957  		}
  6958  		v.reset(OpARM64SUB)
  6959  		v.AddArg(a)
  6960  		v.AddArg(x)
  6961  		return true
  6962  	}
  6963  	// match: (MADD a _ (MOVDconst [0]))
  6964  	// cond:
  6965  	// result: a
  6966  	for {
  6967  		_ = v.Args[2]
  6968  		a := v.Args[0]
  6969  		v_2 := v.Args[2]
  6970  		if v_2.Op != OpARM64MOVDconst {
  6971  			break
  6972  		}
  6973  		if v_2.AuxInt != 0 {
  6974  			break
  6975  		}
  6976  		v.reset(OpCopy)
  6977  		v.Type = a.Type
  6978  		v.AddArg(a)
  6979  		return true
  6980  	}
  6981  	// match: (MADD a x (MOVDconst [1]))
  6982  	// cond:
  6983  	// result: (ADD a x)
  6984  	for {
  6985  		_ = v.Args[2]
  6986  		a := v.Args[0]
  6987  		x := v.Args[1]
  6988  		v_2 := v.Args[2]
  6989  		if v_2.Op != OpARM64MOVDconst {
  6990  			break
  6991  		}
  6992  		if v_2.AuxInt != 1 {
  6993  			break
  6994  		}
  6995  		v.reset(OpARM64ADD)
  6996  		v.AddArg(a)
  6997  		v.AddArg(x)
  6998  		return true
  6999  	}
  7000  	// match: (MADD a x (MOVDconst [c]))
  7001  	// cond: isPowerOfTwo(c)
  7002  	// result: (ADDshiftLL a x [log2(c)])
  7003  	for {
  7004  		_ = v.Args[2]
  7005  		a := v.Args[0]
  7006  		x := v.Args[1]
  7007  		v_2 := v.Args[2]
  7008  		if v_2.Op != OpARM64MOVDconst {
  7009  			break
  7010  		}
  7011  		c := v_2.AuxInt
  7012  		if !(isPowerOfTwo(c)) {
  7013  			break
  7014  		}
  7015  		v.reset(OpARM64ADDshiftLL)
  7016  		v.AuxInt = log2(c)
  7017  		v.AddArg(a)
  7018  		v.AddArg(x)
  7019  		return true
  7020  	}
  7021  	// match: (MADD a x (MOVDconst [c]))
  7022  	// cond: isPowerOfTwo(c-1) && c>=3
  7023  	// result: (ADD a (ADDshiftLL <x.Type> x x [log2(c-1)]))
  7024  	for {
  7025  		_ = v.Args[2]
  7026  		a := v.Args[0]
  7027  		x := v.Args[1]
  7028  		v_2 := v.Args[2]
  7029  		if v_2.Op != OpARM64MOVDconst {
  7030  			break
  7031  		}
  7032  		c := v_2.AuxInt
  7033  		if !(isPowerOfTwo(c-1) && c >= 3) {
  7034  			break
  7035  		}
  7036  		v.reset(OpARM64ADD)
  7037  		v.AddArg(a)
  7038  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  7039  		v0.AuxInt = log2(c - 1)
  7040  		v0.AddArg(x)
  7041  		v0.AddArg(x)
  7042  		v.AddArg(v0)
  7043  		return true
  7044  	}
  7045  	// match: (MADD a x (MOVDconst [c]))
  7046  	// cond: isPowerOfTwo(c+1) && c>=7
  7047  	// result: (SUB a (SUBshiftLL <x.Type> x x [log2(c+1)]))
  7048  	for {
  7049  		_ = v.Args[2]
  7050  		a := v.Args[0]
  7051  		x := v.Args[1]
  7052  		v_2 := v.Args[2]
  7053  		if v_2.Op != OpARM64MOVDconst {
  7054  			break
  7055  		}
  7056  		c := v_2.AuxInt
  7057  		if !(isPowerOfTwo(c+1) && c >= 7) {
  7058  			break
  7059  		}
  7060  		v.reset(OpARM64SUB)
  7061  		v.AddArg(a)
  7062  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  7063  		v0.AuxInt = log2(c + 1)
  7064  		v0.AddArg(x)
  7065  		v0.AddArg(x)
  7066  		v.AddArg(v0)
  7067  		return true
  7068  	}
  7069  	// match: (MADD a x (MOVDconst [c]))
  7070  	// cond: c%3 == 0 && isPowerOfTwo(c/3)
  7071  	// result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log2(c/3)])
  7072  	for {
  7073  		_ = v.Args[2]
  7074  		a := v.Args[0]
  7075  		x := v.Args[1]
  7076  		v_2 := v.Args[2]
  7077  		if v_2.Op != OpARM64MOVDconst {
  7078  			break
  7079  		}
  7080  		c := v_2.AuxInt
  7081  		if !(c%3 == 0 && isPowerOfTwo(c/3)) {
  7082  			break
  7083  		}
  7084  		v.reset(OpARM64SUBshiftLL)
  7085  		v.AuxInt = log2(c / 3)
  7086  		v.AddArg(a)
  7087  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  7088  		v0.AuxInt = 2
  7089  		v0.AddArg(x)
  7090  		v0.AddArg(x)
  7091  		v.AddArg(v0)
  7092  		return true
  7093  	}
  7094  	// match: (MADD a x (MOVDconst [c]))
  7095  	// cond: c%5 == 0 && isPowerOfTwo(c/5)
  7096  	// result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log2(c/5)])
  7097  	for {
  7098  		_ = v.Args[2]
  7099  		a := v.Args[0]
  7100  		x := v.Args[1]
  7101  		v_2 := v.Args[2]
  7102  		if v_2.Op != OpARM64MOVDconst {
  7103  			break
  7104  		}
  7105  		c := v_2.AuxInt
  7106  		if !(c%5 == 0 && isPowerOfTwo(c/5)) {
  7107  			break
  7108  		}
  7109  		v.reset(OpARM64ADDshiftLL)
  7110  		v.AuxInt = log2(c / 5)
  7111  		v.AddArg(a)
  7112  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  7113  		v0.AuxInt = 2
  7114  		v0.AddArg(x)
  7115  		v0.AddArg(x)
  7116  		v.AddArg(v0)
  7117  		return true
  7118  	}
  7119  	// match: (MADD a x (MOVDconst [c]))
  7120  	// cond: c%7 == 0 && isPowerOfTwo(c/7)
  7121  	// result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log2(c/7)])
  7122  	for {
  7123  		_ = v.Args[2]
  7124  		a := v.Args[0]
  7125  		x := v.Args[1]
  7126  		v_2 := v.Args[2]
  7127  		if v_2.Op != OpARM64MOVDconst {
  7128  			break
  7129  		}
  7130  		c := v_2.AuxInt
  7131  		if !(c%7 == 0 && isPowerOfTwo(c/7)) {
  7132  			break
  7133  		}
  7134  		v.reset(OpARM64SUBshiftLL)
  7135  		v.AuxInt = log2(c / 7)
  7136  		v.AddArg(a)
  7137  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  7138  		v0.AuxInt = 3
  7139  		v0.AddArg(x)
  7140  		v0.AddArg(x)
  7141  		v.AddArg(v0)
  7142  		return true
  7143  	}
  7144  	// match: (MADD a x (MOVDconst [c]))
  7145  	// cond: c%9 == 0 && isPowerOfTwo(c/9)
  7146  	// result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log2(c/9)])
  7147  	for {
  7148  		_ = v.Args[2]
  7149  		a := v.Args[0]
  7150  		x := v.Args[1]
  7151  		v_2 := v.Args[2]
  7152  		if v_2.Op != OpARM64MOVDconst {
  7153  			break
  7154  		}
  7155  		c := v_2.AuxInt
  7156  		if !(c%9 == 0 && isPowerOfTwo(c/9)) {
  7157  			break
  7158  		}
  7159  		v.reset(OpARM64ADDshiftLL)
  7160  		v.AuxInt = log2(c / 9)
  7161  		v.AddArg(a)
  7162  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  7163  		v0.AuxInt = 3
  7164  		v0.AddArg(x)
  7165  		v0.AddArg(x)
  7166  		v.AddArg(v0)
  7167  		return true
  7168  	}
  7169  	return false
  7170  }
  7171  func rewriteValueARM64_OpARM64MADD_10(v *Value) bool {
  7172  	b := v.Block
  7173  	// match: (MADD a (MOVDconst [-1]) x)
  7174  	// cond:
  7175  	// result: (SUB a x)
  7176  	for {
  7177  		x := v.Args[2]
  7178  		a := v.Args[0]
  7179  		v_1 := v.Args[1]
  7180  		if v_1.Op != OpARM64MOVDconst {
  7181  			break
  7182  		}
  7183  		if v_1.AuxInt != -1 {
  7184  			break
  7185  		}
  7186  		v.reset(OpARM64SUB)
  7187  		v.AddArg(a)
  7188  		v.AddArg(x)
  7189  		return true
  7190  	}
  7191  	// match: (MADD a (MOVDconst [0]) _)
  7192  	// cond:
  7193  	// result: a
  7194  	for {
  7195  		_ = v.Args[2]
  7196  		a := v.Args[0]
  7197  		v_1 := v.Args[1]
  7198  		if v_1.Op != OpARM64MOVDconst {
  7199  			break
  7200  		}
  7201  		if v_1.AuxInt != 0 {
  7202  			break
  7203  		}
  7204  		v.reset(OpCopy)
  7205  		v.Type = a.Type
  7206  		v.AddArg(a)
  7207  		return true
  7208  	}
  7209  	// match: (MADD a (MOVDconst [1]) x)
  7210  	// cond:
  7211  	// result: (ADD a x)
  7212  	for {
  7213  		x := v.Args[2]
  7214  		a := v.Args[0]
  7215  		v_1 := v.Args[1]
  7216  		if v_1.Op != OpARM64MOVDconst {
  7217  			break
  7218  		}
  7219  		if v_1.AuxInt != 1 {
  7220  			break
  7221  		}
  7222  		v.reset(OpARM64ADD)
  7223  		v.AddArg(a)
  7224  		v.AddArg(x)
  7225  		return true
  7226  	}
  7227  	// match: (MADD a (MOVDconst [c]) x)
  7228  	// cond: isPowerOfTwo(c)
  7229  	// result: (ADDshiftLL a x [log2(c)])
  7230  	for {
  7231  		x := v.Args[2]
  7232  		a := v.Args[0]
  7233  		v_1 := v.Args[1]
  7234  		if v_1.Op != OpARM64MOVDconst {
  7235  			break
  7236  		}
  7237  		c := v_1.AuxInt
  7238  		if !(isPowerOfTwo(c)) {
  7239  			break
  7240  		}
  7241  		v.reset(OpARM64ADDshiftLL)
  7242  		v.AuxInt = log2(c)
  7243  		v.AddArg(a)
  7244  		v.AddArg(x)
  7245  		return true
  7246  	}
  7247  	// match: (MADD a (MOVDconst [c]) x)
  7248  	// cond: isPowerOfTwo(c-1) && c>=3
  7249  	// result: (ADD a (ADDshiftLL <x.Type> x x [log2(c-1)]))
  7250  	for {
  7251  		x := v.Args[2]
  7252  		a := v.Args[0]
  7253  		v_1 := v.Args[1]
  7254  		if v_1.Op != OpARM64MOVDconst {
  7255  			break
  7256  		}
  7257  		c := v_1.AuxInt
  7258  		if !(isPowerOfTwo(c-1) && c >= 3) {
  7259  			break
  7260  		}
  7261  		v.reset(OpARM64ADD)
  7262  		v.AddArg(a)
  7263  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  7264  		v0.AuxInt = log2(c - 1)
  7265  		v0.AddArg(x)
  7266  		v0.AddArg(x)
  7267  		v.AddArg(v0)
  7268  		return true
  7269  	}
  7270  	// match: (MADD a (MOVDconst [c]) x)
  7271  	// cond: isPowerOfTwo(c+1) && c>=7
  7272  	// result: (SUB a (SUBshiftLL <x.Type> x x [log2(c+1)]))
  7273  	for {
  7274  		x := v.Args[2]
  7275  		a := v.Args[0]
  7276  		v_1 := v.Args[1]
  7277  		if v_1.Op != OpARM64MOVDconst {
  7278  			break
  7279  		}
  7280  		c := v_1.AuxInt
  7281  		if !(isPowerOfTwo(c+1) && c >= 7) {
  7282  			break
  7283  		}
  7284  		v.reset(OpARM64SUB)
  7285  		v.AddArg(a)
  7286  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  7287  		v0.AuxInt = log2(c + 1)
  7288  		v0.AddArg(x)
  7289  		v0.AddArg(x)
  7290  		v.AddArg(v0)
  7291  		return true
  7292  	}
  7293  	// match: (MADD a (MOVDconst [c]) x)
  7294  	// cond: c%3 == 0 && isPowerOfTwo(c/3)
  7295  	// result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log2(c/3)])
  7296  	for {
  7297  		x := v.Args[2]
  7298  		a := v.Args[0]
  7299  		v_1 := v.Args[1]
  7300  		if v_1.Op != OpARM64MOVDconst {
  7301  			break
  7302  		}
  7303  		c := v_1.AuxInt
  7304  		if !(c%3 == 0 && isPowerOfTwo(c/3)) {
  7305  			break
  7306  		}
  7307  		v.reset(OpARM64SUBshiftLL)
  7308  		v.AuxInt = log2(c / 3)
  7309  		v.AddArg(a)
  7310  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  7311  		v0.AuxInt = 2
  7312  		v0.AddArg(x)
  7313  		v0.AddArg(x)
  7314  		v.AddArg(v0)
  7315  		return true
  7316  	}
  7317  	// match: (MADD a (MOVDconst [c]) x)
  7318  	// cond: c%5 == 0 && isPowerOfTwo(c/5)
  7319  	// result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log2(c/5)])
  7320  	for {
  7321  		x := v.Args[2]
  7322  		a := v.Args[0]
  7323  		v_1 := v.Args[1]
  7324  		if v_1.Op != OpARM64MOVDconst {
  7325  			break
  7326  		}
  7327  		c := v_1.AuxInt
  7328  		if !(c%5 == 0 && isPowerOfTwo(c/5)) {
  7329  			break
  7330  		}
  7331  		v.reset(OpARM64ADDshiftLL)
  7332  		v.AuxInt = log2(c / 5)
  7333  		v.AddArg(a)
  7334  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  7335  		v0.AuxInt = 2
  7336  		v0.AddArg(x)
  7337  		v0.AddArg(x)
  7338  		v.AddArg(v0)
  7339  		return true
  7340  	}
  7341  	// match: (MADD a (MOVDconst [c]) x)
  7342  	// cond: c%7 == 0 && isPowerOfTwo(c/7)
  7343  	// result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log2(c/7)])
  7344  	for {
  7345  		x := v.Args[2]
  7346  		a := v.Args[0]
  7347  		v_1 := v.Args[1]
  7348  		if v_1.Op != OpARM64MOVDconst {
  7349  			break
  7350  		}
  7351  		c := v_1.AuxInt
  7352  		if !(c%7 == 0 && isPowerOfTwo(c/7)) {
  7353  			break
  7354  		}
  7355  		v.reset(OpARM64SUBshiftLL)
  7356  		v.AuxInt = log2(c / 7)
  7357  		v.AddArg(a)
  7358  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  7359  		v0.AuxInt = 3
  7360  		v0.AddArg(x)
  7361  		v0.AddArg(x)
  7362  		v.AddArg(v0)
  7363  		return true
  7364  	}
  7365  	// match: (MADD a (MOVDconst [c]) x)
  7366  	// cond: c%9 == 0 && isPowerOfTwo(c/9)
  7367  	// result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log2(c/9)])
  7368  	for {
  7369  		x := v.Args[2]
  7370  		a := v.Args[0]
  7371  		v_1 := v.Args[1]
  7372  		if v_1.Op != OpARM64MOVDconst {
  7373  			break
  7374  		}
  7375  		c := v_1.AuxInt
  7376  		if !(c%9 == 0 && isPowerOfTwo(c/9)) {
  7377  			break
  7378  		}
  7379  		v.reset(OpARM64ADDshiftLL)
  7380  		v.AuxInt = log2(c / 9)
  7381  		v.AddArg(a)
  7382  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  7383  		v0.AuxInt = 3
  7384  		v0.AddArg(x)
  7385  		v0.AddArg(x)
  7386  		v.AddArg(v0)
  7387  		return true
  7388  	}
  7389  	return false
  7390  }
  7391  func rewriteValueARM64_OpARM64MADD_20(v *Value) bool {
  7392  	b := v.Block
  7393  	// match: (MADD (MOVDconst [c]) x y)
  7394  	// cond:
  7395  	// result: (ADDconst [c] (MUL <x.Type> x y))
  7396  	for {
  7397  		y := v.Args[2]
  7398  		v_0 := v.Args[0]
  7399  		if v_0.Op != OpARM64MOVDconst {
  7400  			break
  7401  		}
  7402  		c := v_0.AuxInt
  7403  		x := v.Args[1]
  7404  		v.reset(OpARM64ADDconst)
  7405  		v.AuxInt = c
  7406  		v0 := b.NewValue0(v.Pos, OpARM64MUL, x.Type)
  7407  		v0.AddArg(x)
  7408  		v0.AddArg(y)
  7409  		v.AddArg(v0)
  7410  		return true
  7411  	}
  7412  	// match: (MADD a (MOVDconst [c]) (MOVDconst [d]))
  7413  	// cond:
  7414  	// result: (ADDconst [c*d] a)
  7415  	for {
  7416  		_ = v.Args[2]
  7417  		a := v.Args[0]
  7418  		v_1 := v.Args[1]
  7419  		if v_1.Op != OpARM64MOVDconst {
  7420  			break
  7421  		}
  7422  		c := v_1.AuxInt
  7423  		v_2 := v.Args[2]
  7424  		if v_2.Op != OpARM64MOVDconst {
  7425  			break
  7426  		}
  7427  		d := v_2.AuxInt
  7428  		v.reset(OpARM64ADDconst)
  7429  		v.AuxInt = c * d
  7430  		v.AddArg(a)
  7431  		return true
  7432  	}
  7433  	return false
  7434  }
  7435  func rewriteValueARM64_OpARM64MADDW_0(v *Value) bool {
  7436  	b := v.Block
  7437  	// match: (MADDW a x (MOVDconst [c]))
  7438  	// cond: int32(c)==-1
  7439  	// result: (SUB a x)
  7440  	for {
  7441  		_ = v.Args[2]
  7442  		a := v.Args[0]
  7443  		x := v.Args[1]
  7444  		v_2 := v.Args[2]
  7445  		if v_2.Op != OpARM64MOVDconst {
  7446  			break
  7447  		}
  7448  		c := v_2.AuxInt
  7449  		if !(int32(c) == -1) {
  7450  			break
  7451  		}
  7452  		v.reset(OpARM64SUB)
  7453  		v.AddArg(a)
  7454  		v.AddArg(x)
  7455  		return true
  7456  	}
  7457  	// match: (MADDW a _ (MOVDconst [c]))
  7458  	// cond: int32(c)==0
  7459  	// result: a
  7460  	for {
  7461  		_ = v.Args[2]
  7462  		a := v.Args[0]
  7463  		v_2 := v.Args[2]
  7464  		if v_2.Op != OpARM64MOVDconst {
  7465  			break
  7466  		}
  7467  		c := v_2.AuxInt
  7468  		if !(int32(c) == 0) {
  7469  			break
  7470  		}
  7471  		v.reset(OpCopy)
  7472  		v.Type = a.Type
  7473  		v.AddArg(a)
  7474  		return true
  7475  	}
  7476  	// match: (MADDW a x (MOVDconst [c]))
  7477  	// cond: int32(c)==1
  7478  	// result: (ADD a x)
  7479  	for {
  7480  		_ = v.Args[2]
  7481  		a := v.Args[0]
  7482  		x := v.Args[1]
  7483  		v_2 := v.Args[2]
  7484  		if v_2.Op != OpARM64MOVDconst {
  7485  			break
  7486  		}
  7487  		c := v_2.AuxInt
  7488  		if !(int32(c) == 1) {
  7489  			break
  7490  		}
  7491  		v.reset(OpARM64ADD)
  7492  		v.AddArg(a)
  7493  		v.AddArg(x)
  7494  		return true
  7495  	}
  7496  	// match: (MADDW a x (MOVDconst [c]))
  7497  	// cond: isPowerOfTwo(c)
  7498  	// result: (ADDshiftLL a x [log2(c)])
  7499  	for {
  7500  		_ = v.Args[2]
  7501  		a := v.Args[0]
  7502  		x := v.Args[1]
  7503  		v_2 := v.Args[2]
  7504  		if v_2.Op != OpARM64MOVDconst {
  7505  			break
  7506  		}
  7507  		c := v_2.AuxInt
  7508  		if !(isPowerOfTwo(c)) {
  7509  			break
  7510  		}
  7511  		v.reset(OpARM64ADDshiftLL)
  7512  		v.AuxInt = log2(c)
  7513  		v.AddArg(a)
  7514  		v.AddArg(x)
  7515  		return true
  7516  	}
  7517  	// match: (MADDW a x (MOVDconst [c]))
  7518  	// cond: isPowerOfTwo(c-1) && int32(c)>=3
  7519  	// result: (ADD a (ADDshiftLL <x.Type> x x [log2(c-1)]))
  7520  	for {
  7521  		_ = v.Args[2]
  7522  		a := v.Args[0]
  7523  		x := v.Args[1]
  7524  		v_2 := v.Args[2]
  7525  		if v_2.Op != OpARM64MOVDconst {
  7526  			break
  7527  		}
  7528  		c := v_2.AuxInt
  7529  		if !(isPowerOfTwo(c-1) && int32(c) >= 3) {
  7530  			break
  7531  		}
  7532  		v.reset(OpARM64ADD)
  7533  		v.AddArg(a)
  7534  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  7535  		v0.AuxInt = log2(c - 1)
  7536  		v0.AddArg(x)
  7537  		v0.AddArg(x)
  7538  		v.AddArg(v0)
  7539  		return true
  7540  	}
  7541  	// match: (MADDW a x (MOVDconst [c]))
  7542  	// cond: isPowerOfTwo(c+1) && int32(c)>=7
  7543  	// result: (SUB a (SUBshiftLL <x.Type> x x [log2(c+1)]))
  7544  	for {
  7545  		_ = v.Args[2]
  7546  		a := v.Args[0]
  7547  		x := v.Args[1]
  7548  		v_2 := v.Args[2]
  7549  		if v_2.Op != OpARM64MOVDconst {
  7550  			break
  7551  		}
  7552  		c := v_2.AuxInt
  7553  		if !(isPowerOfTwo(c+1) && int32(c) >= 7) {
  7554  			break
  7555  		}
  7556  		v.reset(OpARM64SUB)
  7557  		v.AddArg(a)
  7558  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  7559  		v0.AuxInt = log2(c + 1)
  7560  		v0.AddArg(x)
  7561  		v0.AddArg(x)
  7562  		v.AddArg(v0)
  7563  		return true
  7564  	}
  7565  	// match: (MADDW a x (MOVDconst [c]))
  7566  	// cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)
  7567  	// result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log2(c/3)])
  7568  	for {
  7569  		_ = v.Args[2]
  7570  		a := v.Args[0]
  7571  		x := v.Args[1]
  7572  		v_2 := v.Args[2]
  7573  		if v_2.Op != OpARM64MOVDconst {
  7574  			break
  7575  		}
  7576  		c := v_2.AuxInt
  7577  		if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) {
  7578  			break
  7579  		}
  7580  		v.reset(OpARM64SUBshiftLL)
  7581  		v.AuxInt = log2(c / 3)
  7582  		v.AddArg(a)
  7583  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  7584  		v0.AuxInt = 2
  7585  		v0.AddArg(x)
  7586  		v0.AddArg(x)
  7587  		v.AddArg(v0)
  7588  		return true
  7589  	}
  7590  	// match: (MADDW a x (MOVDconst [c]))
  7591  	// cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)
  7592  	// result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log2(c/5)])
  7593  	for {
  7594  		_ = v.Args[2]
  7595  		a := v.Args[0]
  7596  		x := v.Args[1]
  7597  		v_2 := v.Args[2]
  7598  		if v_2.Op != OpARM64MOVDconst {
  7599  			break
  7600  		}
  7601  		c := v_2.AuxInt
  7602  		if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) {
  7603  			break
  7604  		}
  7605  		v.reset(OpARM64ADDshiftLL)
  7606  		v.AuxInt = log2(c / 5)
  7607  		v.AddArg(a)
  7608  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  7609  		v0.AuxInt = 2
  7610  		v0.AddArg(x)
  7611  		v0.AddArg(x)
  7612  		v.AddArg(v0)
  7613  		return true
  7614  	}
  7615  	// match: (MADDW a x (MOVDconst [c]))
  7616  	// cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)
  7617  	// result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log2(c/7)])
  7618  	for {
  7619  		_ = v.Args[2]
  7620  		a := v.Args[0]
  7621  		x := v.Args[1]
  7622  		v_2 := v.Args[2]
  7623  		if v_2.Op != OpARM64MOVDconst {
  7624  			break
  7625  		}
  7626  		c := v_2.AuxInt
  7627  		if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) {
  7628  			break
  7629  		}
  7630  		v.reset(OpARM64SUBshiftLL)
  7631  		v.AuxInt = log2(c / 7)
  7632  		v.AddArg(a)
  7633  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  7634  		v0.AuxInt = 3
  7635  		v0.AddArg(x)
  7636  		v0.AddArg(x)
  7637  		v.AddArg(v0)
  7638  		return true
  7639  	}
  7640  	// match: (MADDW a x (MOVDconst [c]))
  7641  	// cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)
  7642  	// result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log2(c/9)])
  7643  	for {
  7644  		_ = v.Args[2]
  7645  		a := v.Args[0]
  7646  		x := v.Args[1]
  7647  		v_2 := v.Args[2]
  7648  		if v_2.Op != OpARM64MOVDconst {
  7649  			break
  7650  		}
  7651  		c := v_2.AuxInt
  7652  		if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) {
  7653  			break
  7654  		}
  7655  		v.reset(OpARM64ADDshiftLL)
  7656  		v.AuxInt = log2(c / 9)
  7657  		v.AddArg(a)
  7658  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  7659  		v0.AuxInt = 3
  7660  		v0.AddArg(x)
  7661  		v0.AddArg(x)
  7662  		v.AddArg(v0)
  7663  		return true
  7664  	}
  7665  	return false
  7666  }
  7667  func rewriteValueARM64_OpARM64MADDW_10(v *Value) bool {
  7668  	b := v.Block
  7669  	// match: (MADDW a (MOVDconst [c]) x)
  7670  	// cond: int32(c)==-1
  7671  	// result: (SUB a x)
  7672  	for {
  7673  		x := v.Args[2]
  7674  		a := v.Args[0]
  7675  		v_1 := v.Args[1]
  7676  		if v_1.Op != OpARM64MOVDconst {
  7677  			break
  7678  		}
  7679  		c := v_1.AuxInt
  7680  		if !(int32(c) == -1) {
  7681  			break
  7682  		}
  7683  		v.reset(OpARM64SUB)
  7684  		v.AddArg(a)
  7685  		v.AddArg(x)
  7686  		return true
  7687  	}
  7688  	// match: (MADDW a (MOVDconst [c]) _)
  7689  	// cond: int32(c)==0
  7690  	// result: a
  7691  	for {
  7692  		_ = v.Args[2]
  7693  		a := v.Args[0]
  7694  		v_1 := v.Args[1]
  7695  		if v_1.Op != OpARM64MOVDconst {
  7696  			break
  7697  		}
  7698  		c := v_1.AuxInt
  7699  		if !(int32(c) == 0) {
  7700  			break
  7701  		}
  7702  		v.reset(OpCopy)
  7703  		v.Type = a.Type
  7704  		v.AddArg(a)
  7705  		return true
  7706  	}
  7707  	// match: (MADDW a (MOVDconst [c]) x)
  7708  	// cond: int32(c)==1
  7709  	// result: (ADD a x)
  7710  	for {
  7711  		x := v.Args[2]
  7712  		a := v.Args[0]
  7713  		v_1 := v.Args[1]
  7714  		if v_1.Op != OpARM64MOVDconst {
  7715  			break
  7716  		}
  7717  		c := v_1.AuxInt
  7718  		if !(int32(c) == 1) {
  7719  			break
  7720  		}
  7721  		v.reset(OpARM64ADD)
  7722  		v.AddArg(a)
  7723  		v.AddArg(x)
  7724  		return true
  7725  	}
  7726  	// match: (MADDW a (MOVDconst [c]) x)
  7727  	// cond: isPowerOfTwo(c)
  7728  	// result: (ADDshiftLL a x [log2(c)])
  7729  	for {
  7730  		x := v.Args[2]
  7731  		a := v.Args[0]
  7732  		v_1 := v.Args[1]
  7733  		if v_1.Op != OpARM64MOVDconst {
  7734  			break
  7735  		}
  7736  		c := v_1.AuxInt
  7737  		if !(isPowerOfTwo(c)) {
  7738  			break
  7739  		}
  7740  		v.reset(OpARM64ADDshiftLL)
  7741  		v.AuxInt = log2(c)
  7742  		v.AddArg(a)
  7743  		v.AddArg(x)
  7744  		return true
  7745  	}
  7746  	// match: (MADDW a (MOVDconst [c]) x)
  7747  	// cond: isPowerOfTwo(c-1) && int32(c)>=3
  7748  	// result: (ADD a (ADDshiftLL <x.Type> x x [log2(c-1)]))
  7749  	for {
  7750  		x := v.Args[2]
  7751  		a := v.Args[0]
  7752  		v_1 := v.Args[1]
  7753  		if v_1.Op != OpARM64MOVDconst {
  7754  			break
  7755  		}
  7756  		c := v_1.AuxInt
  7757  		if !(isPowerOfTwo(c-1) && int32(c) >= 3) {
  7758  			break
  7759  		}
  7760  		v.reset(OpARM64ADD)
  7761  		v.AddArg(a)
  7762  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  7763  		v0.AuxInt = log2(c - 1)
  7764  		v0.AddArg(x)
  7765  		v0.AddArg(x)
  7766  		v.AddArg(v0)
  7767  		return true
  7768  	}
  7769  	// match: (MADDW a (MOVDconst [c]) x)
  7770  	// cond: isPowerOfTwo(c+1) && int32(c)>=7
  7771  	// result: (SUB a (SUBshiftLL <x.Type> x x [log2(c+1)]))
  7772  	for {
  7773  		x := v.Args[2]
  7774  		a := v.Args[0]
  7775  		v_1 := v.Args[1]
  7776  		if v_1.Op != OpARM64MOVDconst {
  7777  			break
  7778  		}
  7779  		c := v_1.AuxInt
  7780  		if !(isPowerOfTwo(c+1) && int32(c) >= 7) {
  7781  			break
  7782  		}
  7783  		v.reset(OpARM64SUB)
  7784  		v.AddArg(a)
  7785  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  7786  		v0.AuxInt = log2(c + 1)
  7787  		v0.AddArg(x)
  7788  		v0.AddArg(x)
  7789  		v.AddArg(v0)
  7790  		return true
  7791  	}
  7792  	// match: (MADDW a (MOVDconst [c]) x)
  7793  	// cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)
  7794  	// result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log2(c/3)])
  7795  	for {
  7796  		x := v.Args[2]
  7797  		a := v.Args[0]
  7798  		v_1 := v.Args[1]
  7799  		if v_1.Op != OpARM64MOVDconst {
  7800  			break
  7801  		}
  7802  		c := v_1.AuxInt
  7803  		if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) {
  7804  			break
  7805  		}
  7806  		v.reset(OpARM64SUBshiftLL)
  7807  		v.AuxInt = log2(c / 3)
  7808  		v.AddArg(a)
  7809  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  7810  		v0.AuxInt = 2
  7811  		v0.AddArg(x)
  7812  		v0.AddArg(x)
  7813  		v.AddArg(v0)
  7814  		return true
  7815  	}
  7816  	// match: (MADDW a (MOVDconst [c]) x)
  7817  	// cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)
  7818  	// result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log2(c/5)])
  7819  	for {
  7820  		x := v.Args[2]
  7821  		a := v.Args[0]
  7822  		v_1 := v.Args[1]
  7823  		if v_1.Op != OpARM64MOVDconst {
  7824  			break
  7825  		}
  7826  		c := v_1.AuxInt
  7827  		if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) {
  7828  			break
  7829  		}
  7830  		v.reset(OpARM64ADDshiftLL)
  7831  		v.AuxInt = log2(c / 5)
  7832  		v.AddArg(a)
  7833  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  7834  		v0.AuxInt = 2
  7835  		v0.AddArg(x)
  7836  		v0.AddArg(x)
  7837  		v.AddArg(v0)
  7838  		return true
  7839  	}
  7840  	// match: (MADDW a (MOVDconst [c]) x)
  7841  	// cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)
  7842  	// result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log2(c/7)])
  7843  	for {
  7844  		x := v.Args[2]
  7845  		a := v.Args[0]
  7846  		v_1 := v.Args[1]
  7847  		if v_1.Op != OpARM64MOVDconst {
  7848  			break
  7849  		}
  7850  		c := v_1.AuxInt
  7851  		if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) {
  7852  			break
  7853  		}
  7854  		v.reset(OpARM64SUBshiftLL)
  7855  		v.AuxInt = log2(c / 7)
  7856  		v.AddArg(a)
  7857  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  7858  		v0.AuxInt = 3
  7859  		v0.AddArg(x)
  7860  		v0.AddArg(x)
  7861  		v.AddArg(v0)
  7862  		return true
  7863  	}
  7864  	// match: (MADDW a (MOVDconst [c]) x)
  7865  	// cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)
  7866  	// result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log2(c/9)])
  7867  	for {
  7868  		x := v.Args[2]
  7869  		a := v.Args[0]
  7870  		v_1 := v.Args[1]
  7871  		if v_1.Op != OpARM64MOVDconst {
  7872  			break
  7873  		}
  7874  		c := v_1.AuxInt
  7875  		if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) {
  7876  			break
  7877  		}
  7878  		v.reset(OpARM64ADDshiftLL)
  7879  		v.AuxInt = log2(c / 9)
  7880  		v.AddArg(a)
  7881  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  7882  		v0.AuxInt = 3
  7883  		v0.AddArg(x)
  7884  		v0.AddArg(x)
  7885  		v.AddArg(v0)
  7886  		return true
  7887  	}
  7888  	return false
  7889  }
  7890  func rewriteValueARM64_OpARM64MADDW_20(v *Value) bool {
  7891  	b := v.Block
  7892  	// match: (MADDW (MOVDconst [c]) x y)
  7893  	// cond:
  7894  	// result: (ADDconst [c] (MULW <x.Type> x y))
  7895  	for {
  7896  		y := v.Args[2]
  7897  		v_0 := v.Args[0]
  7898  		if v_0.Op != OpARM64MOVDconst {
  7899  			break
  7900  		}
  7901  		c := v_0.AuxInt
  7902  		x := v.Args[1]
  7903  		v.reset(OpARM64ADDconst)
  7904  		v.AuxInt = c
  7905  		v0 := b.NewValue0(v.Pos, OpARM64MULW, x.Type)
  7906  		v0.AddArg(x)
  7907  		v0.AddArg(y)
  7908  		v.AddArg(v0)
  7909  		return true
  7910  	}
  7911  	// match: (MADDW a (MOVDconst [c]) (MOVDconst [d]))
  7912  	// cond:
  7913  	// result: (ADDconst [int64(int32(c)*int32(d))] a)
  7914  	for {
  7915  		_ = v.Args[2]
  7916  		a := v.Args[0]
  7917  		v_1 := v.Args[1]
  7918  		if v_1.Op != OpARM64MOVDconst {
  7919  			break
  7920  		}
  7921  		c := v_1.AuxInt
  7922  		v_2 := v.Args[2]
  7923  		if v_2.Op != OpARM64MOVDconst {
  7924  			break
  7925  		}
  7926  		d := v_2.AuxInt
  7927  		v.reset(OpARM64ADDconst)
  7928  		v.AuxInt = int64(int32(c) * int32(d))
  7929  		v.AddArg(a)
  7930  		return true
  7931  	}
  7932  	return false
  7933  }
  7934  func rewriteValueARM64_OpARM64MNEG_0(v *Value) bool {
  7935  	b := v.Block
  7936  	// match: (MNEG x (MOVDconst [-1]))
  7937  	// cond:
  7938  	// result: x
  7939  	for {
  7940  		_ = v.Args[1]
  7941  		x := v.Args[0]
  7942  		v_1 := v.Args[1]
  7943  		if v_1.Op != OpARM64MOVDconst {
  7944  			break
  7945  		}
  7946  		if v_1.AuxInt != -1 {
  7947  			break
  7948  		}
  7949  		v.reset(OpCopy)
  7950  		v.Type = x.Type
  7951  		v.AddArg(x)
  7952  		return true
  7953  	}
  7954  	// match: (MNEG (MOVDconst [-1]) x)
  7955  	// cond:
  7956  	// result: x
  7957  	for {
  7958  		x := v.Args[1]
  7959  		v_0 := v.Args[0]
  7960  		if v_0.Op != OpARM64MOVDconst {
  7961  			break
  7962  		}
  7963  		if v_0.AuxInt != -1 {
  7964  			break
  7965  		}
  7966  		v.reset(OpCopy)
  7967  		v.Type = x.Type
  7968  		v.AddArg(x)
  7969  		return true
  7970  	}
  7971  	// match: (MNEG _ (MOVDconst [0]))
  7972  	// cond:
  7973  	// result: (MOVDconst [0])
  7974  	for {
  7975  		_ = v.Args[1]
  7976  		v_1 := v.Args[1]
  7977  		if v_1.Op != OpARM64MOVDconst {
  7978  			break
  7979  		}
  7980  		if v_1.AuxInt != 0 {
  7981  			break
  7982  		}
  7983  		v.reset(OpARM64MOVDconst)
  7984  		v.AuxInt = 0
  7985  		return true
  7986  	}
  7987  	// match: (MNEG (MOVDconst [0]) _)
  7988  	// cond:
  7989  	// result: (MOVDconst [0])
  7990  	for {
  7991  		_ = v.Args[1]
  7992  		v_0 := v.Args[0]
  7993  		if v_0.Op != OpARM64MOVDconst {
  7994  			break
  7995  		}
  7996  		if v_0.AuxInt != 0 {
  7997  			break
  7998  		}
  7999  		v.reset(OpARM64MOVDconst)
  8000  		v.AuxInt = 0
  8001  		return true
  8002  	}
  8003  	// match: (MNEG x (MOVDconst [1]))
  8004  	// cond:
  8005  	// result: (NEG x)
  8006  	for {
  8007  		_ = v.Args[1]
  8008  		x := v.Args[0]
  8009  		v_1 := v.Args[1]
  8010  		if v_1.Op != OpARM64MOVDconst {
  8011  			break
  8012  		}
  8013  		if v_1.AuxInt != 1 {
  8014  			break
  8015  		}
  8016  		v.reset(OpARM64NEG)
  8017  		v.AddArg(x)
  8018  		return true
  8019  	}
  8020  	// match: (MNEG (MOVDconst [1]) x)
  8021  	// cond:
  8022  	// result: (NEG x)
  8023  	for {
  8024  		x := v.Args[1]
  8025  		v_0 := v.Args[0]
  8026  		if v_0.Op != OpARM64MOVDconst {
  8027  			break
  8028  		}
  8029  		if v_0.AuxInt != 1 {
  8030  			break
  8031  		}
  8032  		v.reset(OpARM64NEG)
  8033  		v.AddArg(x)
  8034  		return true
  8035  	}
  8036  	// match: (MNEG x (MOVDconst [c]))
  8037  	// cond: isPowerOfTwo(c)
  8038  	// result: (NEG (SLLconst <x.Type> [log2(c)] x))
  8039  	for {
  8040  		_ = v.Args[1]
  8041  		x := v.Args[0]
  8042  		v_1 := v.Args[1]
  8043  		if v_1.Op != OpARM64MOVDconst {
  8044  			break
  8045  		}
  8046  		c := v_1.AuxInt
  8047  		if !(isPowerOfTwo(c)) {
  8048  			break
  8049  		}
  8050  		v.reset(OpARM64NEG)
  8051  		v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
  8052  		v0.AuxInt = log2(c)
  8053  		v0.AddArg(x)
  8054  		v.AddArg(v0)
  8055  		return true
  8056  	}
  8057  	// match: (MNEG (MOVDconst [c]) x)
  8058  	// cond: isPowerOfTwo(c)
  8059  	// result: (NEG (SLLconst <x.Type> [log2(c)] x))
  8060  	for {
  8061  		x := v.Args[1]
  8062  		v_0 := v.Args[0]
  8063  		if v_0.Op != OpARM64MOVDconst {
  8064  			break
  8065  		}
  8066  		c := v_0.AuxInt
  8067  		if !(isPowerOfTwo(c)) {
  8068  			break
  8069  		}
  8070  		v.reset(OpARM64NEG)
  8071  		v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
  8072  		v0.AuxInt = log2(c)
  8073  		v0.AddArg(x)
  8074  		v.AddArg(v0)
  8075  		return true
  8076  	}
  8077  	// match: (MNEG x (MOVDconst [c]))
  8078  	// cond: isPowerOfTwo(c-1) && c >= 3
  8079  	// result: (NEG (ADDshiftLL <x.Type> x x [log2(c-1)]))
  8080  	for {
  8081  		_ = v.Args[1]
  8082  		x := v.Args[0]
  8083  		v_1 := v.Args[1]
  8084  		if v_1.Op != OpARM64MOVDconst {
  8085  			break
  8086  		}
  8087  		c := v_1.AuxInt
  8088  		if !(isPowerOfTwo(c-1) && c >= 3) {
  8089  			break
  8090  		}
  8091  		v.reset(OpARM64NEG)
  8092  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  8093  		v0.AuxInt = log2(c - 1)
  8094  		v0.AddArg(x)
  8095  		v0.AddArg(x)
  8096  		v.AddArg(v0)
  8097  		return true
  8098  	}
  8099  	// match: (MNEG (MOVDconst [c]) x)
  8100  	// cond: isPowerOfTwo(c-1) && c >= 3
  8101  	// result: (NEG (ADDshiftLL <x.Type> x x [log2(c-1)]))
  8102  	for {
  8103  		x := v.Args[1]
  8104  		v_0 := v.Args[0]
  8105  		if v_0.Op != OpARM64MOVDconst {
  8106  			break
  8107  		}
  8108  		c := v_0.AuxInt
  8109  		if !(isPowerOfTwo(c-1) && c >= 3) {
  8110  			break
  8111  		}
  8112  		v.reset(OpARM64NEG)
  8113  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  8114  		v0.AuxInt = log2(c - 1)
  8115  		v0.AddArg(x)
  8116  		v0.AddArg(x)
  8117  		v.AddArg(v0)
  8118  		return true
  8119  	}
  8120  	return false
  8121  }
  8122  func rewriteValueARM64_OpARM64MNEG_10(v *Value) bool {
  8123  	b := v.Block
  8124  	// match: (MNEG x (MOVDconst [c]))
  8125  	// cond: isPowerOfTwo(c+1) && c >= 7
  8126  	// result: (NEG (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log2(c+1)]))
  8127  	for {
  8128  		_ = v.Args[1]
  8129  		x := v.Args[0]
  8130  		v_1 := v.Args[1]
  8131  		if v_1.Op != OpARM64MOVDconst {
  8132  			break
  8133  		}
  8134  		c := v_1.AuxInt
  8135  		if !(isPowerOfTwo(c+1) && c >= 7) {
  8136  			break
  8137  		}
  8138  		v.reset(OpARM64NEG)
  8139  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  8140  		v0.AuxInt = log2(c + 1)
  8141  		v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type)
  8142  		v1.AddArg(x)
  8143  		v0.AddArg(v1)
  8144  		v0.AddArg(x)
  8145  		v.AddArg(v0)
  8146  		return true
  8147  	}
  8148  	// match: (MNEG (MOVDconst [c]) x)
  8149  	// cond: isPowerOfTwo(c+1) && c >= 7
  8150  	// result: (NEG (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log2(c+1)]))
  8151  	for {
  8152  		x := v.Args[1]
  8153  		v_0 := v.Args[0]
  8154  		if v_0.Op != OpARM64MOVDconst {
  8155  			break
  8156  		}
  8157  		c := v_0.AuxInt
  8158  		if !(isPowerOfTwo(c+1) && c >= 7) {
  8159  			break
  8160  		}
  8161  		v.reset(OpARM64NEG)
  8162  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  8163  		v0.AuxInt = log2(c + 1)
  8164  		v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type)
  8165  		v1.AddArg(x)
  8166  		v0.AddArg(v1)
  8167  		v0.AddArg(x)
  8168  		v.AddArg(v0)
  8169  		return true
  8170  	}
  8171  	// match: (MNEG x (MOVDconst [c]))
  8172  	// cond: c%3 == 0 && isPowerOfTwo(c/3)
  8173  	// result: (SLLconst <x.Type> [log2(c/3)] (SUBshiftLL <x.Type> x x [2]))
  8174  	for {
  8175  		_ = v.Args[1]
  8176  		x := v.Args[0]
  8177  		v_1 := v.Args[1]
  8178  		if v_1.Op != OpARM64MOVDconst {
  8179  			break
  8180  		}
  8181  		c := v_1.AuxInt
  8182  		if !(c%3 == 0 && isPowerOfTwo(c/3)) {
  8183  			break
  8184  		}
  8185  		v.reset(OpARM64SLLconst)
  8186  		v.Type = x.Type
  8187  		v.AuxInt = log2(c / 3)
  8188  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  8189  		v0.AuxInt = 2
  8190  		v0.AddArg(x)
  8191  		v0.AddArg(x)
  8192  		v.AddArg(v0)
  8193  		return true
  8194  	}
  8195  	// match: (MNEG (MOVDconst [c]) x)
  8196  	// cond: c%3 == 0 && isPowerOfTwo(c/3)
  8197  	// result: (SLLconst <x.Type> [log2(c/3)] (SUBshiftLL <x.Type> x x [2]))
  8198  	for {
  8199  		x := v.Args[1]
  8200  		v_0 := v.Args[0]
  8201  		if v_0.Op != OpARM64MOVDconst {
  8202  			break
  8203  		}
  8204  		c := v_0.AuxInt
  8205  		if !(c%3 == 0 && isPowerOfTwo(c/3)) {
  8206  			break
  8207  		}
  8208  		v.reset(OpARM64SLLconst)
  8209  		v.Type = x.Type
  8210  		v.AuxInt = log2(c / 3)
  8211  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  8212  		v0.AuxInt = 2
  8213  		v0.AddArg(x)
  8214  		v0.AddArg(x)
  8215  		v.AddArg(v0)
  8216  		return true
  8217  	}
  8218  	// match: (MNEG x (MOVDconst [c]))
  8219  	// cond: c%5 == 0 && isPowerOfTwo(c/5)
  8220  	// result: (NEG (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2])))
  8221  	for {
  8222  		_ = v.Args[1]
  8223  		x := v.Args[0]
  8224  		v_1 := v.Args[1]
  8225  		if v_1.Op != OpARM64MOVDconst {
  8226  			break
  8227  		}
  8228  		c := v_1.AuxInt
  8229  		if !(c%5 == 0 && isPowerOfTwo(c/5)) {
  8230  			break
  8231  		}
  8232  		v.reset(OpARM64NEG)
  8233  		v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
  8234  		v0.AuxInt = log2(c / 5)
  8235  		v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  8236  		v1.AuxInt = 2
  8237  		v1.AddArg(x)
  8238  		v1.AddArg(x)
  8239  		v0.AddArg(v1)
  8240  		v.AddArg(v0)
  8241  		return true
  8242  	}
  8243  	// match: (MNEG (MOVDconst [c]) x)
  8244  	// cond: c%5 == 0 && isPowerOfTwo(c/5)
  8245  	// result: (NEG (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2])))
  8246  	for {
  8247  		x := v.Args[1]
  8248  		v_0 := v.Args[0]
  8249  		if v_0.Op != OpARM64MOVDconst {
  8250  			break
  8251  		}
  8252  		c := v_0.AuxInt
  8253  		if !(c%5 == 0 && isPowerOfTwo(c/5)) {
  8254  			break
  8255  		}
  8256  		v.reset(OpARM64NEG)
  8257  		v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
  8258  		v0.AuxInt = log2(c / 5)
  8259  		v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  8260  		v1.AuxInt = 2
  8261  		v1.AddArg(x)
  8262  		v1.AddArg(x)
  8263  		v0.AddArg(v1)
  8264  		v.AddArg(v0)
  8265  		return true
  8266  	}
  8267  	// match: (MNEG x (MOVDconst [c]))
  8268  	// cond: c%7 == 0 && isPowerOfTwo(c/7)
  8269  	// result: (SLLconst <x.Type> [log2(c/7)] (SUBshiftLL <x.Type> x x [3]))
  8270  	for {
  8271  		_ = v.Args[1]
  8272  		x := v.Args[0]
  8273  		v_1 := v.Args[1]
  8274  		if v_1.Op != OpARM64MOVDconst {
  8275  			break
  8276  		}
  8277  		c := v_1.AuxInt
  8278  		if !(c%7 == 0 && isPowerOfTwo(c/7)) {
  8279  			break
  8280  		}
  8281  		v.reset(OpARM64SLLconst)
  8282  		v.Type = x.Type
  8283  		v.AuxInt = log2(c / 7)
  8284  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  8285  		v0.AuxInt = 3
  8286  		v0.AddArg(x)
  8287  		v0.AddArg(x)
  8288  		v.AddArg(v0)
  8289  		return true
  8290  	}
  8291  	// match: (MNEG (MOVDconst [c]) x)
  8292  	// cond: c%7 == 0 && isPowerOfTwo(c/7)
  8293  	// result: (SLLconst <x.Type> [log2(c/7)] (SUBshiftLL <x.Type> x x [3]))
  8294  	for {
  8295  		x := v.Args[1]
  8296  		v_0 := v.Args[0]
  8297  		if v_0.Op != OpARM64MOVDconst {
  8298  			break
  8299  		}
  8300  		c := v_0.AuxInt
  8301  		if !(c%7 == 0 && isPowerOfTwo(c/7)) {
  8302  			break
  8303  		}
  8304  		v.reset(OpARM64SLLconst)
  8305  		v.Type = x.Type
  8306  		v.AuxInt = log2(c / 7)
  8307  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  8308  		v0.AuxInt = 3
  8309  		v0.AddArg(x)
  8310  		v0.AddArg(x)
  8311  		v.AddArg(v0)
  8312  		return true
  8313  	}
  8314  	// match: (MNEG x (MOVDconst [c]))
  8315  	// cond: c%9 == 0 && isPowerOfTwo(c/9)
  8316  	// result: (NEG (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3])))
  8317  	for {
  8318  		_ = v.Args[1]
  8319  		x := v.Args[0]
  8320  		v_1 := v.Args[1]
  8321  		if v_1.Op != OpARM64MOVDconst {
  8322  			break
  8323  		}
  8324  		c := v_1.AuxInt
  8325  		if !(c%9 == 0 && isPowerOfTwo(c/9)) {
  8326  			break
  8327  		}
  8328  		v.reset(OpARM64NEG)
  8329  		v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
  8330  		v0.AuxInt = log2(c / 9)
  8331  		v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  8332  		v1.AuxInt = 3
  8333  		v1.AddArg(x)
  8334  		v1.AddArg(x)
  8335  		v0.AddArg(v1)
  8336  		v.AddArg(v0)
  8337  		return true
  8338  	}
  8339  	// match: (MNEG (MOVDconst [c]) x)
  8340  	// cond: c%9 == 0 && isPowerOfTwo(c/9)
  8341  	// result: (NEG (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3])))
  8342  	for {
  8343  		x := v.Args[1]
  8344  		v_0 := v.Args[0]
  8345  		if v_0.Op != OpARM64MOVDconst {
  8346  			break
  8347  		}
  8348  		c := v_0.AuxInt
  8349  		if !(c%9 == 0 && isPowerOfTwo(c/9)) {
  8350  			break
  8351  		}
  8352  		v.reset(OpARM64NEG)
  8353  		v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
  8354  		v0.AuxInt = log2(c / 9)
  8355  		v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  8356  		v1.AuxInt = 3
  8357  		v1.AddArg(x)
  8358  		v1.AddArg(x)
  8359  		v0.AddArg(v1)
  8360  		v.AddArg(v0)
  8361  		return true
  8362  	}
  8363  	return false
  8364  }
  8365  func rewriteValueARM64_OpARM64MNEG_20(v *Value) bool {
  8366  	// match: (MNEG (MOVDconst [c]) (MOVDconst [d]))
  8367  	// cond:
  8368  	// result: (MOVDconst [-c*d])
  8369  	for {
  8370  		_ = v.Args[1]
  8371  		v_0 := v.Args[0]
  8372  		if v_0.Op != OpARM64MOVDconst {
  8373  			break
  8374  		}
  8375  		c := v_0.AuxInt
  8376  		v_1 := v.Args[1]
  8377  		if v_1.Op != OpARM64MOVDconst {
  8378  			break
  8379  		}
  8380  		d := v_1.AuxInt
  8381  		v.reset(OpARM64MOVDconst)
  8382  		v.AuxInt = -c * d
  8383  		return true
  8384  	}
  8385  	// match: (MNEG (MOVDconst [d]) (MOVDconst [c]))
  8386  	// cond:
  8387  	// result: (MOVDconst [-c*d])
  8388  	for {
  8389  		_ = v.Args[1]
  8390  		v_0 := v.Args[0]
  8391  		if v_0.Op != OpARM64MOVDconst {
  8392  			break
  8393  		}
  8394  		d := v_0.AuxInt
  8395  		v_1 := v.Args[1]
  8396  		if v_1.Op != OpARM64MOVDconst {
  8397  			break
  8398  		}
  8399  		c := v_1.AuxInt
  8400  		v.reset(OpARM64MOVDconst)
  8401  		v.AuxInt = -c * d
  8402  		return true
  8403  	}
  8404  	return false
  8405  }
  8406  func rewriteValueARM64_OpARM64MNEGW_0(v *Value) bool {
  8407  	b := v.Block
  8408  	// match: (MNEGW x (MOVDconst [c]))
  8409  	// cond: int32(c)==-1
  8410  	// result: x
  8411  	for {
  8412  		_ = v.Args[1]
  8413  		x := v.Args[0]
  8414  		v_1 := v.Args[1]
  8415  		if v_1.Op != OpARM64MOVDconst {
  8416  			break
  8417  		}
  8418  		c := v_1.AuxInt
  8419  		if !(int32(c) == -1) {
  8420  			break
  8421  		}
  8422  		v.reset(OpCopy)
  8423  		v.Type = x.Type
  8424  		v.AddArg(x)
  8425  		return true
  8426  	}
  8427  	// match: (MNEGW (MOVDconst [c]) x)
  8428  	// cond: int32(c)==-1
  8429  	// result: x
  8430  	for {
  8431  		x := v.Args[1]
  8432  		v_0 := v.Args[0]
  8433  		if v_0.Op != OpARM64MOVDconst {
  8434  			break
  8435  		}
  8436  		c := v_0.AuxInt
  8437  		if !(int32(c) == -1) {
  8438  			break
  8439  		}
  8440  		v.reset(OpCopy)
  8441  		v.Type = x.Type
  8442  		v.AddArg(x)
  8443  		return true
  8444  	}
  8445  	// match: (MNEGW _ (MOVDconst [c]))
  8446  	// cond: int32(c)==0
  8447  	// result: (MOVDconst [0])
  8448  	for {
  8449  		_ = v.Args[1]
  8450  		v_1 := v.Args[1]
  8451  		if v_1.Op != OpARM64MOVDconst {
  8452  			break
  8453  		}
  8454  		c := v_1.AuxInt
  8455  		if !(int32(c) == 0) {
  8456  			break
  8457  		}
  8458  		v.reset(OpARM64MOVDconst)
  8459  		v.AuxInt = 0
  8460  		return true
  8461  	}
  8462  	// match: (MNEGW (MOVDconst [c]) _)
  8463  	// cond: int32(c)==0
  8464  	// result: (MOVDconst [0])
  8465  	for {
  8466  		_ = v.Args[1]
  8467  		v_0 := v.Args[0]
  8468  		if v_0.Op != OpARM64MOVDconst {
  8469  			break
  8470  		}
  8471  		c := v_0.AuxInt
  8472  		if !(int32(c) == 0) {
  8473  			break
  8474  		}
  8475  		v.reset(OpARM64MOVDconst)
  8476  		v.AuxInt = 0
  8477  		return true
  8478  	}
  8479  	// match: (MNEGW x (MOVDconst [c]))
  8480  	// cond: int32(c)==1
  8481  	// result: (NEG x)
  8482  	for {
  8483  		_ = v.Args[1]
  8484  		x := v.Args[0]
  8485  		v_1 := v.Args[1]
  8486  		if v_1.Op != OpARM64MOVDconst {
  8487  			break
  8488  		}
  8489  		c := v_1.AuxInt
  8490  		if !(int32(c) == 1) {
  8491  			break
  8492  		}
  8493  		v.reset(OpARM64NEG)
  8494  		v.AddArg(x)
  8495  		return true
  8496  	}
  8497  	// match: (MNEGW (MOVDconst [c]) x)
  8498  	// cond: int32(c)==1
  8499  	// result: (NEG x)
  8500  	for {
  8501  		x := v.Args[1]
  8502  		v_0 := v.Args[0]
  8503  		if v_0.Op != OpARM64MOVDconst {
  8504  			break
  8505  		}
  8506  		c := v_0.AuxInt
  8507  		if !(int32(c) == 1) {
  8508  			break
  8509  		}
  8510  		v.reset(OpARM64NEG)
  8511  		v.AddArg(x)
  8512  		return true
  8513  	}
  8514  	// match: (MNEGW x (MOVDconst [c]))
  8515  	// cond: isPowerOfTwo(c)
  8516  	// result: (NEG (SLLconst <x.Type> [log2(c)] x))
  8517  	for {
  8518  		_ = v.Args[1]
  8519  		x := v.Args[0]
  8520  		v_1 := v.Args[1]
  8521  		if v_1.Op != OpARM64MOVDconst {
  8522  			break
  8523  		}
  8524  		c := v_1.AuxInt
  8525  		if !(isPowerOfTwo(c)) {
  8526  			break
  8527  		}
  8528  		v.reset(OpARM64NEG)
  8529  		v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
  8530  		v0.AuxInt = log2(c)
  8531  		v0.AddArg(x)
  8532  		v.AddArg(v0)
  8533  		return true
  8534  	}
  8535  	// match: (MNEGW (MOVDconst [c]) x)
  8536  	// cond: isPowerOfTwo(c)
  8537  	// result: (NEG (SLLconst <x.Type> [log2(c)] x))
  8538  	for {
  8539  		x := v.Args[1]
  8540  		v_0 := v.Args[0]
  8541  		if v_0.Op != OpARM64MOVDconst {
  8542  			break
  8543  		}
  8544  		c := v_0.AuxInt
  8545  		if !(isPowerOfTwo(c)) {
  8546  			break
  8547  		}
  8548  		v.reset(OpARM64NEG)
  8549  		v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
  8550  		v0.AuxInt = log2(c)
  8551  		v0.AddArg(x)
  8552  		v.AddArg(v0)
  8553  		return true
  8554  	}
  8555  	// match: (MNEGW x (MOVDconst [c]))
  8556  	// cond: isPowerOfTwo(c-1) && int32(c) >= 3
  8557  	// result: (NEG (ADDshiftLL <x.Type> x x [log2(c-1)]))
  8558  	for {
  8559  		_ = v.Args[1]
  8560  		x := v.Args[0]
  8561  		v_1 := v.Args[1]
  8562  		if v_1.Op != OpARM64MOVDconst {
  8563  			break
  8564  		}
  8565  		c := v_1.AuxInt
  8566  		if !(isPowerOfTwo(c-1) && int32(c) >= 3) {
  8567  			break
  8568  		}
  8569  		v.reset(OpARM64NEG)
  8570  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  8571  		v0.AuxInt = log2(c - 1)
  8572  		v0.AddArg(x)
  8573  		v0.AddArg(x)
  8574  		v.AddArg(v0)
  8575  		return true
  8576  	}
  8577  	// match: (MNEGW (MOVDconst [c]) x)
  8578  	// cond: isPowerOfTwo(c-1) && int32(c) >= 3
  8579  	// result: (NEG (ADDshiftLL <x.Type> x x [log2(c-1)]))
  8580  	for {
  8581  		x := v.Args[1]
  8582  		v_0 := v.Args[0]
  8583  		if v_0.Op != OpARM64MOVDconst {
  8584  			break
  8585  		}
  8586  		c := v_0.AuxInt
  8587  		if !(isPowerOfTwo(c-1) && int32(c) >= 3) {
  8588  			break
  8589  		}
  8590  		v.reset(OpARM64NEG)
  8591  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  8592  		v0.AuxInt = log2(c - 1)
  8593  		v0.AddArg(x)
  8594  		v0.AddArg(x)
  8595  		v.AddArg(v0)
  8596  		return true
  8597  	}
  8598  	return false
  8599  }
  8600  func rewriteValueARM64_OpARM64MNEGW_10(v *Value) bool {
  8601  	b := v.Block
  8602  	// match: (MNEGW x (MOVDconst [c]))
  8603  	// cond: isPowerOfTwo(c+1) && int32(c) >= 7
  8604  	// result: (NEG (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log2(c+1)]))
  8605  	for {
  8606  		_ = v.Args[1]
  8607  		x := v.Args[0]
  8608  		v_1 := v.Args[1]
  8609  		if v_1.Op != OpARM64MOVDconst {
  8610  			break
  8611  		}
  8612  		c := v_1.AuxInt
  8613  		if !(isPowerOfTwo(c+1) && int32(c) >= 7) {
  8614  			break
  8615  		}
  8616  		v.reset(OpARM64NEG)
  8617  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  8618  		v0.AuxInt = log2(c + 1)
  8619  		v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type)
  8620  		v1.AddArg(x)
  8621  		v0.AddArg(v1)
  8622  		v0.AddArg(x)
  8623  		v.AddArg(v0)
  8624  		return true
  8625  	}
  8626  	// match: (MNEGW (MOVDconst [c]) x)
  8627  	// cond: isPowerOfTwo(c+1) && int32(c) >= 7
  8628  	// result: (NEG (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log2(c+1)]))
  8629  	for {
  8630  		x := v.Args[1]
  8631  		v_0 := v.Args[0]
  8632  		if v_0.Op != OpARM64MOVDconst {
  8633  			break
  8634  		}
  8635  		c := v_0.AuxInt
  8636  		if !(isPowerOfTwo(c+1) && int32(c) >= 7) {
  8637  			break
  8638  		}
  8639  		v.reset(OpARM64NEG)
  8640  		v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  8641  		v0.AuxInt = log2(c + 1)
  8642  		v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type)
  8643  		v1.AddArg(x)
  8644  		v0.AddArg(v1)
  8645  		v0.AddArg(x)
  8646  		v.AddArg(v0)
  8647  		return true
  8648  	}
  8649  	// match: (MNEGW x (MOVDconst [c]))
  8650  	// cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)
  8651  	// result: (SLLconst <x.Type> [log2(c/3)] (SUBshiftLL <x.Type> x x [2]))
  8652  	for {
  8653  		_ = v.Args[1]
  8654  		x := v.Args[0]
  8655  		v_1 := v.Args[1]
  8656  		if v_1.Op != OpARM64MOVDconst {
  8657  			break
  8658  		}
  8659  		c := v_1.AuxInt
  8660  		if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) {
  8661  			break
  8662  		}
  8663  		v.reset(OpARM64SLLconst)
  8664  		v.Type = x.Type
  8665  		v.AuxInt = log2(c / 3)
  8666  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  8667  		v0.AuxInt = 2
  8668  		v0.AddArg(x)
  8669  		v0.AddArg(x)
  8670  		v.AddArg(v0)
  8671  		return true
  8672  	}
  8673  	// match: (MNEGW (MOVDconst [c]) x)
  8674  	// cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)
  8675  	// result: (SLLconst <x.Type> [log2(c/3)] (SUBshiftLL <x.Type> x x [2]))
  8676  	for {
  8677  		x := v.Args[1]
  8678  		v_0 := v.Args[0]
  8679  		if v_0.Op != OpARM64MOVDconst {
  8680  			break
  8681  		}
  8682  		c := v_0.AuxInt
  8683  		if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) {
  8684  			break
  8685  		}
  8686  		v.reset(OpARM64SLLconst)
  8687  		v.Type = x.Type
  8688  		v.AuxInt = log2(c / 3)
  8689  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  8690  		v0.AuxInt = 2
  8691  		v0.AddArg(x)
  8692  		v0.AddArg(x)
  8693  		v.AddArg(v0)
  8694  		return true
  8695  	}
  8696  	// match: (MNEGW x (MOVDconst [c]))
  8697  	// cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)
  8698  	// result: (NEG (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2])))
  8699  	for {
  8700  		_ = v.Args[1]
  8701  		x := v.Args[0]
  8702  		v_1 := v.Args[1]
  8703  		if v_1.Op != OpARM64MOVDconst {
  8704  			break
  8705  		}
  8706  		c := v_1.AuxInt
  8707  		if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) {
  8708  			break
  8709  		}
  8710  		v.reset(OpARM64NEG)
  8711  		v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
  8712  		v0.AuxInt = log2(c / 5)
  8713  		v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  8714  		v1.AuxInt = 2
  8715  		v1.AddArg(x)
  8716  		v1.AddArg(x)
  8717  		v0.AddArg(v1)
  8718  		v.AddArg(v0)
  8719  		return true
  8720  	}
  8721  	// match: (MNEGW (MOVDconst [c]) x)
  8722  	// cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)
  8723  	// result: (NEG (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2])))
  8724  	for {
  8725  		x := v.Args[1]
  8726  		v_0 := v.Args[0]
  8727  		if v_0.Op != OpARM64MOVDconst {
  8728  			break
  8729  		}
  8730  		c := v_0.AuxInt
  8731  		if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) {
  8732  			break
  8733  		}
  8734  		v.reset(OpARM64NEG)
  8735  		v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
  8736  		v0.AuxInt = log2(c / 5)
  8737  		v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  8738  		v1.AuxInt = 2
  8739  		v1.AddArg(x)
  8740  		v1.AddArg(x)
  8741  		v0.AddArg(v1)
  8742  		v.AddArg(v0)
  8743  		return true
  8744  	}
  8745  	// match: (MNEGW x (MOVDconst [c]))
  8746  	// cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)
  8747  	// result: (SLLconst <x.Type> [log2(c/7)] (SUBshiftLL <x.Type> x x [3]))
  8748  	for {
  8749  		_ = v.Args[1]
  8750  		x := v.Args[0]
  8751  		v_1 := v.Args[1]
  8752  		if v_1.Op != OpARM64MOVDconst {
  8753  			break
  8754  		}
  8755  		c := v_1.AuxInt
  8756  		if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) {
  8757  			break
  8758  		}
  8759  		v.reset(OpARM64SLLconst)
  8760  		v.Type = x.Type
  8761  		v.AuxInt = log2(c / 7)
  8762  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  8763  		v0.AuxInt = 3
  8764  		v0.AddArg(x)
  8765  		v0.AddArg(x)
  8766  		v.AddArg(v0)
  8767  		return true
  8768  	}
  8769  	// match: (MNEGW (MOVDconst [c]) x)
  8770  	// cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)
  8771  	// result: (SLLconst <x.Type> [log2(c/7)] (SUBshiftLL <x.Type> x x [3]))
  8772  	for {
  8773  		x := v.Args[1]
  8774  		v_0 := v.Args[0]
  8775  		if v_0.Op != OpARM64MOVDconst {
  8776  			break
  8777  		}
  8778  		c := v_0.AuxInt
  8779  		if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) {
  8780  			break
  8781  		}
  8782  		v.reset(OpARM64SLLconst)
  8783  		v.Type = x.Type
  8784  		v.AuxInt = log2(c / 7)
  8785  		v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
  8786  		v0.AuxInt = 3
  8787  		v0.AddArg(x)
  8788  		v0.AddArg(x)
  8789  		v.AddArg(v0)
  8790  		return true
  8791  	}
  8792  	// match: (MNEGW x (MOVDconst [c]))
  8793  	// cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)
  8794  	// result: (NEG (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3])))
  8795  	for {
  8796  		_ = v.Args[1]
  8797  		x := v.Args[0]
  8798  		v_1 := v.Args[1]
  8799  		if v_1.Op != OpARM64MOVDconst {
  8800  			break
  8801  		}
  8802  		c := v_1.AuxInt
  8803  		if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) {
  8804  			break
  8805  		}
  8806  		v.reset(OpARM64NEG)
  8807  		v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
  8808  		v0.AuxInt = log2(c / 9)
  8809  		v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  8810  		v1.AuxInt = 3
  8811  		v1.AddArg(x)
  8812  		v1.AddArg(x)
  8813  		v0.AddArg(v1)
  8814  		v.AddArg(v0)
  8815  		return true
  8816  	}
  8817  	// match: (MNEGW (MOVDconst [c]) x)
  8818  	// cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)
  8819  	// result: (NEG (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3])))
  8820  	for {
  8821  		x := v.Args[1]
  8822  		v_0 := v.Args[0]
  8823  		if v_0.Op != OpARM64MOVDconst {
  8824  			break
  8825  		}
  8826  		c := v_0.AuxInt
  8827  		if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) {
  8828  			break
  8829  		}
  8830  		v.reset(OpARM64NEG)
  8831  		v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
  8832  		v0.AuxInt = log2(c / 9)
  8833  		v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
  8834  		v1.AuxInt = 3
  8835  		v1.AddArg(x)
  8836  		v1.AddArg(x)
  8837  		v0.AddArg(v1)
  8838  		v.AddArg(v0)
  8839  		return true
  8840  	}
  8841  	return false
  8842  }
  8843  func rewriteValueARM64_OpARM64MNEGW_20(v *Value) bool {
  8844  	// match: (MNEGW (MOVDconst [c]) (MOVDconst [d]))
  8845  	// cond:
  8846  	// result: (MOVDconst [-int64(int32(c)*int32(d))])
  8847  	for {
  8848  		_ = v.Args[1]
  8849  		v_0 := v.Args[0]
  8850  		if v_0.Op != OpARM64MOVDconst {
  8851  			break
  8852  		}
  8853  		c := v_0.AuxInt
  8854  		v_1 := v.Args[1]
  8855  		if v_1.Op != OpARM64MOVDconst {
  8856  			break
  8857  		}
  8858  		d := v_1.AuxInt
  8859  		v.reset(OpARM64MOVDconst)
  8860  		v.AuxInt = -int64(int32(c) * int32(d))
  8861  		return true
  8862  	}
  8863  	// match: (MNEGW (MOVDconst [d]) (MOVDconst [c]))
  8864  	// cond:
  8865  	// result: (MOVDconst [-int64(int32(c)*int32(d))])
  8866  	for {
  8867  		_ = v.Args[1]
  8868  		v_0 := v.Args[0]
  8869  		if v_0.Op != OpARM64MOVDconst {
  8870  			break
  8871  		}
  8872  		d := v_0.AuxInt
  8873  		v_1 := v.Args[1]
  8874  		if v_1.Op != OpARM64MOVDconst {
  8875  			break
  8876  		}
  8877  		c := v_1.AuxInt
  8878  		v.reset(OpARM64MOVDconst)
  8879  		v.AuxInt = -int64(int32(c) * int32(d))
  8880  		return true
  8881  	}
  8882  	return false
  8883  }
  8884  func rewriteValueARM64_OpARM64MOD_0(v *Value) bool {
  8885  	// match: (MOD (MOVDconst [c]) (MOVDconst [d]))
  8886  	// cond:
  8887  	// result: (MOVDconst [c%d])
  8888  	for {
  8889  		_ = v.Args[1]
  8890  		v_0 := v.Args[0]
  8891  		if v_0.Op != OpARM64MOVDconst {
  8892  			break
  8893  		}
  8894  		c := v_0.AuxInt
  8895  		v_1 := v.Args[1]
  8896  		if v_1.Op != OpARM64MOVDconst {
  8897  			break
  8898  		}
  8899  		d := v_1.AuxInt
  8900  		v.reset(OpARM64MOVDconst)
  8901  		v.AuxInt = c % d
  8902  		return true
  8903  	}
  8904  	return false
  8905  }
  8906  func rewriteValueARM64_OpARM64MODW_0(v *Value) bool {
  8907  	// match: (MODW (MOVDconst [c]) (MOVDconst [d]))
  8908  	// cond:
  8909  	// result: (MOVDconst [int64(int32(c)%int32(d))])
  8910  	for {
  8911  		_ = v.Args[1]
  8912  		v_0 := v.Args[0]
  8913  		if v_0.Op != OpARM64MOVDconst {
  8914  			break
  8915  		}
  8916  		c := v_0.AuxInt
  8917  		v_1 := v.Args[1]
  8918  		if v_1.Op != OpARM64MOVDconst {
  8919  			break
  8920  		}
  8921  		d := v_1.AuxInt
  8922  		v.reset(OpARM64MOVDconst)
  8923  		v.AuxInt = int64(int32(c) % int32(d))
  8924  		return true
  8925  	}
  8926  	return false
  8927  }
  8928  func rewriteValueARM64_OpARM64MOVBUload_0(v *Value) bool {
  8929  	b := v.Block
  8930  	config := b.Func.Config
  8931  	// match: (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem)
  8932  	// cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  8933  	// result: (MOVBUload [off1+off2] {sym} ptr mem)
  8934  	for {
  8935  		off1 := v.AuxInt
  8936  		sym := v.Aux
  8937  		mem := v.Args[1]
  8938  		v_0 := v.Args[0]
  8939  		if v_0.Op != OpARM64ADDconst {
  8940  			break
  8941  		}
  8942  		off2 := v_0.AuxInt
  8943  		ptr := v_0.Args[0]
  8944  		if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  8945  			break
  8946  		}
  8947  		v.reset(OpARM64MOVBUload)
  8948  		v.AuxInt = off1 + off2
  8949  		v.Aux = sym
  8950  		v.AddArg(ptr)
  8951  		v.AddArg(mem)
  8952  		return true
  8953  	}
  8954  	// match: (MOVBUload [off] {sym} (ADD ptr idx) mem)
  8955  	// cond: off == 0 && sym == nil
  8956  	// result: (MOVBUloadidx ptr idx mem)
  8957  	for {
  8958  		off := v.AuxInt
  8959  		sym := v.Aux
  8960  		mem := v.Args[1]
  8961  		v_0 := v.Args[0]
  8962  		if v_0.Op != OpARM64ADD {
  8963  			break
  8964  		}
  8965  		idx := v_0.Args[1]
  8966  		ptr := v_0.Args[0]
  8967  		if !(off == 0 && sym == nil) {
  8968  			break
  8969  		}
  8970  		v.reset(OpARM64MOVBUloadidx)
  8971  		v.AddArg(ptr)
  8972  		v.AddArg(idx)
  8973  		v.AddArg(mem)
  8974  		return true
  8975  	}
  8976  	// match: (MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
  8977  	// cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  8978  	// result: (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
  8979  	for {
  8980  		off1 := v.AuxInt
  8981  		sym1 := v.Aux
  8982  		mem := v.Args[1]
  8983  		v_0 := v.Args[0]
  8984  		if v_0.Op != OpARM64MOVDaddr {
  8985  			break
  8986  		}
  8987  		off2 := v_0.AuxInt
  8988  		sym2 := v_0.Aux
  8989  		ptr := v_0.Args[0]
  8990  		if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  8991  			break
  8992  		}
  8993  		v.reset(OpARM64MOVBUload)
  8994  		v.AuxInt = off1 + off2
  8995  		v.Aux = mergeSym(sym1, sym2)
  8996  		v.AddArg(ptr)
  8997  		v.AddArg(mem)
  8998  		return true
  8999  	}
  9000  	// match: (MOVBUload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _))
  9001  	// cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
  9002  	// result: (MOVDconst [0])
  9003  	for {
  9004  		off := v.AuxInt
  9005  		sym := v.Aux
  9006  		_ = v.Args[1]
  9007  		ptr := v.Args[0]
  9008  		v_1 := v.Args[1]
  9009  		if v_1.Op != OpARM64MOVBstorezero {
  9010  			break
  9011  		}
  9012  		off2 := v_1.AuxInt
  9013  		sym2 := v_1.Aux
  9014  		_ = v_1.Args[1]
  9015  		ptr2 := v_1.Args[0]
  9016  		if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
  9017  			break
  9018  		}
  9019  		v.reset(OpARM64MOVDconst)
  9020  		v.AuxInt = 0
  9021  		return true
  9022  	}
  9023  	// match: (MOVBUload [off] {sym} (SB) _)
  9024  	// cond: symIsRO(sym)
  9025  	// result: (MOVDconst [int64(read8(sym, off))])
  9026  	for {
  9027  		off := v.AuxInt
  9028  		sym := v.Aux
  9029  		_ = v.Args[1]
  9030  		v_0 := v.Args[0]
  9031  		if v_0.Op != OpSB {
  9032  			break
  9033  		}
  9034  		if !(symIsRO(sym)) {
  9035  			break
  9036  		}
  9037  		v.reset(OpARM64MOVDconst)
  9038  		v.AuxInt = int64(read8(sym, off))
  9039  		return true
  9040  	}
  9041  	return false
  9042  }
  9043  func rewriteValueARM64_OpARM64MOVBUloadidx_0(v *Value) bool {
  9044  	// match: (MOVBUloadidx ptr (MOVDconst [c]) mem)
  9045  	// cond:
  9046  	// result: (MOVBUload [c] ptr mem)
  9047  	for {
  9048  		mem := v.Args[2]
  9049  		ptr := v.Args[0]
  9050  		v_1 := v.Args[1]
  9051  		if v_1.Op != OpARM64MOVDconst {
  9052  			break
  9053  		}
  9054  		c := v_1.AuxInt
  9055  		v.reset(OpARM64MOVBUload)
  9056  		v.AuxInt = c
  9057  		v.AddArg(ptr)
  9058  		v.AddArg(mem)
  9059  		return true
  9060  	}
  9061  	// match: (MOVBUloadidx (MOVDconst [c]) ptr mem)
  9062  	// cond:
  9063  	// result: (MOVBUload [c] ptr mem)
  9064  	for {
  9065  		mem := v.Args[2]
  9066  		v_0 := v.Args[0]
  9067  		if v_0.Op != OpARM64MOVDconst {
  9068  			break
  9069  		}
  9070  		c := v_0.AuxInt
  9071  		ptr := v.Args[1]
  9072  		v.reset(OpARM64MOVBUload)
  9073  		v.AuxInt = c
  9074  		v.AddArg(ptr)
  9075  		v.AddArg(mem)
  9076  		return true
  9077  	}
  9078  	// match: (MOVBUloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _))
  9079  	// cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2))
  9080  	// result: (MOVDconst [0])
  9081  	for {
  9082  		_ = v.Args[2]
  9083  		ptr := v.Args[0]
  9084  		idx := v.Args[1]
  9085  		v_2 := v.Args[2]
  9086  		if v_2.Op != OpARM64MOVBstorezeroidx {
  9087  			break
  9088  		}
  9089  		_ = v_2.Args[2]
  9090  		ptr2 := v_2.Args[0]
  9091  		idx2 := v_2.Args[1]
  9092  		if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) {
  9093  			break
  9094  		}
  9095  		v.reset(OpARM64MOVDconst)
  9096  		v.AuxInt = 0
  9097  		return true
  9098  	}
  9099  	return false
  9100  }
  9101  func rewriteValueARM64_OpARM64MOVBUreg_0(v *Value) bool {
  9102  	// match: (MOVBUreg x:(MOVBUload _ _))
  9103  	// cond:
  9104  	// result: (MOVDreg x)
  9105  	for {
  9106  		x := v.Args[0]
  9107  		if x.Op != OpARM64MOVBUload {
  9108  			break
  9109  		}
  9110  		_ = x.Args[1]
  9111  		v.reset(OpARM64MOVDreg)
  9112  		v.AddArg(x)
  9113  		return true
  9114  	}
  9115  	// match: (MOVBUreg x:(MOVBUloadidx _ _ _))
  9116  	// cond:
  9117  	// result: (MOVDreg x)
  9118  	for {
  9119  		x := v.Args[0]
  9120  		if x.Op != OpARM64MOVBUloadidx {
  9121  			break
  9122  		}
  9123  		_ = x.Args[2]
  9124  		v.reset(OpARM64MOVDreg)
  9125  		v.AddArg(x)
  9126  		return true
  9127  	}
  9128  	// match: (MOVBUreg x:(MOVBUreg _))
  9129  	// cond:
  9130  	// result: (MOVDreg x)
  9131  	for {
  9132  		x := v.Args[0]
  9133  		if x.Op != OpARM64MOVBUreg {
  9134  			break
  9135  		}
  9136  		v.reset(OpARM64MOVDreg)
  9137  		v.AddArg(x)
  9138  		return true
  9139  	}
  9140  	// match: (MOVBUreg (ANDconst [c] x))
  9141  	// cond:
  9142  	// result: (ANDconst [c&(1<<8-1)] x)
  9143  	for {
  9144  		v_0 := v.Args[0]
  9145  		if v_0.Op != OpARM64ANDconst {
  9146  			break
  9147  		}
  9148  		c := v_0.AuxInt
  9149  		x := v_0.Args[0]
  9150  		v.reset(OpARM64ANDconst)
  9151  		v.AuxInt = c & (1<<8 - 1)
  9152  		v.AddArg(x)
  9153  		return true
  9154  	}
  9155  	// match: (MOVBUreg (MOVDconst [c]))
  9156  	// cond:
  9157  	// result: (MOVDconst [int64(uint8(c))])
  9158  	for {
  9159  		v_0 := v.Args[0]
  9160  		if v_0.Op != OpARM64MOVDconst {
  9161  			break
  9162  		}
  9163  		c := v_0.AuxInt
  9164  		v.reset(OpARM64MOVDconst)
  9165  		v.AuxInt = int64(uint8(c))
  9166  		return true
  9167  	}
  9168  	// match: (MOVBUreg x)
  9169  	// cond: x.Type.IsBoolean()
  9170  	// result: (MOVDreg x)
  9171  	for {
  9172  		x := v.Args[0]
  9173  		if !(x.Type.IsBoolean()) {
  9174  			break
  9175  		}
  9176  		v.reset(OpARM64MOVDreg)
  9177  		v.AddArg(x)
  9178  		return true
  9179  	}
  9180  	// match: (MOVBUreg (SLLconst [sc] x))
  9181  	// cond: isARM64BFMask(sc, 1<<8-1, sc)
  9182  	// result: (UBFIZ [armBFAuxInt(sc, arm64BFWidth(1<<8-1, sc))] x)
  9183  	for {
  9184  		v_0 := v.Args[0]
  9185  		if v_0.Op != OpARM64SLLconst {
  9186  			break
  9187  		}
  9188  		sc := v_0.AuxInt
  9189  		x := v_0.Args[0]
  9190  		if !(isARM64BFMask(sc, 1<<8-1, sc)) {
  9191  			break
  9192  		}
  9193  		v.reset(OpARM64UBFIZ)
  9194  		v.AuxInt = armBFAuxInt(sc, arm64BFWidth(1<<8-1, sc))
  9195  		v.AddArg(x)
  9196  		return true
  9197  	}
  9198  	// match: (MOVBUreg (SRLconst [sc] x))
  9199  	// cond: isARM64BFMask(sc, 1<<8-1, 0)
  9200  	// result: (UBFX [armBFAuxInt(sc, 8)] x)
  9201  	for {
  9202  		v_0 := v.Args[0]
  9203  		if v_0.Op != OpARM64SRLconst {
  9204  			break
  9205  		}
  9206  		sc := v_0.AuxInt
  9207  		x := v_0.Args[0]
  9208  		if !(isARM64BFMask(sc, 1<<8-1, 0)) {
  9209  			break
  9210  		}
  9211  		v.reset(OpARM64UBFX)
  9212  		v.AuxInt = armBFAuxInt(sc, 8)
  9213  		v.AddArg(x)
  9214  		return true
  9215  	}
  9216  	return false
  9217  }
  9218  func rewriteValueARM64_OpARM64MOVBload_0(v *Value) bool {
  9219  	b := v.Block
  9220  	config := b.Func.Config
  9221  	// match: (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem)
  9222  	// cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  9223  	// result: (MOVBload [off1+off2] {sym} ptr mem)
  9224  	for {
  9225  		off1 := v.AuxInt
  9226  		sym := v.Aux
  9227  		mem := v.Args[1]
  9228  		v_0 := v.Args[0]
  9229  		if v_0.Op != OpARM64ADDconst {
  9230  			break
  9231  		}
  9232  		off2 := v_0.AuxInt
  9233  		ptr := v_0.Args[0]
  9234  		if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  9235  			break
  9236  		}
  9237  		v.reset(OpARM64MOVBload)
  9238  		v.AuxInt = off1 + off2
  9239  		v.Aux = sym
  9240  		v.AddArg(ptr)
  9241  		v.AddArg(mem)
  9242  		return true
  9243  	}
  9244  	// match: (MOVBload [off] {sym} (ADD ptr idx) mem)
  9245  	// cond: off == 0 && sym == nil
  9246  	// result: (MOVBloadidx ptr idx mem)
  9247  	for {
  9248  		off := v.AuxInt
  9249  		sym := v.Aux
  9250  		mem := v.Args[1]
  9251  		v_0 := v.Args[0]
  9252  		if v_0.Op != OpARM64ADD {
  9253  			break
  9254  		}
  9255  		idx := v_0.Args[1]
  9256  		ptr := v_0.Args[0]
  9257  		if !(off == 0 && sym == nil) {
  9258  			break
  9259  		}
  9260  		v.reset(OpARM64MOVBloadidx)
  9261  		v.AddArg(ptr)
  9262  		v.AddArg(idx)
  9263  		v.AddArg(mem)
  9264  		return true
  9265  	}
  9266  	// match: (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
  9267  	// cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  9268  	// result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
  9269  	for {
  9270  		off1 := v.AuxInt
  9271  		sym1 := v.Aux
  9272  		mem := v.Args[1]
  9273  		v_0 := v.Args[0]
  9274  		if v_0.Op != OpARM64MOVDaddr {
  9275  			break
  9276  		}
  9277  		off2 := v_0.AuxInt
  9278  		sym2 := v_0.Aux
  9279  		ptr := v_0.Args[0]
  9280  		if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  9281  			break
  9282  		}
  9283  		v.reset(OpARM64MOVBload)
  9284  		v.AuxInt = off1 + off2
  9285  		v.Aux = mergeSym(sym1, sym2)
  9286  		v.AddArg(ptr)
  9287  		v.AddArg(mem)
  9288  		return true
  9289  	}
  9290  	// match: (MOVBload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _))
  9291  	// cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
  9292  	// result: (MOVDconst [0])
  9293  	for {
  9294  		off := v.AuxInt
  9295  		sym := v.Aux
  9296  		_ = v.Args[1]
  9297  		ptr := v.Args[0]
  9298  		v_1 := v.Args[1]
  9299  		if v_1.Op != OpARM64MOVBstorezero {
  9300  			break
  9301  		}
  9302  		off2 := v_1.AuxInt
  9303  		sym2 := v_1.Aux
  9304  		_ = v_1.Args[1]
  9305  		ptr2 := v_1.Args[0]
  9306  		if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
  9307  			break
  9308  		}
  9309  		v.reset(OpARM64MOVDconst)
  9310  		v.AuxInt = 0
  9311  		return true
  9312  	}
  9313  	return false
  9314  }
  9315  func rewriteValueARM64_OpARM64MOVBloadidx_0(v *Value) bool {
  9316  	// match: (MOVBloadidx ptr (MOVDconst [c]) mem)
  9317  	// cond:
  9318  	// result: (MOVBload [c] ptr mem)
  9319  	for {
  9320  		mem := v.Args[2]
  9321  		ptr := v.Args[0]
  9322  		v_1 := v.Args[1]
  9323  		if v_1.Op != OpARM64MOVDconst {
  9324  			break
  9325  		}
  9326  		c := v_1.AuxInt
  9327  		v.reset(OpARM64MOVBload)
  9328  		v.AuxInt = c
  9329  		v.AddArg(ptr)
  9330  		v.AddArg(mem)
  9331  		return true
  9332  	}
  9333  	// match: (MOVBloadidx (MOVDconst [c]) ptr mem)
  9334  	// cond:
  9335  	// result: (MOVBload [c] ptr mem)
  9336  	for {
  9337  		mem := v.Args[2]
  9338  		v_0 := v.Args[0]
  9339  		if v_0.Op != OpARM64MOVDconst {
  9340  			break
  9341  		}
  9342  		c := v_0.AuxInt
  9343  		ptr := v.Args[1]
  9344  		v.reset(OpARM64MOVBload)
  9345  		v.AuxInt = c
  9346  		v.AddArg(ptr)
  9347  		v.AddArg(mem)
  9348  		return true
  9349  	}
  9350  	// match: (MOVBloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _))
  9351  	// cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2))
  9352  	// result: (MOVDconst [0])
  9353  	for {
  9354  		_ = v.Args[2]
  9355  		ptr := v.Args[0]
  9356  		idx := v.Args[1]
  9357  		v_2 := v.Args[2]
  9358  		if v_2.Op != OpARM64MOVBstorezeroidx {
  9359  			break
  9360  		}
  9361  		_ = v_2.Args[2]
  9362  		ptr2 := v_2.Args[0]
  9363  		idx2 := v_2.Args[1]
  9364  		if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) {
  9365  			break
  9366  		}
  9367  		v.reset(OpARM64MOVDconst)
  9368  		v.AuxInt = 0
  9369  		return true
  9370  	}
  9371  	return false
  9372  }
  9373  func rewriteValueARM64_OpARM64MOVBreg_0(v *Value) bool {
  9374  	// match: (MOVBreg x:(MOVBload _ _))
  9375  	// cond:
  9376  	// result: (MOVDreg x)
  9377  	for {
  9378  		x := v.Args[0]
  9379  		if x.Op != OpARM64MOVBload {
  9380  			break
  9381  		}
  9382  		_ = x.Args[1]
  9383  		v.reset(OpARM64MOVDreg)
  9384  		v.AddArg(x)
  9385  		return true
  9386  	}
  9387  	// match: (MOVBreg x:(MOVBloadidx _ _ _))
  9388  	// cond:
  9389  	// result: (MOVDreg x)
  9390  	for {
  9391  		x := v.Args[0]
  9392  		if x.Op != OpARM64MOVBloadidx {
  9393  			break
  9394  		}
  9395  		_ = x.Args[2]
  9396  		v.reset(OpARM64MOVDreg)
  9397  		v.AddArg(x)
  9398  		return true
  9399  	}
  9400  	// match: (MOVBreg x:(MOVBreg _))
  9401  	// cond:
  9402  	// result: (MOVDreg x)
  9403  	for {
  9404  		x := v.Args[0]
  9405  		if x.Op != OpARM64MOVBreg {
  9406  			break
  9407  		}
  9408  		v.reset(OpARM64MOVDreg)
  9409  		v.AddArg(x)
  9410  		return true
  9411  	}
  9412  	// match: (MOVBreg (MOVDconst [c]))
  9413  	// cond:
  9414  	// result: (MOVDconst [int64(int8(c))])
  9415  	for {
  9416  		v_0 := v.Args[0]
  9417  		if v_0.Op != OpARM64MOVDconst {
  9418  			break
  9419  		}
  9420  		c := v_0.AuxInt
  9421  		v.reset(OpARM64MOVDconst)
  9422  		v.AuxInt = int64(int8(c))
  9423  		return true
  9424  	}
  9425  	// match: (MOVBreg (SLLconst [lc] x))
  9426  	// cond: lc < 8
  9427  	// result: (SBFIZ [armBFAuxInt(lc, 8-lc)] x)
  9428  	for {
  9429  		v_0 := v.Args[0]
  9430  		if v_0.Op != OpARM64SLLconst {
  9431  			break
  9432  		}
  9433  		lc := v_0.AuxInt
  9434  		x := v_0.Args[0]
  9435  		if !(lc < 8) {
  9436  			break
  9437  		}
  9438  		v.reset(OpARM64SBFIZ)
  9439  		v.AuxInt = armBFAuxInt(lc, 8-lc)
  9440  		v.AddArg(x)
  9441  		return true
  9442  	}
  9443  	return false
  9444  }
  9445  func rewriteValueARM64_OpARM64MOVBstore_0(v *Value) bool {
  9446  	b := v.Block
  9447  	config := b.Func.Config
  9448  	// match: (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem)
  9449  	// cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  9450  	// result: (MOVBstore [off1+off2] {sym} ptr val mem)
  9451  	for {
  9452  		off1 := v.AuxInt
  9453  		sym := v.Aux
  9454  		mem := v.Args[2]
  9455  		v_0 := v.Args[0]
  9456  		if v_0.Op != OpARM64ADDconst {
  9457  			break
  9458  		}
  9459  		off2 := v_0.AuxInt
  9460  		ptr := v_0.Args[0]
  9461  		val := v.Args[1]
  9462  		if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  9463  			break
  9464  		}
  9465  		v.reset(OpARM64MOVBstore)
  9466  		v.AuxInt = off1 + off2
  9467  		v.Aux = sym
  9468  		v.AddArg(ptr)
  9469  		v.AddArg(val)
  9470  		v.AddArg(mem)
  9471  		return true
  9472  	}
  9473  	// match: (MOVBstore [off] {sym} (ADD ptr idx) val mem)
  9474  	// cond: off == 0 && sym == nil
  9475  	// result: (MOVBstoreidx ptr idx val mem)
  9476  	for {
  9477  		off := v.AuxInt
  9478  		sym := v.Aux
  9479  		mem := v.Args[2]
  9480  		v_0 := v.Args[0]
  9481  		if v_0.Op != OpARM64ADD {
  9482  			break
  9483  		}
  9484  		idx := v_0.Args[1]
  9485  		ptr := v_0.Args[0]
  9486  		val := v.Args[1]
  9487  		if !(off == 0 && sym == nil) {
  9488  			break
  9489  		}
  9490  		v.reset(OpARM64MOVBstoreidx)
  9491  		v.AddArg(ptr)
  9492  		v.AddArg(idx)
  9493  		v.AddArg(val)
  9494  		v.AddArg(mem)
  9495  		return true
  9496  	}
  9497  	// match: (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
  9498  	// cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  9499  	// result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
  9500  	for {
  9501  		off1 := v.AuxInt
  9502  		sym1 := v.Aux
  9503  		mem := v.Args[2]
  9504  		v_0 := v.Args[0]
  9505  		if v_0.Op != OpARM64MOVDaddr {
  9506  			break
  9507  		}
  9508  		off2 := v_0.AuxInt
  9509  		sym2 := v_0.Aux
  9510  		ptr := v_0.Args[0]
  9511  		val := v.Args[1]
  9512  		if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  9513  			break
  9514  		}
  9515  		v.reset(OpARM64MOVBstore)
  9516  		v.AuxInt = off1 + off2
  9517  		v.Aux = mergeSym(sym1, sym2)
  9518  		v.AddArg(ptr)
  9519  		v.AddArg(val)
  9520  		v.AddArg(mem)
  9521  		return true
  9522  	}
  9523  	// match: (MOVBstore [off] {sym} ptr (MOVDconst [0]) mem)
  9524  	// cond:
  9525  	// result: (MOVBstorezero [off] {sym} ptr mem)
  9526  	for {
  9527  		off := v.AuxInt
  9528  		sym := v.Aux
  9529  		mem := v.Args[2]
  9530  		ptr := v.Args[0]
  9531  		v_1 := v.Args[1]
  9532  		if v_1.Op != OpARM64MOVDconst {
  9533  			break
  9534  		}
  9535  		if v_1.AuxInt != 0 {
  9536  			break
  9537  		}
  9538  		v.reset(OpARM64MOVBstorezero)
  9539  		v.AuxInt = off
  9540  		v.Aux = sym
  9541  		v.AddArg(ptr)
  9542  		v.AddArg(mem)
  9543  		return true
  9544  	}
  9545  	// match: (MOVBstore [off] {sym} ptr (MOVBreg x) mem)
  9546  	// cond:
  9547  	// result: (MOVBstore [off] {sym} ptr x mem)
  9548  	for {
  9549  		off := v.AuxInt
  9550  		sym := v.Aux
  9551  		mem := v.Args[2]
  9552  		ptr := v.Args[0]
  9553  		v_1 := v.Args[1]
  9554  		if v_1.Op != OpARM64MOVBreg {
  9555  			break
  9556  		}
  9557  		x := v_1.Args[0]
  9558  		v.reset(OpARM64MOVBstore)
  9559  		v.AuxInt = off
  9560  		v.Aux = sym
  9561  		v.AddArg(ptr)
  9562  		v.AddArg(x)
  9563  		v.AddArg(mem)
  9564  		return true
  9565  	}
  9566  	// match: (MOVBstore [off] {sym} ptr (MOVBUreg x) mem)
  9567  	// cond:
  9568  	// result: (MOVBstore [off] {sym} ptr x mem)
  9569  	for {
  9570  		off := v.AuxInt
  9571  		sym := v.Aux
  9572  		mem := v.Args[2]
  9573  		ptr := v.Args[0]
  9574  		v_1 := v.Args[1]
  9575  		if v_1.Op != OpARM64MOVBUreg {
  9576  			break
  9577  		}
  9578  		x := v_1.Args[0]
  9579  		v.reset(OpARM64MOVBstore)
  9580  		v.AuxInt = off
  9581  		v.Aux = sym
  9582  		v.AddArg(ptr)
  9583  		v.AddArg(x)
  9584  		v.AddArg(mem)
  9585  		return true
  9586  	}
  9587  	// match: (MOVBstore [off] {sym} ptr (MOVHreg x) mem)
  9588  	// cond:
  9589  	// result: (MOVBstore [off] {sym} ptr x mem)
  9590  	for {
  9591  		off := v.AuxInt
  9592  		sym := v.Aux
  9593  		mem := v.Args[2]
  9594  		ptr := v.Args[0]
  9595  		v_1 := v.Args[1]
  9596  		if v_1.Op != OpARM64MOVHreg {
  9597  			break
  9598  		}
  9599  		x := v_1.Args[0]
  9600  		v.reset(OpARM64MOVBstore)
  9601  		v.AuxInt = off
  9602  		v.Aux = sym
  9603  		v.AddArg(ptr)
  9604  		v.AddArg(x)
  9605  		v.AddArg(mem)
  9606  		return true
  9607  	}
  9608  	// match: (MOVBstore [off] {sym} ptr (MOVHUreg x) mem)
  9609  	// cond:
  9610  	// result: (MOVBstore [off] {sym} ptr x mem)
  9611  	for {
  9612  		off := v.AuxInt
  9613  		sym := v.Aux
  9614  		mem := v.Args[2]
  9615  		ptr := v.Args[0]
  9616  		v_1 := v.Args[1]
  9617  		if v_1.Op != OpARM64MOVHUreg {
  9618  			break
  9619  		}
  9620  		x := v_1.Args[0]
  9621  		v.reset(OpARM64MOVBstore)
  9622  		v.AuxInt = off
  9623  		v.Aux = sym
  9624  		v.AddArg(ptr)
  9625  		v.AddArg(x)
  9626  		v.AddArg(mem)
  9627  		return true
  9628  	}
  9629  	// match: (MOVBstore [off] {sym} ptr (MOVWreg x) mem)
  9630  	// cond:
  9631  	// result: (MOVBstore [off] {sym} ptr x mem)
  9632  	for {
  9633  		off := v.AuxInt
  9634  		sym := v.Aux
  9635  		mem := v.Args[2]
  9636  		ptr := v.Args[0]
  9637  		v_1 := v.Args[1]
  9638  		if v_1.Op != OpARM64MOVWreg {
  9639  			break
  9640  		}
  9641  		x := v_1.Args[0]
  9642  		v.reset(OpARM64MOVBstore)
  9643  		v.AuxInt = off
  9644  		v.Aux = sym
  9645  		v.AddArg(ptr)
  9646  		v.AddArg(x)
  9647  		v.AddArg(mem)
  9648  		return true
  9649  	}
  9650  	// match: (MOVBstore [off] {sym} ptr (MOVWUreg x) mem)
  9651  	// cond:
  9652  	// result: (MOVBstore [off] {sym} ptr x mem)
  9653  	for {
  9654  		off := v.AuxInt
  9655  		sym := v.Aux
  9656  		mem := v.Args[2]
  9657  		ptr := v.Args[0]
  9658  		v_1 := v.Args[1]
  9659  		if v_1.Op != OpARM64MOVWUreg {
  9660  			break
  9661  		}
  9662  		x := v_1.Args[0]
  9663  		v.reset(OpARM64MOVBstore)
  9664  		v.AuxInt = off
  9665  		v.Aux = sym
  9666  		v.AddArg(ptr)
  9667  		v.AddArg(x)
  9668  		v.AddArg(mem)
  9669  		return true
  9670  	}
  9671  	return false
  9672  }
  9673  func rewriteValueARM64_OpARM64MOVBstore_10(v *Value) bool {
  9674  	// match: (MOVBstore [i] {s} ptr0 (SRLconst [8] w) x:(MOVBstore [i-1] {s} ptr1 w mem))
  9675  	// cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)
  9676  	// result: (MOVHstore [i-1] {s} ptr0 w mem)
  9677  	for {
  9678  		i := v.AuxInt
  9679  		s := v.Aux
  9680  		_ = v.Args[2]
  9681  		ptr0 := v.Args[0]
  9682  		v_1 := v.Args[1]
  9683  		if v_1.Op != OpARM64SRLconst {
  9684  			break
  9685  		}
  9686  		if v_1.AuxInt != 8 {
  9687  			break
  9688  		}
  9689  		w := v_1.Args[0]
  9690  		x := v.Args[2]
  9691  		if x.Op != OpARM64MOVBstore {
  9692  			break
  9693  		}
  9694  		if x.AuxInt != i-1 {
  9695  			break
  9696  		}
  9697  		if x.Aux != s {
  9698  			break
  9699  		}
  9700  		mem := x.Args[2]
  9701  		ptr1 := x.Args[0]
  9702  		if w != x.Args[1] {
  9703  			break
  9704  		}
  9705  		if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) {
  9706  			break
  9707  		}
  9708  		v.reset(OpARM64MOVHstore)
  9709  		v.AuxInt = i - 1
  9710  		v.Aux = s
  9711  		v.AddArg(ptr0)
  9712  		v.AddArg(w)
  9713  		v.AddArg(mem)
  9714  		return true
  9715  	}
  9716  	// match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [8] w) x:(MOVBstoreidx ptr1 idx1 w mem))
  9717  	// cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)
  9718  	// result: (MOVHstoreidx ptr1 idx1 w mem)
  9719  	for {
  9720  		if v.AuxInt != 1 {
  9721  			break
  9722  		}
  9723  		s := v.Aux
  9724  		_ = v.Args[2]
  9725  		v_0 := v.Args[0]
  9726  		if v_0.Op != OpARM64ADD {
  9727  			break
  9728  		}
  9729  		idx0 := v_0.Args[1]
  9730  		ptr0 := v_0.Args[0]
  9731  		v_1 := v.Args[1]
  9732  		if v_1.Op != OpARM64SRLconst {
  9733  			break
  9734  		}
  9735  		if v_1.AuxInt != 8 {
  9736  			break
  9737  		}
  9738  		w := v_1.Args[0]
  9739  		x := v.Args[2]
  9740  		if x.Op != OpARM64MOVBstoreidx {
  9741  			break
  9742  		}
  9743  		mem := x.Args[3]
  9744  		ptr1 := x.Args[0]
  9745  		idx1 := x.Args[1]
  9746  		if w != x.Args[2] {
  9747  			break
  9748  		}
  9749  		if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) {
  9750  			break
  9751  		}
  9752  		v.reset(OpARM64MOVHstoreidx)
  9753  		v.AddArg(ptr1)
  9754  		v.AddArg(idx1)
  9755  		v.AddArg(w)
  9756  		v.AddArg(mem)
  9757  		return true
  9758  	}
  9759  	// match: (MOVBstore [i] {s} ptr0 (UBFX [armBFAuxInt(8, 8)] w) x:(MOVBstore [i-1] {s} ptr1 w mem))
  9760  	// cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)
  9761  	// result: (MOVHstore [i-1] {s} ptr0 w mem)
  9762  	for {
  9763  		i := v.AuxInt
  9764  		s := v.Aux
  9765  		_ = v.Args[2]
  9766  		ptr0 := v.Args[0]
  9767  		v_1 := v.Args[1]
  9768  		if v_1.Op != OpARM64UBFX {
  9769  			break
  9770  		}
  9771  		if v_1.AuxInt != armBFAuxInt(8, 8) {
  9772  			break
  9773  		}
  9774  		w := v_1.Args[0]
  9775  		x := v.Args[2]
  9776  		if x.Op != OpARM64MOVBstore {
  9777  			break
  9778  		}
  9779  		if x.AuxInt != i-1 {
  9780  			break
  9781  		}
  9782  		if x.Aux != s {
  9783  			break
  9784  		}
  9785  		mem := x.Args[2]
  9786  		ptr1 := x.Args[0]
  9787  		if w != x.Args[1] {
  9788  			break
  9789  		}
  9790  		if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) {
  9791  			break
  9792  		}
  9793  		v.reset(OpARM64MOVHstore)
  9794  		v.AuxInt = i - 1
  9795  		v.Aux = s
  9796  		v.AddArg(ptr0)
  9797  		v.AddArg(w)
  9798  		v.AddArg(mem)
  9799  		return true
  9800  	}
  9801  	// match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(8, 8)] w) x:(MOVBstoreidx ptr1 idx1 w mem))
  9802  	// cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)
  9803  	// result: (MOVHstoreidx ptr1 idx1 w mem)
  9804  	for {
  9805  		if v.AuxInt != 1 {
  9806  			break
  9807  		}
  9808  		s := v.Aux
  9809  		_ = v.Args[2]
  9810  		v_0 := v.Args[0]
  9811  		if v_0.Op != OpARM64ADD {
  9812  			break
  9813  		}
  9814  		idx0 := v_0.Args[1]
  9815  		ptr0 := v_0.Args[0]
  9816  		v_1 := v.Args[1]
  9817  		if v_1.Op != OpARM64UBFX {
  9818  			break
  9819  		}
  9820  		if v_1.AuxInt != armBFAuxInt(8, 8) {
  9821  			break
  9822  		}
  9823  		w := v_1.Args[0]
  9824  		x := v.Args[2]
  9825  		if x.Op != OpARM64MOVBstoreidx {
  9826  			break
  9827  		}
  9828  		mem := x.Args[3]
  9829  		ptr1 := x.Args[0]
  9830  		idx1 := x.Args[1]
  9831  		if w != x.Args[2] {
  9832  			break
  9833  		}
  9834  		if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) {
  9835  			break
  9836  		}
  9837  		v.reset(OpARM64MOVHstoreidx)
  9838  		v.AddArg(ptr1)
  9839  		v.AddArg(idx1)
  9840  		v.AddArg(w)
  9841  		v.AddArg(mem)
  9842  		return true
  9843  	}
  9844  	// match: (MOVBstore [i] {s} ptr0 (UBFX [armBFAuxInt(8, 24)] w) x:(MOVBstore [i-1] {s} ptr1 w mem))
  9845  	// cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)
  9846  	// result: (MOVHstore [i-1] {s} ptr0 w mem)
  9847  	for {
  9848  		i := v.AuxInt
  9849  		s := v.Aux
  9850  		_ = v.Args[2]
  9851  		ptr0 := v.Args[0]
  9852  		v_1 := v.Args[1]
  9853  		if v_1.Op != OpARM64UBFX {
  9854  			break
  9855  		}
  9856  		if v_1.AuxInt != armBFAuxInt(8, 24) {
  9857  			break
  9858  		}
  9859  		w := v_1.Args[0]
  9860  		x := v.Args[2]
  9861  		if x.Op != OpARM64MOVBstore {
  9862  			break
  9863  		}
  9864  		if x.AuxInt != i-1 {
  9865  			break
  9866  		}
  9867  		if x.Aux != s {
  9868  			break
  9869  		}
  9870  		mem := x.Args[2]
  9871  		ptr1 := x.Args[0]
  9872  		if w != x.Args[1] {
  9873  			break
  9874  		}
  9875  		if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) {
  9876  			break
  9877  		}
  9878  		v.reset(OpARM64MOVHstore)
  9879  		v.AuxInt = i - 1
  9880  		v.Aux = s
  9881  		v.AddArg(ptr0)
  9882  		v.AddArg(w)
  9883  		v.AddArg(mem)
  9884  		return true
  9885  	}
  9886  	// match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(8, 24)] w) x:(MOVBstoreidx ptr1 idx1 w mem))
  9887  	// cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)
  9888  	// result: (MOVHstoreidx ptr1 idx1 w mem)
  9889  	for {
  9890  		if v.AuxInt != 1 {
  9891  			break
  9892  		}
  9893  		s := v.Aux
  9894  		_ = v.Args[2]
  9895  		v_0 := v.Args[0]
  9896  		if v_0.Op != OpARM64ADD {
  9897  			break
  9898  		}
  9899  		idx0 := v_0.Args[1]
  9900  		ptr0 := v_0.Args[0]
  9901  		v_1 := v.Args[1]
  9902  		if v_1.Op != OpARM64UBFX {
  9903  			break
  9904  		}
  9905  		if v_1.AuxInt != armBFAuxInt(8, 24) {
  9906  			break
  9907  		}
  9908  		w := v_1.Args[0]
  9909  		x := v.Args[2]
  9910  		if x.Op != OpARM64MOVBstoreidx {
  9911  			break
  9912  		}
  9913  		mem := x.Args[3]
  9914  		ptr1 := x.Args[0]
  9915  		idx1 := x.Args[1]
  9916  		if w != x.Args[2] {
  9917  			break
  9918  		}
  9919  		if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) {
  9920  			break
  9921  		}
  9922  		v.reset(OpARM64MOVHstoreidx)
  9923  		v.AddArg(ptr1)
  9924  		v.AddArg(idx1)
  9925  		v.AddArg(w)
  9926  		v.AddArg(mem)
  9927  		return true
  9928  	}
  9929  	// match: (MOVBstore [i] {s} ptr0 (SRLconst [8] (MOVDreg w)) x:(MOVBstore [i-1] {s} ptr1 w mem))
  9930  	// cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)
  9931  	// result: (MOVHstore [i-1] {s} ptr0 w mem)
  9932  	for {
  9933  		i := v.AuxInt
  9934  		s := v.Aux
  9935  		_ = v.Args[2]
  9936  		ptr0 := v.Args[0]
  9937  		v_1 := v.Args[1]
  9938  		if v_1.Op != OpARM64SRLconst {
  9939  			break
  9940  		}
  9941  		if v_1.AuxInt != 8 {
  9942  			break
  9943  		}
  9944  		v_1_0 := v_1.Args[0]
  9945  		if v_1_0.Op != OpARM64MOVDreg {
  9946  			break
  9947  		}
  9948  		w := v_1_0.Args[0]
  9949  		x := v.Args[2]
  9950  		if x.Op != OpARM64MOVBstore {
  9951  			break
  9952  		}
  9953  		if x.AuxInt != i-1 {
  9954  			break
  9955  		}
  9956  		if x.Aux != s {
  9957  			break
  9958  		}
  9959  		mem := x.Args[2]
  9960  		ptr1 := x.Args[0]
  9961  		if w != x.Args[1] {
  9962  			break
  9963  		}
  9964  		if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) {
  9965  			break
  9966  		}
  9967  		v.reset(OpARM64MOVHstore)
  9968  		v.AuxInt = i - 1
  9969  		v.Aux = s
  9970  		v.AddArg(ptr0)
  9971  		v.AddArg(w)
  9972  		v.AddArg(mem)
  9973  		return true
  9974  	}
  9975  	// match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [8] (MOVDreg w)) x:(MOVBstoreidx ptr1 idx1 w mem))
  9976  	// cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)
  9977  	// result: (MOVHstoreidx ptr1 idx1 w mem)
  9978  	for {
  9979  		if v.AuxInt != 1 {
  9980  			break
  9981  		}
  9982  		s := v.Aux
  9983  		_ = v.Args[2]
  9984  		v_0 := v.Args[0]
  9985  		if v_0.Op != OpARM64ADD {
  9986  			break
  9987  		}
  9988  		idx0 := v_0.Args[1]
  9989  		ptr0 := v_0.Args[0]
  9990  		v_1 := v.Args[1]
  9991  		if v_1.Op != OpARM64SRLconst {
  9992  			break
  9993  		}
  9994  		if v_1.AuxInt != 8 {
  9995  			break
  9996  		}
  9997  		v_1_0 := v_1.Args[0]
  9998  		if v_1_0.Op != OpARM64MOVDreg {
  9999  			break
 10000  		}
 10001  		w := v_1_0.Args[0]
 10002  		x := v.Args[2]
 10003  		if x.Op != OpARM64MOVBstoreidx {
 10004  			break
 10005  		}
 10006  		mem := x.Args[3]
 10007  		ptr1 := x.Args[0]
 10008  		idx1 := x.Args[1]
 10009  		if w != x.Args[2] {
 10010  			break
 10011  		}
 10012  		if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) {
 10013  			break
 10014  		}
 10015  		v.reset(OpARM64MOVHstoreidx)
 10016  		v.AddArg(ptr1)
 10017  		v.AddArg(idx1)
 10018  		v.AddArg(w)
 10019  		v.AddArg(mem)
 10020  		return true
 10021  	}
 10022  	// match: (MOVBstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVBstore [i-1] {s} ptr1 w0:(SRLconst [j-8] w) mem))
 10023  	// cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)
 10024  	// result: (MOVHstore [i-1] {s} ptr0 w0 mem)
 10025  	for {
 10026  		i := v.AuxInt
 10027  		s := v.Aux
 10028  		_ = v.Args[2]
 10029  		ptr0 := v.Args[0]
 10030  		v_1 := v.Args[1]
 10031  		if v_1.Op != OpARM64SRLconst {
 10032  			break
 10033  		}
 10034  		j := v_1.AuxInt
 10035  		w := v_1.Args[0]
 10036  		x := v.Args[2]
 10037  		if x.Op != OpARM64MOVBstore {
 10038  			break
 10039  		}
 10040  		if x.AuxInt != i-1 {
 10041  			break
 10042  		}
 10043  		if x.Aux != s {
 10044  			break
 10045  		}
 10046  		mem := x.Args[2]
 10047  		ptr1 := x.Args[0]
 10048  		w0 := x.Args[1]
 10049  		if w0.Op != OpARM64SRLconst {
 10050  			break
 10051  		}
 10052  		if w0.AuxInt != j-8 {
 10053  			break
 10054  		}
 10055  		if w != w0.Args[0] {
 10056  			break
 10057  		}
 10058  		if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) {
 10059  			break
 10060  		}
 10061  		v.reset(OpARM64MOVHstore)
 10062  		v.AuxInt = i - 1
 10063  		v.Aux = s
 10064  		v.AddArg(ptr0)
 10065  		v.AddArg(w0)
 10066  		v.AddArg(mem)
 10067  		return true
 10068  	}
 10069  	// match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVBstoreidx ptr1 idx1 w0:(SRLconst [j-8] w) mem))
 10070  	// cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)
 10071  	// result: (MOVHstoreidx ptr1 idx1 w0 mem)
 10072  	for {
 10073  		if v.AuxInt != 1 {
 10074  			break
 10075  		}
 10076  		s := v.Aux
 10077  		_ = v.Args[2]
 10078  		v_0 := v.Args[0]
 10079  		if v_0.Op != OpARM64ADD {
 10080  			break
 10081  		}
 10082  		idx0 := v_0.Args[1]
 10083  		ptr0 := v_0.Args[0]
 10084  		v_1 := v.Args[1]
 10085  		if v_1.Op != OpARM64SRLconst {
 10086  			break
 10087  		}
 10088  		j := v_1.AuxInt
 10089  		w := v_1.Args[0]
 10090  		x := v.Args[2]
 10091  		if x.Op != OpARM64MOVBstoreidx {
 10092  			break
 10093  		}
 10094  		mem := x.Args[3]
 10095  		ptr1 := x.Args[0]
 10096  		idx1 := x.Args[1]
 10097  		w0 := x.Args[2]
 10098  		if w0.Op != OpARM64SRLconst {
 10099  			break
 10100  		}
 10101  		if w0.AuxInt != j-8 {
 10102  			break
 10103  		}
 10104  		if w != w0.Args[0] {
 10105  			break
 10106  		}
 10107  		if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) {
 10108  			break
 10109  		}
 10110  		v.reset(OpARM64MOVHstoreidx)
 10111  		v.AddArg(ptr1)
 10112  		v.AddArg(idx1)
 10113  		v.AddArg(w0)
 10114  		v.AddArg(mem)
 10115  		return true
 10116  	}
 10117  	return false
 10118  }
 10119  func rewriteValueARM64_OpARM64MOVBstore_20(v *Value) bool {
 10120  	b := v.Block
 10121  	// match: (MOVBstore [i] {s} ptr0 (UBFX [bfc] w) x:(MOVBstore [i-1] {s} ptr1 w0:(UBFX [bfc2] w) mem))
 10122  	// cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && getARM64BFwidth(bfc) == 32 - getARM64BFlsb(bfc) && getARM64BFwidth(bfc2) == 32 - getARM64BFlsb(bfc2) && getARM64BFlsb(bfc2) == getARM64BFlsb(bfc) - 8 && clobber(x)
 10123  	// result: (MOVHstore [i-1] {s} ptr0 w0 mem)
 10124  	for {
 10125  		i := v.AuxInt
 10126  		s := v.Aux
 10127  		_ = v.Args[2]
 10128  		ptr0 := v.Args[0]
 10129  		v_1 := v.Args[1]
 10130  		if v_1.Op != OpARM64UBFX {
 10131  			break
 10132  		}
 10133  		bfc := v_1.AuxInt
 10134  		w := v_1.Args[0]
 10135  		x := v.Args[2]
 10136  		if x.Op != OpARM64MOVBstore {
 10137  			break
 10138  		}
 10139  		if x.AuxInt != i-1 {
 10140  			break
 10141  		}
 10142  		if x.Aux != s {
 10143  			break
 10144  		}
 10145  		mem := x.Args[2]
 10146  		ptr1 := x.Args[0]
 10147  		w0 := x.Args[1]
 10148  		if w0.Op != OpARM64UBFX {
 10149  			break
 10150  		}
 10151  		bfc2 := w0.AuxInt
 10152  		if w != w0.Args[0] {
 10153  			break
 10154  		}
 10155  		if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && getARM64BFwidth(bfc) == 32-getARM64BFlsb(bfc) && getARM64BFwidth(bfc2) == 32-getARM64BFlsb(bfc2) && getARM64BFlsb(bfc2) == getARM64BFlsb(bfc)-8 && clobber(x)) {
 10156  			break
 10157  		}
 10158  		v.reset(OpARM64MOVHstore)
 10159  		v.AuxInt = i - 1
 10160  		v.Aux = s
 10161  		v.AddArg(ptr0)
 10162  		v.AddArg(w0)
 10163  		v.AddArg(mem)
 10164  		return true
 10165  	}
 10166  	// match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [bfc] w) x:(MOVBstoreidx ptr1 idx1 w0:(UBFX [bfc2] w) mem))
 10167  	// cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && getARM64BFwidth(bfc) == 32 - getARM64BFlsb(bfc) && getARM64BFwidth(bfc2) == 32 - getARM64BFlsb(bfc2) && getARM64BFlsb(bfc2) == getARM64BFlsb(bfc) - 8 && clobber(x)
 10168  	// result: (MOVHstoreidx ptr1 idx1 w0 mem)
 10169  	for {
 10170  		if v.AuxInt != 1 {
 10171  			break
 10172  		}
 10173  		s := v.Aux
 10174  		_ = v.Args[2]
 10175  		v_0 := v.Args[0]
 10176  		if v_0.Op != OpARM64ADD {
 10177  			break
 10178  		}
 10179  		idx0 := v_0.Args[1]
 10180  		ptr0 := v_0.Args[0]
 10181  		v_1 := v.Args[1]
 10182  		if v_1.Op != OpARM64UBFX {
 10183  			break
 10184  		}
 10185  		bfc := v_1.AuxInt
 10186  		w := v_1.Args[0]
 10187  		x := v.Args[2]
 10188  		if x.Op != OpARM64MOVBstoreidx {
 10189  			break
 10190  		}
 10191  		mem := x.Args[3]
 10192  		ptr1 := x.Args[0]
 10193  		idx1 := x.Args[1]
 10194  		w0 := x.Args[2]
 10195  		if w0.Op != OpARM64UBFX {
 10196  			break
 10197  		}
 10198  		bfc2 := w0.AuxInt
 10199  		if w != w0.Args[0] {
 10200  			break
 10201  		}
 10202  		if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && getARM64BFwidth(bfc) == 32-getARM64BFlsb(bfc) && getARM64BFwidth(bfc2) == 32-getARM64BFlsb(bfc2) && getARM64BFlsb(bfc2) == getARM64BFlsb(bfc)-8 && clobber(x)) {
 10203  			break
 10204  		}
 10205  		v.reset(OpARM64MOVHstoreidx)
 10206  		v.AddArg(ptr1)
 10207  		v.AddArg(idx1)
 10208  		v.AddArg(w0)
 10209  		v.AddArg(mem)
 10210  		return true
 10211  	}
 10212  	// match: (MOVBstore [i] {s} ptr0 (SRLconst [j] (MOVDreg w)) x:(MOVBstore [i-1] {s} ptr1 w0:(SRLconst [j-8] (MOVDreg w)) mem))
 10213  	// cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)
 10214  	// result: (MOVHstore [i-1] {s} ptr0 w0 mem)
 10215  	for {
 10216  		i := v.AuxInt
 10217  		s := v.Aux
 10218  		_ = v.Args[2]
 10219  		ptr0 := v.Args[0]
 10220  		v_1 := v.Args[1]
 10221  		if v_1.Op != OpARM64SRLconst {
 10222  			break
 10223  		}
 10224  		j := v_1.AuxInt
 10225  		v_1_0 := v_1.Args[0]
 10226  		if v_1_0.Op != OpARM64MOVDreg {
 10227  			break
 10228  		}
 10229  		w := v_1_0.Args[0]
 10230  		x := v.Args[2]
 10231  		if x.Op != OpARM64MOVBstore {
 10232  			break
 10233  		}
 10234  		if x.AuxInt != i-1 {
 10235  			break
 10236  		}
 10237  		if x.Aux != s {
 10238  			break
 10239  		}
 10240  		mem := x.Args[2]
 10241  		ptr1 := x.Args[0]
 10242  		w0 := x.Args[1]
 10243  		if w0.Op != OpARM64SRLconst {
 10244  			break
 10245  		}
 10246  		if w0.AuxInt != j-8 {
 10247  			break
 10248  		}
 10249  		w0_0 := w0.Args[0]
 10250  		if w0_0.Op != OpARM64MOVDreg {
 10251  			break
 10252  		}
 10253  		if w != w0_0.Args[0] {
 10254  			break
 10255  		}
 10256  		if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) {
 10257  			break
 10258  		}
 10259  		v.reset(OpARM64MOVHstore)
 10260  		v.AuxInt = i - 1
 10261  		v.Aux = s
 10262  		v.AddArg(ptr0)
 10263  		v.AddArg(w0)
 10264  		v.AddArg(mem)
 10265  		return true
 10266  	}
 10267  	// match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [j] (MOVDreg w)) x:(MOVBstoreidx ptr1 idx1 w0:(SRLconst [j-8] (MOVDreg w)) mem))
 10268  	// cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)
 10269  	// result: (MOVHstoreidx ptr1 idx1 w0 mem)
 10270  	for {
 10271  		if v.AuxInt != 1 {
 10272  			break
 10273  		}
 10274  		s := v.Aux
 10275  		_ = v.Args[2]
 10276  		v_0 := v.Args[0]
 10277  		if v_0.Op != OpARM64ADD {
 10278  			break
 10279  		}
 10280  		idx0 := v_0.Args[1]
 10281  		ptr0 := v_0.Args[0]
 10282  		v_1 := v.Args[1]
 10283  		if v_1.Op != OpARM64SRLconst {
 10284  			break
 10285  		}
 10286  		j := v_1.AuxInt
 10287  		v_1_0 := v_1.Args[0]
 10288  		if v_1_0.Op != OpARM64MOVDreg {
 10289  			break
 10290  		}
 10291  		w := v_1_0.Args[0]
 10292  		x := v.Args[2]
 10293  		if x.Op != OpARM64MOVBstoreidx {
 10294  			break
 10295  		}
 10296  		mem := x.Args[3]
 10297  		ptr1 := x.Args[0]
 10298  		idx1 := x.Args[1]
 10299  		w0 := x.Args[2]
 10300  		if w0.Op != OpARM64SRLconst {
 10301  			break
 10302  		}
 10303  		if w0.AuxInt != j-8 {
 10304  			break
 10305  		}
 10306  		w0_0 := w0.Args[0]
 10307  		if w0_0.Op != OpARM64MOVDreg {
 10308  			break
 10309  		}
 10310  		if w != w0_0.Args[0] {
 10311  			break
 10312  		}
 10313  		if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) {
 10314  			break
 10315  		}
 10316  		v.reset(OpARM64MOVHstoreidx)
 10317  		v.AddArg(ptr1)
 10318  		v.AddArg(idx1)
 10319  		v.AddArg(w0)
 10320  		v.AddArg(mem)
 10321  		return true
 10322  	}
 10323  	// match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] w) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] w) x3:(MOVBstore [i-4] {s} ptr (SRLconst [32] w) x4:(MOVBstore [i-5] {s} ptr (SRLconst [40] w) x5:(MOVBstore [i-6] {s} ptr (SRLconst [48] w) x6:(MOVBstore [i-7] {s} ptr (SRLconst [56] w) mem))))))))
 10324  	// cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)
 10325  	// result: (MOVDstore [i-7] {s} ptr (REV <w.Type> w) mem)
 10326  	for {
 10327  		i := v.AuxInt
 10328  		s := v.Aux
 10329  		_ = v.Args[2]
 10330  		ptr := v.Args[0]
 10331  		w := v.Args[1]
 10332  		x0 := v.Args[2]
 10333  		if x0.Op != OpARM64MOVBstore {
 10334  			break
 10335  		}
 10336  		if x0.AuxInt != i-1 {
 10337  			break
 10338  		}
 10339  		if x0.Aux != s {
 10340  			break
 10341  		}
 10342  		_ = x0.Args[2]
 10343  		if ptr != x0.Args[0] {
 10344  			break
 10345  		}
 10346  		x0_1 := x0.Args[1]
 10347  		if x0_1.Op != OpARM64SRLconst {
 10348  			break
 10349  		}
 10350  		if x0_1.AuxInt != 8 {
 10351  			break
 10352  		}
 10353  		if w != x0_1.Args[0] {
 10354  			break
 10355  		}
 10356  		x1 := x0.Args[2]
 10357  		if x1.Op != OpARM64MOVBstore {
 10358  			break
 10359  		}
 10360  		if x1.AuxInt != i-2 {
 10361  			break
 10362  		}
 10363  		if x1.Aux != s {
 10364  			break
 10365  		}
 10366  		_ = x1.Args[2]
 10367  		if ptr != x1.Args[0] {
 10368  			break
 10369  		}
 10370  		x1_1 := x1.Args[1]
 10371  		if x1_1.Op != OpARM64SRLconst {
 10372  			break
 10373  		}
 10374  		if x1_1.AuxInt != 16 {
 10375  			break
 10376  		}
 10377  		if w != x1_1.Args[0] {
 10378  			break
 10379  		}
 10380  		x2 := x1.Args[2]
 10381  		if x2.Op != OpARM64MOVBstore {
 10382  			break
 10383  		}
 10384  		if x2.AuxInt != i-3 {
 10385  			break
 10386  		}
 10387  		if x2.Aux != s {
 10388  			break
 10389  		}
 10390  		_ = x2.Args[2]
 10391  		if ptr != x2.Args[0] {
 10392  			break
 10393  		}
 10394  		x2_1 := x2.Args[1]
 10395  		if x2_1.Op != OpARM64SRLconst {
 10396  			break
 10397  		}
 10398  		if x2_1.AuxInt != 24 {
 10399  			break
 10400  		}
 10401  		if w != x2_1.Args[0] {
 10402  			break
 10403  		}
 10404  		x3 := x2.Args[2]
 10405  		if x3.Op != OpARM64MOVBstore {
 10406  			break
 10407  		}
 10408  		if x3.AuxInt != i-4 {
 10409  			break
 10410  		}
 10411  		if x3.Aux != s {
 10412  			break
 10413  		}
 10414  		_ = x3.Args[2]
 10415  		if ptr != x3.Args[0] {
 10416  			break
 10417  		}
 10418  		x3_1 := x3.Args[1]
 10419  		if x3_1.Op != OpARM64SRLconst {
 10420  			break
 10421  		}
 10422  		if x3_1.AuxInt != 32 {
 10423  			break
 10424  		}
 10425  		if w != x3_1.Args[0] {
 10426  			break
 10427  		}
 10428  		x4 := x3.Args[2]
 10429  		if x4.Op != OpARM64MOVBstore {
 10430  			break
 10431  		}
 10432  		if x4.AuxInt != i-5 {
 10433  			break
 10434  		}
 10435  		if x4.Aux != s {
 10436  			break
 10437  		}
 10438  		_ = x4.Args[2]
 10439  		if ptr != x4.Args[0] {
 10440  			break
 10441  		}
 10442  		x4_1 := x4.Args[1]
 10443  		if x4_1.Op != OpARM64SRLconst {
 10444  			break
 10445  		}
 10446  		if x4_1.AuxInt != 40 {
 10447  			break
 10448  		}
 10449  		if w != x4_1.Args[0] {
 10450  			break
 10451  		}
 10452  		x5 := x4.Args[2]
 10453  		if x5.Op != OpARM64MOVBstore {
 10454  			break
 10455  		}
 10456  		if x5.AuxInt != i-6 {
 10457  			break
 10458  		}
 10459  		if x5.Aux != s {
 10460  			break
 10461  		}
 10462  		_ = x5.Args[2]
 10463  		if ptr != x5.Args[0] {
 10464  			break
 10465  		}
 10466  		x5_1 := x5.Args[1]
 10467  		if x5_1.Op != OpARM64SRLconst {
 10468  			break
 10469  		}
 10470  		if x5_1.AuxInt != 48 {
 10471  			break
 10472  		}
 10473  		if w != x5_1.Args[0] {
 10474  			break
 10475  		}
 10476  		x6 := x5.Args[2]
 10477  		if x6.Op != OpARM64MOVBstore {
 10478  			break
 10479  		}
 10480  		if x6.AuxInt != i-7 {
 10481  			break
 10482  		}
 10483  		if x6.Aux != s {
 10484  			break
 10485  		}
 10486  		mem := x6.Args[2]
 10487  		if ptr != x6.Args[0] {
 10488  			break
 10489  		}
 10490  		x6_1 := x6.Args[1]
 10491  		if x6_1.Op != OpARM64SRLconst {
 10492  			break
 10493  		}
 10494  		if x6_1.AuxInt != 56 {
 10495  			break
 10496  		}
 10497  		if w != x6_1.Args[0] {
 10498  			break
 10499  		}
 10500  		if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) {
 10501  			break
 10502  		}
 10503  		v.reset(OpARM64MOVDstore)
 10504  		v.AuxInt = i - 7
 10505  		v.Aux = s
 10506  		v.AddArg(ptr)
 10507  		v0 := b.NewValue0(x6.Pos, OpARM64REV, w.Type)
 10508  		v0.AddArg(w)
 10509  		v.AddArg(v0)
 10510  		v.AddArg(mem)
 10511  		return true
 10512  	}
 10513  	// match: (MOVBstore [7] {s} p w x0:(MOVBstore [6] {s} p (SRLconst [8] w) x1:(MOVBstore [5] {s} p (SRLconst [16] w) x2:(MOVBstore [4] {s} p (SRLconst [24] w) x3:(MOVBstore [3] {s} p (SRLconst [32] w) x4:(MOVBstore [2] {s} p (SRLconst [40] w) x5:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [48] w) x6:(MOVBstoreidx ptr0 idx0 (SRLconst [56] w) mem))))))))
 10514  	// cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)
 10515  	// result: (MOVDstoreidx ptr0 idx0 (REV <w.Type> w) mem)
 10516  	for {
 10517  		if v.AuxInt != 7 {
 10518  			break
 10519  		}
 10520  		s := v.Aux
 10521  		_ = v.Args[2]
 10522  		p := v.Args[0]
 10523  		w := v.Args[1]
 10524  		x0 := v.Args[2]
 10525  		if x0.Op != OpARM64MOVBstore {
 10526  			break
 10527  		}
 10528  		if x0.AuxInt != 6 {
 10529  			break
 10530  		}
 10531  		if x0.Aux != s {
 10532  			break
 10533  		}
 10534  		_ = x0.Args[2]
 10535  		if p != x0.Args[0] {
 10536  			break
 10537  		}
 10538  		x0_1 := x0.Args[1]
 10539  		if x0_1.Op != OpARM64SRLconst {
 10540  			break
 10541  		}
 10542  		if x0_1.AuxInt != 8 {
 10543  			break
 10544  		}
 10545  		if w != x0_1.Args[0] {
 10546  			break
 10547  		}
 10548  		x1 := x0.Args[2]
 10549  		if x1.Op != OpARM64MOVBstore {
 10550  			break
 10551  		}
 10552  		if x1.AuxInt != 5 {
 10553  			break
 10554  		}
 10555  		if x1.Aux != s {
 10556  			break
 10557  		}
 10558  		_ = x1.Args[2]
 10559  		if p != x1.Args[0] {
 10560  			break
 10561  		}
 10562  		x1_1 := x1.Args[1]
 10563  		if x1_1.Op != OpARM64SRLconst {
 10564  			break
 10565  		}
 10566  		if x1_1.AuxInt != 16 {
 10567  			break
 10568  		}
 10569  		if w != x1_1.Args[0] {
 10570  			break
 10571  		}
 10572  		x2 := x1.Args[2]
 10573  		if x2.Op != OpARM64MOVBstore {
 10574  			break
 10575  		}
 10576  		if x2.AuxInt != 4 {
 10577  			break
 10578  		}
 10579  		if x2.Aux != s {
 10580  			break
 10581  		}
 10582  		_ = x2.Args[2]
 10583  		if p != x2.Args[0] {
 10584  			break
 10585  		}
 10586  		x2_1 := x2.Args[1]
 10587  		if x2_1.Op != OpARM64SRLconst {
 10588  			break
 10589  		}
 10590  		if x2_1.AuxInt != 24 {
 10591  			break
 10592  		}
 10593  		if w != x2_1.Args[0] {
 10594  			break
 10595  		}
 10596  		x3 := x2.Args[2]
 10597  		if x3.Op != OpARM64MOVBstore {
 10598  			break
 10599  		}
 10600  		if x3.AuxInt != 3 {
 10601  			break
 10602  		}
 10603  		if x3.Aux != s {
 10604  			break
 10605  		}
 10606  		_ = x3.Args[2]
 10607  		if p != x3.Args[0] {
 10608  			break
 10609  		}
 10610  		x3_1 := x3.Args[1]
 10611  		if x3_1.Op != OpARM64SRLconst {
 10612  			break
 10613  		}
 10614  		if x3_1.AuxInt != 32 {
 10615  			break
 10616  		}
 10617  		if w != x3_1.Args[0] {
 10618  			break
 10619  		}
 10620  		x4 := x3.Args[2]
 10621  		if x4.Op != OpARM64MOVBstore {
 10622  			break
 10623  		}
 10624  		if x4.AuxInt != 2 {
 10625  			break
 10626  		}
 10627  		if x4.Aux != s {
 10628  			break
 10629  		}
 10630  		_ = x4.Args[2]
 10631  		if p != x4.Args[0] {
 10632  			break
 10633  		}
 10634  		x4_1 := x4.Args[1]
 10635  		if x4_1.Op != OpARM64SRLconst {
 10636  			break
 10637  		}
 10638  		if x4_1.AuxInt != 40 {
 10639  			break
 10640  		}
 10641  		if w != x4_1.Args[0] {
 10642  			break
 10643  		}
 10644  		x5 := x4.Args[2]
 10645  		if x5.Op != OpARM64MOVBstore {
 10646  			break
 10647  		}
 10648  		if x5.AuxInt != 1 {
 10649  			break
 10650  		}
 10651  		if x5.Aux != s {
 10652  			break
 10653  		}
 10654  		_ = x5.Args[2]
 10655  		p1 := x5.Args[0]
 10656  		if p1.Op != OpARM64ADD {
 10657  			break
 10658  		}
 10659  		idx1 := p1.Args[1]
 10660  		ptr1 := p1.Args[0]
 10661  		x5_1 := x5.Args[1]
 10662  		if x5_1.Op != OpARM64SRLconst {
 10663  			break
 10664  		}
 10665  		if x5_1.AuxInt != 48 {
 10666  			break
 10667  		}
 10668  		if w != x5_1.Args[0] {
 10669  			break
 10670  		}
 10671  		x6 := x5.Args[2]
 10672  		if x6.Op != OpARM64MOVBstoreidx {
 10673  			break
 10674  		}
 10675  		mem := x6.Args[3]
 10676  		ptr0 := x6.Args[0]
 10677  		idx0 := x6.Args[1]
 10678  		x6_2 := x6.Args[2]
 10679  		if x6_2.Op != OpARM64SRLconst {
 10680  			break
 10681  		}
 10682  		if x6_2.AuxInt != 56 {
 10683  			break
 10684  		}
 10685  		if w != x6_2.Args[0] {
 10686  			break
 10687  		}
 10688  		if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) {
 10689  			break
 10690  		}
 10691  		v.reset(OpARM64MOVDstoreidx)
 10692  		v.AddArg(ptr0)
 10693  		v.AddArg(idx0)
 10694  		v0 := b.NewValue0(x5.Pos, OpARM64REV, w.Type)
 10695  		v0.AddArg(w)
 10696  		v.AddArg(v0)
 10697  		v.AddArg(mem)
 10698  		return true
 10699  	}
 10700  	// match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstore [i-2] {s} ptr (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstore [i-3] {s} ptr (UBFX [armBFAuxInt(24, 8)] w) mem))))
 10701  	// cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)
 10702  	// result: (MOVWstore [i-3] {s} ptr (REVW <w.Type> w) mem)
 10703  	for {
 10704  		i := v.AuxInt
 10705  		s := v.Aux
 10706  		_ = v.Args[2]
 10707  		ptr := v.Args[0]
 10708  		w := v.Args[1]
 10709  		x0 := v.Args[2]
 10710  		if x0.Op != OpARM64MOVBstore {
 10711  			break
 10712  		}
 10713  		if x0.AuxInt != i-1 {
 10714  			break
 10715  		}
 10716  		if x0.Aux != s {
 10717  			break
 10718  		}
 10719  		_ = x0.Args[2]
 10720  		if ptr != x0.Args[0] {
 10721  			break
 10722  		}
 10723  		x0_1 := x0.Args[1]
 10724  		if x0_1.Op != OpARM64UBFX {
 10725  			break
 10726  		}
 10727  		if x0_1.AuxInt != armBFAuxInt(8, 24) {
 10728  			break
 10729  		}
 10730  		if w != x0_1.Args[0] {
 10731  			break
 10732  		}
 10733  		x1 := x0.Args[2]
 10734  		if x1.Op != OpARM64MOVBstore {
 10735  			break
 10736  		}
 10737  		if x1.AuxInt != i-2 {
 10738  			break
 10739  		}
 10740  		if x1.Aux != s {
 10741  			break
 10742  		}
 10743  		_ = x1.Args[2]
 10744  		if ptr != x1.Args[0] {
 10745  			break
 10746  		}
 10747  		x1_1 := x1.Args[1]
 10748  		if x1_1.Op != OpARM64UBFX {
 10749  			break
 10750  		}
 10751  		if x1_1.AuxInt != armBFAuxInt(16, 16) {
 10752  			break
 10753  		}
 10754  		if w != x1_1.Args[0] {
 10755  			break
 10756  		}
 10757  		x2 := x1.Args[2]
 10758  		if x2.Op != OpARM64MOVBstore {
 10759  			break
 10760  		}
 10761  		if x2.AuxInt != i-3 {
 10762  			break
 10763  		}
 10764  		if x2.Aux != s {
 10765  			break
 10766  		}
 10767  		mem := x2.Args[2]
 10768  		if ptr != x2.Args[0] {
 10769  			break
 10770  		}
 10771  		x2_1 := x2.Args[1]
 10772  		if x2_1.Op != OpARM64UBFX {
 10773  			break
 10774  		}
 10775  		if x2_1.AuxInt != armBFAuxInt(24, 8) {
 10776  			break
 10777  		}
 10778  		if w != x2_1.Args[0] {
 10779  			break
 10780  		}
 10781  		if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) {
 10782  			break
 10783  		}
 10784  		v.reset(OpARM64MOVWstore)
 10785  		v.AuxInt = i - 3
 10786  		v.Aux = s
 10787  		v.AddArg(ptr)
 10788  		v0 := b.NewValue0(x2.Pos, OpARM64REVW, w.Type)
 10789  		v0.AddArg(w)
 10790  		v.AddArg(v0)
 10791  		v.AddArg(mem)
 10792  		return true
 10793  	}
 10794  	// match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(24, 8)] w) mem))))
 10795  	// cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2)
 10796  	// result: (MOVWstoreidx ptr0 idx0 (REVW <w.Type> w) mem)
 10797  	for {
 10798  		if v.AuxInt != 3 {
 10799  			break
 10800  		}
 10801  		s := v.Aux
 10802  		_ = v.Args[2]
 10803  		p := v.Args[0]
 10804  		w := v.Args[1]
 10805  		x0 := v.Args[2]
 10806  		if x0.Op != OpARM64MOVBstore {
 10807  			break
 10808  		}
 10809  		if x0.AuxInt != 2 {
 10810  			break
 10811  		}
 10812  		if x0.Aux != s {
 10813  			break
 10814  		}
 10815  		_ = x0.Args[2]
 10816  		if p != x0.Args[0] {
 10817  			break
 10818  		}
 10819  		x0_1 := x0.Args[1]
 10820  		if x0_1.Op != OpARM64UBFX {
 10821  			break
 10822  		}
 10823  		if x0_1.AuxInt != armBFAuxInt(8, 24) {
 10824  			break
 10825  		}
 10826  		if w != x0_1.Args[0] {
 10827  			break
 10828  		}
 10829  		x1 := x0.Args[2]
 10830  		if x1.Op != OpARM64MOVBstore {
 10831  			break
 10832  		}
 10833  		if x1.AuxInt != 1 {
 10834  			break
 10835  		}
 10836  		if x1.Aux != s {
 10837  			break
 10838  		}
 10839  		_ = x1.Args[2]
 10840  		p1 := x1.Args[0]
 10841  		if p1.Op != OpARM64ADD {
 10842  			break
 10843  		}
 10844  		idx1 := p1.Args[1]
 10845  		ptr1 := p1.Args[0]
 10846  		x1_1 := x1.Args[1]
 10847  		if x1_1.Op != OpARM64UBFX {
 10848  			break
 10849  		}
 10850  		if x1_1.AuxInt != armBFAuxInt(16, 16) {
 10851  			break
 10852  		}
 10853  		if w != x1_1.Args[0] {
 10854  			break
 10855  		}
 10856  		x2 := x1.Args[2]
 10857  		if x2.Op != OpARM64MOVBstoreidx {
 10858  			break
 10859  		}
 10860  		mem := x2.Args[3]
 10861  		ptr0 := x2.Args[0]
 10862  		idx0 := x2.Args[1]
 10863  		x2_2 := x2.Args[2]
 10864  		if x2_2.Op != OpARM64UBFX {
 10865  			break
 10866  		}
 10867  		if x2_2.AuxInt != armBFAuxInt(24, 8) {
 10868  			break
 10869  		}
 10870  		if w != x2_2.Args[0] {
 10871  			break
 10872  		}
 10873  		if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2)) {
 10874  			break
 10875  		}
 10876  		v.reset(OpARM64MOVWstoreidx)
 10877  		v.AddArg(ptr0)
 10878  		v.AddArg(idx0)
 10879  		v0 := b.NewValue0(x1.Pos, OpARM64REVW, w.Type)
 10880  		v0.AddArg(w)
 10881  		v.AddArg(v0)
 10882  		v.AddArg(mem)
 10883  		return true
 10884  	}
 10885  	// match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] (MOVDreg w)) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] (MOVDreg w)) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] (MOVDreg w)) mem))))
 10886  	// cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)
 10887  	// result: (MOVWstore [i-3] {s} ptr (REVW <w.Type> w) mem)
 10888  	for {
 10889  		i := v.AuxInt
 10890  		s := v.Aux
 10891  		_ = v.Args[2]
 10892  		ptr := v.Args[0]
 10893  		w := v.Args[1]
 10894  		x0 := v.Args[2]
 10895  		if x0.Op != OpARM64MOVBstore {
 10896  			break
 10897  		}
 10898  		if x0.AuxInt != i-1 {
 10899  			break
 10900  		}
 10901  		if x0.Aux != s {
 10902  			break
 10903  		}
 10904  		_ = x0.Args[2]
 10905  		if ptr != x0.Args[0] {
 10906  			break
 10907  		}
 10908  		x0_1 := x0.Args[1]
 10909  		if x0_1.Op != OpARM64SRLconst {
 10910  			break
 10911  		}
 10912  		if x0_1.AuxInt != 8 {
 10913  			break
 10914  		}
 10915  		x0_1_0 := x0_1.Args[0]
 10916  		if x0_1_0.Op != OpARM64MOVDreg {
 10917  			break
 10918  		}
 10919  		if w != x0_1_0.Args[0] {
 10920  			break
 10921  		}
 10922  		x1 := x0.Args[2]
 10923  		if x1.Op != OpARM64MOVBstore {
 10924  			break
 10925  		}
 10926  		if x1.AuxInt != i-2 {
 10927  			break
 10928  		}
 10929  		if x1.Aux != s {
 10930  			break
 10931  		}
 10932  		_ = x1.Args[2]
 10933  		if ptr != x1.Args[0] {
 10934  			break
 10935  		}
 10936  		x1_1 := x1.Args[1]
 10937  		if x1_1.Op != OpARM64SRLconst {
 10938  			break
 10939  		}
 10940  		if x1_1.AuxInt != 16 {
 10941  			break
 10942  		}
 10943  		x1_1_0 := x1_1.Args[0]
 10944  		if x1_1_0.Op != OpARM64MOVDreg {
 10945  			break
 10946  		}
 10947  		if w != x1_1_0.Args[0] {
 10948  			break
 10949  		}
 10950  		x2 := x1.Args[2]
 10951  		if x2.Op != OpARM64MOVBstore {
 10952  			break
 10953  		}
 10954  		if x2.AuxInt != i-3 {
 10955  			break
 10956  		}
 10957  		if x2.Aux != s {
 10958  			break
 10959  		}
 10960  		mem := x2.Args[2]
 10961  		if ptr != x2.Args[0] {
 10962  			break
 10963  		}
 10964  		x2_1 := x2.Args[1]
 10965  		if x2_1.Op != OpARM64SRLconst {
 10966  			break
 10967  		}
 10968  		if x2_1.AuxInt != 24 {
 10969  			break
 10970  		}
 10971  		x2_1_0 := x2_1.Args[0]
 10972  		if x2_1_0.Op != OpARM64MOVDreg {
 10973  			break
 10974  		}
 10975  		if w != x2_1_0.Args[0] {
 10976  			break
 10977  		}
 10978  		if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) {
 10979  			break
 10980  		}
 10981  		v.reset(OpARM64MOVWstore)
 10982  		v.AuxInt = i - 3
 10983  		v.Aux = s
 10984  		v.AddArg(ptr)
 10985  		v0 := b.NewValue0(x2.Pos, OpARM64REVW, w.Type)
 10986  		v0.AddArg(w)
 10987  		v.AddArg(v0)
 10988  		v.AddArg(mem)
 10989  		return true
 10990  	}
 10991  	// match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (SRLconst [8] (MOVDreg w)) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [16] (MOVDreg w)) x2:(MOVBstoreidx ptr0 idx0 (SRLconst [24] (MOVDreg w)) mem))))
 10992  	// cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2)
 10993  	// result: (MOVWstoreidx ptr0 idx0 (REVW <w.Type> w) mem)
 10994  	for {
 10995  		if v.AuxInt != 3 {
 10996  			break
 10997  		}
 10998  		s := v.Aux
 10999  		_ = v.Args[2]
 11000  		p := v.Args[0]
 11001  		w := v.Args[1]
 11002  		x0 := v.Args[2]
 11003  		if x0.Op != OpARM64MOVBstore {
 11004  			break
 11005  		}
 11006  		if x0.AuxInt != 2 {
 11007  			break
 11008  		}
 11009  		if x0.Aux != s {
 11010  			break
 11011  		}
 11012  		_ = x0.Args[2]
 11013  		if p != x0.Args[0] {
 11014  			break
 11015  		}
 11016  		x0_1 := x0.Args[1]
 11017  		if x0_1.Op != OpARM64SRLconst {
 11018  			break
 11019  		}
 11020  		if x0_1.AuxInt != 8 {
 11021  			break
 11022  		}
 11023  		x0_1_0 := x0_1.Args[0]
 11024  		if x0_1_0.Op != OpARM64MOVDreg {
 11025  			break
 11026  		}
 11027  		if w != x0_1_0.Args[0] {
 11028  			break
 11029  		}
 11030  		x1 := x0.Args[2]
 11031  		if x1.Op != OpARM64MOVBstore {
 11032  			break
 11033  		}
 11034  		if x1.AuxInt != 1 {
 11035  			break
 11036  		}
 11037  		if x1.Aux != s {
 11038  			break
 11039  		}
 11040  		_ = x1.Args[2]
 11041  		p1 := x1.Args[0]
 11042  		if p1.Op != OpARM64ADD {
 11043  			break
 11044  		}
 11045  		idx1 := p1.Args[1]
 11046  		ptr1 := p1.Args[0]
 11047  		x1_1 := x1.Args[1]
 11048  		if x1_1.Op != OpARM64SRLconst {
 11049  			break
 11050  		}
 11051  		if x1_1.AuxInt != 16 {
 11052  			break
 11053  		}
 11054  		x1_1_0 := x1_1.Args[0]
 11055  		if x1_1_0.Op != OpARM64MOVDreg {
 11056  			break
 11057  		}
 11058  		if w != x1_1_0.Args[0] {
 11059  			break
 11060  		}
 11061  		x2 := x1.Args[2]
 11062  		if x2.Op != OpARM64MOVBstoreidx {
 11063  			break
 11064  		}
 11065  		mem := x2.Args[3]
 11066  		ptr0 := x2.Args[0]
 11067  		idx0 := x2.Args[1]
 11068  		x2_2 := x2.Args[2]
 11069  		if x2_2.Op != OpARM64SRLconst {
 11070  			break
 11071  		}
 11072  		if x2_2.AuxInt != 24 {
 11073  			break
 11074  		}
 11075  		x2_2_0 := x2_2.Args[0]
 11076  		if x2_2_0.Op != OpARM64MOVDreg {
 11077  			break
 11078  		}
 11079  		if w != x2_2_0.Args[0] {
 11080  			break
 11081  		}
 11082  		if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2)) {
 11083  			break
 11084  		}
 11085  		v.reset(OpARM64MOVWstoreidx)
 11086  		v.AddArg(ptr0)
 11087  		v.AddArg(idx0)
 11088  		v0 := b.NewValue0(x1.Pos, OpARM64REVW, w.Type)
 11089  		v0.AddArg(w)
 11090  		v.AddArg(v0)
 11091  		v.AddArg(mem)
 11092  		return true
 11093  	}
 11094  	return false
 11095  }
 11096  func rewriteValueARM64_OpARM64MOVBstore_30(v *Value) bool {
 11097  	b := v.Block
 11098  	// match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] w) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] w) mem))))
 11099  	// cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)
 11100  	// result: (MOVWstore [i-3] {s} ptr (REVW <w.Type> w) mem)
 11101  	for {
 11102  		i := v.AuxInt
 11103  		s := v.Aux
 11104  		_ = v.Args[2]
 11105  		ptr := v.Args[0]
 11106  		w := v.Args[1]
 11107  		x0 := v.Args[2]
 11108  		if x0.Op != OpARM64MOVBstore {
 11109  			break
 11110  		}
 11111  		if x0.AuxInt != i-1 {
 11112  			break
 11113  		}
 11114  		if x0.Aux != s {
 11115  			break
 11116  		}
 11117  		_ = x0.Args[2]
 11118  		if ptr != x0.Args[0] {
 11119  			break
 11120  		}
 11121  		x0_1 := x0.Args[1]
 11122  		if x0_1.Op != OpARM64SRLconst {
 11123  			break
 11124  		}
 11125  		if x0_1.AuxInt != 8 {
 11126  			break
 11127  		}
 11128  		if w != x0_1.Args[0] {
 11129  			break
 11130  		}
 11131  		x1 := x0.Args[2]
 11132  		if x1.Op != OpARM64MOVBstore {
 11133  			break
 11134  		}
 11135  		if x1.AuxInt != i-2 {
 11136  			break
 11137  		}
 11138  		if x1.Aux != s {
 11139  			break
 11140  		}
 11141  		_ = x1.Args[2]
 11142  		if ptr != x1.Args[0] {
 11143  			break
 11144  		}
 11145  		x1_1 := x1.Args[1]
 11146  		if x1_1.Op != OpARM64SRLconst {
 11147  			break
 11148  		}
 11149  		if x1_1.AuxInt != 16 {
 11150  			break
 11151  		}
 11152  		if w != x1_1.Args[0] {
 11153  			break
 11154  		}
 11155  		x2 := x1.Args[2]
 11156  		if x2.Op != OpARM64MOVBstore {
 11157  			break
 11158  		}
 11159  		if x2.AuxInt != i-3 {
 11160  			break
 11161  		}
 11162  		if x2.Aux != s {
 11163  			break
 11164  		}
 11165  		mem := x2.Args[2]
 11166  		if ptr != x2.Args[0] {
 11167  			break
 11168  		}
 11169  		x2_1 := x2.Args[1]
 11170  		if x2_1.Op != OpARM64SRLconst {
 11171  			break
 11172  		}
 11173  		if x2_1.AuxInt != 24 {
 11174  			break
 11175  		}
 11176  		if w != x2_1.Args[0] {
 11177  			break
 11178  		}
 11179  		if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) {
 11180  			break
 11181  		}
 11182  		v.reset(OpARM64MOVWstore)
 11183  		v.AuxInt = i - 3
 11184  		v.Aux = s
 11185  		v.AddArg(ptr)
 11186  		v0 := b.NewValue0(x2.Pos, OpARM64REVW, w.Type)
 11187  		v0.AddArg(w)
 11188  		v.AddArg(v0)
 11189  		v.AddArg(mem)
 11190  		return true
 11191  	}
 11192  	// match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (SRLconst [8] w) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [16] w) x2:(MOVBstoreidx ptr0 idx0 (SRLconst [24] w) mem))))
 11193  	// cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2)
 11194  	// result: (MOVWstoreidx ptr0 idx0 (REVW <w.Type> w) mem)
 11195  	for {
 11196  		if v.AuxInt != 3 {
 11197  			break
 11198  		}
 11199  		s := v.Aux
 11200  		_ = v.Args[2]
 11201  		p := v.Args[0]
 11202  		w := v.Args[1]
 11203  		x0 := v.Args[2]
 11204  		if x0.Op != OpARM64MOVBstore {
 11205  			break
 11206  		}
 11207  		if x0.AuxInt != 2 {
 11208  			break
 11209  		}
 11210  		if x0.Aux != s {
 11211  			break
 11212  		}
 11213  		_ = x0.Args[2]
 11214  		if p != x0.Args[0] {
 11215  			break
 11216  		}
 11217  		x0_1 := x0.Args[1]
 11218  		if x0_1.Op != OpARM64SRLconst {
 11219  			break
 11220  		}
 11221  		if x0_1.AuxInt != 8 {
 11222  			break
 11223  		}
 11224  		if w != x0_1.Args[0] {
 11225  			break
 11226  		}
 11227  		x1 := x0.Args[2]
 11228  		if x1.Op != OpARM64MOVBstore {
 11229  			break
 11230  		}
 11231  		if x1.AuxInt != 1 {
 11232  			break
 11233  		}
 11234  		if x1.Aux != s {
 11235  			break
 11236  		}
 11237  		_ = x1.Args[2]
 11238  		p1 := x1.Args[0]
 11239  		if p1.Op != OpARM64ADD {
 11240  			break
 11241  		}
 11242  		idx1 := p1.Args[1]
 11243  		ptr1 := p1.Args[0]
 11244  		x1_1 := x1.Args[1]
 11245  		if x1_1.Op != OpARM64SRLconst {
 11246  			break
 11247  		}
 11248  		if x1_1.AuxInt != 16 {
 11249  			break
 11250  		}
 11251  		if w != x1_1.Args[0] {
 11252  			break
 11253  		}
 11254  		x2 := x1.Args[2]
 11255  		if x2.Op != OpARM64MOVBstoreidx {
 11256  			break
 11257  		}
 11258  		mem := x2.Args[3]
 11259  		ptr0 := x2.Args[0]
 11260  		idx0 := x2.Args[1]
 11261  		x2_2 := x2.Args[2]
 11262  		if x2_2.Op != OpARM64SRLconst {
 11263  			break
 11264  		}
 11265  		if x2_2.AuxInt != 24 {
 11266  			break
 11267  		}
 11268  		if w != x2_2.Args[0] {
 11269  			break
 11270  		}
 11271  		if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2)) {
 11272  			break
 11273  		}
 11274  		v.reset(OpARM64MOVWstoreidx)
 11275  		v.AddArg(ptr0)
 11276  		v.AddArg(idx0)
 11277  		v0 := b.NewValue0(x1.Pos, OpARM64REVW, w.Type)
 11278  		v0.AddArg(w)
 11279  		v.AddArg(v0)
 11280  		v.AddArg(mem)
 11281  		return true
 11282  	}
 11283  	// match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) mem))
 11284  	// cond: x.Uses == 1 && clobber(x)
 11285  	// result: (MOVHstore [i-1] {s} ptr (REV16W <w.Type> w) mem)
 11286  	for {
 11287  		i := v.AuxInt
 11288  		s := v.Aux
 11289  		_ = v.Args[2]
 11290  		ptr := v.Args[0]
 11291  		w := v.Args[1]
 11292  		x := v.Args[2]
 11293  		if x.Op != OpARM64MOVBstore {
 11294  			break
 11295  		}
 11296  		if x.AuxInt != i-1 {
 11297  			break
 11298  		}
 11299  		if x.Aux != s {
 11300  			break
 11301  		}
 11302  		mem := x.Args[2]
 11303  		if ptr != x.Args[0] {
 11304  			break
 11305  		}
 11306  		x_1 := x.Args[1]
 11307  		if x_1.Op != OpARM64SRLconst {
 11308  			break
 11309  		}
 11310  		if x_1.AuxInt != 8 {
 11311  			break
 11312  		}
 11313  		if w != x_1.Args[0] {
 11314  			break
 11315  		}
 11316  		if !(x.Uses == 1 && clobber(x)) {
 11317  			break
 11318  		}
 11319  		v.reset(OpARM64MOVHstore)
 11320  		v.AuxInt = i - 1
 11321  		v.Aux = s
 11322  		v.AddArg(ptr)
 11323  		v0 := b.NewValue0(x.Pos, OpARM64REV16W, w.Type)
 11324  		v0.AddArg(w)
 11325  		v.AddArg(v0)
 11326  		v.AddArg(mem)
 11327  		return true
 11328  	}
 11329  	// match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (SRLconst [8] w) mem))
 11330  	// cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)
 11331  	// result: (MOVHstoreidx ptr0 idx0 (REV16W <w.Type> w) mem)
 11332  	for {
 11333  		if v.AuxInt != 1 {
 11334  			break
 11335  		}
 11336  		s := v.Aux
 11337  		_ = v.Args[2]
 11338  		v_0 := v.Args[0]
 11339  		if v_0.Op != OpARM64ADD {
 11340  			break
 11341  		}
 11342  		idx1 := v_0.Args[1]
 11343  		ptr1 := v_0.Args[0]
 11344  		w := v.Args[1]
 11345  		x := v.Args[2]
 11346  		if x.Op != OpARM64MOVBstoreidx {
 11347  			break
 11348  		}
 11349  		mem := x.Args[3]
 11350  		ptr0 := x.Args[0]
 11351  		idx0 := x.Args[1]
 11352  		x_2 := x.Args[2]
 11353  		if x_2.Op != OpARM64SRLconst {
 11354  			break
 11355  		}
 11356  		if x_2.AuxInt != 8 {
 11357  			break
 11358  		}
 11359  		if w != x_2.Args[0] {
 11360  			break
 11361  		}
 11362  		if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) {
 11363  			break
 11364  		}
 11365  		v.reset(OpARM64MOVHstoreidx)
 11366  		v.AddArg(ptr0)
 11367  		v.AddArg(idx0)
 11368  		v0 := b.NewValue0(v.Pos, OpARM64REV16W, w.Type)
 11369  		v0.AddArg(w)
 11370  		v.AddArg(v0)
 11371  		v.AddArg(mem)
 11372  		return true
 11373  	}
 11374  	// match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 8)] w) mem))
 11375  	// cond: x.Uses == 1 && clobber(x)
 11376  	// result: (MOVHstore [i-1] {s} ptr (REV16W <w.Type> w) mem)
 11377  	for {
 11378  		i := v.AuxInt
 11379  		s := v.Aux
 11380  		_ = v.Args[2]
 11381  		ptr := v.Args[0]
 11382  		w := v.Args[1]
 11383  		x := v.Args[2]
 11384  		if x.Op != OpARM64MOVBstore {
 11385  			break
 11386  		}
 11387  		if x.AuxInt != i-1 {
 11388  			break
 11389  		}
 11390  		if x.Aux != s {
 11391  			break
 11392  		}
 11393  		mem := x.Args[2]
 11394  		if ptr != x.Args[0] {
 11395  			break
 11396  		}
 11397  		x_1 := x.Args[1]
 11398  		if x_1.Op != OpARM64UBFX {
 11399  			break
 11400  		}
 11401  		if x_1.AuxInt != armBFAuxInt(8, 8) {
 11402  			break
 11403  		}
 11404  		if w != x_1.Args[0] {
 11405  			break
 11406  		}
 11407  		if !(x.Uses == 1 && clobber(x)) {
 11408  			break
 11409  		}
 11410  		v.reset(OpARM64MOVHstore)
 11411  		v.AuxInt = i - 1
 11412  		v.Aux = s
 11413  		v.AddArg(ptr)
 11414  		v0 := b.NewValue0(x.Pos, OpARM64REV16W, w.Type)
 11415  		v0.AddArg(w)
 11416  		v.AddArg(v0)
 11417  		v.AddArg(mem)
 11418  		return true
 11419  	}
 11420  	// match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(8, 8)] w) mem))
 11421  	// cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)
 11422  	// result: (MOVHstoreidx ptr0 idx0 (REV16W <w.Type> w) mem)
 11423  	for {
 11424  		if v.AuxInt != 1 {
 11425  			break
 11426  		}
 11427  		s := v.Aux
 11428  		_ = v.Args[2]
 11429  		v_0 := v.Args[0]
 11430  		if v_0.Op != OpARM64ADD {
 11431  			break
 11432  		}
 11433  		idx1 := v_0.Args[1]
 11434  		ptr1 := v_0.Args[0]
 11435  		w := v.Args[1]
 11436  		x := v.Args[2]
 11437  		if x.Op != OpARM64MOVBstoreidx {
 11438  			break
 11439  		}
 11440  		mem := x.Args[3]
 11441  		ptr0 := x.Args[0]
 11442  		idx0 := x.Args[1]
 11443  		x_2 := x.Args[2]
 11444  		if x_2.Op != OpARM64UBFX {
 11445  			break
 11446  		}
 11447  		if x_2.AuxInt != armBFAuxInt(8, 8) {
 11448  			break
 11449  		}
 11450  		if w != x_2.Args[0] {
 11451  			break
 11452  		}
 11453  		if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) {
 11454  			break
 11455  		}
 11456  		v.reset(OpARM64MOVHstoreidx)
 11457  		v.AddArg(ptr0)
 11458  		v.AddArg(idx0)
 11459  		v0 := b.NewValue0(v.Pos, OpARM64REV16W, w.Type)
 11460  		v0.AddArg(w)
 11461  		v.AddArg(v0)
 11462  		v.AddArg(mem)
 11463  		return true
 11464  	}
 11465  	// match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (SRLconst [8] (MOVDreg w)) mem))
 11466  	// cond: x.Uses == 1 && clobber(x)
 11467  	// result: (MOVHstore [i-1] {s} ptr (REV16W <w.Type> w) mem)
 11468  	for {
 11469  		i := v.AuxInt
 11470  		s := v.Aux
 11471  		_ = v.Args[2]
 11472  		ptr := v.Args[0]
 11473  		w := v.Args[1]
 11474  		x := v.Args[2]
 11475  		if x.Op != OpARM64MOVBstore {
 11476  			break
 11477  		}
 11478  		if x.AuxInt != i-1 {
 11479  			break
 11480  		}
 11481  		if x.Aux != s {
 11482  			break
 11483  		}
 11484  		mem := x.Args[2]
 11485  		if ptr != x.Args[0] {
 11486  			break
 11487  		}
 11488  		x_1 := x.Args[1]
 11489  		if x_1.Op != OpARM64SRLconst {
 11490  			break
 11491  		}
 11492  		if x_1.AuxInt != 8 {
 11493  			break
 11494  		}
 11495  		x_1_0 := x_1.Args[0]
 11496  		if x_1_0.Op != OpARM64MOVDreg {
 11497  			break
 11498  		}
 11499  		if w != x_1_0.Args[0] {
 11500  			break
 11501  		}
 11502  		if !(x.Uses == 1 && clobber(x)) {
 11503  			break
 11504  		}
 11505  		v.reset(OpARM64MOVHstore)
 11506  		v.AuxInt = i - 1
 11507  		v.Aux = s
 11508  		v.AddArg(ptr)
 11509  		v0 := b.NewValue0(x.Pos, OpARM64REV16W, w.Type)
 11510  		v0.AddArg(w)
 11511  		v.AddArg(v0)
 11512  		v.AddArg(mem)
 11513  		return true
 11514  	}
 11515  	// match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (SRLconst [8] (MOVDreg w)) mem))
 11516  	// cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)
 11517  	// result: (MOVHstoreidx ptr0 idx0 (REV16W <w.Type> w) mem)
 11518  	for {
 11519  		if v.AuxInt != 1 {
 11520  			break
 11521  		}
 11522  		s := v.Aux
 11523  		_ = v.Args[2]
 11524  		v_0 := v.Args[0]
 11525  		if v_0.Op != OpARM64ADD {
 11526  			break
 11527  		}
 11528  		idx1 := v_0.Args[1]
 11529  		ptr1 := v_0.Args[0]
 11530  		w := v.Args[1]
 11531  		x := v.Args[2]
 11532  		if x.Op != OpARM64MOVBstoreidx {
 11533  			break
 11534  		}
 11535  		mem := x.Args[3]
 11536  		ptr0 := x.Args[0]
 11537  		idx0 := x.Args[1]
 11538  		x_2 := x.Args[2]
 11539  		if x_2.Op != OpARM64SRLconst {
 11540  			break
 11541  		}
 11542  		if x_2.AuxInt != 8 {
 11543  			break
 11544  		}
 11545  		x_2_0 := x_2.Args[0]
 11546  		if x_2_0.Op != OpARM64MOVDreg {
 11547  			break
 11548  		}
 11549  		if w != x_2_0.Args[0] {
 11550  			break
 11551  		}
 11552  		if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) {
 11553  			break
 11554  		}
 11555  		v.reset(OpARM64MOVHstoreidx)
 11556  		v.AddArg(ptr0)
 11557  		v.AddArg(idx0)
 11558  		v0 := b.NewValue0(v.Pos, OpARM64REV16W, w.Type)
 11559  		v0.AddArg(w)
 11560  		v.AddArg(v0)
 11561  		v.AddArg(mem)
 11562  		return true
 11563  	}
 11564  	// match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 24)] w) mem))
 11565  	// cond: x.Uses == 1 && clobber(x)
 11566  	// result: (MOVHstore [i-1] {s} ptr (REV16W <w.Type> w) mem)
 11567  	for {
 11568  		i := v.AuxInt
 11569  		s := v.Aux
 11570  		_ = v.Args[2]
 11571  		ptr := v.Args[0]
 11572  		w := v.Args[1]
 11573  		x := v.Args[2]
 11574  		if x.Op != OpARM64MOVBstore {
 11575  			break
 11576  		}
 11577  		if x.AuxInt != i-1 {
 11578  			break
 11579  		}
 11580  		if x.Aux != s {
 11581  			break
 11582  		}
 11583  		mem := x.Args[2]
 11584  		if ptr != x.Args[0] {
 11585  			break
 11586  		}
 11587  		x_1 := x.Args[1]
 11588  		if x_1.Op != OpARM64UBFX {
 11589  			break
 11590  		}
 11591  		if x_1.AuxInt != armBFAuxInt(8, 24) {
 11592  			break
 11593  		}
 11594  		if w != x_1.Args[0] {
 11595  			break
 11596  		}
 11597  		if !(x.Uses == 1 && clobber(x)) {
 11598  			break
 11599  		}
 11600  		v.reset(OpARM64MOVHstore)
 11601  		v.AuxInt = i - 1
 11602  		v.Aux = s
 11603  		v.AddArg(ptr)
 11604  		v0 := b.NewValue0(x.Pos, OpARM64REV16W, w.Type)
 11605  		v0.AddArg(w)
 11606  		v.AddArg(v0)
 11607  		v.AddArg(mem)
 11608  		return true
 11609  	}
 11610  	// match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(8, 24)] w) mem))
 11611  	// cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)
 11612  	// result: (MOVHstoreidx ptr0 idx0 (REV16W <w.Type> w) mem)
 11613  	for {
 11614  		if v.AuxInt != 1 {
 11615  			break
 11616  		}
 11617  		s := v.Aux
 11618  		_ = v.Args[2]
 11619  		v_0 := v.Args[0]
 11620  		if v_0.Op != OpARM64ADD {
 11621  			break
 11622  		}
 11623  		idx1 := v_0.Args[1]
 11624  		ptr1 := v_0.Args[0]
 11625  		w := v.Args[1]
 11626  		x := v.Args[2]
 11627  		if x.Op != OpARM64MOVBstoreidx {
 11628  			break
 11629  		}
 11630  		mem := x.Args[3]
 11631  		ptr0 := x.Args[0]
 11632  		idx0 := x.Args[1]
 11633  		x_2 := x.Args[2]
 11634  		if x_2.Op != OpARM64UBFX {
 11635  			break
 11636  		}
 11637  		if x_2.AuxInt != armBFAuxInt(8, 24) {
 11638  			break
 11639  		}
 11640  		if w != x_2.Args[0] {
 11641  			break
 11642  		}
 11643  		if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) {
 11644  			break
 11645  		}
 11646  		v.reset(OpARM64MOVHstoreidx)
 11647  		v.AddArg(ptr0)
 11648  		v.AddArg(idx0)
 11649  		v0 := b.NewValue0(v.Pos, OpARM64REV16W, w.Type)
 11650  		v0.AddArg(w)
 11651  		v.AddArg(v0)
 11652  		v.AddArg(mem)
 11653  		return true
 11654  	}
 11655  	return false
 11656  }
 11657  func rewriteValueARM64_OpARM64MOVBstore_40(v *Value) bool {
 11658  	b := v.Block
 11659  	// match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (SRLconst [8] (MOVDreg w)) mem))
 11660  	// cond: x.Uses == 1 && clobber(x)
 11661  	// result: (MOVHstore [i-1] {s} ptr (REV16W <w.Type> w) mem)
 11662  	for {
 11663  		i := v.AuxInt
 11664  		s := v.Aux
 11665  		_ = v.Args[2]
 11666  		ptr := v.Args[0]
 11667  		w := v.Args[1]
 11668  		x := v.Args[2]
 11669  		if x.Op != OpARM64MOVBstore {
 11670  			break
 11671  		}
 11672  		if x.AuxInt != i-1 {
 11673  			break
 11674  		}
 11675  		if x.Aux != s {
 11676  			break
 11677  		}
 11678  		mem := x.Args[2]
 11679  		if ptr != x.Args[0] {
 11680  			break
 11681  		}
 11682  		x_1 := x.Args[1]
 11683  		if x_1.Op != OpARM64SRLconst {
 11684  			break
 11685  		}
 11686  		if x_1.AuxInt != 8 {
 11687  			break
 11688  		}
 11689  		x_1_0 := x_1.Args[0]
 11690  		if x_1_0.Op != OpARM64MOVDreg {
 11691  			break
 11692  		}
 11693  		if w != x_1_0.Args[0] {
 11694  			break
 11695  		}
 11696  		if !(x.Uses == 1 && clobber(x)) {
 11697  			break
 11698  		}
 11699  		v.reset(OpARM64MOVHstore)
 11700  		v.AuxInt = i - 1
 11701  		v.Aux = s
 11702  		v.AddArg(ptr)
 11703  		v0 := b.NewValue0(x.Pos, OpARM64REV16W, w.Type)
 11704  		v0.AddArg(w)
 11705  		v.AddArg(v0)
 11706  		v.AddArg(mem)
 11707  		return true
 11708  	}
 11709  	// match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (SRLconst [8] (MOVDreg w)) mem))
 11710  	// cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)
 11711  	// result: (MOVHstoreidx ptr0 idx0 (REV16W <w.Type> w) mem)
 11712  	for {
 11713  		if v.AuxInt != 1 {
 11714  			break
 11715  		}
 11716  		s := v.Aux
 11717  		_ = v.Args[2]
 11718  		v_0 := v.Args[0]
 11719  		if v_0.Op != OpARM64ADD {
 11720  			break
 11721  		}
 11722  		idx1 := v_0.Args[1]
 11723  		ptr1 := v_0.Args[0]
 11724  		w := v.Args[1]
 11725  		x := v.Args[2]
 11726  		if x.Op != OpARM64MOVBstoreidx {
 11727  			break
 11728  		}
 11729  		mem := x.Args[3]
 11730  		ptr0 := x.Args[0]
 11731  		idx0 := x.Args[1]
 11732  		x_2 := x.Args[2]
 11733  		if x_2.Op != OpARM64SRLconst {
 11734  			break
 11735  		}
 11736  		if x_2.AuxInt != 8 {
 11737  			break
 11738  		}
 11739  		x_2_0 := x_2.Args[0]
 11740  		if x_2_0.Op != OpARM64MOVDreg {
 11741  			break
 11742  		}
 11743  		if w != x_2_0.Args[0] {
 11744  			break
 11745  		}
 11746  		if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) {
 11747  			break
 11748  		}
 11749  		v.reset(OpARM64MOVHstoreidx)
 11750  		v.AddArg(ptr0)
 11751  		v.AddArg(idx0)
 11752  		v0 := b.NewValue0(v.Pos, OpARM64REV16W, w.Type)
 11753  		v0.AddArg(w)
 11754  		v.AddArg(v0)
 11755  		v.AddArg(mem)
 11756  		return true
 11757  	}
 11758  	return false
 11759  }
 11760  func rewriteValueARM64_OpARM64MOVBstoreidx_0(v *Value) bool {
 11761  	// match: (MOVBstoreidx ptr (MOVDconst [c]) val mem)
 11762  	// cond:
 11763  	// result: (MOVBstore [c] ptr val mem)
 11764  	for {
 11765  		mem := v.Args[3]
 11766  		ptr := v.Args[0]
 11767  		v_1 := v.Args[1]
 11768  		if v_1.Op != OpARM64MOVDconst {
 11769  			break
 11770  		}
 11771  		c := v_1.AuxInt
 11772  		val := v.Args[2]
 11773  		v.reset(OpARM64MOVBstore)
 11774  		v.AuxInt = c
 11775  		v.AddArg(ptr)
 11776  		v.AddArg(val)
 11777  		v.AddArg(mem)
 11778  		return true
 11779  	}
 11780  	// match: (MOVBstoreidx (MOVDconst [c]) idx val mem)
 11781  	// cond:
 11782  	// result: (MOVBstore [c] idx val mem)
 11783  	for {
 11784  		mem := v.Args[3]
 11785  		v_0 := v.Args[0]
 11786  		if v_0.Op != OpARM64MOVDconst {
 11787  			break
 11788  		}
 11789  		c := v_0.AuxInt
 11790  		idx := v.Args[1]
 11791  		val := v.Args[2]
 11792  		v.reset(OpARM64MOVBstore)
 11793  		v.AuxInt = c
 11794  		v.AddArg(idx)
 11795  		v.AddArg(val)
 11796  		v.AddArg(mem)
 11797  		return true
 11798  	}
 11799  	// match: (MOVBstoreidx ptr idx (MOVDconst [0]) mem)
 11800  	// cond:
 11801  	// result: (MOVBstorezeroidx ptr idx mem)
 11802  	for {
 11803  		mem := v.Args[3]
 11804  		ptr := v.Args[0]
 11805  		idx := v.Args[1]
 11806  		v_2 := v.Args[2]
 11807  		if v_2.Op != OpARM64MOVDconst {
 11808  			break
 11809  		}
 11810  		if v_2.AuxInt != 0 {
 11811  			break
 11812  		}
 11813  		v.reset(OpARM64MOVBstorezeroidx)
 11814  		v.AddArg(ptr)
 11815  		v.AddArg(idx)
 11816  		v.AddArg(mem)
 11817  		return true
 11818  	}
 11819  	// match: (MOVBstoreidx ptr idx (MOVBreg x) mem)
 11820  	// cond:
 11821  	// result: (MOVBstoreidx ptr idx x mem)
 11822  	for {
 11823  		mem := v.Args[3]
 11824  		ptr := v.Args[0]
 11825  		idx := v.Args[1]
 11826  		v_2 := v.Args[2]
 11827  		if v_2.Op != OpARM64MOVBreg {
 11828  			break
 11829  		}
 11830  		x := v_2.Args[0]
 11831  		v.reset(OpARM64MOVBstoreidx)
 11832  		v.AddArg(ptr)
 11833  		v.AddArg(idx)
 11834  		v.AddArg(x)
 11835  		v.AddArg(mem)
 11836  		return true
 11837  	}
 11838  	// match: (MOVBstoreidx ptr idx (MOVBUreg x) mem)
 11839  	// cond:
 11840  	// result: (MOVBstoreidx ptr idx x mem)
 11841  	for {
 11842  		mem := v.Args[3]
 11843  		ptr := v.Args[0]
 11844  		idx := v.Args[1]
 11845  		v_2 := v.Args[2]
 11846  		if v_2.Op != OpARM64MOVBUreg {
 11847  			break
 11848  		}
 11849  		x := v_2.Args[0]
 11850  		v.reset(OpARM64MOVBstoreidx)
 11851  		v.AddArg(ptr)
 11852  		v.AddArg(idx)
 11853  		v.AddArg(x)
 11854  		v.AddArg(mem)
 11855  		return true
 11856  	}
 11857  	// match: (MOVBstoreidx ptr idx (MOVHreg x) mem)
 11858  	// cond:
 11859  	// result: (MOVBstoreidx ptr idx x mem)
 11860  	for {
 11861  		mem := v.Args[3]
 11862  		ptr := v.Args[0]
 11863  		idx := v.Args[1]
 11864  		v_2 := v.Args[2]
 11865  		if v_2.Op != OpARM64MOVHreg {
 11866  			break
 11867  		}
 11868  		x := v_2.Args[0]
 11869  		v.reset(OpARM64MOVBstoreidx)
 11870  		v.AddArg(ptr)
 11871  		v.AddArg(idx)
 11872  		v.AddArg(x)
 11873  		v.AddArg(mem)
 11874  		return true
 11875  	}
 11876  	// match: (MOVBstoreidx ptr idx (MOVHUreg x) mem)
 11877  	// cond:
 11878  	// result: (MOVBstoreidx ptr idx x mem)
 11879  	for {
 11880  		mem := v.Args[3]
 11881  		ptr := v.Args[0]
 11882  		idx := v.Args[1]
 11883  		v_2 := v.Args[2]
 11884  		if v_2.Op != OpARM64MOVHUreg {
 11885  			break
 11886  		}
 11887  		x := v_2.Args[0]
 11888  		v.reset(OpARM64MOVBstoreidx)
 11889  		v.AddArg(ptr)
 11890  		v.AddArg(idx)
 11891  		v.AddArg(x)
 11892  		v.AddArg(mem)
 11893  		return true
 11894  	}
 11895  	// match: (MOVBstoreidx ptr idx (MOVWreg x) mem)
 11896  	// cond:
 11897  	// result: (MOVBstoreidx ptr idx x mem)
 11898  	for {
 11899  		mem := v.Args[3]
 11900  		ptr := v.Args[0]
 11901  		idx := v.Args[1]
 11902  		v_2 := v.Args[2]
 11903  		if v_2.Op != OpARM64MOVWreg {
 11904  			break
 11905  		}
 11906  		x := v_2.Args[0]
 11907  		v.reset(OpARM64MOVBstoreidx)
 11908  		v.AddArg(ptr)
 11909  		v.AddArg(idx)
 11910  		v.AddArg(x)
 11911  		v.AddArg(mem)
 11912  		return true
 11913  	}
 11914  	// match: (MOVBstoreidx ptr idx (MOVWUreg x) mem)
 11915  	// cond:
 11916  	// result: (MOVBstoreidx ptr idx x mem)
 11917  	for {
 11918  		mem := v.Args[3]
 11919  		ptr := v.Args[0]
 11920  		idx := v.Args[1]
 11921  		v_2 := v.Args[2]
 11922  		if v_2.Op != OpARM64MOVWUreg {
 11923  			break
 11924  		}
 11925  		x := v_2.Args[0]
 11926  		v.reset(OpARM64MOVBstoreidx)
 11927  		v.AddArg(ptr)
 11928  		v.AddArg(idx)
 11929  		v.AddArg(x)
 11930  		v.AddArg(mem)
 11931  		return true
 11932  	}
 11933  	// match: (MOVBstoreidx ptr (ADDconst [1] idx) (SRLconst [8] w) x:(MOVBstoreidx ptr idx w mem))
 11934  	// cond: x.Uses == 1 && clobber(x)
 11935  	// result: (MOVHstoreidx ptr idx w mem)
 11936  	for {
 11937  		_ = v.Args[3]
 11938  		ptr := v.Args[0]
 11939  		v_1 := v.Args[1]
 11940  		if v_1.Op != OpARM64ADDconst {
 11941  			break
 11942  		}
 11943  		if v_1.AuxInt != 1 {
 11944  			break
 11945  		}
 11946  		idx := v_1.Args[0]
 11947  		v_2 := v.Args[2]
 11948  		if v_2.Op != OpARM64SRLconst {
 11949  			break
 11950  		}
 11951  		if v_2.AuxInt != 8 {
 11952  			break
 11953  		}
 11954  		w := v_2.Args[0]
 11955  		x := v.Args[3]
 11956  		if x.Op != OpARM64MOVBstoreidx {
 11957  			break
 11958  		}
 11959  		mem := x.Args[3]
 11960  		if ptr != x.Args[0] {
 11961  			break
 11962  		}
 11963  		if idx != x.Args[1] {
 11964  			break
 11965  		}
 11966  		if w != x.Args[2] {
 11967  			break
 11968  		}
 11969  		if !(x.Uses == 1 && clobber(x)) {
 11970  			break
 11971  		}
 11972  		v.reset(OpARM64MOVHstoreidx)
 11973  		v.AddArg(ptr)
 11974  		v.AddArg(idx)
 11975  		v.AddArg(w)
 11976  		v.AddArg(mem)
 11977  		return true
 11978  	}
 11979  	return false
 11980  }
 11981  func rewriteValueARM64_OpARM64MOVBstoreidx_10(v *Value) bool {
 11982  	b := v.Block
 11983  	// match: (MOVBstoreidx ptr (ADDconst [3] idx) w x0:(MOVBstoreidx ptr (ADDconst [2] idx) (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr idx (UBFX [armBFAuxInt(24, 8)] w) mem))))
 11984  	// cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)
 11985  	// result: (MOVWstoreidx ptr idx (REVW <w.Type> w) mem)
 11986  	for {
 11987  		_ = v.Args[3]
 11988  		ptr := v.Args[0]
 11989  		v_1 := v.Args[1]
 11990  		if v_1.Op != OpARM64ADDconst {
 11991  			break
 11992  		}
 11993  		if v_1.AuxInt != 3 {
 11994  			break
 11995  		}
 11996  		idx := v_1.Args[0]
 11997  		w := v.Args[2]
 11998  		x0 := v.Args[3]
 11999  		if x0.Op != OpARM64MOVBstoreidx {
 12000  			break
 12001  		}
 12002  		_ = x0.Args[3]
 12003  		if ptr != x0.Args[0] {
 12004  			break
 12005  		}
 12006  		x0_1 := x0.Args[1]
 12007  		if x0_1.Op != OpARM64ADDconst {
 12008  			break
 12009  		}
 12010  		if x0_1.AuxInt != 2 {
 12011  			break
 12012  		}
 12013  		if idx != x0_1.Args[0] {
 12014  			break
 12015  		}
 12016  		x0_2 := x0.Args[2]
 12017  		if x0_2.Op != OpARM64UBFX {
 12018  			break
 12019  		}
 12020  		if x0_2.AuxInt != armBFAuxInt(8, 24) {
 12021  			break
 12022  		}
 12023  		if w != x0_2.Args[0] {
 12024  			break
 12025  		}
 12026  		x1 := x0.Args[3]
 12027  		if x1.Op != OpARM64MOVBstoreidx {
 12028  			break
 12029  		}
 12030  		_ = x1.Args[3]
 12031  		if ptr != x1.Args[0] {
 12032  			break
 12033  		}
 12034  		x1_1 := x1.Args[1]
 12035  		if x1_1.Op != OpARM64ADDconst {
 12036  			break
 12037  		}
 12038  		if x1_1.AuxInt != 1 {
 12039  			break
 12040  		}
 12041  		if idx != x1_1.Args[0] {
 12042  			break
 12043  		}
 12044  		x1_2 := x1.Args[2]
 12045  		if x1_2.Op != OpARM64UBFX {
 12046  			break
 12047  		}
 12048  		if x1_2.AuxInt != armBFAuxInt(16, 16) {
 12049  			break
 12050  		}
 12051  		if w != x1_2.Args[0] {
 12052  			break
 12053  		}
 12054  		x2 := x1.Args[3]
 12055  		if x2.Op != OpARM64MOVBstoreidx {
 12056  			break
 12057  		}
 12058  		mem := x2.Args[3]
 12059  		if ptr != x2.Args[0] {
 12060  			break
 12061  		}
 12062  		if idx != x2.Args[1] {
 12063  			break
 12064  		}
 12065  		x2_2 := x2.Args[2]
 12066  		if x2_2.Op != OpARM64UBFX {
 12067  			break
 12068  		}
 12069  		if x2_2.AuxInt != armBFAuxInt(24, 8) {
 12070  			break
 12071  		}
 12072  		if w != x2_2.Args[0] {
 12073  			break
 12074  		}
 12075  		if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) {
 12076  			break
 12077  		}
 12078  		v.reset(OpARM64MOVWstoreidx)
 12079  		v.AddArg(ptr)
 12080  		v.AddArg(idx)
 12081  		v0 := b.NewValue0(v.Pos, OpARM64REVW, w.Type)
 12082  		v0.AddArg(w)
 12083  		v.AddArg(v0)
 12084  		v.AddArg(mem)
 12085  		return true
 12086  	}
 12087  	// match: (MOVBstoreidx ptr idx w x0:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstoreidx ptr (ADDconst [2] idx) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr (ADDconst [3] idx) (UBFX [armBFAuxInt(24, 8)] w) mem))))
 12088  	// cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)
 12089  	// result: (MOVWstoreidx ptr idx w mem)
 12090  	for {
 12091  		_ = v.Args[3]
 12092  		ptr := v.Args[0]
 12093  		idx := v.Args[1]
 12094  		w := v.Args[2]
 12095  		x0 := v.Args[3]
 12096  		if x0.Op != OpARM64MOVBstoreidx {
 12097  			break
 12098  		}
 12099  		_ = x0.Args[3]
 12100  		if ptr != x0.Args[0] {
 12101  			break
 12102  		}
 12103  		x0_1 := x0.Args[1]
 12104  		if x0_1.Op != OpARM64ADDconst {
 12105  			break
 12106  		}
 12107  		if x0_1.AuxInt != 1 {
 12108  			break
 12109  		}
 12110  		if idx != x0_1.Args[0] {
 12111  			break
 12112  		}
 12113  		x0_2 := x0.Args[2]
 12114  		if x0_2.Op != OpARM64UBFX {
 12115  			break
 12116  		}
 12117  		if x0_2.AuxInt != armBFAuxInt(8, 24) {
 12118  			break
 12119  		}
 12120  		if w != x0_2.Args[0] {
 12121  			break
 12122  		}
 12123  		x1 := x0.Args[3]
 12124  		if x1.Op != OpARM64MOVBstoreidx {
 12125  			break
 12126  		}
 12127  		_ = x1.Args[3]
 12128  		if ptr != x1.Args[0] {
 12129  			break
 12130  		}
 12131  		x1_1 := x1.Args[1]
 12132  		if x1_1.Op != OpARM64ADDconst {
 12133  			break
 12134  		}
 12135  		if x1_1.AuxInt != 2 {
 12136  			break
 12137  		}
 12138  		if idx != x1_1.Args[0] {
 12139  			break
 12140  		}
 12141  		x1_2 := x1.Args[2]
 12142  		if x1_2.Op != OpARM64UBFX {
 12143  			break
 12144  		}
 12145  		if x1_2.AuxInt != armBFAuxInt(16, 16) {
 12146  			break
 12147  		}
 12148  		if w != x1_2.Args[0] {
 12149  			break
 12150  		}
 12151  		x2 := x1.Args[3]
 12152  		if x2.Op != OpARM64MOVBstoreidx {
 12153  			break
 12154  		}
 12155  		mem := x2.Args[3]
 12156  		if ptr != x2.Args[0] {
 12157  			break
 12158  		}
 12159  		x2_1 := x2.Args[1]
 12160  		if x2_1.Op != OpARM64ADDconst {
 12161  			break
 12162  		}
 12163  		if x2_1.AuxInt != 3 {
 12164  			break
 12165  		}
 12166  		if idx != x2_1.Args[0] {
 12167  			break
 12168  		}
 12169  		x2_2 := x2.Args[2]
 12170  		if x2_2.Op != OpARM64UBFX {
 12171  			break
 12172  		}
 12173  		if x2_2.AuxInt != armBFAuxInt(24, 8) {
 12174  			break
 12175  		}
 12176  		if w != x2_2.Args[0] {
 12177  			break
 12178  		}
 12179  		if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) {
 12180  			break
 12181  		}
 12182  		v.reset(OpARM64MOVWstoreidx)
 12183  		v.AddArg(ptr)
 12184  		v.AddArg(idx)
 12185  		v.AddArg(w)
 12186  		v.AddArg(mem)
 12187  		return true
 12188  	}
 12189  	// match: (MOVBstoreidx ptr (ADDconst [1] idx) w x:(MOVBstoreidx ptr idx (UBFX [armBFAuxInt(8, 8)] w) mem))
 12190  	// cond: x.Uses == 1 && clobber(x)
 12191  	// result: (MOVHstoreidx ptr idx (REV16W <w.Type> w) mem)
 12192  	for {
 12193  		_ = v.Args[3]
 12194  		ptr := v.Args[0]
 12195  		v_1 := v.Args[1]
 12196  		if v_1.Op != OpARM64ADDconst {
 12197  			break
 12198  		}
 12199  		if v_1.AuxInt != 1 {
 12200  			break
 12201  		}
 12202  		idx := v_1.Args[0]
 12203  		w := v.Args[2]
 12204  		x := v.Args[3]
 12205  		if x.Op != OpARM64MOVBstoreidx {
 12206  			break
 12207  		}
 12208  		mem := x.Args[3]
 12209  		if ptr != x.Args[0] {
 12210  			break
 12211  		}
 12212  		if idx != x.Args[1] {
 12213  			break
 12214  		}
 12215  		x_2 := x.Args[2]
 12216  		if x_2.Op != OpARM64UBFX {
 12217  			break
 12218  		}
 12219  		if x_2.AuxInt != armBFAuxInt(8, 8) {
 12220  			break
 12221  		}
 12222  		if w != x_2.Args[0] {
 12223  			break
 12224  		}
 12225  		if !(x.Uses == 1 && clobber(x)) {
 12226  			break
 12227  		}
 12228  		v.reset(OpARM64MOVHstoreidx)
 12229  		v.AddArg(ptr)
 12230  		v.AddArg(idx)
 12231  		v0 := b.NewValue0(v.Pos, OpARM64REV16W, w.Type)
 12232  		v0.AddArg(w)
 12233  		v.AddArg(v0)
 12234  		v.AddArg(mem)
 12235  		return true
 12236  	}
 12237  	// match: (MOVBstoreidx ptr idx w x:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(8, 8)] w) mem))
 12238  	// cond: x.Uses == 1 && clobber(x)
 12239  	// result: (MOVHstoreidx ptr idx w mem)
 12240  	for {
 12241  		_ = v.Args[3]
 12242  		ptr := v.Args[0]
 12243  		idx := v.Args[1]
 12244  		w := v.Args[2]
 12245  		x := v.Args[3]
 12246  		if x.Op != OpARM64MOVBstoreidx {
 12247  			break
 12248  		}
 12249  		mem := x.Args[3]
 12250  		if ptr != x.Args[0] {
 12251  			break
 12252  		}
 12253  		x_1 := x.Args[1]
 12254  		if x_1.Op != OpARM64ADDconst {
 12255  			break
 12256  		}
 12257  		if x_1.AuxInt != 1 {
 12258  			break
 12259  		}
 12260  		if idx != x_1.Args[0] {
 12261  			break
 12262  		}
 12263  		x_2 := x.Args[2]
 12264  		if x_2.Op != OpARM64UBFX {
 12265  			break
 12266  		}
 12267  		if x_2.AuxInt != armBFAuxInt(8, 8) {
 12268  			break
 12269  		}
 12270  		if w != x_2.Args[0] {
 12271  			break
 12272  		}
 12273  		if !(x.Uses == 1 && clobber(x)) {
 12274  			break
 12275  		}
 12276  		v.reset(OpARM64MOVHstoreidx)
 12277  		v.AddArg(ptr)
 12278  		v.AddArg(idx)
 12279  		v.AddArg(w)
 12280  		v.AddArg(mem)
 12281  		return true
 12282  	}
 12283  	return false
 12284  }
 12285  func rewriteValueARM64_OpARM64MOVBstorezero_0(v *Value) bool {
 12286  	b := v.Block
 12287  	config := b.Func.Config
 12288  	// match: (MOVBstorezero [off1] {sym} (ADDconst [off2] ptr) mem)
 12289  	// cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
 12290  	// result: (MOVBstorezero [off1+off2] {sym} ptr mem)
 12291  	for {
 12292  		off1 := v.AuxInt
 12293  		sym := v.Aux
 12294  		mem := v.Args[1]
 12295  		v_0 := v.Args[0]
 12296  		if v_0.Op != OpARM64ADDconst {
 12297  			break
 12298  		}
 12299  		off2 := v_0.AuxInt
 12300  		ptr := v_0.Args[0]
 12301  		if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
 12302  			break
 12303  		}
 12304  		v.reset(OpARM64MOVBstorezero)
 12305  		v.AuxInt = off1 + off2
 12306  		v.Aux = sym
 12307  		v.AddArg(ptr)
 12308  		v.AddArg(mem)
 12309  		return true
 12310  	}
 12311  	// match: (MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
 12312  	// cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
 12313  	// result: (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
 12314  	for {
 12315  		off1 := v.AuxInt
 12316  		sym1 := v.Aux
 12317  		mem := v.Args[1]
 12318  		v_0 := v.Args[0]
 12319  		if v_0.Op != OpARM64MOVDaddr {
 12320  			break
 12321  		}
 12322  		off2 := v_0.AuxInt
 12323  		sym2 := v_0.Aux
 12324  		ptr := v_0.Args[0]
 12325  		if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
 12326  			break
 12327  		}
 12328  		v.reset(OpARM64MOVBstorezero)
 12329  		v.AuxInt = off1 + off2
 12330  		v.Aux = mergeSym(sym1, sym2)
 12331  		v.AddArg(ptr)
 12332  		v.AddArg(mem)
 12333  		return true
 12334  	}
 12335  	// match: (MOVBstorezero [off] {sym} (ADD ptr idx) mem)
 12336  	// cond: off == 0 && sym == nil
 12337  	// result: (MOVBstorezeroidx ptr idx mem)
 12338  	for {
 12339  		off := v.AuxInt
 12340  		sym := v.Aux
 12341  		mem := v.Args[1]
 12342  		v_0 := v.Args[0]
 12343  		if v_0.Op != OpARM64ADD {
 12344  			break
 12345  		}
 12346  		idx := v_0.Args[1]
 12347  		ptr := v_0.Args[0]
 12348  		if !(off == 0 && sym == nil) {
 12349  			break
 12350  		}
 12351  		v.reset(OpARM64MOVBstorezeroidx)
 12352  		v.AddArg(ptr)
 12353  		v.AddArg(idx)
 12354  		v.AddArg(mem)
 12355  		return true
 12356  	}
 12357  	// match: (MOVBstorezero [i] {s} ptr0 x:(MOVBstorezero [j] {s} ptr1 mem))
 12358  	// cond: x.Uses == 1 && areAdjacentOffsets(i,j,1) && is32Bit(min(i,j)) && isSamePtr(ptr0, ptr1) && clobber(x)
 12359  	// result: (MOVHstorezero [min(i,j)] {s} ptr0 mem)
 12360  	for {
 12361  		i := v.AuxInt
 12362  		s := v.Aux
 12363  		_ = v.Args[1]
 12364  		ptr0 := v.Args[0]
 12365  		x := v.Args[1]
 12366  		if x.Op != OpARM64MOVBstorezero {
 12367  			break
 12368  		}
 12369  		j := x.AuxInt
 12370  		if x.Aux != s {
 12371  			break
 12372  		}
 12373  		mem := x.Args[1]
 12374  		ptr1 := x.Args[0]
 12375  		if !(x.Uses == 1 && areAdjacentOffsets(i, j, 1) && is32Bit(min(i, j)) && isSamePtr(ptr0, ptr1) && clobber(x)) {
 12376  			break
 12377  		}
 12378  		v.reset(OpARM64MOVHstorezero)
 12379  		v.AuxInt = min(i, j)
 12380  		v.Aux = s
 12381  		v.AddArg(ptr0)
 12382  		v.AddArg(mem)
 12383  		return true
 12384  	}
 12385  	// match: (MOVBstorezero [1] {s} (ADD ptr0 idx0) x:(MOVBstorezeroidx ptr1 idx1 mem))
 12386  	// cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)
 12387  	// result: (MOVHstorezeroidx ptr1 idx1 mem)
 12388  	for {
 12389  		if v.AuxInt != 1 {
 12390  			break
 12391  		}
 12392  		s := v.Aux
 12393  		_ = v.Args[1]
 12394  		v_0 := v.Args[0]
 12395  		if v_0.Op != OpARM64ADD {
 12396  			break
 12397  		}
 12398  		idx0 := v_0.Args[1]
 12399  		ptr0 := v_0.Args[0]
 12400  		x := v.Args[1]
 12401  		if x.Op != OpARM64MOVBstorezeroidx {
 12402  			break
 12403  		}
 12404  		mem := x.Args[2]
 12405  		ptr1 := x.Args[0]
 12406  		idx1 := x.Args[1]
 12407  		if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) {
 12408  			break
 12409  		}
 12410  		v.reset(OpARM64MOVHstorezeroidx)
 12411  		v.AddArg(ptr1)
 12412  		v.AddArg(idx1)
 12413  		v.AddArg(mem)
 12414  		return true
 12415  	}
 12416  	return false
 12417  }
 12418  func rewriteValueARM64_OpARM64MOVBstorezeroidx_0(v *Value) bool {
 12419  	// match: (MOVBstorezeroidx ptr (MOVDconst [c]) mem)
 12420  	// cond:
 12421  	// result: (MOVBstorezero [c] ptr mem)
 12422  	for {
 12423  		mem := v.Args[2]
 12424  		ptr := v.Args[0]
 12425  		v_1 := v.Args[1]
 12426  		if v_1.Op != OpARM64MOVDconst {
 12427  			break
 12428  		}
 12429  		c := v_1.AuxInt
 12430  		v.reset(OpARM64MOVBstorezero)
 12431  		v.AuxInt = c
 12432  		v.AddArg(ptr)
 12433  		v.AddArg(mem)
 12434  		return true
 12435  	}
 12436  	// match: (MOVBstorezeroidx (MOVDconst [c]) idx mem)
 12437  	// cond:
 12438  	// result: (MOVBstorezero [c] idx mem)
 12439  	for {
 12440  		mem := v.Args[2]
 12441  		v_0 := v.Args[0]
 12442  		if v_0.Op != OpARM64MOVDconst {
 12443  			break
 12444  		}
 12445  		c := v_0.AuxInt
 12446  		idx := v.Args[1]
 12447  		v.reset(OpARM64MOVBstorezero)
 12448  		v.AuxInt = c
 12449  		v.AddArg(idx)
 12450  		v.AddArg(mem)
 12451  		return true
 12452  	}
 12453  	// match: (MOVBstorezeroidx ptr (ADDconst [1] idx) x:(MOVBstorezeroidx ptr idx mem))
 12454  	// cond: x.Uses == 1 && clobber(x)
 12455  	// result: (MOVHstorezeroidx ptr idx mem)
 12456  	for {
 12457  		_ = v.Args[2]
 12458  		ptr := v.Args[0]
 12459  		v_1 := v.Args[1]
 12460  		if v_1.Op != OpARM64ADDconst {
 12461  			break
 12462  		}
 12463  		if v_1.AuxInt != 1 {
 12464  			break
 12465  		}
 12466  		idx := v_1.Args[0]
 12467  		x := v.Args[2]
 12468  		if x.Op != OpARM64MOVBstorezeroidx {
 12469  			break
 12470  		}
 12471  		mem := x.Args[2]
 12472  		if ptr != x.Args[0] {
 12473  			break
 12474  		}
 12475  		if idx != x.Args[1] {
 12476  			break
 12477  		}
 12478  		if !(x.Uses == 1 && clobber(x)) {
 12479  			break
 12480  		}
 12481  		v.reset(OpARM64MOVHstorezeroidx)
 12482  		v.AddArg(ptr)
 12483  		v.AddArg(idx)
 12484  		v.AddArg(mem)
 12485  		return true
 12486  	}
 12487  	return false
 12488  }
 12489  func rewriteValueARM64_OpARM64MOVDload_0(v *Value) bool {
 12490  	b := v.Block
 12491  	config := b.Func.Config
 12492  	// match: (MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr val _))
 12493  	// cond:
 12494  	// result: (FMOVDfpgp val)
 12495  	for {
 12496  		off := v.AuxInt
 12497  		sym := v.Aux
 12498  		_ = v.Args[1]
 12499  		ptr := v.Args[0]
 12500  		v_1 := v.Args[1]
 12501  		if v_1.Op != OpARM64FMOVDstore {
 12502  			break
 12503  		}
 12504  		if v_1.AuxInt != off {
 12505  			break
 12506  		}
 12507  		if v_1.Aux != sym {
 12508  			break
 12509  		}
 12510  		_ = v_1.Args[2]
 12511  		if ptr != v_1.Args[0] {
 12512  			break
 12513  		}
 12514  		val := v_1.Args[1]
 12515  		v.reset(OpARM64FMOVDfpgp)
 12516  		v.AddArg(val)
 12517  		return true
 12518  	}
 12519  	// match: (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem)
 12520  	// cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
 12521  	// result: (MOVDload [off1+off2] {sym} ptr mem)
 12522  	for {
 12523  		off1 := v.AuxInt
 12524  		sym := v.Aux
 12525  		mem := v.Args[1]
 12526  		v_0 := v.Args[0]
 12527  		if v_0.Op != OpARM64ADDconst {
 12528  			break
 12529  		}
 12530  		off2 := v_0.AuxInt
 12531  		ptr := v_0.Args[0]
 12532  		if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
 12533  			break
 12534  		}
 12535  		v.reset(OpARM64MOVDload)
 12536  		v.AuxInt = off1 + off2
 12537  		v.Aux = sym
 12538  		v.AddArg(ptr)
 12539  		v.AddArg(mem)
 12540  		return true
 12541  	}
 12542  	// match: (MOVDload [off] {sym} (ADD ptr idx) mem)
 12543  	// cond: off == 0 && sym == nil
 12544  	// result: (MOVDloadidx ptr idx mem)
 12545  	for {
 12546  		off := v.AuxInt
 12547  		sym := v.Aux
 12548  		mem := v.Args[1]
 12549  		v_0 := v.Args[0]
 12550  		if v_0.Op != OpARM64ADD {
 12551  			break
 12552  		}
 12553  		idx := v_0.Args[1]
 12554  		ptr := v_0.Args[0]
 12555  		if !(off == 0 && sym == nil) {
 12556  			break
 12557  		}
 12558  		v.reset(OpARM64MOVDloadidx)
 12559  		v.AddArg(ptr)
 12560  		v.AddArg(idx)
 12561  		v.AddArg(mem)
 12562  		return true
 12563  	}
 12564  	// match: (MOVDload [off] {sym} (ADDshiftLL [3] ptr idx) mem)
 12565  	// cond: off == 0 && sym == nil
 12566  	// result: (MOVDloadidx8 ptr idx mem)
 12567  	for {
 12568  		off := v.AuxInt
 12569  		sym := v.Aux
 12570  		mem := v.Args[1]
 12571  		v_0 := v.Args[0]
 12572  		if v_0.Op != OpARM64ADDshiftLL {
 12573  			break
 12574  		}
 12575  		if v_0.AuxInt != 3 {
 12576  			break
 12577  		}
 12578  		idx := v_0.Args[1]
 12579  		ptr := v_0.Args[0]
 12580  		if !(off == 0 && sym == nil) {
 12581  			break
 12582  		}
 12583  		v.reset(OpARM64MOVDloadidx8)
 12584  		v.AddArg(ptr)
 12585  		v.AddArg(idx)
 12586  		v.AddArg(mem)
 12587  		return true
 12588  	}
 12589  	// match: (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
 12590  	// cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
 12591  	// result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
 12592  	for {
 12593  		off1 := v.AuxInt
 12594  		sym1 := v.Aux
 12595  		mem := v.Args[1]
 12596  		v_0 := v.Args[0]
 12597  		if v_0.Op != OpARM64MOVDaddr {
 12598  			break
 12599  		}
 12600  		off2 := v_0.AuxInt
 12601  		sym2 := v_0.Aux
 12602  		ptr := v_0.Args[0]
 12603  		if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
 12604  			break
 12605  		}
 12606  		v.reset(OpARM64MOVDload)
 12607  		v.AuxInt = off1 + off2
 12608  		v.Aux = mergeSym(sym1, sym2)
 12609  		v.AddArg(ptr)
 12610  		v.AddArg(mem)
 12611  		return true
 12612  	}
 12613  	// match: (MOVDload [off] {sym} ptr (MOVDstorezero [off2] {sym2} ptr2 _))
 12614  	// cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
 12615  	// result: (MOVDconst [0])
 12616  	for {
 12617  		off := v.AuxInt
 12618  		sym := v.Aux
 12619  		_ = v.Args[1]
 12620  		ptr := v.Args[0]
 12621  		v_1 := v.Args[1]
 12622  		if v_1.Op != OpARM64MOVDstorezero {
 12623  			break
 12624  		}
 12625  		off2 := v_1.AuxInt
 12626  		sym2 := v_1.Aux
 12627  		_ = v_1.Args[1]
 12628  		ptr2 := v_1.Args[0]
 12629  		if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
 12630  			break
 12631  		}
 12632  		v.reset(OpARM64MOVDconst)
 12633  		v.AuxInt = 0
 12634  		return true
 12635  	}
 12636  	// match: (MOVDload [off] {sym} (SB) _)
 12637  	// cond: symIsRO(sym)
 12638  	// result: (MOVDconst [int64(read64(sym, off, config.BigEndian))])
 12639  	for {
 12640  		off := v.AuxInt
 12641  		sym := v.Aux
 12642  		_ = v.Args[1]
 12643  		v_0 := v.Args[0]
 12644  		if v_0.Op != OpSB {
 12645  			break
 12646  		}
 12647  		if !(symIsRO(sym)) {
 12648  			break
 12649  		}
 12650  		v.reset(OpARM64MOVDconst)
 12651  		v.AuxInt = int64(read64(sym, off, config.BigEndian))
 12652  		return true
 12653  	}
 12654  	return false
 12655  }
 12656  func rewriteValueARM64_OpARM64MOVDloadidx_0(v *Value) bool {
 12657  	// match: (MOVDloadidx ptr (MOVDconst [c]) mem)
 12658  	// cond:
 12659  	// result: (MOVDload [c] ptr mem)
 12660  	for {
 12661  		mem := v.Args[2]
 12662  		ptr := v.Args[0]
 12663  		v_1 := v.Args[1]
 12664  		if v_1.Op != OpARM64MOVDconst {
 12665  			break
 12666  		}
 12667  		c := v_1.AuxInt
 12668  		v.reset(OpARM64MOVDload)
 12669  		v.AuxInt = c
 12670  		v.AddArg(ptr)
 12671  		v.AddArg(mem)
 12672  		return true
 12673  	}
 12674  	// match: (MOVDloadidx (MOVDconst [c]) ptr mem)
 12675  	// cond:
 12676  	// result: (MOVDload [c] ptr mem)
 12677  	for {
 12678  		mem := v.Args[2]
 12679  		v_0 := v.Args[0]
 12680  		if v_0.Op != OpARM64MOVDconst {
 12681  			break
 12682  		}
 12683  		c := v_0.AuxInt
 12684  		ptr := v.Args[1]
 12685  		v.reset(OpARM64MOVDload)
 12686  		v.AuxInt = c
 12687  		v.AddArg(ptr)
 12688  		v.AddArg(mem)
 12689  		return true
 12690  	}
 12691  	// match: (MOVDloadidx ptr (SLLconst [3] idx) mem)
 12692  	// cond:
 12693  	// result: (MOVDloadidx8 ptr idx mem)
 12694  	for {
 12695  		mem := v.Args[2]
 12696  		ptr := v.Args[0]
 12697  		v_1 := v.Args[1]
 12698  		if v_1.Op != OpARM64SLLconst {
 12699  			break
 12700  		}
 12701  		if v_1.AuxInt != 3 {
 12702  			break
 12703  		}
 12704  		idx := v_1.Args[0]
 12705  		v.reset(OpARM64MOVDloadidx8)
 12706  		v.AddArg(ptr)
 12707  		v.AddArg(idx)
 12708  		v.AddArg(mem)
 12709  		return true
 12710  	}
 12711  	// match: (MOVDloadidx (SLLconst [3] idx) ptr mem)
 12712  	// cond:
 12713  	// result: (MOVDloadidx8 ptr idx mem)
 12714  	for {
 12715  		mem := v.Args[2]
 12716  		v_0 := v.Args[0]
 12717  		if v_0.Op != OpARM64SLLconst {
 12718  			break
 12719  		}
 12720  		if v_0.AuxInt != 3 {
 12721  			break
 12722  		}
 12723  		idx := v_0.Args[0]
 12724  		ptr := v.Args[1]
 12725  		v.reset(OpARM64MOVDloadidx8)
 12726  		v.AddArg(ptr)
 12727  		v.AddArg(idx)
 12728  		v.AddArg(mem)
 12729  		return true
 12730  	}
 12731  	// match: (MOVDloadidx ptr idx (MOVDstorezeroidx ptr2 idx2 _))
 12732  	// cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2))
 12733  	// result: (MOVDconst [0])
 12734  	for {
 12735  		_ = v.Args[2]
 12736  		ptr := v.Args[0]
 12737  		idx := v.Args[1]
 12738  		v_2 := v.Args[2]
 12739  		if v_2.Op != OpARM64MOVDstorezeroidx {
 12740  			break
 12741  		}
 12742  		_ = v_2.Args[2]
 12743  		ptr2 := v_2.Args[0]
 12744  		idx2 := v_2.Args[1]
 12745  		if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) {
 12746  			break
 12747  		}
 12748  		v.reset(OpARM64MOVDconst)
 12749  		v.AuxInt = 0
 12750  		return true
 12751  	}
 12752  	return false
 12753  }
 12754  func rewriteValueARM64_OpARM64MOVDloadidx8_0(v *Value) bool {
 12755  	// match: (MOVDloadidx8 ptr (MOVDconst [c]) mem)
 12756  	// cond:
 12757  	// result: (MOVDload [c<<3] ptr mem)
 12758  	for {
 12759  		mem := v.Args[2]
 12760  		ptr := v.Args[0]
 12761  		v_1 := v.Args[1]
 12762  		if v_1.Op != OpARM64MOVDconst {
 12763  			break
 12764  		}
 12765  		c := v_1.AuxInt
 12766  		v.reset(OpARM64MOVDload)
 12767  		v.AuxInt = c << 3
 12768  		v.AddArg(ptr)
 12769  		v.AddArg(mem)
 12770  		return true
 12771  	}
 12772  	// match: (MOVDloadidx8 ptr idx (MOVDstorezeroidx8 ptr2 idx2 _))
 12773  	// cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)
 12774  	// result: (MOVDconst [0])
 12775  	for {
 12776  		_ = v.Args[2]
 12777  		ptr := v.Args[0]
 12778  		idx := v.Args[1]
 12779  		v_2 := v.Args[2]
 12780  		if v_2.Op != OpARM64MOVDstorezeroidx8 {
 12781  			break
 12782  		}
 12783  		_ = v_2.Args[2]
 12784  		ptr2 := v_2.Args[0]
 12785  		idx2 := v_2.Args[1]
 12786  		if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) {
 12787  			break
 12788  		}
 12789  		v.reset(OpARM64MOVDconst)
 12790  		v.AuxInt = 0
 12791  		return true
 12792  	}
 12793  	return false
 12794  }
 12795  func rewriteValueARM64_OpARM64MOVDreg_0(v *Value) bool {
 12796  	// match: (MOVDreg x)
 12797  	// cond: x.Uses == 1
 12798  	// result: (MOVDnop x)
 12799  	for {
 12800  		x := v.Args[0]
 12801  		if !(x.Uses == 1) {
 12802  			break
 12803  		}
 12804  		v.reset(OpARM64MOVDnop)
 12805  		v.AddArg(x)
 12806  		return true
 12807  	}
 12808  	// match: (MOVDreg (MOVDconst [c]))
 12809  	// cond:
 12810  	// result: (MOVDconst [c])
 12811  	for {
 12812  		v_0 := v.Args[0]
 12813  		if v_0.Op != OpARM64MOVDconst {
 12814  			break
 12815  		}
 12816  		c := v_0.AuxInt
 12817  		v.reset(OpARM64MOVDconst)
 12818  		v.AuxInt = c
 12819  		return true
 12820  	}
 12821  	return false
 12822  }
 12823  func rewriteValueARM64_OpARM64MOVDstore_0(v *Value) bool {
 12824  	b := v.Block
 12825  	config := b.Func.Config
 12826  	// match: (MOVDstore [off] {sym} ptr (FMOVDfpgp val) mem)
 12827  	// cond:
 12828  	// result: (FMOVDstore [off] {sym} ptr val mem)
 12829  	for {
 12830  		off := v.AuxInt
 12831  		sym := v.Aux
 12832  		mem := v.Args[2]
 12833  		ptr := v.Args[0]
 12834  		v_1 := v.Args[1]
 12835  		if v_1.Op != OpARM64FMOVDfpgp {
 12836  			break
 12837  		}
 12838  		val := v_1.Args[0]
 12839  		v.reset(OpARM64FMOVDstore)
 12840  		v.AuxInt = off
 12841  		v.Aux = sym
 12842  		v.AddArg(ptr)
 12843  		v.AddArg(val)
 12844  		v.AddArg(mem)
 12845  		return true
 12846  	}
 12847  	// match: (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem)
 12848  	// cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
 12849  	// result: (MOVDstore [off1+off2] {sym} ptr val mem)
 12850  	for {
 12851  		off1 := v.AuxInt
 12852  		sym := v.Aux
 12853  		mem := v.Args[2]
 12854  		v_0 := v.Args[0]
 12855  		if v_0.Op != OpARM64ADDconst {
 12856  			break
 12857  		}
 12858  		off2 := v_0.AuxInt
 12859  		ptr := v_0.Args[0]
 12860  		val := v.Args[1]
 12861  		if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
 12862  			break
 12863  		}
 12864  		v.reset(OpARM64MOVDstore)
 12865  		v.AuxInt = off1 + off2
 12866  		v.Aux = sym
 12867  		v.AddArg(ptr)
 12868  		v.AddArg(val)
 12869  		v.AddArg(mem)
 12870  		return true
 12871  	}
 12872  	// match: (MOVDstore [off] {sym} (ADD ptr idx) val mem)
 12873  	// cond: off == 0 && sym == nil
 12874  	// result: (MOVDstoreidx ptr idx val mem)
 12875  	for {
 12876  		off := v.AuxInt
 12877  		sym := v.Aux
 12878  		mem := v.Args[2]
 12879  		v_0 := v.Args[0]
 12880  		if v_0.Op != OpARM64ADD {
 12881  			break
 12882  		}
 12883  		idx := v_0.Args[1]
 12884  		ptr := v_0.Args[0]
 12885  		val := v.Args[1]
 12886  		if !(off == 0 && sym == nil) {
 12887  			break
 12888  		}
 12889  		v.reset(OpARM64MOVDstoreidx)
 12890  		v.AddArg(ptr)
 12891  		v.AddArg(idx)
 12892  		v.AddArg(val)
 12893  		v.AddArg(mem)
 12894  		return true
 12895  	}
 12896  	// match: (MOVDstore [off] {sym} (ADDshiftLL [3] ptr idx) val mem)
 12897  	// cond: off == 0 && sym == nil
 12898  	// result: (MOVDstoreidx8 ptr idx val mem)
 12899  	for {
 12900  		off := v.AuxInt
 12901  		sym := v.Aux
 12902  		mem := v.Args[2]
 12903  		v_0 := v.Args[0]
 12904  		if v_0.Op != OpARM64ADDshiftLL {
 12905  			break
 12906  		}
 12907  		if v_0.AuxInt != 3 {
 12908  			break
 12909  		}
 12910  		idx := v_0.Args[1]
 12911  		ptr := v_0.Args[0]
 12912  		val := v.Args[1]
 12913  		if !(off == 0 && sym == nil) {
 12914  			break
 12915  		}
 12916  		v.reset(OpARM64MOVDstoreidx8)
 12917  		v.AddArg(ptr)
 12918  		v.AddArg(idx)
 12919  		v.AddArg(val)
 12920  		v.AddArg(mem)
 12921  		return true
 12922  	}
 12923  	// match: (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
 12924  	// cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
 12925  	// result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
 12926  	for {
 12927  		off1 := v.AuxInt
 12928  		sym1 := v.Aux
 12929  		mem := v.Args[2]
 12930  		v_0 := v.Args[0]
 12931  		if v_0.Op != OpARM64MOVDaddr {
 12932  			break
 12933  		}
 12934  		off2 := v_0.AuxInt
 12935  		sym2 := v_0.Aux
 12936  		ptr := v_0.Args[0]
 12937  		val := v.Args[1]
 12938  		if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
 12939  			break
 12940  		}
 12941  		v.reset(OpARM64MOVDstore)
 12942  		v.AuxInt = off1 + off2
 12943  		v.Aux = mergeSym(sym1, sym2)
 12944  		v.AddArg(ptr)
 12945  		v.AddArg(val)
 12946  		v.AddArg(mem)
 12947  		return true
 12948  	}
 12949  	// match: (MOVDstore [off] {sym} ptr (MOVDconst [0]) mem)
 12950  	// cond:
 12951  	// result: (MOVDstorezero [off] {sym} ptr mem)
 12952  	for {
 12953  		off := v.AuxInt
 12954  		sym := v.Aux
 12955  		mem := v.Args[2]
 12956  		ptr := v.Args[0]
 12957  		v_1 := v.Args[1]
 12958  		if v_1.Op != OpARM64MOVDconst {
 12959  			break
 12960  		}
 12961  		if v_1.AuxInt != 0 {
 12962  			break
 12963  		}
 12964  		v.reset(OpARM64MOVDstorezero)
 12965  		v.AuxInt = off
 12966  		v.Aux = sym
 12967  		v.AddArg(ptr)
 12968  		v.AddArg(mem)
 12969  		return true
 12970  	}
 12971  	return false
 12972  }
 12973  func rewriteValueARM64_OpARM64MOVDstoreidx_0(v *Value) bool {
 12974  	// match: (MOVDstoreidx ptr (MOVDconst [c]) val mem)
 12975  	// cond:
 12976  	// result: (MOVDstore [c] ptr val mem)
 12977  	for {
 12978  		mem := v.Args[3]
 12979  		ptr := v.Args[0]
 12980  		v_1 := v.Args[1]
 12981  		if v_1.Op != OpARM64MOVDconst {
 12982  			break
 12983  		}
 12984  		c := v_1.AuxInt
 12985  		val := v.Args[2]
 12986  		v.reset(OpARM64MOVDstore)
 12987  		v.AuxInt = c
 12988  		v.AddArg(ptr)
 12989  		v.AddArg(val)
 12990  		v.AddArg(mem)
 12991  		return true
 12992  	}
 12993  	// match: (MOVDstoreidx (MOVDconst [c]) idx val mem)
 12994  	// cond:
 12995  	// result: (MOVDstore [c] idx val mem)
 12996  	for {
 12997  		mem := v.Args[3]
 12998  		v_0 := v.Args[0]
 12999  		if v_0.Op != OpARM64MOVDconst {
 13000  			break
 13001  		}
 13002  		c := v_0.AuxInt
 13003  		idx := v.Args[1]
 13004  		val := v.Args[2]
 13005  		v.reset(OpARM64MOVDstore)
 13006  		v.AuxInt = c
 13007  		v.AddArg(idx)
 13008  		v.AddArg(val)
 13009  		v.AddArg(mem)
 13010  		return true
 13011  	}
 13012  	// match: (MOVDstoreidx ptr (SLLconst [3] idx) val mem)
 13013  	// cond:
 13014  	// result: (MOVDstoreidx8 ptr idx val mem)
 13015  	for {
 13016  		mem := v.Args[3]
 13017  		ptr := v.Args[0]
 13018  		v_1 := v.Args[1]
 13019  		if v_1.Op != OpARM64SLLconst {
 13020  			break
 13021  		}
 13022  		if v_1.AuxInt != 3 {
 13023  			break
 13024  		}
 13025  		idx := v_1.Args[0]
 13026  		val := v.Args[2]
 13027  		v.reset(OpARM64MOVDstoreidx8)
 13028  		v.AddArg(ptr)
 13029  		v.AddArg(idx)
 13030  		v.AddArg(val)
 13031  		v.AddArg(mem)
 13032  		return true
 13033  	}
 13034  	// match: (MOVDstoreidx (SLLconst [3] idx) ptr val mem)
 13035  	// cond:
 13036  	// result: (MOVDstoreidx8 ptr idx val mem)
 13037  	for {
 13038  		mem := v.Args[3]
 13039  		v_0 := v.Args[0]
 13040  		if v_0.Op != OpARM64SLLconst {
 13041  			break
 13042  		}
 13043  		if v_0.AuxInt != 3 {
 13044  			break
 13045  		}
 13046  		idx := v_0.Args[0]
 13047  		ptr := v.Args[1]
 13048  		val := v.Args[2]
 13049  		v.reset(OpARM64MOVDstoreidx8)
 13050  		v.AddArg(ptr)
 13051  		v.AddArg(idx)
 13052  		v.AddArg(val)
 13053  		v.AddArg(mem)
 13054  		return true
 13055  	}
 13056  	// match: (MOVDstoreidx ptr idx (MOVDconst [0]) mem)
 13057  	// cond:
 13058  	// result: (MOVDstorezeroidx ptr idx mem)
 13059  	for {
 13060  		mem := v.Args[3]
 13061  		ptr := v.Args[0]
 13062  		idx := v.Args[1]
 13063  		v_2 := v.Args[2]
 13064  		if v_2.Op != OpARM64MOVDconst {
 13065  			break
 13066  		}
 13067  		if v_2.AuxInt != 0 {
 13068  			break
 13069  		}
 13070  		v.reset(OpARM64MOVDstorezeroidx)
 13071  		v.AddArg(ptr)
 13072  		v.AddArg(idx)
 13073  		v.AddArg(mem)
 13074  		return true
 13075  	}
 13076  	return false
 13077  }
 13078  func rewriteValueARM64_OpARM64MOVDstoreidx8_0(v *Value) bool {
 13079  	// match: (MOVDstoreidx8 ptr (MOVDconst [c]) val mem)
 13080  	// cond:
 13081  	// result: (MOVDstore [c<<3] ptr val mem)
 13082  	for {
 13083  		mem := v.Args[3]
 13084  		ptr := v.Args[0]
 13085  		v_1 := v.Args[1]
 13086  		if v_1.Op != OpARM64MOVDconst {
 13087  			break
 13088  		}
 13089  		c := v_1.AuxInt
 13090  		val := v.Args[2]
 13091  		v.reset(OpARM64MOVDstore)
 13092  		v.AuxInt = c << 3
 13093  		v.AddArg(ptr)
 13094  		v.AddArg(val)
 13095  		v.AddArg(mem)
 13096  		return true
 13097  	}
 13098  	// match: (MOVDstoreidx8 ptr idx (MOVDconst [0]) mem)
 13099  	// cond:
 13100  	// result: (MOVDstorezeroidx8 ptr idx mem)
 13101  	for {
 13102  		mem := v.Args[3]
 13103  		ptr := v.Args[0]
 13104  		idx := v.Args[1]
 13105  		v_2 := v.Args[2]
 13106  		if v_2.Op != OpARM64MOVDconst {
 13107  			break
 13108  		}
 13109  		if v_2.AuxInt != 0 {
 13110  			break
 13111  		}
 13112  		v.reset(OpARM64MOVDstorezeroidx8)
 13113  		v.AddArg(ptr)
 13114  		v.AddArg(idx)
 13115  		v.AddArg(mem)
 13116  		return true
 13117  	}
 13118  	return false
 13119  }
 13120  func rewriteValueARM64_OpARM64MOVDstorezero_0(v *Value) bool {
 13121  	b := v.Block
 13122  	config := b.Func.Config
 13123  	// match: (MOVDstorezero [off1] {sym} (ADDconst [off2] ptr) mem)
 13124  	// cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
 13125  	// result: (MOVDstorezero [off1+off2] {sym} ptr mem)
 13126  	for {
 13127  		off1 := v.AuxInt
 13128  		sym := v.Aux
 13129  		mem := v.Args[1]
 13130  		v_0 := v.Args[0]
 13131  		if v_0.Op != OpARM64ADDconst {
 13132  			break
 13133  		}
 13134  		off2 := v_0.AuxInt
 13135  		ptr := v_0.Args[0]
 13136  		if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
 13137  			break
 13138  		}
 13139  		v.reset(OpARM64MOVDstorezero)
 13140  		v.AuxInt = off1 + off2
 13141  		v.Aux = sym
 13142  		v.AddArg(ptr)
 13143  		v.AddArg(mem)
 13144  		return true
 13145  	}
 13146  	// match: (MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
 13147  	// cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
 13148  	// result: (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
 13149  	for {
 13150  		off1 := v.AuxInt
 13151  		sym1 := v.Aux
 13152  		mem := v.Args[1]
 13153  		v_0 := v.Args[0]
 13154  		if v_0.Op != OpARM64MOVDaddr {
 13155  			break
 13156  		}
 13157  		off2 := v_0.AuxInt
 13158  		sym2 := v_0.Aux
 13159  		ptr := v_0.Args[0]
 13160  		if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
 13161  			break
 13162  		}
 13163  		v.reset(OpARM64MOVDstorezero)
 13164  		v.AuxInt = off1 + off2
 13165  		v.Aux = mergeSym(sym1, sym2)
 13166  		v.AddArg(ptr)
 13167  		v.AddArg(mem)
 13168  		return true
 13169  	}
 13170  	// match: (MOVDstorezero [off] {sym} (ADD ptr idx) mem)
 13171  	// cond: off == 0 && sym == nil
 13172  	// result: (MOVDstorezeroidx ptr idx mem)
 13173  	for {
 13174  		off := v.AuxInt
 13175  		sym := v.Aux
 13176  		mem := v.Args[1]
 13177  		v_0 := v.Args[0]
 13178  		if v_0.Op != OpARM64ADD {
 13179  			break
 13180  		}
 13181  		idx := v_0.Args[1]
 13182  		ptr := v_0.Args[0]
 13183  		if !(off == 0 && sym == nil) {
 13184  			break
 13185  		}
 13186  		v.reset(OpARM64MOVDstorezeroidx)
 13187  		v.AddArg(ptr)
 13188  		v.AddArg(idx)
 13189  		v.AddArg(mem)
 13190  		return true
 13191  	}
 13192  	// match: (MOVDstorezero [off] {sym} (ADDshiftLL [3] ptr idx) mem)
 13193  	// cond: off == 0 && sym == nil
 13194  	// result: (MOVDstorezeroidx8 ptr idx mem)
 13195  	for {
 13196  		off := v.AuxInt
 13197  		sym := v.Aux
 13198  		mem := v.Args[1]
 13199  		v_0 := v.Args[0]
 13200  		if v_0.Op != OpARM64ADDshiftLL {
 13201  			break
 13202  		}
 13203  		if v_0.AuxInt != 3 {
 13204  			break
 13205  		}
 13206  		idx := v_0.Args[1]
 13207  		ptr := v_0.Args[0]
 13208  		if !(off == 0 && sym == nil) {
 13209  			break
 13210  		}
 13211  		v.reset(OpARM64MOVDstorezeroidx8)
 13212  		v.AddArg(ptr)
 13213  		v.AddArg(idx)
 13214  		v.AddArg(mem)
 13215  		return true
 13216  	}
 13217  	// match: (MOVDstorezero [i] {s} ptr0 x:(MOVDstorezero [j] {s} ptr1 mem))
 13218  	// cond: x.Uses == 1 && areAdjacentOffsets(i,j,8) && is32Bit(min(i,j)) && isSamePtr(ptr0, ptr1) && clobber(x)
 13219  	// result: (MOVQstorezero [min(i,j)] {s} ptr0 mem)
 13220  	for {
 13221  		i := v.AuxInt
 13222  		s := v.Aux
 13223  		_ = v.Args[1]
 13224  		ptr0 := v.Args[0]
 13225  		x := v.Args[1]
 13226  		if x.Op != OpARM64MOVDstorezero {
 13227  			break
 13228  		}
 13229  		j := x.AuxInt
 13230  		if x.Aux != s {
 13231  			break
 13232  		}
 13233  		mem := x.Args[1]
 13234  		ptr1 := x.Args[0]
 13235  		if !(x.Uses == 1 && areAdjacentOffsets(i, j, 8) && is32Bit(min(i, j)) && isSamePtr(ptr0, ptr1) && clobber(x)) {
 13236  			break
 13237  		}
 13238  		v.reset(OpARM64MOVQstorezero)
 13239  		v.AuxInt = min(i, j)
 13240  		v.Aux = s
 13241  		v.AddArg(ptr0)
 13242  		v.AddArg(mem)
 13243  		return true
 13244  	}
 13245  	// match: (MOVDstorezero [8] {s} p0:(ADD ptr0 idx0) x:(MOVDstorezeroidx ptr1 idx1 mem))
 13246  	// cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)
 13247  	// result: (MOVQstorezero [0] {s} p0 mem)
 13248  	for {
 13249  		if v.AuxInt != 8 {
 13250  			break
 13251  		}
 13252  		s := v.Aux
 13253  		_ = v.Args[1]
 13254  		p0 := v.Args[0]
 13255  		if p0.Op != OpARM64ADD {
 13256  			break
 13257  		}
 13258  		idx0 := p0.Args[1]
 13259  		ptr0 := p0.Args[0]
 13260  		x := v.Args[1]
 13261  		if x.Op != OpARM64MOVDstorezeroidx {
 13262  			break
 13263  		}
 13264  		mem := x.Args[2]
 13265  		ptr1 := x.Args[0]
 13266  		idx1 := x.Args[1]
 13267  		if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) {
 13268  			break
 13269  		}
 13270  		v.reset(OpARM64MOVQstorezero)
 13271  		v.AuxInt = 0
 13272  		v.Aux = s
 13273  		v.AddArg(p0)
 13274  		v.AddArg(mem)
 13275  		return true
 13276  	}
 13277  	// match: (MOVDstorezero [8] {s} p0:(ADDshiftLL [3] ptr0 idx0) x:(MOVDstorezeroidx8 ptr1 idx1 mem))
 13278  	// cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)
 13279  	// result: (MOVQstorezero [0] {s} p0 mem)
 13280  	for {
 13281  		if v.AuxInt != 8 {
 13282  			break
 13283  		}
 13284  		s := v.Aux
 13285  		_ = v.Args[1]
 13286  		p0 := v.Args[0]
 13287  		if p0.Op != OpARM64ADDshiftLL {
 13288  			break
 13289  		}
 13290  		if p0.AuxInt != 3 {
 13291  			break
 13292  		}
 13293  		idx0 := p0.Args[1]
 13294  		ptr0 := p0.Args[0]
 13295  		x := v.Args[1]
 13296  		if x.Op != OpARM64MOVDstorezeroidx8 {
 13297  			break
 13298  		}
 13299  		mem := x.Args[2]
 13300  		ptr1 := x.Args[0]
 13301  		idx1 := x.Args[1]
 13302  		if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) {
 13303  			break
 13304  		}
 13305  		v.reset(OpARM64MOVQstorezero)
 13306  		v.AuxInt = 0
 13307  		v.Aux = s
 13308  		v.AddArg(p0)
 13309  		v.AddArg(mem)
 13310  		return true
 13311  	}
 13312  	return false
 13313  }
 13314  func rewriteValueARM64_OpARM64MOVDstorezeroidx_0(v *Value) bool {
 13315  	// match: (MOVDstorezeroidx ptr (MOVDconst [c]) mem)
 13316  	// cond:
 13317  	// result: (MOVDstorezero [c] ptr mem)
 13318  	for {
 13319  		mem := v.Args[2]
 13320  		ptr := v.Args[0]
 13321  		v_1 := v.Args[1]
 13322  		if v_1.Op != OpARM64MOVDconst {
 13323  			break
 13324  		}
 13325  		c := v_1.AuxInt
 13326  		v.reset(OpARM64MOVDstorezero)
 13327  		v.AuxInt = c
 13328  		v.AddArg(ptr)
 13329  		v.AddArg(mem)
 13330  		return true
 13331  	}
 13332  	// match: (MOVDstorezeroidx (MOVDconst [c]) idx mem)
 13333  	// cond:
 13334  	// result: (MOVDstorezero [c] idx mem)
 13335  	for {
 13336  		mem := v.Args[2]
 13337  		v_0 := v.Args[0]
 13338  		if v_0.Op != OpARM64MOVDconst {
 13339  			break
 13340  		}
 13341  		c := v_0.AuxInt
 13342  		idx := v.Args[1]
 13343  		v.reset(OpARM64MOVDstorezero)
 13344  		v.AuxInt = c
 13345  		v.AddArg(idx)
 13346  		v.AddArg(mem)
 13347  		return true
 13348  	}
 13349  	// match: (MOVDstorezeroidx ptr (SLLconst [3] idx) mem)
 13350  	// cond:
 13351  	// result: (MOVDstorezeroidx8 ptr idx mem)
 13352  	for {
 13353  		mem := v.Args[2]
 13354  		ptr := v.Args[0]
 13355  		v_1 := v.Args[1]
 13356  		if v_1.Op != OpARM64SLLconst {
 13357  			break
 13358  		}
 13359  		if v_1.AuxInt != 3 {
 13360  			break
 13361  		}
 13362  		idx := v_1.Args[0]
 13363  		v.reset(OpARM64MOVDstorezeroidx8)
 13364  		v.AddArg(ptr)
 13365  		v.AddArg(idx)
 13366  		v.AddArg(mem)
 13367  		return true
 13368  	}
 13369  	// match: (MOVDstorezeroidx (SLLconst [3] idx) ptr mem)
 13370  	// cond:
 13371  	// result: (MOVDstorezeroidx8 ptr idx mem)
 13372  	for {
 13373  		mem := v.Args[2]
 13374  		v_0 := v.Args[0]
 13375  		if v_0.Op != OpARM64SLLconst {
 13376  			break
 13377  		}
 13378  		if v_0.AuxInt != 3 {
 13379  			break
 13380  		}
 13381  		idx := v_0.Args[0]
 13382  		ptr := v.Args[1]
 13383  		v.reset(OpARM64MOVDstorezeroidx8)
 13384  		v.AddArg(ptr)
 13385  		v.AddArg(idx)
 13386  		v.AddArg(mem)
 13387  		return true
 13388  	}
 13389  	return false
 13390  }
 13391  func rewriteValueARM64_OpARM64MOVDstorezeroidx8_0(v *Value) bool {
 13392  	// match: (MOVDstorezeroidx8 ptr (MOVDconst [c]) mem)
 13393  	// cond:
 13394  	// result: (MOVDstorezero [c<<3] ptr mem)
 13395  	for {
 13396  		mem := v.Args[2]
 13397  		ptr := v.Args[0]
 13398  		v_1 := v.Args[1]
 13399  		if v_1.Op != OpARM64MOVDconst {
 13400  			break
 13401  		}
 13402  		c := v_1.AuxInt
 13403  		v.reset(OpARM64MOVDstorezero)
 13404  		v.AuxInt = c << 3
 13405  		v.AddArg(ptr)
 13406  		v.AddArg(mem)
 13407  		return true
 13408