Source file src/cmd/compile/internal/ssa/rewriteAMD64.go

Documentation: cmd/compile/internal/ssa

     1  // Code generated from gen/AMD64.rules; DO NOT EDIT.
     2  // generated with: cd gen; go run *.go
     3  
     4  package ssa
     5  
     6  import "math"
     7  import "cmd/compile/internal/types"
     8  
     9  func rewriteValueAMD64(v *Value) bool {
    10  	switch v.Op {
    11  	case OpAMD64ADCQ:
    12  		return rewriteValueAMD64_OpAMD64ADCQ_0(v)
    13  	case OpAMD64ADCQconst:
    14  		return rewriteValueAMD64_OpAMD64ADCQconst_0(v)
    15  	case OpAMD64ADDL:
    16  		return rewriteValueAMD64_OpAMD64ADDL_0(v) || rewriteValueAMD64_OpAMD64ADDL_10(v) || rewriteValueAMD64_OpAMD64ADDL_20(v)
    17  	case OpAMD64ADDLconst:
    18  		return rewriteValueAMD64_OpAMD64ADDLconst_0(v) || rewriteValueAMD64_OpAMD64ADDLconst_10(v)
    19  	case OpAMD64ADDLconstmodify:
    20  		return rewriteValueAMD64_OpAMD64ADDLconstmodify_0(v)
    21  	case OpAMD64ADDLload:
    22  		return rewriteValueAMD64_OpAMD64ADDLload_0(v)
    23  	case OpAMD64ADDLmodify:
    24  		return rewriteValueAMD64_OpAMD64ADDLmodify_0(v)
    25  	case OpAMD64ADDQ:
    26  		return rewriteValueAMD64_OpAMD64ADDQ_0(v) || rewriteValueAMD64_OpAMD64ADDQ_10(v) || rewriteValueAMD64_OpAMD64ADDQ_20(v)
    27  	case OpAMD64ADDQcarry:
    28  		return rewriteValueAMD64_OpAMD64ADDQcarry_0(v)
    29  	case OpAMD64ADDQconst:
    30  		return rewriteValueAMD64_OpAMD64ADDQconst_0(v) || rewriteValueAMD64_OpAMD64ADDQconst_10(v)
    31  	case OpAMD64ADDQconstmodify:
    32  		return rewriteValueAMD64_OpAMD64ADDQconstmodify_0(v)
    33  	case OpAMD64ADDQload:
    34  		return rewriteValueAMD64_OpAMD64ADDQload_0(v)
    35  	case OpAMD64ADDQmodify:
    36  		return rewriteValueAMD64_OpAMD64ADDQmodify_0(v)
    37  	case OpAMD64ADDSD:
    38  		return rewriteValueAMD64_OpAMD64ADDSD_0(v)
    39  	case OpAMD64ADDSDload:
    40  		return rewriteValueAMD64_OpAMD64ADDSDload_0(v)
    41  	case OpAMD64ADDSS:
    42  		return rewriteValueAMD64_OpAMD64ADDSS_0(v)
    43  	case OpAMD64ADDSSload:
    44  		return rewriteValueAMD64_OpAMD64ADDSSload_0(v)
    45  	case OpAMD64ANDL:
    46  		return rewriteValueAMD64_OpAMD64ANDL_0(v)
    47  	case OpAMD64ANDLconst:
    48  		return rewriteValueAMD64_OpAMD64ANDLconst_0(v)
    49  	case OpAMD64ANDLconstmodify:
    50  		return rewriteValueAMD64_OpAMD64ANDLconstmodify_0(v)
    51  	case OpAMD64ANDLload:
    52  		return rewriteValueAMD64_OpAMD64ANDLload_0(v)
    53  	case OpAMD64ANDLmodify:
    54  		return rewriteValueAMD64_OpAMD64ANDLmodify_0(v)
    55  	case OpAMD64ANDQ:
    56  		return rewriteValueAMD64_OpAMD64ANDQ_0(v)
    57  	case OpAMD64ANDQconst:
    58  		return rewriteValueAMD64_OpAMD64ANDQconst_0(v)
    59  	case OpAMD64ANDQconstmodify:
    60  		return rewriteValueAMD64_OpAMD64ANDQconstmodify_0(v)
    61  	case OpAMD64ANDQload:
    62  		return rewriteValueAMD64_OpAMD64ANDQload_0(v)
    63  	case OpAMD64ANDQmodify:
    64  		return rewriteValueAMD64_OpAMD64ANDQmodify_0(v)
    65  	case OpAMD64BSFQ:
    66  		return rewriteValueAMD64_OpAMD64BSFQ_0(v)
    67  	case OpAMD64BTCLconst:
    68  		return rewriteValueAMD64_OpAMD64BTCLconst_0(v)
    69  	case OpAMD64BTCLconstmodify:
    70  		return rewriteValueAMD64_OpAMD64BTCLconstmodify_0(v)
    71  	case OpAMD64BTCLmodify:
    72  		return rewriteValueAMD64_OpAMD64BTCLmodify_0(v)
    73  	case OpAMD64BTCQconst:
    74  		return rewriteValueAMD64_OpAMD64BTCQconst_0(v)
    75  	case OpAMD64BTCQconstmodify:
    76  		return rewriteValueAMD64_OpAMD64BTCQconstmodify_0(v)
    77  	case OpAMD64BTCQmodify:
    78  		return rewriteValueAMD64_OpAMD64BTCQmodify_0(v)
    79  	case OpAMD64BTLconst:
    80  		return rewriteValueAMD64_OpAMD64BTLconst_0(v)
    81  	case OpAMD64BTQconst:
    82  		return rewriteValueAMD64_OpAMD64BTQconst_0(v)
    83  	case OpAMD64BTRLconst:
    84  		return rewriteValueAMD64_OpAMD64BTRLconst_0(v)
    85  	case OpAMD64BTRLconstmodify:
    86  		return rewriteValueAMD64_OpAMD64BTRLconstmodify_0(v)
    87  	case OpAMD64BTRLmodify:
    88  		return rewriteValueAMD64_OpAMD64BTRLmodify_0(v)
    89  	case OpAMD64BTRQconst:
    90  		return rewriteValueAMD64_OpAMD64BTRQconst_0(v)
    91  	case OpAMD64BTRQconstmodify:
    92  		return rewriteValueAMD64_OpAMD64BTRQconstmodify_0(v)
    93  	case OpAMD64BTRQmodify:
    94  		return rewriteValueAMD64_OpAMD64BTRQmodify_0(v)
    95  	case OpAMD64BTSLconst:
    96  		return rewriteValueAMD64_OpAMD64BTSLconst_0(v)
    97  	case OpAMD64BTSLconstmodify:
    98  		return rewriteValueAMD64_OpAMD64BTSLconstmodify_0(v)
    99  	case OpAMD64BTSLmodify:
   100  		return rewriteValueAMD64_OpAMD64BTSLmodify_0(v)
   101  	case OpAMD64BTSQconst:
   102  		return rewriteValueAMD64_OpAMD64BTSQconst_0(v)
   103  	case OpAMD64BTSQconstmodify:
   104  		return rewriteValueAMD64_OpAMD64BTSQconstmodify_0(v)
   105  	case OpAMD64BTSQmodify:
   106  		return rewriteValueAMD64_OpAMD64BTSQmodify_0(v)
   107  	case OpAMD64CMOVLCC:
   108  		return rewriteValueAMD64_OpAMD64CMOVLCC_0(v)
   109  	case OpAMD64CMOVLCS:
   110  		return rewriteValueAMD64_OpAMD64CMOVLCS_0(v)
   111  	case OpAMD64CMOVLEQ:
   112  		return rewriteValueAMD64_OpAMD64CMOVLEQ_0(v)
   113  	case OpAMD64CMOVLGE:
   114  		return rewriteValueAMD64_OpAMD64CMOVLGE_0(v)
   115  	case OpAMD64CMOVLGT:
   116  		return rewriteValueAMD64_OpAMD64CMOVLGT_0(v)
   117  	case OpAMD64CMOVLHI:
   118  		return rewriteValueAMD64_OpAMD64CMOVLHI_0(v)
   119  	case OpAMD64CMOVLLE:
   120  		return rewriteValueAMD64_OpAMD64CMOVLLE_0(v)
   121  	case OpAMD64CMOVLLS:
   122  		return rewriteValueAMD64_OpAMD64CMOVLLS_0(v)
   123  	case OpAMD64CMOVLLT:
   124  		return rewriteValueAMD64_OpAMD64CMOVLLT_0(v)
   125  	case OpAMD64CMOVLNE:
   126  		return rewriteValueAMD64_OpAMD64CMOVLNE_0(v)
   127  	case OpAMD64CMOVQCC:
   128  		return rewriteValueAMD64_OpAMD64CMOVQCC_0(v)
   129  	case OpAMD64CMOVQCS:
   130  		return rewriteValueAMD64_OpAMD64CMOVQCS_0(v)
   131  	case OpAMD64CMOVQEQ:
   132  		return rewriteValueAMD64_OpAMD64CMOVQEQ_0(v)
   133  	case OpAMD64CMOVQGE:
   134  		return rewriteValueAMD64_OpAMD64CMOVQGE_0(v)
   135  	case OpAMD64CMOVQGT:
   136  		return rewriteValueAMD64_OpAMD64CMOVQGT_0(v)
   137  	case OpAMD64CMOVQHI:
   138  		return rewriteValueAMD64_OpAMD64CMOVQHI_0(v)
   139  	case OpAMD64CMOVQLE:
   140  		return rewriteValueAMD64_OpAMD64CMOVQLE_0(v)
   141  	case OpAMD64CMOVQLS:
   142  		return rewriteValueAMD64_OpAMD64CMOVQLS_0(v)
   143  	case OpAMD64CMOVQLT:
   144  		return rewriteValueAMD64_OpAMD64CMOVQLT_0(v)
   145  	case OpAMD64CMOVQNE:
   146  		return rewriteValueAMD64_OpAMD64CMOVQNE_0(v)
   147  	case OpAMD64CMOVWCC:
   148  		return rewriteValueAMD64_OpAMD64CMOVWCC_0(v)
   149  	case OpAMD64CMOVWCS:
   150  		return rewriteValueAMD64_OpAMD64CMOVWCS_0(v)
   151  	case OpAMD64CMOVWEQ:
   152  		return rewriteValueAMD64_OpAMD64CMOVWEQ_0(v)
   153  	case OpAMD64CMOVWGE:
   154  		return rewriteValueAMD64_OpAMD64CMOVWGE_0(v)
   155  	case OpAMD64CMOVWGT:
   156  		return rewriteValueAMD64_OpAMD64CMOVWGT_0(v)
   157  	case OpAMD64CMOVWHI:
   158  		return rewriteValueAMD64_OpAMD64CMOVWHI_0(v)
   159  	case OpAMD64CMOVWLE:
   160  		return rewriteValueAMD64_OpAMD64CMOVWLE_0(v)
   161  	case OpAMD64CMOVWLS:
   162  		return rewriteValueAMD64_OpAMD64CMOVWLS_0(v)
   163  	case OpAMD64CMOVWLT:
   164  		return rewriteValueAMD64_OpAMD64CMOVWLT_0(v)
   165  	case OpAMD64CMOVWNE:
   166  		return rewriteValueAMD64_OpAMD64CMOVWNE_0(v)
   167  	case OpAMD64CMPB:
   168  		return rewriteValueAMD64_OpAMD64CMPB_0(v)
   169  	case OpAMD64CMPBconst:
   170  		return rewriteValueAMD64_OpAMD64CMPBconst_0(v)
   171  	case OpAMD64CMPBconstload:
   172  		return rewriteValueAMD64_OpAMD64CMPBconstload_0(v)
   173  	case OpAMD64CMPBload:
   174  		return rewriteValueAMD64_OpAMD64CMPBload_0(v)
   175  	case OpAMD64CMPL:
   176  		return rewriteValueAMD64_OpAMD64CMPL_0(v)
   177  	case OpAMD64CMPLconst:
   178  		return rewriteValueAMD64_OpAMD64CMPLconst_0(v) || rewriteValueAMD64_OpAMD64CMPLconst_10(v)
   179  	case OpAMD64CMPLconstload:
   180  		return rewriteValueAMD64_OpAMD64CMPLconstload_0(v)
   181  	case OpAMD64CMPLload:
   182  		return rewriteValueAMD64_OpAMD64CMPLload_0(v)
   183  	case OpAMD64CMPQ:
   184  		return rewriteValueAMD64_OpAMD64CMPQ_0(v)
   185  	case OpAMD64CMPQconst:
   186  		return rewriteValueAMD64_OpAMD64CMPQconst_0(v) || rewriteValueAMD64_OpAMD64CMPQconst_10(v)
   187  	case OpAMD64CMPQconstload:
   188  		return rewriteValueAMD64_OpAMD64CMPQconstload_0(v)
   189  	case OpAMD64CMPQload:
   190  		return rewriteValueAMD64_OpAMD64CMPQload_0(v)
   191  	case OpAMD64CMPW:
   192  		return rewriteValueAMD64_OpAMD64CMPW_0(v)
   193  	case OpAMD64CMPWconst:
   194  		return rewriteValueAMD64_OpAMD64CMPWconst_0(v)
   195  	case OpAMD64CMPWconstload:
   196  		return rewriteValueAMD64_OpAMD64CMPWconstload_0(v)
   197  	case OpAMD64CMPWload:
   198  		return rewriteValueAMD64_OpAMD64CMPWload_0(v)
   199  	case OpAMD64CMPXCHGLlock:
   200  		return rewriteValueAMD64_OpAMD64CMPXCHGLlock_0(v)
   201  	case OpAMD64CMPXCHGQlock:
   202  		return rewriteValueAMD64_OpAMD64CMPXCHGQlock_0(v)
   203  	case OpAMD64DIVSD:
   204  		return rewriteValueAMD64_OpAMD64DIVSD_0(v)
   205  	case OpAMD64DIVSDload:
   206  		return rewriteValueAMD64_OpAMD64DIVSDload_0(v)
   207  	case OpAMD64DIVSS:
   208  		return rewriteValueAMD64_OpAMD64DIVSS_0(v)
   209  	case OpAMD64DIVSSload:
   210  		return rewriteValueAMD64_OpAMD64DIVSSload_0(v)
   211  	case OpAMD64HMULL:
   212  		return rewriteValueAMD64_OpAMD64HMULL_0(v)
   213  	case OpAMD64HMULLU:
   214  		return rewriteValueAMD64_OpAMD64HMULLU_0(v)
   215  	case OpAMD64HMULQ:
   216  		return rewriteValueAMD64_OpAMD64HMULQ_0(v)
   217  	case OpAMD64HMULQU:
   218  		return rewriteValueAMD64_OpAMD64HMULQU_0(v)
   219  	case OpAMD64LEAL:
   220  		return rewriteValueAMD64_OpAMD64LEAL_0(v)
   221  	case OpAMD64LEAL1:
   222  		return rewriteValueAMD64_OpAMD64LEAL1_0(v)
   223  	case OpAMD64LEAL2:
   224  		return rewriteValueAMD64_OpAMD64LEAL2_0(v)
   225  	case OpAMD64LEAL4:
   226  		return rewriteValueAMD64_OpAMD64LEAL4_0(v)
   227  	case OpAMD64LEAL8:
   228  		return rewriteValueAMD64_OpAMD64LEAL8_0(v)
   229  	case OpAMD64LEAQ:
   230  		return rewriteValueAMD64_OpAMD64LEAQ_0(v)
   231  	case OpAMD64LEAQ1:
   232  		return rewriteValueAMD64_OpAMD64LEAQ1_0(v)
   233  	case OpAMD64LEAQ2:
   234  		return rewriteValueAMD64_OpAMD64LEAQ2_0(v)
   235  	case OpAMD64LEAQ4:
   236  		return rewriteValueAMD64_OpAMD64LEAQ4_0(v)
   237  	case OpAMD64LEAQ8:
   238  		return rewriteValueAMD64_OpAMD64LEAQ8_0(v)
   239  	case OpAMD64MOVBQSX:
   240  		return rewriteValueAMD64_OpAMD64MOVBQSX_0(v)
   241  	case OpAMD64MOVBQSXload:
   242  		return rewriteValueAMD64_OpAMD64MOVBQSXload_0(v)
   243  	case OpAMD64MOVBQZX:
   244  		return rewriteValueAMD64_OpAMD64MOVBQZX_0(v)
   245  	case OpAMD64MOVBatomicload:
   246  		return rewriteValueAMD64_OpAMD64MOVBatomicload_0(v)
   247  	case OpAMD64MOVBload:
   248  		return rewriteValueAMD64_OpAMD64MOVBload_0(v)
   249  	case OpAMD64MOVBloadidx1:
   250  		return rewriteValueAMD64_OpAMD64MOVBloadidx1_0(v)
   251  	case OpAMD64MOVBstore:
   252  		return rewriteValueAMD64_OpAMD64MOVBstore_0(v) || rewriteValueAMD64_OpAMD64MOVBstore_10(v) || rewriteValueAMD64_OpAMD64MOVBstore_20(v) || rewriteValueAMD64_OpAMD64MOVBstore_30(v)
   253  	case OpAMD64MOVBstoreconst:
   254  		return rewriteValueAMD64_OpAMD64MOVBstoreconst_0(v)
   255  	case OpAMD64MOVBstoreconstidx1:
   256  		return rewriteValueAMD64_OpAMD64MOVBstoreconstidx1_0(v)
   257  	case OpAMD64MOVBstoreidx1:
   258  		return rewriteValueAMD64_OpAMD64MOVBstoreidx1_0(v) || rewriteValueAMD64_OpAMD64MOVBstoreidx1_10(v)
   259  	case OpAMD64MOVLQSX:
   260  		return rewriteValueAMD64_OpAMD64MOVLQSX_0(v)
   261  	case OpAMD64MOVLQSXload:
   262  		return rewriteValueAMD64_OpAMD64MOVLQSXload_0(v)
   263  	case OpAMD64MOVLQZX:
   264  		return rewriteValueAMD64_OpAMD64MOVLQZX_0(v)
   265  	case OpAMD64MOVLatomicload:
   266  		return rewriteValueAMD64_OpAMD64MOVLatomicload_0(v)
   267  	case OpAMD64MOVLf2i:
   268  		return rewriteValueAMD64_OpAMD64MOVLf2i_0(v)
   269  	case OpAMD64MOVLi2f:
   270  		return rewriteValueAMD64_OpAMD64MOVLi2f_0(v)
   271  	case OpAMD64MOVLload:
   272  		return rewriteValueAMD64_OpAMD64MOVLload_0(v) || rewriteValueAMD64_OpAMD64MOVLload_10(v)
   273  	case OpAMD64MOVLloadidx1:
   274  		return rewriteValueAMD64_OpAMD64MOVLloadidx1_0(v)
   275  	case OpAMD64MOVLloadidx4:
   276  		return rewriteValueAMD64_OpAMD64MOVLloadidx4_0(v)
   277  	case OpAMD64MOVLloadidx8:
   278  		return rewriteValueAMD64_OpAMD64MOVLloadidx8_0(v)
   279  	case OpAMD64MOVLstore:
   280  		return rewriteValueAMD64_OpAMD64MOVLstore_0(v) || rewriteValueAMD64_OpAMD64MOVLstore_10(v) || rewriteValueAMD64_OpAMD64MOVLstore_20(v) || rewriteValueAMD64_OpAMD64MOVLstore_30(v)
   281  	case OpAMD64MOVLstoreconst:
   282  		return rewriteValueAMD64_OpAMD64MOVLstoreconst_0(v)
   283  	case OpAMD64MOVLstoreconstidx1:
   284  		return rewriteValueAMD64_OpAMD64MOVLstoreconstidx1_0(v)
   285  	case OpAMD64MOVLstoreconstidx4:
   286  		return rewriteValueAMD64_OpAMD64MOVLstoreconstidx4_0(v)
   287  	case OpAMD64MOVLstoreidx1:
   288  		return rewriteValueAMD64_OpAMD64MOVLstoreidx1_0(v)
   289  	case OpAMD64MOVLstoreidx4:
   290  		return rewriteValueAMD64_OpAMD64MOVLstoreidx4_0(v)
   291  	case OpAMD64MOVLstoreidx8:
   292  		return rewriteValueAMD64_OpAMD64MOVLstoreidx8_0(v)
   293  	case OpAMD64MOVOload:
   294  		return rewriteValueAMD64_OpAMD64MOVOload_0(v)
   295  	case OpAMD64MOVOstore:
   296  		return rewriteValueAMD64_OpAMD64MOVOstore_0(v)
   297  	case OpAMD64MOVQatomicload:
   298  		return rewriteValueAMD64_OpAMD64MOVQatomicload_0(v)
   299  	case OpAMD64MOVQf2i:
   300  		return rewriteValueAMD64_OpAMD64MOVQf2i_0(v)
   301  	case OpAMD64MOVQi2f:
   302  		return rewriteValueAMD64_OpAMD64MOVQi2f_0(v)
   303  	case OpAMD64MOVQload:
   304  		return rewriteValueAMD64_OpAMD64MOVQload_0(v)
   305  	case OpAMD64MOVQloadidx1:
   306  		return rewriteValueAMD64_OpAMD64MOVQloadidx1_0(v)
   307  	case OpAMD64MOVQloadidx8:
   308  		return rewriteValueAMD64_OpAMD64MOVQloadidx8_0(v)
   309  	case OpAMD64MOVQstore:
   310  		return rewriteValueAMD64_OpAMD64MOVQstore_0(v) || rewriteValueAMD64_OpAMD64MOVQstore_10(v) || rewriteValueAMD64_OpAMD64MOVQstore_20(v) || rewriteValueAMD64_OpAMD64MOVQstore_30(v)
   311  	case OpAMD64MOVQstoreconst:
   312  		return rewriteValueAMD64_OpAMD64MOVQstoreconst_0(v)
   313  	case OpAMD64MOVQstoreconstidx1:
   314  		return rewriteValueAMD64_OpAMD64MOVQstoreconstidx1_0(v)
   315  	case OpAMD64MOVQstoreconstidx8:
   316  		return rewriteValueAMD64_OpAMD64MOVQstoreconstidx8_0(v)
   317  	case OpAMD64MOVQstoreidx1:
   318  		return rewriteValueAMD64_OpAMD64MOVQstoreidx1_0(v)
   319  	case OpAMD64MOVQstoreidx8:
   320  		return rewriteValueAMD64_OpAMD64MOVQstoreidx8_0(v)
   321  	case OpAMD64MOVSDload:
   322  		return rewriteValueAMD64_OpAMD64MOVSDload_0(v)
   323  	case OpAMD64MOVSDloadidx1:
   324  		return rewriteValueAMD64_OpAMD64MOVSDloadidx1_0(v)
   325  	case OpAMD64MOVSDloadidx8:
   326  		return rewriteValueAMD64_OpAMD64MOVSDloadidx8_0(v)
   327  	case OpAMD64MOVSDstore:
   328  		return rewriteValueAMD64_OpAMD64MOVSDstore_0(v)
   329  	case OpAMD64MOVSDstoreidx1:
   330  		return rewriteValueAMD64_OpAMD64MOVSDstoreidx1_0(v)
   331  	case OpAMD64MOVSDstoreidx8:
   332  		return rewriteValueAMD64_OpAMD64MOVSDstoreidx8_0(v)
   333  	case OpAMD64MOVSSload:
   334  		return rewriteValueAMD64_OpAMD64MOVSSload_0(v)
   335  	case OpAMD64MOVSSloadidx1:
   336  		return rewriteValueAMD64_OpAMD64MOVSSloadidx1_0(v)
   337  	case OpAMD64MOVSSloadidx4:
   338  		return rewriteValueAMD64_OpAMD64MOVSSloadidx4_0(v)
   339  	case OpAMD64MOVSSstore:
   340  		return rewriteValueAMD64_OpAMD64MOVSSstore_0(v)
   341  	case OpAMD64MOVSSstoreidx1:
   342  		return rewriteValueAMD64_OpAMD64MOVSSstoreidx1_0(v)
   343  	case OpAMD64MOVSSstoreidx4:
   344  		return rewriteValueAMD64_OpAMD64MOVSSstoreidx4_0(v)
   345  	case OpAMD64MOVWQSX:
   346  		return rewriteValueAMD64_OpAMD64MOVWQSX_0(v)
   347  	case OpAMD64MOVWQSXload:
   348  		return rewriteValueAMD64_OpAMD64MOVWQSXload_0(v)
   349  	case OpAMD64MOVWQZX:
   350  		return rewriteValueAMD64_OpAMD64MOVWQZX_0(v)
   351  	case OpAMD64MOVWload:
   352  		return rewriteValueAMD64_OpAMD64MOVWload_0(v)
   353  	case OpAMD64MOVWloadidx1:
   354  		return rewriteValueAMD64_OpAMD64MOVWloadidx1_0(v)
   355  	case OpAMD64MOVWloadidx2:
   356  		return rewriteValueAMD64_OpAMD64MOVWloadidx2_0(v)
   357  	case OpAMD64MOVWstore:
   358  		return rewriteValueAMD64_OpAMD64MOVWstore_0(v) || rewriteValueAMD64_OpAMD64MOVWstore_10(v)
   359  	case OpAMD64MOVWstoreconst:
   360  		return rewriteValueAMD64_OpAMD64MOVWstoreconst_0(v)
   361  	case OpAMD64MOVWstoreconstidx1:
   362  		return rewriteValueAMD64_OpAMD64MOVWstoreconstidx1_0(v)
   363  	case OpAMD64MOVWstoreconstidx2:
   364  		return rewriteValueAMD64_OpAMD64MOVWstoreconstidx2_0(v)
   365  	case OpAMD64MOVWstoreidx1:
   366  		return rewriteValueAMD64_OpAMD64MOVWstoreidx1_0(v)
   367  	case OpAMD64MOVWstoreidx2:
   368  		return rewriteValueAMD64_OpAMD64MOVWstoreidx2_0(v)
   369  	case OpAMD64MULL:
   370  		return rewriteValueAMD64_OpAMD64MULL_0(v)
   371  	case OpAMD64MULLconst:
   372  		return rewriteValueAMD64_OpAMD64MULLconst_0(v) || rewriteValueAMD64_OpAMD64MULLconst_10(v) || rewriteValueAMD64_OpAMD64MULLconst_20(v) || rewriteValueAMD64_OpAMD64MULLconst_30(v)
   373  	case OpAMD64MULQ:
   374  		return rewriteValueAMD64_OpAMD64MULQ_0(v)
   375  	case OpAMD64MULQconst:
   376  		return rewriteValueAMD64_OpAMD64MULQconst_0(v) || rewriteValueAMD64_OpAMD64MULQconst_10(v) || rewriteValueAMD64_OpAMD64MULQconst_20(v) || rewriteValueAMD64_OpAMD64MULQconst_30(v)
   377  	case OpAMD64MULSD:
   378  		return rewriteValueAMD64_OpAMD64MULSD_0(v)
   379  	case OpAMD64MULSDload:
   380  		return rewriteValueAMD64_OpAMD64MULSDload_0(v)
   381  	case OpAMD64MULSS:
   382  		return rewriteValueAMD64_OpAMD64MULSS_0(v)
   383  	case OpAMD64MULSSload:
   384  		return rewriteValueAMD64_OpAMD64MULSSload_0(v)
   385  	case OpAMD64NEGL:
   386  		return rewriteValueAMD64_OpAMD64NEGL_0(v)
   387  	case OpAMD64NEGQ:
   388  		return rewriteValueAMD64_OpAMD64NEGQ_0(v)
   389  	case OpAMD64NOTL:
   390  		return rewriteValueAMD64_OpAMD64NOTL_0(v)
   391  	case OpAMD64NOTQ:
   392  		return rewriteValueAMD64_OpAMD64NOTQ_0(v)
   393  	case OpAMD64ORL:
   394  		return rewriteValueAMD64_OpAMD64ORL_0(v) || rewriteValueAMD64_OpAMD64ORL_10(v) || rewriteValueAMD64_OpAMD64ORL_20(v) || rewriteValueAMD64_OpAMD64ORL_30(v) || rewriteValueAMD64_OpAMD64ORL_40(v) || rewriteValueAMD64_OpAMD64ORL_50(v) || rewriteValueAMD64_OpAMD64ORL_60(v) || rewriteValueAMD64_OpAMD64ORL_70(v) || rewriteValueAMD64_OpAMD64ORL_80(v) || rewriteValueAMD64_OpAMD64ORL_90(v) || rewriteValueAMD64_OpAMD64ORL_100(v) || rewriteValueAMD64_OpAMD64ORL_110(v) || rewriteValueAMD64_OpAMD64ORL_120(v) || rewriteValueAMD64_OpAMD64ORL_130(v)
   395  	case OpAMD64ORLconst:
   396  		return rewriteValueAMD64_OpAMD64ORLconst_0(v)
   397  	case OpAMD64ORLconstmodify:
   398  		return rewriteValueAMD64_OpAMD64ORLconstmodify_0(v)
   399  	case OpAMD64ORLload:
   400  		return rewriteValueAMD64_OpAMD64ORLload_0(v)
   401  	case OpAMD64ORLmodify:
   402  		return rewriteValueAMD64_OpAMD64ORLmodify_0(v)
   403  	case OpAMD64ORQ:
   404  		return rewriteValueAMD64_OpAMD64ORQ_0(v) || rewriteValueAMD64_OpAMD64ORQ_10(v) || rewriteValueAMD64_OpAMD64ORQ_20(v) || rewriteValueAMD64_OpAMD64ORQ_30(v) || rewriteValueAMD64_OpAMD64ORQ_40(v) || rewriteValueAMD64_OpAMD64ORQ_50(v) || rewriteValueAMD64_OpAMD64ORQ_60(v) || rewriteValueAMD64_OpAMD64ORQ_70(v) || rewriteValueAMD64_OpAMD64ORQ_80(v) || rewriteValueAMD64_OpAMD64ORQ_90(v) || rewriteValueAMD64_OpAMD64ORQ_100(v) || rewriteValueAMD64_OpAMD64ORQ_110(v) || rewriteValueAMD64_OpAMD64ORQ_120(v) || rewriteValueAMD64_OpAMD64ORQ_130(v) || rewriteValueAMD64_OpAMD64ORQ_140(v) || rewriteValueAMD64_OpAMD64ORQ_150(v) || rewriteValueAMD64_OpAMD64ORQ_160(v)
   405  	case OpAMD64ORQconst:
   406  		return rewriteValueAMD64_OpAMD64ORQconst_0(v)
   407  	case OpAMD64ORQconstmodify:
   408  		return rewriteValueAMD64_OpAMD64ORQconstmodify_0(v)
   409  	case OpAMD64ORQload:
   410  		return rewriteValueAMD64_OpAMD64ORQload_0(v)
   411  	case OpAMD64ORQmodify:
   412  		return rewriteValueAMD64_OpAMD64ORQmodify_0(v)
   413  	case OpAMD64ROLB:
   414  		return rewriteValueAMD64_OpAMD64ROLB_0(v)
   415  	case OpAMD64ROLBconst:
   416  		return rewriteValueAMD64_OpAMD64ROLBconst_0(v)
   417  	case OpAMD64ROLL:
   418  		return rewriteValueAMD64_OpAMD64ROLL_0(v)
   419  	case OpAMD64ROLLconst:
   420  		return rewriteValueAMD64_OpAMD64ROLLconst_0(v)
   421  	case OpAMD64ROLQ:
   422  		return rewriteValueAMD64_OpAMD64ROLQ_0(v)
   423  	case OpAMD64ROLQconst:
   424  		return rewriteValueAMD64_OpAMD64ROLQconst_0(v)
   425  	case OpAMD64ROLW:
   426  		return rewriteValueAMD64_OpAMD64ROLW_0(v)
   427  	case OpAMD64ROLWconst:
   428  		return rewriteValueAMD64_OpAMD64ROLWconst_0(v)
   429  	case OpAMD64RORB:
   430  		return rewriteValueAMD64_OpAMD64RORB_0(v)
   431  	case OpAMD64RORL:
   432  		return rewriteValueAMD64_OpAMD64RORL_0(v)
   433  	case OpAMD64RORQ:
   434  		return rewriteValueAMD64_OpAMD64RORQ_0(v)
   435  	case OpAMD64RORW:
   436  		return rewriteValueAMD64_OpAMD64RORW_0(v)
   437  	case OpAMD64SARB:
   438  		return rewriteValueAMD64_OpAMD64SARB_0(v)
   439  	case OpAMD64SARBconst:
   440  		return rewriteValueAMD64_OpAMD64SARBconst_0(v)
   441  	case OpAMD64SARL:
   442  		return rewriteValueAMD64_OpAMD64SARL_0(v)
   443  	case OpAMD64SARLconst:
   444  		return rewriteValueAMD64_OpAMD64SARLconst_0(v)
   445  	case OpAMD64SARQ:
   446  		return rewriteValueAMD64_OpAMD64SARQ_0(v)
   447  	case OpAMD64SARQconst:
   448  		return rewriteValueAMD64_OpAMD64SARQconst_0(v)
   449  	case OpAMD64SARW:
   450  		return rewriteValueAMD64_OpAMD64SARW_0(v)
   451  	case OpAMD64SARWconst:
   452  		return rewriteValueAMD64_OpAMD64SARWconst_0(v)
   453  	case OpAMD64SBBLcarrymask:
   454  		return rewriteValueAMD64_OpAMD64SBBLcarrymask_0(v)
   455  	case OpAMD64SBBQ:
   456  		return rewriteValueAMD64_OpAMD64SBBQ_0(v)
   457  	case OpAMD64SBBQcarrymask:
   458  		return rewriteValueAMD64_OpAMD64SBBQcarrymask_0(v)
   459  	case OpAMD64SBBQconst:
   460  		return rewriteValueAMD64_OpAMD64SBBQconst_0(v)
   461  	case OpAMD64SETA:
   462  		return rewriteValueAMD64_OpAMD64SETA_0(v)
   463  	case OpAMD64SETAE:
   464  		return rewriteValueAMD64_OpAMD64SETAE_0(v)
   465  	case OpAMD64SETAEstore:
   466  		return rewriteValueAMD64_OpAMD64SETAEstore_0(v)
   467  	case OpAMD64SETAstore:
   468  		return rewriteValueAMD64_OpAMD64SETAstore_0(v)
   469  	case OpAMD64SETB:
   470  		return rewriteValueAMD64_OpAMD64SETB_0(v)
   471  	case OpAMD64SETBE:
   472  		return rewriteValueAMD64_OpAMD64SETBE_0(v)
   473  	case OpAMD64SETBEstore:
   474  		return rewriteValueAMD64_OpAMD64SETBEstore_0(v)
   475  	case OpAMD64SETBstore:
   476  		return rewriteValueAMD64_OpAMD64SETBstore_0(v)
   477  	case OpAMD64SETEQ:
   478  		return rewriteValueAMD64_OpAMD64SETEQ_0(v) || rewriteValueAMD64_OpAMD64SETEQ_10(v) || rewriteValueAMD64_OpAMD64SETEQ_20(v)
   479  	case OpAMD64SETEQstore:
   480  		return rewriteValueAMD64_OpAMD64SETEQstore_0(v) || rewriteValueAMD64_OpAMD64SETEQstore_10(v) || rewriteValueAMD64_OpAMD64SETEQstore_20(v)
   481  	case OpAMD64SETG:
   482  		return rewriteValueAMD64_OpAMD64SETG_0(v)
   483  	case OpAMD64SETGE:
   484  		return rewriteValueAMD64_OpAMD64SETGE_0(v)
   485  	case OpAMD64SETGEstore:
   486  		return rewriteValueAMD64_OpAMD64SETGEstore_0(v)
   487  	case OpAMD64SETGstore:
   488  		return rewriteValueAMD64_OpAMD64SETGstore_0(v)
   489  	case OpAMD64SETL:
   490  		return rewriteValueAMD64_OpAMD64SETL_0(v)
   491  	case OpAMD64SETLE:
   492  		return rewriteValueAMD64_OpAMD64SETLE_0(v)
   493  	case OpAMD64SETLEstore:
   494  		return rewriteValueAMD64_OpAMD64SETLEstore_0(v)
   495  	case OpAMD64SETLstore:
   496  		return rewriteValueAMD64_OpAMD64SETLstore_0(v)
   497  	case OpAMD64SETNE:
   498  		return rewriteValueAMD64_OpAMD64SETNE_0(v) || rewriteValueAMD64_OpAMD64SETNE_10(v) || rewriteValueAMD64_OpAMD64SETNE_20(v)
   499  	case OpAMD64SETNEstore:
   500  		return rewriteValueAMD64_OpAMD64SETNEstore_0(v) || rewriteValueAMD64_OpAMD64SETNEstore_10(v) || rewriteValueAMD64_OpAMD64SETNEstore_20(v)
   501  	case OpAMD64SHLL:
   502  		return rewriteValueAMD64_OpAMD64SHLL_0(v)
   503  	case OpAMD64SHLLconst:
   504  		return rewriteValueAMD64_OpAMD64SHLLconst_0(v)
   505  	case OpAMD64SHLQ:
   506  		return rewriteValueAMD64_OpAMD64SHLQ_0(v)
   507  	case OpAMD64SHLQconst:
   508  		return rewriteValueAMD64_OpAMD64SHLQconst_0(v)
   509  	case OpAMD64SHRB:
   510  		return rewriteValueAMD64_OpAMD64SHRB_0(v)
   511  	case OpAMD64SHRBconst:
   512  		return rewriteValueAMD64_OpAMD64SHRBconst_0(v)
   513  	case OpAMD64SHRL:
   514  		return rewriteValueAMD64_OpAMD64SHRL_0(v)
   515  	case OpAMD64SHRLconst:
   516  		return rewriteValueAMD64_OpAMD64SHRLconst_0(v)
   517  	case OpAMD64SHRQ:
   518  		return rewriteValueAMD64_OpAMD64SHRQ_0(v)
   519  	case OpAMD64SHRQconst:
   520  		return rewriteValueAMD64_OpAMD64SHRQconst_0(v)
   521  	case OpAMD64SHRW:
   522  		return rewriteValueAMD64_OpAMD64SHRW_0(v)
   523  	case OpAMD64SHRWconst:
   524  		return rewriteValueAMD64_OpAMD64SHRWconst_0(v)
   525  	case OpAMD64SUBL:
   526  		return rewriteValueAMD64_OpAMD64SUBL_0(v)
   527  	case OpAMD64SUBLconst:
   528  		return rewriteValueAMD64_OpAMD64SUBLconst_0(v)
   529  	case OpAMD64SUBLload:
   530  		return rewriteValueAMD64_OpAMD64SUBLload_0(v)
   531  	case OpAMD64SUBLmodify:
   532  		return rewriteValueAMD64_OpAMD64SUBLmodify_0(v)
   533  	case OpAMD64SUBQ:
   534  		return rewriteValueAMD64_OpAMD64SUBQ_0(v)
   535  	case OpAMD64SUBQborrow:
   536  		return rewriteValueAMD64_OpAMD64SUBQborrow_0(v)
   537  	case OpAMD64SUBQconst:
   538  		return rewriteValueAMD64_OpAMD64SUBQconst_0(v)
   539  	case OpAMD64SUBQload:
   540  		return rewriteValueAMD64_OpAMD64SUBQload_0(v)
   541  	case OpAMD64SUBQmodify:
   542  		return rewriteValueAMD64_OpAMD64SUBQmodify_0(v)
   543  	case OpAMD64SUBSD:
   544  		return rewriteValueAMD64_OpAMD64SUBSD_0(v)
   545  	case OpAMD64SUBSDload:
   546  		return rewriteValueAMD64_OpAMD64SUBSDload_0(v)
   547  	case OpAMD64SUBSS:
   548  		return rewriteValueAMD64_OpAMD64SUBSS_0(v)
   549  	case OpAMD64SUBSSload:
   550  		return rewriteValueAMD64_OpAMD64SUBSSload_0(v)
   551  	case OpAMD64TESTB:
   552  		return rewriteValueAMD64_OpAMD64TESTB_0(v)
   553  	case OpAMD64TESTBconst:
   554  		return rewriteValueAMD64_OpAMD64TESTBconst_0(v)
   555  	case OpAMD64TESTL:
   556  		return rewriteValueAMD64_OpAMD64TESTL_0(v)
   557  	case OpAMD64TESTLconst:
   558  		return rewriteValueAMD64_OpAMD64TESTLconst_0(v)
   559  	case OpAMD64TESTQ:
   560  		return rewriteValueAMD64_OpAMD64TESTQ_0(v)
   561  	case OpAMD64TESTQconst:
   562  		return rewriteValueAMD64_OpAMD64TESTQconst_0(v)
   563  	case OpAMD64TESTW:
   564  		return rewriteValueAMD64_OpAMD64TESTW_0(v)
   565  	case OpAMD64TESTWconst:
   566  		return rewriteValueAMD64_OpAMD64TESTWconst_0(v)
   567  	case OpAMD64XADDLlock:
   568  		return rewriteValueAMD64_OpAMD64XADDLlock_0(v)
   569  	case OpAMD64XADDQlock:
   570  		return rewriteValueAMD64_OpAMD64XADDQlock_0(v)
   571  	case OpAMD64XCHGL:
   572  		return rewriteValueAMD64_OpAMD64XCHGL_0(v)
   573  	case OpAMD64XCHGQ:
   574  		return rewriteValueAMD64_OpAMD64XCHGQ_0(v)
   575  	case OpAMD64XORL:
   576  		return rewriteValueAMD64_OpAMD64XORL_0(v) || rewriteValueAMD64_OpAMD64XORL_10(v)
   577  	case OpAMD64XORLconst:
   578  		return rewriteValueAMD64_OpAMD64XORLconst_0(v) || rewriteValueAMD64_OpAMD64XORLconst_10(v)
   579  	case OpAMD64XORLconstmodify:
   580  		return rewriteValueAMD64_OpAMD64XORLconstmodify_0(v)
   581  	case OpAMD64XORLload:
   582  		return rewriteValueAMD64_OpAMD64XORLload_0(v)
   583  	case OpAMD64XORLmodify:
   584  		return rewriteValueAMD64_OpAMD64XORLmodify_0(v)
   585  	case OpAMD64XORQ:
   586  		return rewriteValueAMD64_OpAMD64XORQ_0(v) || rewriteValueAMD64_OpAMD64XORQ_10(v)
   587  	case OpAMD64XORQconst:
   588  		return rewriteValueAMD64_OpAMD64XORQconst_0(v)
   589  	case OpAMD64XORQconstmodify:
   590  		return rewriteValueAMD64_OpAMD64XORQconstmodify_0(v)
   591  	case OpAMD64XORQload:
   592  		return rewriteValueAMD64_OpAMD64XORQload_0(v)
   593  	case OpAMD64XORQmodify:
   594  		return rewriteValueAMD64_OpAMD64XORQmodify_0(v)
   595  	case OpAdd16:
   596  		return rewriteValueAMD64_OpAdd16_0(v)
   597  	case OpAdd32:
   598  		return rewriteValueAMD64_OpAdd32_0(v)
   599  	case OpAdd32F:
   600  		return rewriteValueAMD64_OpAdd32F_0(v)
   601  	case OpAdd64:
   602  		return rewriteValueAMD64_OpAdd64_0(v)
   603  	case OpAdd64F:
   604  		return rewriteValueAMD64_OpAdd64F_0(v)
   605  	case OpAdd8:
   606  		return rewriteValueAMD64_OpAdd8_0(v)
   607  	case OpAddPtr:
   608  		return rewriteValueAMD64_OpAddPtr_0(v)
   609  	case OpAddr:
   610  		return rewriteValueAMD64_OpAddr_0(v)
   611  	case OpAnd16:
   612  		return rewriteValueAMD64_OpAnd16_0(v)
   613  	case OpAnd32:
   614  		return rewriteValueAMD64_OpAnd32_0(v)
   615  	case OpAnd64:
   616  		return rewriteValueAMD64_OpAnd64_0(v)
   617  	case OpAnd8:
   618  		return rewriteValueAMD64_OpAnd8_0(v)
   619  	case OpAndB:
   620  		return rewriteValueAMD64_OpAndB_0(v)
   621  	case OpAtomicAdd32:
   622  		return rewriteValueAMD64_OpAtomicAdd32_0(v)
   623  	case OpAtomicAdd64:
   624  		return rewriteValueAMD64_OpAtomicAdd64_0(v)
   625  	case OpAtomicAnd8:
   626  		return rewriteValueAMD64_OpAtomicAnd8_0(v)
   627  	case OpAtomicCompareAndSwap32:
   628  		return rewriteValueAMD64_OpAtomicCompareAndSwap32_0(v)
   629  	case OpAtomicCompareAndSwap64:
   630  		return rewriteValueAMD64_OpAtomicCompareAndSwap64_0(v)
   631  	case OpAtomicExchange32:
   632  		return rewriteValueAMD64_OpAtomicExchange32_0(v)
   633  	case OpAtomicExchange64:
   634  		return rewriteValueAMD64_OpAtomicExchange64_0(v)
   635  	case OpAtomicLoad32:
   636  		return rewriteValueAMD64_OpAtomicLoad32_0(v)
   637  	case OpAtomicLoad64:
   638  		return rewriteValueAMD64_OpAtomicLoad64_0(v)
   639  	case OpAtomicLoad8:
   640  		return rewriteValueAMD64_OpAtomicLoad8_0(v)
   641  	case OpAtomicLoadPtr:
   642  		return rewriteValueAMD64_OpAtomicLoadPtr_0(v)
   643  	case OpAtomicOr8:
   644  		return rewriteValueAMD64_OpAtomicOr8_0(v)
   645  	case OpAtomicStore32:
   646  		return rewriteValueAMD64_OpAtomicStore32_0(v)
   647  	case OpAtomicStore64:
   648  		return rewriteValueAMD64_OpAtomicStore64_0(v)
   649  	case OpAtomicStore8:
   650  		return rewriteValueAMD64_OpAtomicStore8_0(v)
   651  	case OpAtomicStorePtrNoWB:
   652  		return rewriteValueAMD64_OpAtomicStorePtrNoWB_0(v)
   653  	case OpAvg64u:
   654  		return rewriteValueAMD64_OpAvg64u_0(v)
   655  	case OpBitLen16:
   656  		return rewriteValueAMD64_OpBitLen16_0(v)
   657  	case OpBitLen32:
   658  		return rewriteValueAMD64_OpBitLen32_0(v)
   659  	case OpBitLen64:
   660  		return rewriteValueAMD64_OpBitLen64_0(v)
   661  	case OpBitLen8:
   662  		return rewriteValueAMD64_OpBitLen8_0(v)
   663  	case OpBswap32:
   664  		return rewriteValueAMD64_OpBswap32_0(v)
   665  	case OpBswap64:
   666  		return rewriteValueAMD64_OpBswap64_0(v)
   667  	case OpCeil:
   668  		return rewriteValueAMD64_OpCeil_0(v)
   669  	case OpClosureCall:
   670  		return rewriteValueAMD64_OpClosureCall_0(v)
   671  	case OpCom16:
   672  		return rewriteValueAMD64_OpCom16_0(v)
   673  	case OpCom32:
   674  		return rewriteValueAMD64_OpCom32_0(v)
   675  	case OpCom64:
   676  		return rewriteValueAMD64_OpCom64_0(v)
   677  	case OpCom8:
   678  		return rewriteValueAMD64_OpCom8_0(v)
   679  	case OpCondSelect:
   680  		return rewriteValueAMD64_OpCondSelect_0(v) || rewriteValueAMD64_OpCondSelect_10(v) || rewriteValueAMD64_OpCondSelect_20(v) || rewriteValueAMD64_OpCondSelect_30(v) || rewriteValueAMD64_OpCondSelect_40(v)
   681  	case OpConst16:
   682  		return rewriteValueAMD64_OpConst16_0(v)
   683  	case OpConst32:
   684  		return rewriteValueAMD64_OpConst32_0(v)
   685  	case OpConst32F:
   686  		return rewriteValueAMD64_OpConst32F_0(v)
   687  	case OpConst64:
   688  		return rewriteValueAMD64_OpConst64_0(v)
   689  	case OpConst64F:
   690  		return rewriteValueAMD64_OpConst64F_0(v)
   691  	case OpConst8:
   692  		return rewriteValueAMD64_OpConst8_0(v)
   693  	case OpConstBool:
   694  		return rewriteValueAMD64_OpConstBool_0(v)
   695  	case OpConstNil:
   696  		return rewriteValueAMD64_OpConstNil_0(v)
   697  	case OpCtz16:
   698  		return rewriteValueAMD64_OpCtz16_0(v)
   699  	case OpCtz16NonZero:
   700  		return rewriteValueAMD64_OpCtz16NonZero_0(v)
   701  	case OpCtz32:
   702  		return rewriteValueAMD64_OpCtz32_0(v)
   703  	case OpCtz32NonZero:
   704  		return rewriteValueAMD64_OpCtz32NonZero_0(v)
   705  	case OpCtz64:
   706  		return rewriteValueAMD64_OpCtz64_0(v)
   707  	case OpCtz64NonZero:
   708  		return rewriteValueAMD64_OpCtz64NonZero_0(v)
   709  	case OpCtz8:
   710  		return rewriteValueAMD64_OpCtz8_0(v)
   711  	case OpCtz8NonZero:
   712  		return rewriteValueAMD64_OpCtz8NonZero_0(v)
   713  	case OpCvt32Fto32:
   714  		return rewriteValueAMD64_OpCvt32Fto32_0(v)
   715  	case OpCvt32Fto64:
   716  		return rewriteValueAMD64_OpCvt32Fto64_0(v)
   717  	case OpCvt32Fto64F:
   718  		return rewriteValueAMD64_OpCvt32Fto64F_0(v)
   719  	case OpCvt32to32F:
   720  		return rewriteValueAMD64_OpCvt32to32F_0(v)
   721  	case OpCvt32to64F:
   722  		return rewriteValueAMD64_OpCvt32to64F_0(v)
   723  	case OpCvt64Fto32:
   724  		return rewriteValueAMD64_OpCvt64Fto32_0(v)
   725  	case OpCvt64Fto32F:
   726  		return rewriteValueAMD64_OpCvt64Fto32F_0(v)
   727  	case OpCvt64Fto64:
   728  		return rewriteValueAMD64_OpCvt64Fto64_0(v)
   729  	case OpCvt64to32F:
   730  		return rewriteValueAMD64_OpCvt64to32F_0(v)
   731  	case OpCvt64to64F:
   732  		return rewriteValueAMD64_OpCvt64to64F_0(v)
   733  	case OpDiv128u:
   734  		return rewriteValueAMD64_OpDiv128u_0(v)
   735  	case OpDiv16:
   736  		return rewriteValueAMD64_OpDiv16_0(v)
   737  	case OpDiv16u:
   738  		return rewriteValueAMD64_OpDiv16u_0(v)
   739  	case OpDiv32:
   740  		return rewriteValueAMD64_OpDiv32_0(v)
   741  	case OpDiv32F:
   742  		return rewriteValueAMD64_OpDiv32F_0(v)
   743  	case OpDiv32u:
   744  		return rewriteValueAMD64_OpDiv32u_0(v)
   745  	case OpDiv64:
   746  		return rewriteValueAMD64_OpDiv64_0(v)
   747  	case OpDiv64F:
   748  		return rewriteValueAMD64_OpDiv64F_0(v)
   749  	case OpDiv64u:
   750  		return rewriteValueAMD64_OpDiv64u_0(v)
   751  	case OpDiv8:
   752  		return rewriteValueAMD64_OpDiv8_0(v)
   753  	case OpDiv8u:
   754  		return rewriteValueAMD64_OpDiv8u_0(v)
   755  	case OpEq16:
   756  		return rewriteValueAMD64_OpEq16_0(v)
   757  	case OpEq32:
   758  		return rewriteValueAMD64_OpEq32_0(v)
   759  	case OpEq32F:
   760  		return rewriteValueAMD64_OpEq32F_0(v)
   761  	case OpEq64:
   762  		return rewriteValueAMD64_OpEq64_0(v)
   763  	case OpEq64F:
   764  		return rewriteValueAMD64_OpEq64F_0(v)
   765  	case OpEq8:
   766  		return rewriteValueAMD64_OpEq8_0(v)
   767  	case OpEqB:
   768  		return rewriteValueAMD64_OpEqB_0(v)
   769  	case OpEqPtr:
   770  		return rewriteValueAMD64_OpEqPtr_0(v)
   771  	case OpFMA:
   772  		return rewriteValueAMD64_OpFMA_0(v)
   773  	case OpFloor:
   774  		return rewriteValueAMD64_OpFloor_0(v)
   775  	case OpGeq16:
   776  		return rewriteValueAMD64_OpGeq16_0(v)
   777  	case OpGeq16U:
   778  		return rewriteValueAMD64_OpGeq16U_0(v)
   779  	case OpGeq32:
   780  		return rewriteValueAMD64_OpGeq32_0(v)
   781  	case OpGeq32F:
   782  		return rewriteValueAMD64_OpGeq32F_0(v)
   783  	case OpGeq32U:
   784  		return rewriteValueAMD64_OpGeq32U_0(v)
   785  	case OpGeq64:
   786  		return rewriteValueAMD64_OpGeq64_0(v)
   787  	case OpGeq64F:
   788  		return rewriteValueAMD64_OpGeq64F_0(v)
   789  	case OpGeq64U:
   790  		return rewriteValueAMD64_OpGeq64U_0(v)
   791  	case OpGeq8:
   792  		return rewriteValueAMD64_OpGeq8_0(v)
   793  	case OpGeq8U:
   794  		return rewriteValueAMD64_OpGeq8U_0(v)
   795  	case OpGetCallerPC:
   796  		return rewriteValueAMD64_OpGetCallerPC_0(v)
   797  	case OpGetCallerSP:
   798  		return rewriteValueAMD64_OpGetCallerSP_0(v)
   799  	case OpGetClosurePtr:
   800  		return rewriteValueAMD64_OpGetClosurePtr_0(v)
   801  	case OpGetG:
   802  		return rewriteValueAMD64_OpGetG_0(v)
   803  	case OpGreater16:
   804  		return rewriteValueAMD64_OpGreater16_0(v)
   805  	case OpGreater16U:
   806  		return rewriteValueAMD64_OpGreater16U_0(v)
   807  	case OpGreater32:
   808  		return rewriteValueAMD64_OpGreater32_0(v)
   809  	case OpGreater32F:
   810  		return rewriteValueAMD64_OpGreater32F_0(v)
   811  	case OpGreater32U:
   812  		return rewriteValueAMD64_OpGreater32U_0(v)
   813  	case OpGreater64:
   814  		return rewriteValueAMD64_OpGreater64_0(v)
   815  	case OpGreater64F:
   816  		return rewriteValueAMD64_OpGreater64F_0(v)
   817  	case OpGreater64U:
   818  		return rewriteValueAMD64_OpGreater64U_0(v)
   819  	case OpGreater8:
   820  		return rewriteValueAMD64_OpGreater8_0(v)
   821  	case OpGreater8U:
   822  		return rewriteValueAMD64_OpGreater8U_0(v)
   823  	case OpHmul32:
   824  		return rewriteValueAMD64_OpHmul32_0(v)
   825  	case OpHmul32u:
   826  		return rewriteValueAMD64_OpHmul32u_0(v)
   827  	case OpHmul64:
   828  		return rewriteValueAMD64_OpHmul64_0(v)
   829  	case OpHmul64u:
   830  		return rewriteValueAMD64_OpHmul64u_0(v)
   831  	case OpInterCall:
   832  		return rewriteValueAMD64_OpInterCall_0(v)
   833  	case OpIsInBounds:
   834  		return rewriteValueAMD64_OpIsInBounds_0(v)
   835  	case OpIsNonNil:
   836  		return rewriteValueAMD64_OpIsNonNil_0(v)
   837  	case OpIsSliceInBounds:
   838  		return rewriteValueAMD64_OpIsSliceInBounds_0(v)
   839  	case OpLeq16:
   840  		return rewriteValueAMD64_OpLeq16_0(v)
   841  	case OpLeq16U:
   842  		return rewriteValueAMD64_OpLeq16U_0(v)
   843  	case OpLeq32:
   844  		return rewriteValueAMD64_OpLeq32_0(v)
   845  	case OpLeq32F:
   846  		return rewriteValueAMD64_OpLeq32F_0(v)
   847  	case OpLeq32U:
   848  		return rewriteValueAMD64_OpLeq32U_0(v)
   849  	case OpLeq64:
   850  		return rewriteValueAMD64_OpLeq64_0(v)
   851  	case OpLeq64F:
   852  		return rewriteValueAMD64_OpLeq64F_0(v)
   853  	case OpLeq64U:
   854  		return rewriteValueAMD64_OpLeq64U_0(v)
   855  	case OpLeq8:
   856  		return rewriteValueAMD64_OpLeq8_0(v)
   857  	case OpLeq8U:
   858  		return rewriteValueAMD64_OpLeq8U_0(v)
   859  	case OpLess16:
   860  		return rewriteValueAMD64_OpLess16_0(v)
   861  	case OpLess16U:
   862  		return rewriteValueAMD64_OpLess16U_0(v)
   863  	case OpLess32:
   864  		return rewriteValueAMD64_OpLess32_0(v)
   865  	case OpLess32F:
   866  		return rewriteValueAMD64_OpLess32F_0(v)
   867  	case OpLess32U:
   868  		return rewriteValueAMD64_OpLess32U_0(v)
   869  	case OpLess64:
   870  		return rewriteValueAMD64_OpLess64_0(v)
   871  	case OpLess64F:
   872  		return rewriteValueAMD64_OpLess64F_0(v)
   873  	case OpLess64U:
   874  		return rewriteValueAMD64_OpLess64U_0(v)
   875  	case OpLess8:
   876  		return rewriteValueAMD64_OpLess8_0(v)
   877  	case OpLess8U:
   878  		return rewriteValueAMD64_OpLess8U_0(v)
   879  	case OpLoad:
   880  		return rewriteValueAMD64_OpLoad_0(v)
   881  	case OpLocalAddr:
   882  		return rewriteValueAMD64_OpLocalAddr_0(v)
   883  	case OpLsh16x16:
   884  		return rewriteValueAMD64_OpLsh16x16_0(v)
   885  	case OpLsh16x32:
   886  		return rewriteValueAMD64_OpLsh16x32_0(v)
   887  	case OpLsh16x64:
   888  		return rewriteValueAMD64_OpLsh16x64_0(v)
   889  	case OpLsh16x8:
   890  		return rewriteValueAMD64_OpLsh16x8_0(v)
   891  	case OpLsh32x16:
   892  		return rewriteValueAMD64_OpLsh32x16_0(v)
   893  	case OpLsh32x32:
   894  		return rewriteValueAMD64_OpLsh32x32_0(v)
   895  	case OpLsh32x64:
   896  		return rewriteValueAMD64_OpLsh32x64_0(v)
   897  	case OpLsh32x8:
   898  		return rewriteValueAMD64_OpLsh32x8_0(v)
   899  	case OpLsh64x16:
   900  		return rewriteValueAMD64_OpLsh64x16_0(v)
   901  	case OpLsh64x32:
   902  		return rewriteValueAMD64_OpLsh64x32_0(v)
   903  	case OpLsh64x64:
   904  		return rewriteValueAMD64_OpLsh64x64_0(v)
   905  	case OpLsh64x8:
   906  		return rewriteValueAMD64_OpLsh64x8_0(v)
   907  	case OpLsh8x16:
   908  		return rewriteValueAMD64_OpLsh8x16_0(v)
   909  	case OpLsh8x32:
   910  		return rewriteValueAMD64_OpLsh8x32_0(v)
   911  	case OpLsh8x64:
   912  		return rewriteValueAMD64_OpLsh8x64_0(v)
   913  	case OpLsh8x8:
   914  		return rewriteValueAMD64_OpLsh8x8_0(v)
   915  	case OpMod16:
   916  		return rewriteValueAMD64_OpMod16_0(v)
   917  	case OpMod16u:
   918  		return rewriteValueAMD64_OpMod16u_0(v)
   919  	case OpMod32:
   920  		return rewriteValueAMD64_OpMod32_0(v)
   921  	case OpMod32u:
   922  		return rewriteValueAMD64_OpMod32u_0(v)
   923  	case OpMod64:
   924  		return rewriteValueAMD64_OpMod64_0(v)
   925  	case OpMod64u:
   926  		return rewriteValueAMD64_OpMod64u_0(v)
   927  	case OpMod8:
   928  		return rewriteValueAMD64_OpMod8_0(v)
   929  	case OpMod8u:
   930  		return rewriteValueAMD64_OpMod8u_0(v)
   931  	case OpMove:
   932  		return rewriteValueAMD64_OpMove_0(v) || rewriteValueAMD64_OpMove_10(v) || rewriteValueAMD64_OpMove_20(v)
   933  	case OpMul16:
   934  		return rewriteValueAMD64_OpMul16_0(v)
   935  	case OpMul32:
   936  		return rewriteValueAMD64_OpMul32_0(v)
   937  	case OpMul32F:
   938  		return rewriteValueAMD64_OpMul32F_0(v)
   939  	case OpMul64:
   940  		return rewriteValueAMD64_OpMul64_0(v)
   941  	case OpMul64F:
   942  		return rewriteValueAMD64_OpMul64F_0(v)
   943  	case OpMul64uhilo:
   944  		return rewriteValueAMD64_OpMul64uhilo_0(v)
   945  	case OpMul8:
   946  		return rewriteValueAMD64_OpMul8_0(v)
   947  	case OpNeg16:
   948  		return rewriteValueAMD64_OpNeg16_0(v)
   949  	case OpNeg32:
   950  		return rewriteValueAMD64_OpNeg32_0(v)
   951  	case OpNeg32F:
   952  		return rewriteValueAMD64_OpNeg32F_0(v)
   953  	case OpNeg64:
   954  		return rewriteValueAMD64_OpNeg64_0(v)
   955  	case OpNeg64F:
   956  		return rewriteValueAMD64_OpNeg64F_0(v)
   957  	case OpNeg8:
   958  		return rewriteValueAMD64_OpNeg8_0(v)
   959  	case OpNeq16:
   960  		return rewriteValueAMD64_OpNeq16_0(v)
   961  	case OpNeq32:
   962  		return rewriteValueAMD64_OpNeq32_0(v)
   963  	case OpNeq32F:
   964  		return rewriteValueAMD64_OpNeq32F_0(v)
   965  	case OpNeq64:
   966  		return rewriteValueAMD64_OpNeq64_0(v)
   967  	case OpNeq64F:
   968  		return rewriteValueAMD64_OpNeq64F_0(v)
   969  	case OpNeq8:
   970  		return rewriteValueAMD64_OpNeq8_0(v)
   971  	case OpNeqB:
   972  		return rewriteValueAMD64_OpNeqB_0(v)
   973  	case OpNeqPtr:
   974  		return rewriteValueAMD64_OpNeqPtr_0(v)
   975  	case OpNilCheck:
   976  		return rewriteValueAMD64_OpNilCheck_0(v)
   977  	case OpNot:
   978  		return rewriteValueAMD64_OpNot_0(v)
   979  	case OpOffPtr:
   980  		return rewriteValueAMD64_OpOffPtr_0(v)
   981  	case OpOr16:
   982  		return rewriteValueAMD64_OpOr16_0(v)
   983  	case OpOr32:
   984  		return rewriteValueAMD64_OpOr32_0(v)
   985  	case OpOr64:
   986  		return rewriteValueAMD64_OpOr64_0(v)
   987  	case OpOr8:
   988  		return rewriteValueAMD64_OpOr8_0(v)
   989  	case OpOrB:
   990  		return rewriteValueAMD64_OpOrB_0(v)
   991  	case OpPanicBounds:
   992  		return rewriteValueAMD64_OpPanicBounds_0(v)
   993  	case OpPopCount16:
   994  		return rewriteValueAMD64_OpPopCount16_0(v)
   995  	case OpPopCount32:
   996  		return rewriteValueAMD64_OpPopCount32_0(v)
   997  	case OpPopCount64:
   998  		return rewriteValueAMD64_OpPopCount64_0(v)
   999  	case OpPopCount8:
  1000  		return rewriteValueAMD64_OpPopCount8_0(v)
  1001  	case OpRotateLeft16:
  1002  		return rewriteValueAMD64_OpRotateLeft16_0(v)
  1003  	case OpRotateLeft32:
  1004  		return rewriteValueAMD64_OpRotateLeft32_0(v)
  1005  	case OpRotateLeft64:
  1006  		return rewriteValueAMD64_OpRotateLeft64_0(v)
  1007  	case OpRotateLeft8:
  1008  		return rewriteValueAMD64_OpRotateLeft8_0(v)
  1009  	case OpRound32F:
  1010  		return rewriteValueAMD64_OpRound32F_0(v)
  1011  	case OpRound64F:
  1012  		return rewriteValueAMD64_OpRound64F_0(v)
  1013  	case OpRoundToEven:
  1014  		return rewriteValueAMD64_OpRoundToEven_0(v)
  1015  	case OpRsh16Ux16:
  1016  		return rewriteValueAMD64_OpRsh16Ux16_0(v)
  1017  	case OpRsh16Ux32:
  1018  		return rewriteValueAMD64_OpRsh16Ux32_0(v)
  1019  	case OpRsh16Ux64:
  1020  		return rewriteValueAMD64_OpRsh16Ux64_0(v)
  1021  	case OpRsh16Ux8:
  1022  		return rewriteValueAMD64_OpRsh16Ux8_0(v)
  1023  	case OpRsh16x16:
  1024  		return rewriteValueAMD64_OpRsh16x16_0(v)
  1025  	case OpRsh16x32:
  1026  		return rewriteValueAMD64_OpRsh16x32_0(v)
  1027  	case OpRsh16x64:
  1028  		return rewriteValueAMD64_OpRsh16x64_0(v)
  1029  	case OpRsh16x8:
  1030  		return rewriteValueAMD64_OpRsh16x8_0(v)
  1031  	case OpRsh32Ux16:
  1032  		return rewriteValueAMD64_OpRsh32Ux16_0(v)
  1033  	case OpRsh32Ux32:
  1034  		return rewriteValueAMD64_OpRsh32Ux32_0(v)
  1035  	case OpRsh32Ux64:
  1036  		return rewriteValueAMD64_OpRsh32Ux64_0(v)
  1037  	case OpRsh32Ux8:
  1038  		return rewriteValueAMD64_OpRsh32Ux8_0(v)
  1039  	case OpRsh32x16:
  1040  		return rewriteValueAMD64_OpRsh32x16_0(v)
  1041  	case OpRsh32x32:
  1042  		return rewriteValueAMD64_OpRsh32x32_0(v)
  1043  	case OpRsh32x64:
  1044  		return rewriteValueAMD64_OpRsh32x64_0(v)
  1045  	case OpRsh32x8:
  1046  		return rewriteValueAMD64_OpRsh32x8_0(v)
  1047  	case OpRsh64Ux16:
  1048  		return rewriteValueAMD64_OpRsh64Ux16_0(v)
  1049  	case OpRsh64Ux32:
  1050  		return rewriteValueAMD64_OpRsh64Ux32_0(v)
  1051  	case OpRsh64Ux64:
  1052  		return rewriteValueAMD64_OpRsh64Ux64_0(v)
  1053  	case OpRsh64Ux8:
  1054  		return rewriteValueAMD64_OpRsh64Ux8_0(v)
  1055  	case OpRsh64x16:
  1056  		return rewriteValueAMD64_OpRsh64x16_0(v)
  1057  	case OpRsh64x32:
  1058  		return rewriteValueAMD64_OpRsh64x32_0(v)
  1059  	case OpRsh64x64:
  1060  		return rewriteValueAMD64_OpRsh64x64_0(v)
  1061  	case OpRsh64x8:
  1062  		return rewriteValueAMD64_OpRsh64x8_0(v)
  1063  	case OpRsh8Ux16:
  1064  		return rewriteValueAMD64_OpRsh8Ux16_0(v)
  1065  	case OpRsh8Ux32:
  1066  		return rewriteValueAMD64_OpRsh8Ux32_0(v)
  1067  	case OpRsh8Ux64:
  1068  		return rewriteValueAMD64_OpRsh8Ux64_0(v)
  1069  	case OpRsh8Ux8:
  1070  		return rewriteValueAMD64_OpRsh8Ux8_0(v)
  1071  	case OpRsh8x16:
  1072  		return rewriteValueAMD64_OpRsh8x16_0(v)
  1073  	case OpRsh8x32:
  1074  		return rewriteValueAMD64_OpRsh8x32_0(v)
  1075  	case OpRsh8x64:
  1076  		return rewriteValueAMD64_OpRsh8x64_0(v)
  1077  	case OpRsh8x8:
  1078  		return rewriteValueAMD64_OpRsh8x8_0(v)
  1079  	case OpSelect0:
  1080  		return rewriteValueAMD64_OpSelect0_0(v)
  1081  	case OpSelect1:
  1082  		return rewriteValueAMD64_OpSelect1_0(v)
  1083  	case OpSignExt16to32:
  1084  		return rewriteValueAMD64_OpSignExt16to32_0(v)
  1085  	case OpSignExt16to64:
  1086  		return rewriteValueAMD64_OpSignExt16to64_0(v)
  1087  	case OpSignExt32to64:
  1088  		return rewriteValueAMD64_OpSignExt32to64_0(v)
  1089  	case OpSignExt8to16:
  1090  		return rewriteValueAMD64_OpSignExt8to16_0(v)
  1091  	case OpSignExt8to32:
  1092  		return rewriteValueAMD64_OpSignExt8to32_0(v)
  1093  	case OpSignExt8to64:
  1094  		return rewriteValueAMD64_OpSignExt8to64_0(v)
  1095  	case OpSlicemask:
  1096  		return rewriteValueAMD64_OpSlicemask_0(v)
  1097  	case OpSqrt:
  1098  		return rewriteValueAMD64_OpSqrt_0(v)
  1099  	case OpStaticCall:
  1100  		return rewriteValueAMD64_OpStaticCall_0(v)
  1101  	case OpStore:
  1102  		return rewriteValueAMD64_OpStore_0(v)
  1103  	case OpSub16:
  1104  		return rewriteValueAMD64_OpSub16_0(v)
  1105  	case OpSub32:
  1106  		return rewriteValueAMD64_OpSub32_0(v)
  1107  	case OpSub32F:
  1108  		return rewriteValueAMD64_OpSub32F_0(v)
  1109  	case OpSub64:
  1110  		return rewriteValueAMD64_OpSub64_0(v)
  1111  	case OpSub64F:
  1112  		return rewriteValueAMD64_OpSub64F_0(v)
  1113  	case OpSub8:
  1114  		return rewriteValueAMD64_OpSub8_0(v)
  1115  	case OpSubPtr:
  1116  		return rewriteValueAMD64_OpSubPtr_0(v)
  1117  	case OpTrunc:
  1118  		return rewriteValueAMD64_OpTrunc_0(v)
  1119  	case OpTrunc16to8:
  1120  		return rewriteValueAMD64_OpTrunc16to8_0(v)
  1121  	case OpTrunc32to16:
  1122  		return rewriteValueAMD64_OpTrunc32to16_0(v)
  1123  	case OpTrunc32to8:
  1124  		return rewriteValueAMD64_OpTrunc32to8_0(v)
  1125  	case OpTrunc64to16:
  1126  		return rewriteValueAMD64_OpTrunc64to16_0(v)
  1127  	case OpTrunc64to32:
  1128  		return rewriteValueAMD64_OpTrunc64to32_0(v)
  1129  	case OpTrunc64to8:
  1130  		return rewriteValueAMD64_OpTrunc64to8_0(v)
  1131  	case OpWB:
  1132  		return rewriteValueAMD64_OpWB_0(v)
  1133  	case OpXor16:
  1134  		return rewriteValueAMD64_OpXor16_0(v)
  1135  	case OpXor32:
  1136  		return rewriteValueAMD64_OpXor32_0(v)
  1137  	case OpXor64:
  1138  		return rewriteValueAMD64_OpXor64_0(v)
  1139  	case OpXor8:
  1140  		return rewriteValueAMD64_OpXor8_0(v)
  1141  	case OpZero:
  1142  		return rewriteValueAMD64_OpZero_0(v) || rewriteValueAMD64_OpZero_10(v) || rewriteValueAMD64_OpZero_20(v)
  1143  	case OpZeroExt16to32:
  1144  		return rewriteValueAMD64_OpZeroExt16to32_0(v)
  1145  	case OpZeroExt16to64:
  1146  		return rewriteValueAMD64_OpZeroExt16to64_0(v)
  1147  	case OpZeroExt32to64:
  1148  		return rewriteValueAMD64_OpZeroExt32to64_0(v)
  1149  	case OpZeroExt8to16:
  1150  		return rewriteValueAMD64_OpZeroExt8to16_0(v)
  1151  	case OpZeroExt8to32:
  1152  		return rewriteValueAMD64_OpZeroExt8to32_0(v)
  1153  	case OpZeroExt8to64:
  1154  		return rewriteValueAMD64_OpZeroExt8to64_0(v)
  1155  	}
  1156  	return false
  1157  }
  1158  func rewriteValueAMD64_OpAMD64ADCQ_0(v *Value) bool {
  1159  	// match: (ADCQ x (MOVQconst [c]) carry)
  1160  	// cond: is32Bit(c)
  1161  	// result: (ADCQconst x [c] carry)
  1162  	for {
  1163  		carry := v.Args[2]
  1164  		x := v.Args[0]
  1165  		v_1 := v.Args[1]
  1166  		if v_1.Op != OpAMD64MOVQconst {
  1167  			break
  1168  		}
  1169  		c := v_1.AuxInt
  1170  		if !(is32Bit(c)) {
  1171  			break
  1172  		}
  1173  		v.reset(OpAMD64ADCQconst)
  1174  		v.AuxInt = c
  1175  		v.AddArg(x)
  1176  		v.AddArg(carry)
  1177  		return true
  1178  	}
  1179  	// match: (ADCQ (MOVQconst [c]) x carry)
  1180  	// cond: is32Bit(c)
  1181  	// result: (ADCQconst x [c] carry)
  1182  	for {
  1183  		carry := v.Args[2]
  1184  		v_0 := v.Args[0]
  1185  		if v_0.Op != OpAMD64MOVQconst {
  1186  			break
  1187  		}
  1188  		c := v_0.AuxInt
  1189  		x := v.Args[1]
  1190  		if !(is32Bit(c)) {
  1191  			break
  1192  		}
  1193  		v.reset(OpAMD64ADCQconst)
  1194  		v.AuxInt = c
  1195  		v.AddArg(x)
  1196  		v.AddArg(carry)
  1197  		return true
  1198  	}
  1199  	// match: (ADCQ x y (FlagEQ))
  1200  	// result: (ADDQcarry x y)
  1201  	for {
  1202  		_ = v.Args[2]
  1203  		x := v.Args[0]
  1204  		y := v.Args[1]
  1205  		v_2 := v.Args[2]
  1206  		if v_2.Op != OpAMD64FlagEQ {
  1207  			break
  1208  		}
  1209  		v.reset(OpAMD64ADDQcarry)
  1210  		v.AddArg(x)
  1211  		v.AddArg(y)
  1212  		return true
  1213  	}
  1214  	return false
  1215  }
  1216  func rewriteValueAMD64_OpAMD64ADCQconst_0(v *Value) bool {
  1217  	// match: (ADCQconst x [c] (FlagEQ))
  1218  	// result: (ADDQconstcarry x [c])
  1219  	for {
  1220  		c := v.AuxInt
  1221  		_ = v.Args[1]
  1222  		x := v.Args[0]
  1223  		v_1 := v.Args[1]
  1224  		if v_1.Op != OpAMD64FlagEQ {
  1225  			break
  1226  		}
  1227  		v.reset(OpAMD64ADDQconstcarry)
  1228  		v.AuxInt = c
  1229  		v.AddArg(x)
  1230  		return true
  1231  	}
  1232  	return false
  1233  }
  1234  func rewriteValueAMD64_OpAMD64ADDL_0(v *Value) bool {
  1235  	// match: (ADDL x (MOVLconst [c]))
  1236  	// result: (ADDLconst [c] x)
  1237  	for {
  1238  		_ = v.Args[1]
  1239  		x := v.Args[0]
  1240  		v_1 := v.Args[1]
  1241  		if v_1.Op != OpAMD64MOVLconst {
  1242  			break
  1243  		}
  1244  		c := v_1.AuxInt
  1245  		v.reset(OpAMD64ADDLconst)
  1246  		v.AuxInt = c
  1247  		v.AddArg(x)
  1248  		return true
  1249  	}
  1250  	// match: (ADDL (MOVLconst [c]) x)
  1251  	// result: (ADDLconst [c] x)
  1252  	for {
  1253  		x := v.Args[1]
  1254  		v_0 := v.Args[0]
  1255  		if v_0.Op != OpAMD64MOVLconst {
  1256  			break
  1257  		}
  1258  		c := v_0.AuxInt
  1259  		v.reset(OpAMD64ADDLconst)
  1260  		v.AuxInt = c
  1261  		v.AddArg(x)
  1262  		return true
  1263  	}
  1264  	// match: (ADDL (SHLLconst x [c]) (SHRLconst x [d]))
  1265  	// cond: d==32-c
  1266  	// result: (ROLLconst x [c])
  1267  	for {
  1268  		_ = v.Args[1]
  1269  		v_0 := v.Args[0]
  1270  		if v_0.Op != OpAMD64SHLLconst {
  1271  			break
  1272  		}
  1273  		c := v_0.AuxInt
  1274  		x := v_0.Args[0]
  1275  		v_1 := v.Args[1]
  1276  		if v_1.Op != OpAMD64SHRLconst {
  1277  			break
  1278  		}
  1279  		d := v_1.AuxInt
  1280  		if x != v_1.Args[0] || !(d == 32-c) {
  1281  			break
  1282  		}
  1283  		v.reset(OpAMD64ROLLconst)
  1284  		v.AuxInt = c
  1285  		v.AddArg(x)
  1286  		return true
  1287  	}
  1288  	// match: (ADDL (SHRLconst x [d]) (SHLLconst x [c]))
  1289  	// cond: d==32-c
  1290  	// result: (ROLLconst x [c])
  1291  	for {
  1292  		_ = v.Args[1]
  1293  		v_0 := v.Args[0]
  1294  		if v_0.Op != OpAMD64SHRLconst {
  1295  			break
  1296  		}
  1297  		d := v_0.AuxInt
  1298  		x := v_0.Args[0]
  1299  		v_1 := v.Args[1]
  1300  		if v_1.Op != OpAMD64SHLLconst {
  1301  			break
  1302  		}
  1303  		c := v_1.AuxInt
  1304  		if x != v_1.Args[0] || !(d == 32-c) {
  1305  			break
  1306  		}
  1307  		v.reset(OpAMD64ROLLconst)
  1308  		v.AuxInt = c
  1309  		v.AddArg(x)
  1310  		return true
  1311  	}
  1312  	// match: (ADDL <t> (SHLLconst x [c]) (SHRWconst x [d]))
  1313  	// cond: d==16-c && c < 16 && t.Size() == 2
  1314  	// result: (ROLWconst x [c])
  1315  	for {
  1316  		t := v.Type
  1317  		_ = v.Args[1]
  1318  		v_0 := v.Args[0]
  1319  		if v_0.Op != OpAMD64SHLLconst {
  1320  			break
  1321  		}
  1322  		c := v_0.AuxInt
  1323  		x := v_0.Args[0]
  1324  		v_1 := v.Args[1]
  1325  		if v_1.Op != OpAMD64SHRWconst {
  1326  			break
  1327  		}
  1328  		d := v_1.AuxInt
  1329  		if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) {
  1330  			break
  1331  		}
  1332  		v.reset(OpAMD64ROLWconst)
  1333  		v.AuxInt = c
  1334  		v.AddArg(x)
  1335  		return true
  1336  	}
  1337  	// match: (ADDL <t> (SHRWconst x [d]) (SHLLconst x [c]))
  1338  	// cond: d==16-c && c < 16 && t.Size() == 2
  1339  	// result: (ROLWconst x [c])
  1340  	for {
  1341  		t := v.Type
  1342  		_ = v.Args[1]
  1343  		v_0 := v.Args[0]
  1344  		if v_0.Op != OpAMD64SHRWconst {
  1345  			break
  1346  		}
  1347  		d := v_0.AuxInt
  1348  		x := v_0.Args[0]
  1349  		v_1 := v.Args[1]
  1350  		if v_1.Op != OpAMD64SHLLconst {
  1351  			break
  1352  		}
  1353  		c := v_1.AuxInt
  1354  		if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) {
  1355  			break
  1356  		}
  1357  		v.reset(OpAMD64ROLWconst)
  1358  		v.AuxInt = c
  1359  		v.AddArg(x)
  1360  		return true
  1361  	}
  1362  	// match: (ADDL <t> (SHLLconst x [c]) (SHRBconst x [d]))
  1363  	// cond: d==8-c && c < 8 && t.Size() == 1
  1364  	// result: (ROLBconst x [c])
  1365  	for {
  1366  		t := v.Type
  1367  		_ = v.Args[1]
  1368  		v_0 := v.Args[0]
  1369  		if v_0.Op != OpAMD64SHLLconst {
  1370  			break
  1371  		}
  1372  		c := v_0.AuxInt
  1373  		x := v_0.Args[0]
  1374  		v_1 := v.Args[1]
  1375  		if v_1.Op != OpAMD64SHRBconst {
  1376  			break
  1377  		}
  1378  		d := v_1.AuxInt
  1379  		if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) {
  1380  			break
  1381  		}
  1382  		v.reset(OpAMD64ROLBconst)
  1383  		v.AuxInt = c
  1384  		v.AddArg(x)
  1385  		return true
  1386  	}
  1387  	// match: (ADDL <t> (SHRBconst x [d]) (SHLLconst x [c]))
  1388  	// cond: d==8-c && c < 8 && t.Size() == 1
  1389  	// result: (ROLBconst x [c])
  1390  	for {
  1391  		t := v.Type
  1392  		_ = v.Args[1]
  1393  		v_0 := v.Args[0]
  1394  		if v_0.Op != OpAMD64SHRBconst {
  1395  			break
  1396  		}
  1397  		d := v_0.AuxInt
  1398  		x := v_0.Args[0]
  1399  		v_1 := v.Args[1]
  1400  		if v_1.Op != OpAMD64SHLLconst {
  1401  			break
  1402  		}
  1403  		c := v_1.AuxInt
  1404  		if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) {
  1405  			break
  1406  		}
  1407  		v.reset(OpAMD64ROLBconst)
  1408  		v.AuxInt = c
  1409  		v.AddArg(x)
  1410  		return true
  1411  	}
  1412  	// match: (ADDL x (SHLLconst [3] y))
  1413  	// result: (LEAL8 x y)
  1414  	for {
  1415  		_ = v.Args[1]
  1416  		x := v.Args[0]
  1417  		v_1 := v.Args[1]
  1418  		if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 {
  1419  			break
  1420  		}
  1421  		y := v_1.Args[0]
  1422  		v.reset(OpAMD64LEAL8)
  1423  		v.AddArg(x)
  1424  		v.AddArg(y)
  1425  		return true
  1426  	}
  1427  	// match: (ADDL (SHLLconst [3] y) x)
  1428  	// result: (LEAL8 x y)
  1429  	for {
  1430  		x := v.Args[1]
  1431  		v_0 := v.Args[0]
  1432  		if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 3 {
  1433  			break
  1434  		}
  1435  		y := v_0.Args[0]
  1436  		v.reset(OpAMD64LEAL8)
  1437  		v.AddArg(x)
  1438  		v.AddArg(y)
  1439  		return true
  1440  	}
  1441  	return false
  1442  }
  1443  func rewriteValueAMD64_OpAMD64ADDL_10(v *Value) bool {
  1444  	// match: (ADDL x (SHLLconst [2] y))
  1445  	// result: (LEAL4 x y)
  1446  	for {
  1447  		_ = v.Args[1]
  1448  		x := v.Args[0]
  1449  		v_1 := v.Args[1]
  1450  		if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 {
  1451  			break
  1452  		}
  1453  		y := v_1.Args[0]
  1454  		v.reset(OpAMD64LEAL4)
  1455  		v.AddArg(x)
  1456  		v.AddArg(y)
  1457  		return true
  1458  	}
  1459  	// match: (ADDL (SHLLconst [2] y) x)
  1460  	// result: (LEAL4 x y)
  1461  	for {
  1462  		x := v.Args[1]
  1463  		v_0 := v.Args[0]
  1464  		if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 2 {
  1465  			break
  1466  		}
  1467  		y := v_0.Args[0]
  1468  		v.reset(OpAMD64LEAL4)
  1469  		v.AddArg(x)
  1470  		v.AddArg(y)
  1471  		return true
  1472  	}
  1473  	// match: (ADDL x (SHLLconst [1] y))
  1474  	// result: (LEAL2 x y)
  1475  	for {
  1476  		_ = v.Args[1]
  1477  		x := v.Args[0]
  1478  		v_1 := v.Args[1]
  1479  		if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 {
  1480  			break
  1481  		}
  1482  		y := v_1.Args[0]
  1483  		v.reset(OpAMD64LEAL2)
  1484  		v.AddArg(x)
  1485  		v.AddArg(y)
  1486  		return true
  1487  	}
  1488  	// match: (ADDL (SHLLconst [1] y) x)
  1489  	// result: (LEAL2 x y)
  1490  	for {
  1491  		x := v.Args[1]
  1492  		v_0 := v.Args[0]
  1493  		if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 {
  1494  			break
  1495  		}
  1496  		y := v_0.Args[0]
  1497  		v.reset(OpAMD64LEAL2)
  1498  		v.AddArg(x)
  1499  		v.AddArg(y)
  1500  		return true
  1501  	}
  1502  	// match: (ADDL x (ADDL y y))
  1503  	// result: (LEAL2 x y)
  1504  	for {
  1505  		_ = v.Args[1]
  1506  		x := v.Args[0]
  1507  		v_1 := v.Args[1]
  1508  		if v_1.Op != OpAMD64ADDL {
  1509  			break
  1510  		}
  1511  		y := v_1.Args[1]
  1512  		if y != v_1.Args[0] {
  1513  			break
  1514  		}
  1515  		v.reset(OpAMD64LEAL2)
  1516  		v.AddArg(x)
  1517  		v.AddArg(y)
  1518  		return true
  1519  	}
  1520  	// match: (ADDL (ADDL y y) x)
  1521  	// result: (LEAL2 x y)
  1522  	for {
  1523  		x := v.Args[1]
  1524  		v_0 := v.Args[0]
  1525  		if v_0.Op != OpAMD64ADDL {
  1526  			break
  1527  		}
  1528  		y := v_0.Args[1]
  1529  		if y != v_0.Args[0] {
  1530  			break
  1531  		}
  1532  		v.reset(OpAMD64LEAL2)
  1533  		v.AddArg(x)
  1534  		v.AddArg(y)
  1535  		return true
  1536  	}
  1537  	// match: (ADDL x (ADDL x y))
  1538  	// result: (LEAL2 y x)
  1539  	for {
  1540  		_ = v.Args[1]
  1541  		x := v.Args[0]
  1542  		v_1 := v.Args[1]
  1543  		if v_1.Op != OpAMD64ADDL {
  1544  			break
  1545  		}
  1546  		y := v_1.Args[1]
  1547  		if x != v_1.Args[0] {
  1548  			break
  1549  		}
  1550  		v.reset(OpAMD64LEAL2)
  1551  		v.AddArg(y)
  1552  		v.AddArg(x)
  1553  		return true
  1554  	}
  1555  	// match: (ADDL x (ADDL y x))
  1556  	// result: (LEAL2 y x)
  1557  	for {
  1558  		_ = v.Args[1]
  1559  		x := v.Args[0]
  1560  		v_1 := v.Args[1]
  1561  		if v_1.Op != OpAMD64ADDL {
  1562  			break
  1563  		}
  1564  		_ = v_1.Args[1]
  1565  		y := v_1.Args[0]
  1566  		if x != v_1.Args[1] {
  1567  			break
  1568  		}
  1569  		v.reset(OpAMD64LEAL2)
  1570  		v.AddArg(y)
  1571  		v.AddArg(x)
  1572  		return true
  1573  	}
  1574  	// match: (ADDL (ADDL x y) x)
  1575  	// result: (LEAL2 y x)
  1576  	for {
  1577  		x := v.Args[1]
  1578  		v_0 := v.Args[0]
  1579  		if v_0.Op != OpAMD64ADDL {
  1580  			break
  1581  		}
  1582  		y := v_0.Args[1]
  1583  		if x != v_0.Args[0] {
  1584  			break
  1585  		}
  1586  		v.reset(OpAMD64LEAL2)
  1587  		v.AddArg(y)
  1588  		v.AddArg(x)
  1589  		return true
  1590  	}
  1591  	// match: (ADDL (ADDL y x) x)
  1592  	// result: (LEAL2 y x)
  1593  	for {
  1594  		x := v.Args[1]
  1595  		v_0 := v.Args[0]
  1596  		if v_0.Op != OpAMD64ADDL {
  1597  			break
  1598  		}
  1599  		_ = v_0.Args[1]
  1600  		y := v_0.Args[0]
  1601  		if x != v_0.Args[1] {
  1602  			break
  1603  		}
  1604  		v.reset(OpAMD64LEAL2)
  1605  		v.AddArg(y)
  1606  		v.AddArg(x)
  1607  		return true
  1608  	}
  1609  	return false
  1610  }
  1611  func rewriteValueAMD64_OpAMD64ADDL_20(v *Value) bool {
  1612  	// match: (ADDL (ADDLconst [c] x) y)
  1613  	// result: (LEAL1 [c] x y)
  1614  	for {
  1615  		y := v.Args[1]
  1616  		v_0 := v.Args[0]
  1617  		if v_0.Op != OpAMD64ADDLconst {
  1618  			break
  1619  		}
  1620  		c := v_0.AuxInt
  1621  		x := v_0.Args[0]
  1622  		v.reset(OpAMD64LEAL1)
  1623  		v.AuxInt = c
  1624  		v.AddArg(x)
  1625  		v.AddArg(y)
  1626  		return true
  1627  	}
  1628  	// match: (ADDL y (ADDLconst [c] x))
  1629  	// result: (LEAL1 [c] x y)
  1630  	for {
  1631  		_ = v.Args[1]
  1632  		y := v.Args[0]
  1633  		v_1 := v.Args[1]
  1634  		if v_1.Op != OpAMD64ADDLconst {
  1635  			break
  1636  		}
  1637  		c := v_1.AuxInt
  1638  		x := v_1.Args[0]
  1639  		v.reset(OpAMD64LEAL1)
  1640  		v.AuxInt = c
  1641  		v.AddArg(x)
  1642  		v.AddArg(y)
  1643  		return true
  1644  	}
  1645  	// match: (ADDL x (LEAL [c] {s} y))
  1646  	// cond: x.Op != OpSB && y.Op != OpSB
  1647  	// result: (LEAL1 [c] {s} x y)
  1648  	for {
  1649  		_ = v.Args[1]
  1650  		x := v.Args[0]
  1651  		v_1 := v.Args[1]
  1652  		if v_1.Op != OpAMD64LEAL {
  1653  			break
  1654  		}
  1655  		c := v_1.AuxInt
  1656  		s := v_1.Aux
  1657  		y := v_1.Args[0]
  1658  		if !(x.Op != OpSB && y.Op != OpSB) {
  1659  			break
  1660  		}
  1661  		v.reset(OpAMD64LEAL1)
  1662  		v.AuxInt = c
  1663  		v.Aux = s
  1664  		v.AddArg(x)
  1665  		v.AddArg(y)
  1666  		return true
  1667  	}
  1668  	// match: (ADDL (LEAL [c] {s} y) x)
  1669  	// cond: x.Op != OpSB && y.Op != OpSB
  1670  	// result: (LEAL1 [c] {s} x y)
  1671  	for {
  1672  		x := v.Args[1]
  1673  		v_0 := v.Args[0]
  1674  		if v_0.Op != OpAMD64LEAL {
  1675  			break
  1676  		}
  1677  		c := v_0.AuxInt
  1678  		s := v_0.Aux
  1679  		y := v_0.Args[0]
  1680  		if !(x.Op != OpSB && y.Op != OpSB) {
  1681  			break
  1682  		}
  1683  		v.reset(OpAMD64LEAL1)
  1684  		v.AuxInt = c
  1685  		v.Aux = s
  1686  		v.AddArg(x)
  1687  		v.AddArg(y)
  1688  		return true
  1689  	}
  1690  	// match: (ADDL x (NEGL y))
  1691  	// result: (SUBL x y)
  1692  	for {
  1693  		_ = v.Args[1]
  1694  		x := v.Args[0]
  1695  		v_1 := v.Args[1]
  1696  		if v_1.Op != OpAMD64NEGL {
  1697  			break
  1698  		}
  1699  		y := v_1.Args[0]
  1700  		v.reset(OpAMD64SUBL)
  1701  		v.AddArg(x)
  1702  		v.AddArg(y)
  1703  		return true
  1704  	}
  1705  	// match: (ADDL (NEGL y) x)
  1706  	// result: (SUBL x y)
  1707  	for {
  1708  		x := v.Args[1]
  1709  		v_0 := v.Args[0]
  1710  		if v_0.Op != OpAMD64NEGL {
  1711  			break
  1712  		}
  1713  		y := v_0.Args[0]
  1714  		v.reset(OpAMD64SUBL)
  1715  		v.AddArg(x)
  1716  		v.AddArg(y)
  1717  		return true
  1718  	}
  1719  	// match: (ADDL x l:(MOVLload [off] {sym} ptr mem))
  1720  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  1721  	// result: (ADDLload x [off] {sym} ptr mem)
  1722  	for {
  1723  		_ = v.Args[1]
  1724  		x := v.Args[0]
  1725  		l := v.Args[1]
  1726  		if l.Op != OpAMD64MOVLload {
  1727  			break
  1728  		}
  1729  		off := l.AuxInt
  1730  		sym := l.Aux
  1731  		mem := l.Args[1]
  1732  		ptr := l.Args[0]
  1733  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  1734  			break
  1735  		}
  1736  		v.reset(OpAMD64ADDLload)
  1737  		v.AuxInt = off
  1738  		v.Aux = sym
  1739  		v.AddArg(x)
  1740  		v.AddArg(ptr)
  1741  		v.AddArg(mem)
  1742  		return true
  1743  	}
  1744  	// match: (ADDL l:(MOVLload [off] {sym} ptr mem) x)
  1745  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  1746  	// result: (ADDLload x [off] {sym} ptr mem)
  1747  	for {
  1748  		x := v.Args[1]
  1749  		l := v.Args[0]
  1750  		if l.Op != OpAMD64MOVLload {
  1751  			break
  1752  		}
  1753  		off := l.AuxInt
  1754  		sym := l.Aux
  1755  		mem := l.Args[1]
  1756  		ptr := l.Args[0]
  1757  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  1758  			break
  1759  		}
  1760  		v.reset(OpAMD64ADDLload)
  1761  		v.AuxInt = off
  1762  		v.Aux = sym
  1763  		v.AddArg(x)
  1764  		v.AddArg(ptr)
  1765  		v.AddArg(mem)
  1766  		return true
  1767  	}
  1768  	return false
  1769  }
  1770  func rewriteValueAMD64_OpAMD64ADDLconst_0(v *Value) bool {
  1771  	// match: (ADDLconst [c] (ADDL x y))
  1772  	// result: (LEAL1 [c] x y)
  1773  	for {
  1774  		c := v.AuxInt
  1775  		v_0 := v.Args[0]
  1776  		if v_0.Op != OpAMD64ADDL {
  1777  			break
  1778  		}
  1779  		y := v_0.Args[1]
  1780  		x := v_0.Args[0]
  1781  		v.reset(OpAMD64LEAL1)
  1782  		v.AuxInt = c
  1783  		v.AddArg(x)
  1784  		v.AddArg(y)
  1785  		return true
  1786  	}
  1787  	// match: (ADDLconst [c] (SHLLconst [1] x))
  1788  	// result: (LEAL1 [c] x x)
  1789  	for {
  1790  		c := v.AuxInt
  1791  		v_0 := v.Args[0]
  1792  		if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 {
  1793  			break
  1794  		}
  1795  		x := v_0.Args[0]
  1796  		v.reset(OpAMD64LEAL1)
  1797  		v.AuxInt = c
  1798  		v.AddArg(x)
  1799  		v.AddArg(x)
  1800  		return true
  1801  	}
  1802  	// match: (ADDLconst [c] (LEAL [d] {s} x))
  1803  	// cond: is32Bit(c+d)
  1804  	// result: (LEAL [c+d] {s} x)
  1805  	for {
  1806  		c := v.AuxInt
  1807  		v_0 := v.Args[0]
  1808  		if v_0.Op != OpAMD64LEAL {
  1809  			break
  1810  		}
  1811  		d := v_0.AuxInt
  1812  		s := v_0.Aux
  1813  		x := v_0.Args[0]
  1814  		if !(is32Bit(c + d)) {
  1815  			break
  1816  		}
  1817  		v.reset(OpAMD64LEAL)
  1818  		v.AuxInt = c + d
  1819  		v.Aux = s
  1820  		v.AddArg(x)
  1821  		return true
  1822  	}
  1823  	// match: (ADDLconst [c] (LEAL1 [d] {s} x y))
  1824  	// cond: is32Bit(c+d)
  1825  	// result: (LEAL1 [c+d] {s} x y)
  1826  	for {
  1827  		c := v.AuxInt
  1828  		v_0 := v.Args[0]
  1829  		if v_0.Op != OpAMD64LEAL1 {
  1830  			break
  1831  		}
  1832  		d := v_0.AuxInt
  1833  		s := v_0.Aux
  1834  		y := v_0.Args[1]
  1835  		x := v_0.Args[0]
  1836  		if !(is32Bit(c + d)) {
  1837  			break
  1838  		}
  1839  		v.reset(OpAMD64LEAL1)
  1840  		v.AuxInt = c + d
  1841  		v.Aux = s
  1842  		v.AddArg(x)
  1843  		v.AddArg(y)
  1844  		return true
  1845  	}
  1846  	// match: (ADDLconst [c] (LEAL2 [d] {s} x y))
  1847  	// cond: is32Bit(c+d)
  1848  	// result: (LEAL2 [c+d] {s} x y)
  1849  	for {
  1850  		c := v.AuxInt
  1851  		v_0 := v.Args[0]
  1852  		if v_0.Op != OpAMD64LEAL2 {
  1853  			break
  1854  		}
  1855  		d := v_0.AuxInt
  1856  		s := v_0.Aux
  1857  		y := v_0.Args[1]
  1858  		x := v_0.Args[0]
  1859  		if !(is32Bit(c + d)) {
  1860  			break
  1861  		}
  1862  		v.reset(OpAMD64LEAL2)
  1863  		v.AuxInt = c + d
  1864  		v.Aux = s
  1865  		v.AddArg(x)
  1866  		v.AddArg(y)
  1867  		return true
  1868  	}
  1869  	// match: (ADDLconst [c] (LEAL4 [d] {s} x y))
  1870  	// cond: is32Bit(c+d)
  1871  	// result: (LEAL4 [c+d] {s} x y)
  1872  	for {
  1873  		c := v.AuxInt
  1874  		v_0 := v.Args[0]
  1875  		if v_0.Op != OpAMD64LEAL4 {
  1876  			break
  1877  		}
  1878  		d := v_0.AuxInt
  1879  		s := v_0.Aux
  1880  		y := v_0.Args[1]
  1881  		x := v_0.Args[0]
  1882  		if !(is32Bit(c + d)) {
  1883  			break
  1884  		}
  1885  		v.reset(OpAMD64LEAL4)
  1886  		v.AuxInt = c + d
  1887  		v.Aux = s
  1888  		v.AddArg(x)
  1889  		v.AddArg(y)
  1890  		return true
  1891  	}
  1892  	// match: (ADDLconst [c] (LEAL8 [d] {s} x y))
  1893  	// cond: is32Bit(c+d)
  1894  	// result: (LEAL8 [c+d] {s} x y)
  1895  	for {
  1896  		c := v.AuxInt
  1897  		v_0 := v.Args[0]
  1898  		if v_0.Op != OpAMD64LEAL8 {
  1899  			break
  1900  		}
  1901  		d := v_0.AuxInt
  1902  		s := v_0.Aux
  1903  		y := v_0.Args[1]
  1904  		x := v_0.Args[0]
  1905  		if !(is32Bit(c + d)) {
  1906  			break
  1907  		}
  1908  		v.reset(OpAMD64LEAL8)
  1909  		v.AuxInt = c + d
  1910  		v.Aux = s
  1911  		v.AddArg(x)
  1912  		v.AddArg(y)
  1913  		return true
  1914  	}
  1915  	// match: (ADDLconst [c] x)
  1916  	// cond: int32(c)==0
  1917  	// result: x
  1918  	for {
  1919  		c := v.AuxInt
  1920  		x := v.Args[0]
  1921  		if !(int32(c) == 0) {
  1922  			break
  1923  		}
  1924  		v.reset(OpCopy)
  1925  		v.Type = x.Type
  1926  		v.AddArg(x)
  1927  		return true
  1928  	}
  1929  	// match: (ADDLconst [c] (MOVLconst [d]))
  1930  	// result: (MOVLconst [int64(int32(c+d))])
  1931  	for {
  1932  		c := v.AuxInt
  1933  		v_0 := v.Args[0]
  1934  		if v_0.Op != OpAMD64MOVLconst {
  1935  			break
  1936  		}
  1937  		d := v_0.AuxInt
  1938  		v.reset(OpAMD64MOVLconst)
  1939  		v.AuxInt = int64(int32(c + d))
  1940  		return true
  1941  	}
  1942  	// match: (ADDLconst [c] (ADDLconst [d] x))
  1943  	// result: (ADDLconst [int64(int32(c+d))] x)
  1944  	for {
  1945  		c := v.AuxInt
  1946  		v_0 := v.Args[0]
  1947  		if v_0.Op != OpAMD64ADDLconst {
  1948  			break
  1949  		}
  1950  		d := v_0.AuxInt
  1951  		x := v_0.Args[0]
  1952  		v.reset(OpAMD64ADDLconst)
  1953  		v.AuxInt = int64(int32(c + d))
  1954  		v.AddArg(x)
  1955  		return true
  1956  	}
  1957  	return false
  1958  }
  1959  func rewriteValueAMD64_OpAMD64ADDLconst_10(v *Value) bool {
  1960  	// match: (ADDLconst [off] x:(SP))
  1961  	// result: (LEAL [off] x)
  1962  	for {
  1963  		off := v.AuxInt
  1964  		x := v.Args[0]
  1965  		if x.Op != OpSP {
  1966  			break
  1967  		}
  1968  		v.reset(OpAMD64LEAL)
  1969  		v.AuxInt = off
  1970  		v.AddArg(x)
  1971  		return true
  1972  	}
  1973  	return false
  1974  }
  1975  func rewriteValueAMD64_OpAMD64ADDLconstmodify_0(v *Value) bool {
  1976  	// match: (ADDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  1977  	// cond: ValAndOff(valoff1).canAdd(off2)
  1978  	// result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  1979  	for {
  1980  		valoff1 := v.AuxInt
  1981  		sym := v.Aux
  1982  		mem := v.Args[1]
  1983  		v_0 := v.Args[0]
  1984  		if v_0.Op != OpAMD64ADDQconst {
  1985  			break
  1986  		}
  1987  		off2 := v_0.AuxInt
  1988  		base := v_0.Args[0]
  1989  		if !(ValAndOff(valoff1).canAdd(off2)) {
  1990  			break
  1991  		}
  1992  		v.reset(OpAMD64ADDLconstmodify)
  1993  		v.AuxInt = ValAndOff(valoff1).add(off2)
  1994  		v.Aux = sym
  1995  		v.AddArg(base)
  1996  		v.AddArg(mem)
  1997  		return true
  1998  	}
  1999  	// match: (ADDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  2000  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  2001  	// result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  2002  	for {
  2003  		valoff1 := v.AuxInt
  2004  		sym1 := v.Aux
  2005  		mem := v.Args[1]
  2006  		v_0 := v.Args[0]
  2007  		if v_0.Op != OpAMD64LEAQ {
  2008  			break
  2009  		}
  2010  		off2 := v_0.AuxInt
  2011  		sym2 := v_0.Aux
  2012  		base := v_0.Args[0]
  2013  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  2014  			break
  2015  		}
  2016  		v.reset(OpAMD64ADDLconstmodify)
  2017  		v.AuxInt = ValAndOff(valoff1).add(off2)
  2018  		v.Aux = mergeSym(sym1, sym2)
  2019  		v.AddArg(base)
  2020  		v.AddArg(mem)
  2021  		return true
  2022  	}
  2023  	return false
  2024  }
  2025  func rewriteValueAMD64_OpAMD64ADDLload_0(v *Value) bool {
  2026  	b := v.Block
  2027  	typ := &b.Func.Config.Types
  2028  	// match: (ADDLload [off1] {sym} val (ADDQconst [off2] base) mem)
  2029  	// cond: is32Bit(off1+off2)
  2030  	// result: (ADDLload [off1+off2] {sym} val base mem)
  2031  	for {
  2032  		off1 := v.AuxInt
  2033  		sym := v.Aux
  2034  		mem := v.Args[2]
  2035  		val := v.Args[0]
  2036  		v_1 := v.Args[1]
  2037  		if v_1.Op != OpAMD64ADDQconst {
  2038  			break
  2039  		}
  2040  		off2 := v_1.AuxInt
  2041  		base := v_1.Args[0]
  2042  		if !(is32Bit(off1 + off2)) {
  2043  			break
  2044  		}
  2045  		v.reset(OpAMD64ADDLload)
  2046  		v.AuxInt = off1 + off2
  2047  		v.Aux = sym
  2048  		v.AddArg(val)
  2049  		v.AddArg(base)
  2050  		v.AddArg(mem)
  2051  		return true
  2052  	}
  2053  	// match: (ADDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
  2054  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  2055  	// result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  2056  	for {
  2057  		off1 := v.AuxInt
  2058  		sym1 := v.Aux
  2059  		mem := v.Args[2]
  2060  		val := v.Args[0]
  2061  		v_1 := v.Args[1]
  2062  		if v_1.Op != OpAMD64LEAQ {
  2063  			break
  2064  		}
  2065  		off2 := v_1.AuxInt
  2066  		sym2 := v_1.Aux
  2067  		base := v_1.Args[0]
  2068  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  2069  			break
  2070  		}
  2071  		v.reset(OpAMD64ADDLload)
  2072  		v.AuxInt = off1 + off2
  2073  		v.Aux = mergeSym(sym1, sym2)
  2074  		v.AddArg(val)
  2075  		v.AddArg(base)
  2076  		v.AddArg(mem)
  2077  		return true
  2078  	}
  2079  	// match: (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _))
  2080  	// result: (ADDL x (MOVLf2i y))
  2081  	for {
  2082  		off := v.AuxInt
  2083  		sym := v.Aux
  2084  		_ = v.Args[2]
  2085  		x := v.Args[0]
  2086  		ptr := v.Args[1]
  2087  		v_2 := v.Args[2]
  2088  		if v_2.Op != OpAMD64MOVSSstore || v_2.AuxInt != off || v_2.Aux != sym {
  2089  			break
  2090  		}
  2091  		_ = v_2.Args[2]
  2092  		if ptr != v_2.Args[0] {
  2093  			break
  2094  		}
  2095  		y := v_2.Args[1]
  2096  		v.reset(OpAMD64ADDL)
  2097  		v.AddArg(x)
  2098  		v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32)
  2099  		v0.AddArg(y)
  2100  		v.AddArg(v0)
  2101  		return true
  2102  	}
  2103  	return false
  2104  }
  2105  func rewriteValueAMD64_OpAMD64ADDLmodify_0(v *Value) bool {
  2106  	// match: (ADDLmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  2107  	// cond: is32Bit(off1+off2)
  2108  	// result: (ADDLmodify [off1+off2] {sym} base val mem)
  2109  	for {
  2110  		off1 := v.AuxInt
  2111  		sym := v.Aux
  2112  		mem := v.Args[2]
  2113  		v_0 := v.Args[0]
  2114  		if v_0.Op != OpAMD64ADDQconst {
  2115  			break
  2116  		}
  2117  		off2 := v_0.AuxInt
  2118  		base := v_0.Args[0]
  2119  		val := v.Args[1]
  2120  		if !(is32Bit(off1 + off2)) {
  2121  			break
  2122  		}
  2123  		v.reset(OpAMD64ADDLmodify)
  2124  		v.AuxInt = off1 + off2
  2125  		v.Aux = sym
  2126  		v.AddArg(base)
  2127  		v.AddArg(val)
  2128  		v.AddArg(mem)
  2129  		return true
  2130  	}
  2131  	// match: (ADDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  2132  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  2133  	// result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  2134  	for {
  2135  		off1 := v.AuxInt
  2136  		sym1 := v.Aux
  2137  		mem := v.Args[2]
  2138  		v_0 := v.Args[0]
  2139  		if v_0.Op != OpAMD64LEAQ {
  2140  			break
  2141  		}
  2142  		off2 := v_0.AuxInt
  2143  		sym2 := v_0.Aux
  2144  		base := v_0.Args[0]
  2145  		val := v.Args[1]
  2146  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  2147  			break
  2148  		}
  2149  		v.reset(OpAMD64ADDLmodify)
  2150  		v.AuxInt = off1 + off2
  2151  		v.Aux = mergeSym(sym1, sym2)
  2152  		v.AddArg(base)
  2153  		v.AddArg(val)
  2154  		v.AddArg(mem)
  2155  		return true
  2156  	}
  2157  	return false
  2158  }
  2159  func rewriteValueAMD64_OpAMD64ADDQ_0(v *Value) bool {
  2160  	// match: (ADDQ x (MOVQconst [c]))
  2161  	// cond: is32Bit(c)
  2162  	// result: (ADDQconst [c] x)
  2163  	for {
  2164  		_ = v.Args[1]
  2165  		x := v.Args[0]
  2166  		v_1 := v.Args[1]
  2167  		if v_1.Op != OpAMD64MOVQconst {
  2168  			break
  2169  		}
  2170  		c := v_1.AuxInt
  2171  		if !(is32Bit(c)) {
  2172  			break
  2173  		}
  2174  		v.reset(OpAMD64ADDQconst)
  2175  		v.AuxInt = c
  2176  		v.AddArg(x)
  2177  		return true
  2178  	}
  2179  	// match: (ADDQ (MOVQconst [c]) x)
  2180  	// cond: is32Bit(c)
  2181  	// result: (ADDQconst [c] x)
  2182  	for {
  2183  		x := v.Args[1]
  2184  		v_0 := v.Args[0]
  2185  		if v_0.Op != OpAMD64MOVQconst {
  2186  			break
  2187  		}
  2188  		c := v_0.AuxInt
  2189  		if !(is32Bit(c)) {
  2190  			break
  2191  		}
  2192  		v.reset(OpAMD64ADDQconst)
  2193  		v.AuxInt = c
  2194  		v.AddArg(x)
  2195  		return true
  2196  	}
  2197  	// match: (ADDQ (SHLQconst x [c]) (SHRQconst x [d]))
  2198  	// cond: d==64-c
  2199  	// result: (ROLQconst x [c])
  2200  	for {
  2201  		_ = v.Args[1]
  2202  		v_0 := v.Args[0]
  2203  		if v_0.Op != OpAMD64SHLQconst {
  2204  			break
  2205  		}
  2206  		c := v_0.AuxInt
  2207  		x := v_0.Args[0]
  2208  		v_1 := v.Args[1]
  2209  		if v_1.Op != OpAMD64SHRQconst {
  2210  			break
  2211  		}
  2212  		d := v_1.AuxInt
  2213  		if x != v_1.Args[0] || !(d == 64-c) {
  2214  			break
  2215  		}
  2216  		v.reset(OpAMD64ROLQconst)
  2217  		v.AuxInt = c
  2218  		v.AddArg(x)
  2219  		return true
  2220  	}
  2221  	// match: (ADDQ (SHRQconst x [d]) (SHLQconst x [c]))
  2222  	// cond: d==64-c
  2223  	// result: (ROLQconst x [c])
  2224  	for {
  2225  		_ = v.Args[1]
  2226  		v_0 := v.Args[0]
  2227  		if v_0.Op != OpAMD64SHRQconst {
  2228  			break
  2229  		}
  2230  		d := v_0.AuxInt
  2231  		x := v_0.Args[0]
  2232  		v_1 := v.Args[1]
  2233  		if v_1.Op != OpAMD64SHLQconst {
  2234  			break
  2235  		}
  2236  		c := v_1.AuxInt
  2237  		if x != v_1.Args[0] || !(d == 64-c) {
  2238  			break
  2239  		}
  2240  		v.reset(OpAMD64ROLQconst)
  2241  		v.AuxInt = c
  2242  		v.AddArg(x)
  2243  		return true
  2244  	}
  2245  	// match: (ADDQ x (SHLQconst [3] y))
  2246  	// result: (LEAQ8 x y)
  2247  	for {
  2248  		_ = v.Args[1]
  2249  		x := v.Args[0]
  2250  		v_1 := v.Args[1]
  2251  		if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 {
  2252  			break
  2253  		}
  2254  		y := v_1.Args[0]
  2255  		v.reset(OpAMD64LEAQ8)
  2256  		v.AddArg(x)
  2257  		v.AddArg(y)
  2258  		return true
  2259  	}
  2260  	// match: (ADDQ (SHLQconst [3] y) x)
  2261  	// result: (LEAQ8 x y)
  2262  	for {
  2263  		x := v.Args[1]
  2264  		v_0 := v.Args[0]
  2265  		if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 {
  2266  			break
  2267  		}
  2268  		y := v_0.Args[0]
  2269  		v.reset(OpAMD64LEAQ8)
  2270  		v.AddArg(x)
  2271  		v.AddArg(y)
  2272  		return true
  2273  	}
  2274  	// match: (ADDQ x (SHLQconst [2] y))
  2275  	// result: (LEAQ4 x y)
  2276  	for {
  2277  		_ = v.Args[1]
  2278  		x := v.Args[0]
  2279  		v_1 := v.Args[1]
  2280  		if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 {
  2281  			break
  2282  		}
  2283  		y := v_1.Args[0]
  2284  		v.reset(OpAMD64LEAQ4)
  2285  		v.AddArg(x)
  2286  		v.AddArg(y)
  2287  		return true
  2288  	}
  2289  	// match: (ADDQ (SHLQconst [2] y) x)
  2290  	// result: (LEAQ4 x y)
  2291  	for {
  2292  		x := v.Args[1]
  2293  		v_0 := v.Args[0]
  2294  		if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 2 {
  2295  			break
  2296  		}
  2297  		y := v_0.Args[0]
  2298  		v.reset(OpAMD64LEAQ4)
  2299  		v.AddArg(x)
  2300  		v.AddArg(y)
  2301  		return true
  2302  	}
  2303  	// match: (ADDQ x (SHLQconst [1] y))
  2304  	// result: (LEAQ2 x y)
  2305  	for {
  2306  		_ = v.Args[1]
  2307  		x := v.Args[0]
  2308  		v_1 := v.Args[1]
  2309  		if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 {
  2310  			break
  2311  		}
  2312  		y := v_1.Args[0]
  2313  		v.reset(OpAMD64LEAQ2)
  2314  		v.AddArg(x)
  2315  		v.AddArg(y)
  2316  		return true
  2317  	}
  2318  	// match: (ADDQ (SHLQconst [1] y) x)
  2319  	// result: (LEAQ2 x y)
  2320  	for {
  2321  		x := v.Args[1]
  2322  		v_0 := v.Args[0]
  2323  		if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 {
  2324  			break
  2325  		}
  2326  		y := v_0.Args[0]
  2327  		v.reset(OpAMD64LEAQ2)
  2328  		v.AddArg(x)
  2329  		v.AddArg(y)
  2330  		return true
  2331  	}
  2332  	return false
  2333  }
  2334  func rewriteValueAMD64_OpAMD64ADDQ_10(v *Value) bool {
  2335  	// match: (ADDQ x (ADDQ y y))
  2336  	// result: (LEAQ2 x y)
  2337  	for {
  2338  		_ = v.Args[1]
  2339  		x := v.Args[0]
  2340  		v_1 := v.Args[1]
  2341  		if v_1.Op != OpAMD64ADDQ {
  2342  			break
  2343  		}
  2344  		y := v_1.Args[1]
  2345  		if y != v_1.Args[0] {
  2346  			break
  2347  		}
  2348  		v.reset(OpAMD64LEAQ2)
  2349  		v.AddArg(x)
  2350  		v.AddArg(y)
  2351  		return true
  2352  	}
  2353  	// match: (ADDQ (ADDQ y y) x)
  2354  	// result: (LEAQ2 x y)
  2355  	for {
  2356  		x := v.Args[1]
  2357  		v_0 := v.Args[0]
  2358  		if v_0.Op != OpAMD64ADDQ {
  2359  			break
  2360  		}
  2361  		y := v_0.Args[1]
  2362  		if y != v_0.Args[0] {
  2363  			break
  2364  		}
  2365  		v.reset(OpAMD64LEAQ2)
  2366  		v.AddArg(x)
  2367  		v.AddArg(y)
  2368  		return true
  2369  	}
  2370  	// match: (ADDQ x (ADDQ x y))
  2371  	// result: (LEAQ2 y x)
  2372  	for {
  2373  		_ = v.Args[1]
  2374  		x := v.Args[0]
  2375  		v_1 := v.Args[1]
  2376  		if v_1.Op != OpAMD64ADDQ {
  2377  			break
  2378  		}
  2379  		y := v_1.Args[1]
  2380  		if x != v_1.Args[0] {
  2381  			break
  2382  		}
  2383  		v.reset(OpAMD64LEAQ2)
  2384  		v.AddArg(y)
  2385  		v.AddArg(x)
  2386  		return true
  2387  	}
  2388  	// match: (ADDQ x (ADDQ y x))
  2389  	// result: (LEAQ2 y x)
  2390  	for {
  2391  		_ = v.Args[1]
  2392  		x := v.Args[0]
  2393  		v_1 := v.Args[1]
  2394  		if v_1.Op != OpAMD64ADDQ {
  2395  			break
  2396  		}
  2397  		_ = v_1.Args[1]
  2398  		y := v_1.Args[0]
  2399  		if x != v_1.Args[1] {
  2400  			break
  2401  		}
  2402  		v.reset(OpAMD64LEAQ2)
  2403  		v.AddArg(y)
  2404  		v.AddArg(x)
  2405  		return true
  2406  	}
  2407  	// match: (ADDQ (ADDQ x y) x)
  2408  	// result: (LEAQ2 y x)
  2409  	for {
  2410  		x := v.Args[1]
  2411  		v_0 := v.Args[0]
  2412  		if v_0.Op != OpAMD64ADDQ {
  2413  			break
  2414  		}
  2415  		y := v_0.Args[1]
  2416  		if x != v_0.Args[0] {
  2417  			break
  2418  		}
  2419  		v.reset(OpAMD64LEAQ2)
  2420  		v.AddArg(y)
  2421  		v.AddArg(x)
  2422  		return true
  2423  	}
  2424  	// match: (ADDQ (ADDQ y x) x)
  2425  	// result: (LEAQ2 y x)
  2426  	for {
  2427  		x := v.Args[1]
  2428  		v_0 := v.Args[0]
  2429  		if v_0.Op != OpAMD64ADDQ {
  2430  			break
  2431  		}
  2432  		_ = v_0.Args[1]
  2433  		y := v_0.Args[0]
  2434  		if x != v_0.Args[1] {
  2435  			break
  2436  		}
  2437  		v.reset(OpAMD64LEAQ2)
  2438  		v.AddArg(y)
  2439  		v.AddArg(x)
  2440  		return true
  2441  	}
  2442  	// match: (ADDQ (ADDQconst [c] x) y)
  2443  	// result: (LEAQ1 [c] x y)
  2444  	for {
  2445  		y := v.Args[1]
  2446  		v_0 := v.Args[0]
  2447  		if v_0.Op != OpAMD64ADDQconst {
  2448  			break
  2449  		}
  2450  		c := v_0.AuxInt
  2451  		x := v_0.Args[0]
  2452  		v.reset(OpAMD64LEAQ1)
  2453  		v.AuxInt = c
  2454  		v.AddArg(x)
  2455  		v.AddArg(y)
  2456  		return true
  2457  	}
  2458  	// match: (ADDQ y (ADDQconst [c] x))
  2459  	// result: (LEAQ1 [c] x y)
  2460  	for {
  2461  		_ = v.Args[1]
  2462  		y := v.Args[0]
  2463  		v_1 := v.Args[1]
  2464  		if v_1.Op != OpAMD64ADDQconst {
  2465  			break
  2466  		}
  2467  		c := v_1.AuxInt
  2468  		x := v_1.Args[0]
  2469  		v.reset(OpAMD64LEAQ1)
  2470  		v.AuxInt = c
  2471  		v.AddArg(x)
  2472  		v.AddArg(y)
  2473  		return true
  2474  	}
  2475  	// match: (ADDQ x (LEAQ [c] {s} y))
  2476  	// cond: x.Op != OpSB && y.Op != OpSB
  2477  	// result: (LEAQ1 [c] {s} x y)
  2478  	for {
  2479  		_ = v.Args[1]
  2480  		x := v.Args[0]
  2481  		v_1 := v.Args[1]
  2482  		if v_1.Op != OpAMD64LEAQ {
  2483  			break
  2484  		}
  2485  		c := v_1.AuxInt
  2486  		s := v_1.Aux
  2487  		y := v_1.Args[0]
  2488  		if !(x.Op != OpSB && y.Op != OpSB) {
  2489  			break
  2490  		}
  2491  		v.reset(OpAMD64LEAQ1)
  2492  		v.AuxInt = c
  2493  		v.Aux = s
  2494  		v.AddArg(x)
  2495  		v.AddArg(y)
  2496  		return true
  2497  	}
  2498  	// match: (ADDQ (LEAQ [c] {s} y) x)
  2499  	// cond: x.Op != OpSB && y.Op != OpSB
  2500  	// result: (LEAQ1 [c] {s} x y)
  2501  	for {
  2502  		x := v.Args[1]
  2503  		v_0 := v.Args[0]
  2504  		if v_0.Op != OpAMD64LEAQ {
  2505  			break
  2506  		}
  2507  		c := v_0.AuxInt
  2508  		s := v_0.Aux
  2509  		y := v_0.Args[0]
  2510  		if !(x.Op != OpSB && y.Op != OpSB) {
  2511  			break
  2512  		}
  2513  		v.reset(OpAMD64LEAQ1)
  2514  		v.AuxInt = c
  2515  		v.Aux = s
  2516  		v.AddArg(x)
  2517  		v.AddArg(y)
  2518  		return true
  2519  	}
  2520  	return false
  2521  }
  2522  func rewriteValueAMD64_OpAMD64ADDQ_20(v *Value) bool {
  2523  	// match: (ADDQ x (NEGQ y))
  2524  	// result: (SUBQ x y)
  2525  	for {
  2526  		_ = v.Args[1]
  2527  		x := v.Args[0]
  2528  		v_1 := v.Args[1]
  2529  		if v_1.Op != OpAMD64NEGQ {
  2530  			break
  2531  		}
  2532  		y := v_1.Args[0]
  2533  		v.reset(OpAMD64SUBQ)
  2534  		v.AddArg(x)
  2535  		v.AddArg(y)
  2536  		return true
  2537  	}
  2538  	// match: (ADDQ (NEGQ y) x)
  2539  	// result: (SUBQ x y)
  2540  	for {
  2541  		x := v.Args[1]
  2542  		v_0 := v.Args[0]
  2543  		if v_0.Op != OpAMD64NEGQ {
  2544  			break
  2545  		}
  2546  		y := v_0.Args[0]
  2547  		v.reset(OpAMD64SUBQ)
  2548  		v.AddArg(x)
  2549  		v.AddArg(y)
  2550  		return true
  2551  	}
  2552  	// match: (ADDQ x l:(MOVQload [off] {sym} ptr mem))
  2553  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  2554  	// result: (ADDQload x [off] {sym} ptr mem)
  2555  	for {
  2556  		_ = v.Args[1]
  2557  		x := v.Args[0]
  2558  		l := v.Args[1]
  2559  		if l.Op != OpAMD64MOVQload {
  2560  			break
  2561  		}
  2562  		off := l.AuxInt
  2563  		sym := l.Aux
  2564  		mem := l.Args[1]
  2565  		ptr := l.Args[0]
  2566  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  2567  			break
  2568  		}
  2569  		v.reset(OpAMD64ADDQload)
  2570  		v.AuxInt = off
  2571  		v.Aux = sym
  2572  		v.AddArg(x)
  2573  		v.AddArg(ptr)
  2574  		v.AddArg(mem)
  2575  		return true
  2576  	}
  2577  	// match: (ADDQ l:(MOVQload [off] {sym} ptr mem) x)
  2578  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  2579  	// result: (ADDQload x [off] {sym} ptr mem)
  2580  	for {
  2581  		x := v.Args[1]
  2582  		l := v.Args[0]
  2583  		if l.Op != OpAMD64MOVQload {
  2584  			break
  2585  		}
  2586  		off := l.AuxInt
  2587  		sym := l.Aux
  2588  		mem := l.Args[1]
  2589  		ptr := l.Args[0]
  2590  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  2591  			break
  2592  		}
  2593  		v.reset(OpAMD64ADDQload)
  2594  		v.AuxInt = off
  2595  		v.Aux = sym
  2596  		v.AddArg(x)
  2597  		v.AddArg(ptr)
  2598  		v.AddArg(mem)
  2599  		return true
  2600  	}
  2601  	return false
  2602  }
  2603  func rewriteValueAMD64_OpAMD64ADDQcarry_0(v *Value) bool {
  2604  	// match: (ADDQcarry x (MOVQconst [c]))
  2605  	// cond: is32Bit(c)
  2606  	// result: (ADDQconstcarry x [c])
  2607  	for {
  2608  		_ = v.Args[1]
  2609  		x := v.Args[0]
  2610  		v_1 := v.Args[1]
  2611  		if v_1.Op != OpAMD64MOVQconst {
  2612  			break
  2613  		}
  2614  		c := v_1.AuxInt
  2615  		if !(is32Bit(c)) {
  2616  			break
  2617  		}
  2618  		v.reset(OpAMD64ADDQconstcarry)
  2619  		v.AuxInt = c
  2620  		v.AddArg(x)
  2621  		return true
  2622  	}
  2623  	// match: (ADDQcarry (MOVQconst [c]) x)
  2624  	// cond: is32Bit(c)
  2625  	// result: (ADDQconstcarry x [c])
  2626  	for {
  2627  		x := v.Args[1]
  2628  		v_0 := v.Args[0]
  2629  		if v_0.Op != OpAMD64MOVQconst {
  2630  			break
  2631  		}
  2632  		c := v_0.AuxInt
  2633  		if !(is32Bit(c)) {
  2634  			break
  2635  		}
  2636  		v.reset(OpAMD64ADDQconstcarry)
  2637  		v.AuxInt = c
  2638  		v.AddArg(x)
  2639  		return true
  2640  	}
  2641  	return false
  2642  }
  2643  func rewriteValueAMD64_OpAMD64ADDQconst_0(v *Value) bool {
  2644  	// match: (ADDQconst [c] (ADDQ x y))
  2645  	// result: (LEAQ1 [c] x y)
  2646  	for {
  2647  		c := v.AuxInt
  2648  		v_0 := v.Args[0]
  2649  		if v_0.Op != OpAMD64ADDQ {
  2650  			break
  2651  		}
  2652  		y := v_0.Args[1]
  2653  		x := v_0.Args[0]
  2654  		v.reset(OpAMD64LEAQ1)
  2655  		v.AuxInt = c
  2656  		v.AddArg(x)
  2657  		v.AddArg(y)
  2658  		return true
  2659  	}
  2660  	// match: (ADDQconst [c] (SHLQconst [1] x))
  2661  	// result: (LEAQ1 [c] x x)
  2662  	for {
  2663  		c := v.AuxInt
  2664  		v_0 := v.Args[0]
  2665  		if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 {
  2666  			break
  2667  		}
  2668  		x := v_0.Args[0]
  2669  		v.reset(OpAMD64LEAQ1)
  2670  		v.AuxInt = c
  2671  		v.AddArg(x)
  2672  		v.AddArg(x)
  2673  		return true
  2674  	}
  2675  	// match: (ADDQconst [c] (LEAQ [d] {s} x))
  2676  	// cond: is32Bit(c+d)
  2677  	// result: (LEAQ [c+d] {s} x)
  2678  	for {
  2679  		c := v.AuxInt
  2680  		v_0 := v.Args[0]
  2681  		if v_0.Op != OpAMD64LEAQ {
  2682  			break
  2683  		}
  2684  		d := v_0.AuxInt
  2685  		s := v_0.Aux
  2686  		x := v_0.Args[0]
  2687  		if !(is32Bit(c + d)) {
  2688  			break
  2689  		}
  2690  		v.reset(OpAMD64LEAQ)
  2691  		v.AuxInt = c + d
  2692  		v.Aux = s
  2693  		v.AddArg(x)
  2694  		return true
  2695  	}
  2696  	// match: (ADDQconst [c] (LEAQ1 [d] {s} x y))
  2697  	// cond: is32Bit(c+d)
  2698  	// result: (LEAQ1 [c+d] {s} x y)
  2699  	for {
  2700  		c := v.AuxInt
  2701  		v_0 := v.Args[0]
  2702  		if v_0.Op != OpAMD64LEAQ1 {
  2703  			break
  2704  		}
  2705  		d := v_0.AuxInt
  2706  		s := v_0.Aux
  2707  		y := v_0.Args[1]
  2708  		x := v_0.Args[0]
  2709  		if !(is32Bit(c + d)) {
  2710  			break
  2711  		}
  2712  		v.reset(OpAMD64LEAQ1)
  2713  		v.AuxInt = c + d
  2714  		v.Aux = s
  2715  		v.AddArg(x)
  2716  		v.AddArg(y)
  2717  		return true
  2718  	}
  2719  	// match: (ADDQconst [c] (LEAQ2 [d] {s} x y))
  2720  	// cond: is32Bit(c+d)
  2721  	// result: (LEAQ2 [c+d] {s} x y)
  2722  	for {
  2723  		c := v.AuxInt
  2724  		v_0 := v.Args[0]
  2725  		if v_0.Op != OpAMD64LEAQ2 {
  2726  			break
  2727  		}
  2728  		d := v_0.AuxInt
  2729  		s := v_0.Aux
  2730  		y := v_0.Args[1]
  2731  		x := v_0.Args[0]
  2732  		if !(is32Bit(c + d)) {
  2733  			break
  2734  		}
  2735  		v.reset(OpAMD64LEAQ2)
  2736  		v.AuxInt = c + d
  2737  		v.Aux = s
  2738  		v.AddArg(x)
  2739  		v.AddArg(y)
  2740  		return true
  2741  	}
  2742  	// match: (ADDQconst [c] (LEAQ4 [d] {s} x y))
  2743  	// cond: is32Bit(c+d)
  2744  	// result: (LEAQ4 [c+d] {s} x y)
  2745  	for {
  2746  		c := v.AuxInt
  2747  		v_0 := v.Args[0]
  2748  		if v_0.Op != OpAMD64LEAQ4 {
  2749  			break
  2750  		}
  2751  		d := v_0.AuxInt
  2752  		s := v_0.Aux
  2753  		y := v_0.Args[1]
  2754  		x := v_0.Args[0]
  2755  		if !(is32Bit(c + d)) {
  2756  			break
  2757  		}
  2758  		v.reset(OpAMD64LEAQ4)
  2759  		v.AuxInt = c + d
  2760  		v.Aux = s
  2761  		v.AddArg(x)
  2762  		v.AddArg(y)
  2763  		return true
  2764  	}
  2765  	// match: (ADDQconst [c] (LEAQ8 [d] {s} x y))
  2766  	// cond: is32Bit(c+d)
  2767  	// result: (LEAQ8 [c+d] {s} x y)
  2768  	for {
  2769  		c := v.AuxInt
  2770  		v_0 := v.Args[0]
  2771  		if v_0.Op != OpAMD64LEAQ8 {
  2772  			break
  2773  		}
  2774  		d := v_0.AuxInt
  2775  		s := v_0.Aux
  2776  		y := v_0.Args[1]
  2777  		x := v_0.Args[0]
  2778  		if !(is32Bit(c + d)) {
  2779  			break
  2780  		}
  2781  		v.reset(OpAMD64LEAQ8)
  2782  		v.AuxInt = c + d
  2783  		v.Aux = s
  2784  		v.AddArg(x)
  2785  		v.AddArg(y)
  2786  		return true
  2787  	}
  2788  	// match: (ADDQconst [0] x)
  2789  	// result: x
  2790  	for {
  2791  		if v.AuxInt != 0 {
  2792  			break
  2793  		}
  2794  		x := v.Args[0]
  2795  		v.reset(OpCopy)
  2796  		v.Type = x.Type
  2797  		v.AddArg(x)
  2798  		return true
  2799  	}
  2800  	// match: (ADDQconst [c] (MOVQconst [d]))
  2801  	// result: (MOVQconst [c+d])
  2802  	for {
  2803  		c := v.AuxInt
  2804  		v_0 := v.Args[0]
  2805  		if v_0.Op != OpAMD64MOVQconst {
  2806  			break
  2807  		}
  2808  		d := v_0.AuxInt
  2809  		v.reset(OpAMD64MOVQconst)
  2810  		v.AuxInt = c + d
  2811  		return true
  2812  	}
  2813  	// match: (ADDQconst [c] (ADDQconst [d] x))
  2814  	// cond: is32Bit(c+d)
  2815  	// result: (ADDQconst [c+d] x)
  2816  	for {
  2817  		c := v.AuxInt
  2818  		v_0 := v.Args[0]
  2819  		if v_0.Op != OpAMD64ADDQconst {
  2820  			break
  2821  		}
  2822  		d := v_0.AuxInt
  2823  		x := v_0.Args[0]
  2824  		if !(is32Bit(c + d)) {
  2825  			break
  2826  		}
  2827  		v.reset(OpAMD64ADDQconst)
  2828  		v.AuxInt = c + d
  2829  		v.AddArg(x)
  2830  		return true
  2831  	}
  2832  	return false
  2833  }
  2834  func rewriteValueAMD64_OpAMD64ADDQconst_10(v *Value) bool {
  2835  	// match: (ADDQconst [off] x:(SP))
  2836  	// result: (LEAQ [off] x)
  2837  	for {
  2838  		off := v.AuxInt
  2839  		x := v.Args[0]
  2840  		if x.Op != OpSP {
  2841  			break
  2842  		}
  2843  		v.reset(OpAMD64LEAQ)
  2844  		v.AuxInt = off
  2845  		v.AddArg(x)
  2846  		return true
  2847  	}
  2848  	return false
  2849  }
  2850  func rewriteValueAMD64_OpAMD64ADDQconstmodify_0(v *Value) bool {
  2851  	// match: (ADDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  2852  	// cond: ValAndOff(valoff1).canAdd(off2)
  2853  	// result: (ADDQconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  2854  	for {
  2855  		valoff1 := v.AuxInt
  2856  		sym := v.Aux
  2857  		mem := v.Args[1]
  2858  		v_0 := v.Args[0]
  2859  		if v_0.Op != OpAMD64ADDQconst {
  2860  			break
  2861  		}
  2862  		off2 := v_0.AuxInt
  2863  		base := v_0.Args[0]
  2864  		if !(ValAndOff(valoff1).canAdd(off2)) {
  2865  			break
  2866  		}
  2867  		v.reset(OpAMD64ADDQconstmodify)
  2868  		v.AuxInt = ValAndOff(valoff1).add(off2)
  2869  		v.Aux = sym
  2870  		v.AddArg(base)
  2871  		v.AddArg(mem)
  2872  		return true
  2873  	}
  2874  	// match: (ADDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  2875  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  2876  	// result: (ADDQconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  2877  	for {
  2878  		valoff1 := v.AuxInt
  2879  		sym1 := v.Aux
  2880  		mem := v.Args[1]
  2881  		v_0 := v.Args[0]
  2882  		if v_0.Op != OpAMD64LEAQ {
  2883  			break
  2884  		}
  2885  		off2 := v_0.AuxInt
  2886  		sym2 := v_0.Aux
  2887  		base := v_0.Args[0]
  2888  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  2889  			break
  2890  		}
  2891  		v.reset(OpAMD64ADDQconstmodify)
  2892  		v.AuxInt = ValAndOff(valoff1).add(off2)
  2893  		v.Aux = mergeSym(sym1, sym2)
  2894  		v.AddArg(base)
  2895  		v.AddArg(mem)
  2896  		return true
  2897  	}
  2898  	return false
  2899  }
  2900  func rewriteValueAMD64_OpAMD64ADDQload_0(v *Value) bool {
  2901  	b := v.Block
  2902  	typ := &b.Func.Config.Types
  2903  	// match: (ADDQload [off1] {sym} val (ADDQconst [off2] base) mem)
  2904  	// cond: is32Bit(off1+off2)
  2905  	// result: (ADDQload [off1+off2] {sym} val base mem)
  2906  	for {
  2907  		off1 := v.AuxInt
  2908  		sym := v.Aux
  2909  		mem := v.Args[2]
  2910  		val := v.Args[0]
  2911  		v_1 := v.Args[1]
  2912  		if v_1.Op != OpAMD64ADDQconst {
  2913  			break
  2914  		}
  2915  		off2 := v_1.AuxInt
  2916  		base := v_1.Args[0]
  2917  		if !(is32Bit(off1 + off2)) {
  2918  			break
  2919  		}
  2920  		v.reset(OpAMD64ADDQload)
  2921  		v.AuxInt = off1 + off2
  2922  		v.Aux = sym
  2923  		v.AddArg(val)
  2924  		v.AddArg(base)
  2925  		v.AddArg(mem)
  2926  		return true
  2927  	}
  2928  	// match: (ADDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
  2929  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  2930  	// result: (ADDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  2931  	for {
  2932  		off1 := v.AuxInt
  2933  		sym1 := v.Aux
  2934  		mem := v.Args[2]
  2935  		val := v.Args[0]
  2936  		v_1 := v.Args[1]
  2937  		if v_1.Op != OpAMD64LEAQ {
  2938  			break
  2939  		}
  2940  		off2 := v_1.AuxInt
  2941  		sym2 := v_1.Aux
  2942  		base := v_1.Args[0]
  2943  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  2944  			break
  2945  		}
  2946  		v.reset(OpAMD64ADDQload)
  2947  		v.AuxInt = off1 + off2
  2948  		v.Aux = mergeSym(sym1, sym2)
  2949  		v.AddArg(val)
  2950  		v.AddArg(base)
  2951  		v.AddArg(mem)
  2952  		return true
  2953  	}
  2954  	// match: (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _))
  2955  	// result: (ADDQ x (MOVQf2i y))
  2956  	for {
  2957  		off := v.AuxInt
  2958  		sym := v.Aux
  2959  		_ = v.Args[2]
  2960  		x := v.Args[0]
  2961  		ptr := v.Args[1]
  2962  		v_2 := v.Args[2]
  2963  		if v_2.Op != OpAMD64MOVSDstore || v_2.AuxInt != off || v_2.Aux != sym {
  2964  			break
  2965  		}
  2966  		_ = v_2.Args[2]
  2967  		if ptr != v_2.Args[0] {
  2968  			break
  2969  		}
  2970  		y := v_2.Args[1]
  2971  		v.reset(OpAMD64ADDQ)
  2972  		v.AddArg(x)
  2973  		v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64)
  2974  		v0.AddArg(y)
  2975  		v.AddArg(v0)
  2976  		return true
  2977  	}
  2978  	return false
  2979  }
  2980  func rewriteValueAMD64_OpAMD64ADDQmodify_0(v *Value) bool {
  2981  	// match: (ADDQmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  2982  	// cond: is32Bit(off1+off2)
  2983  	// result: (ADDQmodify [off1+off2] {sym} base val mem)
  2984  	for {
  2985  		off1 := v.AuxInt
  2986  		sym := v.Aux
  2987  		mem := v.Args[2]
  2988  		v_0 := v.Args[0]
  2989  		if v_0.Op != OpAMD64ADDQconst {
  2990  			break
  2991  		}
  2992  		off2 := v_0.AuxInt
  2993  		base := v_0.Args[0]
  2994  		val := v.Args[1]
  2995  		if !(is32Bit(off1 + off2)) {
  2996  			break
  2997  		}
  2998  		v.reset(OpAMD64ADDQmodify)
  2999  		v.AuxInt = off1 + off2
  3000  		v.Aux = sym
  3001  		v.AddArg(base)
  3002  		v.AddArg(val)
  3003  		v.AddArg(mem)
  3004  		return true
  3005  	}
  3006  	// match: (ADDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  3007  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  3008  	// result: (ADDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  3009  	for {
  3010  		off1 := v.AuxInt
  3011  		sym1 := v.Aux
  3012  		mem := v.Args[2]
  3013  		v_0 := v.Args[0]
  3014  		if v_0.Op != OpAMD64LEAQ {
  3015  			break
  3016  		}
  3017  		off2 := v_0.AuxInt
  3018  		sym2 := v_0.Aux
  3019  		base := v_0.Args[0]
  3020  		val := v.Args[1]
  3021  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  3022  			break
  3023  		}
  3024  		v.reset(OpAMD64ADDQmodify)
  3025  		v.AuxInt = off1 + off2
  3026  		v.Aux = mergeSym(sym1, sym2)
  3027  		v.AddArg(base)
  3028  		v.AddArg(val)
  3029  		v.AddArg(mem)
  3030  		return true
  3031  	}
  3032  	return false
  3033  }
  3034  func rewriteValueAMD64_OpAMD64ADDSD_0(v *Value) bool {
  3035  	// match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem))
  3036  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  3037  	// result: (ADDSDload x [off] {sym} ptr mem)
  3038  	for {
  3039  		_ = v.Args[1]
  3040  		x := v.Args[0]
  3041  		l := v.Args[1]
  3042  		if l.Op != OpAMD64MOVSDload {
  3043  			break
  3044  		}
  3045  		off := l.AuxInt
  3046  		sym := l.Aux
  3047  		mem := l.Args[1]
  3048  		ptr := l.Args[0]
  3049  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  3050  			break
  3051  		}
  3052  		v.reset(OpAMD64ADDSDload)
  3053  		v.AuxInt = off
  3054  		v.Aux = sym
  3055  		v.AddArg(x)
  3056  		v.AddArg(ptr)
  3057  		v.AddArg(mem)
  3058  		return true
  3059  	}
  3060  	// match: (ADDSD l:(MOVSDload [off] {sym} ptr mem) x)
  3061  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  3062  	// result: (ADDSDload x [off] {sym} ptr mem)
  3063  	for {
  3064  		x := v.Args[1]
  3065  		l := v.Args[0]
  3066  		if l.Op != OpAMD64MOVSDload {
  3067  			break
  3068  		}
  3069  		off := l.AuxInt
  3070  		sym := l.Aux
  3071  		mem := l.Args[1]
  3072  		ptr := l.Args[0]
  3073  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  3074  			break
  3075  		}
  3076  		v.reset(OpAMD64ADDSDload)
  3077  		v.AuxInt = off
  3078  		v.Aux = sym
  3079  		v.AddArg(x)
  3080  		v.AddArg(ptr)
  3081  		v.AddArg(mem)
  3082  		return true
  3083  	}
  3084  	return false
  3085  }
  3086  func rewriteValueAMD64_OpAMD64ADDSDload_0(v *Value) bool {
  3087  	b := v.Block
  3088  	typ := &b.Func.Config.Types
  3089  	// match: (ADDSDload [off1] {sym} val (ADDQconst [off2] base) mem)
  3090  	// cond: is32Bit(off1+off2)
  3091  	// result: (ADDSDload [off1+off2] {sym} val base mem)
  3092  	for {
  3093  		off1 := v.AuxInt
  3094  		sym := v.Aux
  3095  		mem := v.Args[2]
  3096  		val := v.Args[0]
  3097  		v_1 := v.Args[1]
  3098  		if v_1.Op != OpAMD64ADDQconst {
  3099  			break
  3100  		}
  3101  		off2 := v_1.AuxInt
  3102  		base := v_1.Args[0]
  3103  		if !(is32Bit(off1 + off2)) {
  3104  			break
  3105  		}
  3106  		v.reset(OpAMD64ADDSDload)
  3107  		v.AuxInt = off1 + off2
  3108  		v.Aux = sym
  3109  		v.AddArg(val)
  3110  		v.AddArg(base)
  3111  		v.AddArg(mem)
  3112  		return true
  3113  	}
  3114  	// match: (ADDSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
  3115  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  3116  	// result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  3117  	for {
  3118  		off1 := v.AuxInt
  3119  		sym1 := v.Aux
  3120  		mem := v.Args[2]
  3121  		val := v.Args[0]
  3122  		v_1 := v.Args[1]
  3123  		if v_1.Op != OpAMD64LEAQ {
  3124  			break
  3125  		}
  3126  		off2 := v_1.AuxInt
  3127  		sym2 := v_1.Aux
  3128  		base := v_1.Args[0]
  3129  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  3130  			break
  3131  		}
  3132  		v.reset(OpAMD64ADDSDload)
  3133  		v.AuxInt = off1 + off2
  3134  		v.Aux = mergeSym(sym1, sym2)
  3135  		v.AddArg(val)
  3136  		v.AddArg(base)
  3137  		v.AddArg(mem)
  3138  		return true
  3139  	}
  3140  	// match: (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _))
  3141  	// result: (ADDSD x (MOVQi2f y))
  3142  	for {
  3143  		off := v.AuxInt
  3144  		sym := v.Aux
  3145  		_ = v.Args[2]
  3146  		x := v.Args[0]
  3147  		ptr := v.Args[1]
  3148  		v_2 := v.Args[2]
  3149  		if v_2.Op != OpAMD64MOVQstore || v_2.AuxInt != off || v_2.Aux != sym {
  3150  			break
  3151  		}
  3152  		_ = v_2.Args[2]
  3153  		if ptr != v_2.Args[0] {
  3154  			break
  3155  		}
  3156  		y := v_2.Args[1]
  3157  		v.reset(OpAMD64ADDSD)
  3158  		v.AddArg(x)
  3159  		v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64)
  3160  		v0.AddArg(y)
  3161  		v.AddArg(v0)
  3162  		return true
  3163  	}
  3164  	return false
  3165  }
  3166  func rewriteValueAMD64_OpAMD64ADDSS_0(v *Value) bool {
  3167  	// match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem))
  3168  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  3169  	// result: (ADDSSload x [off] {sym} ptr mem)
  3170  	for {
  3171  		_ = v.Args[1]
  3172  		x := v.Args[0]
  3173  		l := v.Args[1]
  3174  		if l.Op != OpAMD64MOVSSload {
  3175  			break
  3176  		}
  3177  		off := l.AuxInt
  3178  		sym := l.Aux
  3179  		mem := l.Args[1]
  3180  		ptr := l.Args[0]
  3181  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  3182  			break
  3183  		}
  3184  		v.reset(OpAMD64ADDSSload)
  3185  		v.AuxInt = off
  3186  		v.Aux = sym
  3187  		v.AddArg(x)
  3188  		v.AddArg(ptr)
  3189  		v.AddArg(mem)
  3190  		return true
  3191  	}
  3192  	// match: (ADDSS l:(MOVSSload [off] {sym} ptr mem) x)
  3193  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  3194  	// result: (ADDSSload x [off] {sym} ptr mem)
  3195  	for {
  3196  		x := v.Args[1]
  3197  		l := v.Args[0]
  3198  		if l.Op != OpAMD64MOVSSload {
  3199  			break
  3200  		}
  3201  		off := l.AuxInt
  3202  		sym := l.Aux
  3203  		mem := l.Args[1]
  3204  		ptr := l.Args[0]
  3205  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  3206  			break
  3207  		}
  3208  		v.reset(OpAMD64ADDSSload)
  3209  		v.AuxInt = off
  3210  		v.Aux = sym
  3211  		v.AddArg(x)
  3212  		v.AddArg(ptr)
  3213  		v.AddArg(mem)
  3214  		return true
  3215  	}
  3216  	return false
  3217  }
  3218  func rewriteValueAMD64_OpAMD64ADDSSload_0(v *Value) bool {
  3219  	b := v.Block
  3220  	typ := &b.Func.Config.Types
  3221  	// match: (ADDSSload [off1] {sym} val (ADDQconst [off2] base) mem)
  3222  	// cond: is32Bit(off1+off2)
  3223  	// result: (ADDSSload [off1+off2] {sym} val base mem)
  3224  	for {
  3225  		off1 := v.AuxInt
  3226  		sym := v.Aux
  3227  		mem := v.Args[2]
  3228  		val := v.Args[0]
  3229  		v_1 := v.Args[1]
  3230  		if v_1.Op != OpAMD64ADDQconst {
  3231  			break
  3232  		}
  3233  		off2 := v_1.AuxInt
  3234  		base := v_1.Args[0]
  3235  		if !(is32Bit(off1 + off2)) {
  3236  			break
  3237  		}
  3238  		v.reset(OpAMD64ADDSSload)
  3239  		v.AuxInt = off1 + off2
  3240  		v.Aux = sym
  3241  		v.AddArg(val)
  3242  		v.AddArg(base)
  3243  		v.AddArg(mem)
  3244  		return true
  3245  	}
  3246  	// match: (ADDSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
  3247  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  3248  	// result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  3249  	for {
  3250  		off1 := v.AuxInt
  3251  		sym1 := v.Aux
  3252  		mem := v.Args[2]
  3253  		val := v.Args[0]
  3254  		v_1 := v.Args[1]
  3255  		if v_1.Op != OpAMD64LEAQ {
  3256  			break
  3257  		}
  3258  		off2 := v_1.AuxInt
  3259  		sym2 := v_1.Aux
  3260  		base := v_1.Args[0]
  3261  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  3262  			break
  3263  		}
  3264  		v.reset(OpAMD64ADDSSload)
  3265  		v.AuxInt = off1 + off2
  3266  		v.Aux = mergeSym(sym1, sym2)
  3267  		v.AddArg(val)
  3268  		v.AddArg(base)
  3269  		v.AddArg(mem)
  3270  		return true
  3271  	}
  3272  	// match: (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _))
  3273  	// result: (ADDSS x (MOVLi2f y))
  3274  	for {
  3275  		off := v.AuxInt
  3276  		sym := v.Aux
  3277  		_ = v.Args[2]
  3278  		x := v.Args[0]
  3279  		ptr := v.Args[1]
  3280  		v_2 := v.Args[2]
  3281  		if v_2.Op != OpAMD64MOVLstore || v_2.AuxInt != off || v_2.Aux != sym {
  3282  			break
  3283  		}
  3284  		_ = v_2.Args[2]
  3285  		if ptr != v_2.Args[0] {
  3286  			break
  3287  		}
  3288  		y := v_2.Args[1]
  3289  		v.reset(OpAMD64ADDSS)
  3290  		v.AddArg(x)
  3291  		v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32)
  3292  		v0.AddArg(y)
  3293  		v.AddArg(v0)
  3294  		return true
  3295  	}
  3296  	return false
  3297  }
  3298  func rewriteValueAMD64_OpAMD64ANDL_0(v *Value) bool {
  3299  	// match: (ANDL (NOTL (SHLL (MOVLconst [1]) y)) x)
  3300  	// result: (BTRL x y)
  3301  	for {
  3302  		x := v.Args[1]
  3303  		v_0 := v.Args[0]
  3304  		if v_0.Op != OpAMD64NOTL {
  3305  			break
  3306  		}
  3307  		v_0_0 := v_0.Args[0]
  3308  		if v_0_0.Op != OpAMD64SHLL {
  3309  			break
  3310  		}
  3311  		y := v_0_0.Args[1]
  3312  		v_0_0_0 := v_0_0.Args[0]
  3313  		if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 {
  3314  			break
  3315  		}
  3316  		v.reset(OpAMD64BTRL)
  3317  		v.AddArg(x)
  3318  		v.AddArg(y)
  3319  		return true
  3320  	}
  3321  	// match: (ANDL x (NOTL (SHLL (MOVLconst [1]) y)))
  3322  	// result: (BTRL x y)
  3323  	for {
  3324  		_ = v.Args[1]
  3325  		x := v.Args[0]
  3326  		v_1 := v.Args[1]
  3327  		if v_1.Op != OpAMD64NOTL {
  3328  			break
  3329  		}
  3330  		v_1_0 := v_1.Args[0]
  3331  		if v_1_0.Op != OpAMD64SHLL {
  3332  			break
  3333  		}
  3334  		y := v_1_0.Args[1]
  3335  		v_1_0_0 := v_1_0.Args[0]
  3336  		if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 {
  3337  			break
  3338  		}
  3339  		v.reset(OpAMD64BTRL)
  3340  		v.AddArg(x)
  3341  		v.AddArg(y)
  3342  		return true
  3343  	}
  3344  	// match: (ANDL (MOVLconst [c]) x)
  3345  	// cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128
  3346  	// result: (BTRLconst [log2uint32(^c)] x)
  3347  	for {
  3348  		x := v.Args[1]
  3349  		v_0 := v.Args[0]
  3350  		if v_0.Op != OpAMD64MOVLconst {
  3351  			break
  3352  		}
  3353  		c := v_0.AuxInt
  3354  		if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) {
  3355  			break
  3356  		}
  3357  		v.reset(OpAMD64BTRLconst)
  3358  		v.AuxInt = log2uint32(^c)
  3359  		v.AddArg(x)
  3360  		return true
  3361  	}
  3362  	// match: (ANDL x (MOVLconst [c]))
  3363  	// cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128
  3364  	// result: (BTRLconst [log2uint32(^c)] x)
  3365  	for {
  3366  		_ = v.Args[1]
  3367  		x := v.Args[0]
  3368  		v_1 := v.Args[1]
  3369  		if v_1.Op != OpAMD64MOVLconst {
  3370  			break
  3371  		}
  3372  		c := v_1.AuxInt
  3373  		if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) {
  3374  			break
  3375  		}
  3376  		v.reset(OpAMD64BTRLconst)
  3377  		v.AuxInt = log2uint32(^c)
  3378  		v.AddArg(x)
  3379  		return true
  3380  	}
  3381  	// match: (ANDL x (MOVLconst [c]))
  3382  	// result: (ANDLconst [c] x)
  3383  	for {
  3384  		_ = v.Args[1]
  3385  		x := v.Args[0]
  3386  		v_1 := v.Args[1]
  3387  		if v_1.Op != OpAMD64MOVLconst {
  3388  			break
  3389  		}
  3390  		c := v_1.AuxInt
  3391  		v.reset(OpAMD64ANDLconst)
  3392  		v.AuxInt = c
  3393  		v.AddArg(x)
  3394  		return true
  3395  	}
  3396  	// match: (ANDL (MOVLconst [c]) x)
  3397  	// result: (ANDLconst [c] x)
  3398  	for {
  3399  		x := v.Args[1]
  3400  		v_0 := v.Args[0]
  3401  		if v_0.Op != OpAMD64MOVLconst {
  3402  			break
  3403  		}
  3404  		c := v_0.AuxInt
  3405  		v.reset(OpAMD64ANDLconst)
  3406  		v.AuxInt = c
  3407  		v.AddArg(x)
  3408  		return true
  3409  	}
  3410  	// match: (ANDL x x)
  3411  	// result: x
  3412  	for {
  3413  		x := v.Args[1]
  3414  		if x != v.Args[0] {
  3415  			break
  3416  		}
  3417  		v.reset(OpCopy)
  3418  		v.Type = x.Type
  3419  		v.AddArg(x)
  3420  		return true
  3421  	}
  3422  	// match: (ANDL x l:(MOVLload [off] {sym} ptr mem))
  3423  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  3424  	// result: (ANDLload x [off] {sym} ptr mem)
  3425  	for {
  3426  		_ = v.Args[1]
  3427  		x := v.Args[0]
  3428  		l := v.Args[1]
  3429  		if l.Op != OpAMD64MOVLload {
  3430  			break
  3431  		}
  3432  		off := l.AuxInt
  3433  		sym := l.Aux
  3434  		mem := l.Args[1]
  3435  		ptr := l.Args[0]
  3436  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  3437  			break
  3438  		}
  3439  		v.reset(OpAMD64ANDLload)
  3440  		v.AuxInt = off
  3441  		v.Aux = sym
  3442  		v.AddArg(x)
  3443  		v.AddArg(ptr)
  3444  		v.AddArg(mem)
  3445  		return true
  3446  	}
  3447  	// match: (ANDL l:(MOVLload [off] {sym} ptr mem) x)
  3448  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  3449  	// result: (ANDLload x [off] {sym} ptr mem)
  3450  	for {
  3451  		x := v.Args[1]
  3452  		l := v.Args[0]
  3453  		if l.Op != OpAMD64MOVLload {
  3454  			break
  3455  		}
  3456  		off := l.AuxInt
  3457  		sym := l.Aux
  3458  		mem := l.Args[1]
  3459  		ptr := l.Args[0]
  3460  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  3461  			break
  3462  		}
  3463  		v.reset(OpAMD64ANDLload)
  3464  		v.AuxInt = off
  3465  		v.Aux = sym
  3466  		v.AddArg(x)
  3467  		v.AddArg(ptr)
  3468  		v.AddArg(mem)
  3469  		return true
  3470  	}
  3471  	return false
  3472  }
  3473  func rewriteValueAMD64_OpAMD64ANDLconst_0(v *Value) bool {
  3474  	// match: (ANDLconst [c] x)
  3475  	// cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128
  3476  	// result: (BTRLconst [log2uint32(^c)] x)
  3477  	for {
  3478  		c := v.AuxInt
  3479  		x := v.Args[0]
  3480  		if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) {
  3481  			break
  3482  		}
  3483  		v.reset(OpAMD64BTRLconst)
  3484  		v.AuxInt = log2uint32(^c)
  3485  		v.AddArg(x)
  3486  		return true
  3487  	}
  3488  	// match: (ANDLconst [c] (ANDLconst [d] x))
  3489  	// result: (ANDLconst [c & d] x)
  3490  	for {
  3491  		c := v.AuxInt
  3492  		v_0 := v.Args[0]
  3493  		if v_0.Op != OpAMD64ANDLconst {
  3494  			break
  3495  		}
  3496  		d := v_0.AuxInt
  3497  		x := v_0.Args[0]
  3498  		v.reset(OpAMD64ANDLconst)
  3499  		v.AuxInt = c & d
  3500  		v.AddArg(x)
  3501  		return true
  3502  	}
  3503  	// match: (ANDLconst [c] (BTRLconst [d] x))
  3504  	// result: (ANDLconst [c &^ (1<<uint32(d))] x)
  3505  	for {
  3506  		c := v.AuxInt
  3507  		v_0 := v.Args[0]
  3508  		if v_0.Op != OpAMD64BTRLconst {
  3509  			break
  3510  		}
  3511  		d := v_0.AuxInt
  3512  		x := v_0.Args[0]
  3513  		v.reset(OpAMD64ANDLconst)
  3514  		v.AuxInt = c &^ (1 << uint32(d))
  3515  		v.AddArg(x)
  3516  		return true
  3517  	}
  3518  	// match: (ANDLconst [ 0xFF] x)
  3519  	// result: (MOVBQZX x)
  3520  	for {
  3521  		if v.AuxInt != 0xFF {
  3522  			break
  3523  		}
  3524  		x := v.Args[0]
  3525  		v.reset(OpAMD64MOVBQZX)
  3526  		v.AddArg(x)
  3527  		return true
  3528  	}
  3529  	// match: (ANDLconst [0xFFFF] x)
  3530  	// result: (MOVWQZX x)
  3531  	for {
  3532  		if v.AuxInt != 0xFFFF {
  3533  			break
  3534  		}
  3535  		x := v.Args[0]
  3536  		v.reset(OpAMD64MOVWQZX)
  3537  		v.AddArg(x)
  3538  		return true
  3539  	}
  3540  	// match: (ANDLconst [c] _)
  3541  	// cond: int32(c)==0
  3542  	// result: (MOVLconst [0])
  3543  	for {
  3544  		c := v.AuxInt
  3545  		if !(int32(c) == 0) {
  3546  			break
  3547  		}
  3548  		v.reset(OpAMD64MOVLconst)
  3549  		v.AuxInt = 0
  3550  		return true
  3551  	}
  3552  	// match: (ANDLconst [c] x)
  3553  	// cond: int32(c)==-1
  3554  	// result: x
  3555  	for {
  3556  		c := v.AuxInt
  3557  		x := v.Args[0]
  3558  		if !(int32(c) == -1) {
  3559  			break
  3560  		}
  3561  		v.reset(OpCopy)
  3562  		v.Type = x.Type
  3563  		v.AddArg(x)
  3564  		return true
  3565  	}
  3566  	// match: (ANDLconst [c] (MOVLconst [d]))
  3567  	// result: (MOVLconst [c&d])
  3568  	for {
  3569  		c := v.AuxInt
  3570  		v_0 := v.Args[0]
  3571  		if v_0.Op != OpAMD64MOVLconst {
  3572  			break
  3573  		}
  3574  		d := v_0.AuxInt
  3575  		v.reset(OpAMD64MOVLconst)
  3576  		v.AuxInt = c & d
  3577  		return true
  3578  	}
  3579  	return false
  3580  }
  3581  func rewriteValueAMD64_OpAMD64ANDLconstmodify_0(v *Value) bool {
  3582  	// match: (ANDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  3583  	// cond: ValAndOff(valoff1).canAdd(off2)
  3584  	// result: (ANDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  3585  	for {
  3586  		valoff1 := v.AuxInt
  3587  		sym := v.Aux
  3588  		mem := v.Args[1]
  3589  		v_0 := v.Args[0]
  3590  		if v_0.Op != OpAMD64ADDQconst {
  3591  			break
  3592  		}
  3593  		off2 := v_0.AuxInt
  3594  		base := v_0.Args[0]
  3595  		if !(ValAndOff(valoff1).canAdd(off2)) {
  3596  			break
  3597  		}
  3598  		v.reset(OpAMD64ANDLconstmodify)
  3599  		v.AuxInt = ValAndOff(valoff1).add(off2)
  3600  		v.Aux = sym
  3601  		v.AddArg(base)
  3602  		v.AddArg(mem)
  3603  		return true
  3604  	}
  3605  	// match: (ANDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  3606  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  3607  	// result: (ANDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  3608  	for {
  3609  		valoff1 := v.AuxInt
  3610  		sym1 := v.Aux
  3611  		mem := v.Args[1]
  3612  		v_0 := v.Args[0]
  3613  		if v_0.Op != OpAMD64LEAQ {
  3614  			break
  3615  		}
  3616  		off2 := v_0.AuxInt
  3617  		sym2 := v_0.Aux
  3618  		base := v_0.Args[0]
  3619  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  3620  			break
  3621  		}
  3622  		v.reset(OpAMD64ANDLconstmodify)
  3623  		v.AuxInt = ValAndOff(valoff1).add(off2)
  3624  		v.Aux = mergeSym(sym1, sym2)
  3625  		v.AddArg(base)
  3626  		v.AddArg(mem)
  3627  		return true
  3628  	}
  3629  	return false
  3630  }
  3631  func rewriteValueAMD64_OpAMD64ANDLload_0(v *Value) bool {
  3632  	b := v.Block
  3633  	typ := &b.Func.Config.Types
  3634  	// match: (ANDLload [off1] {sym} val (ADDQconst [off2] base) mem)
  3635  	// cond: is32Bit(off1+off2)
  3636  	// result: (ANDLload [off1+off2] {sym} val base mem)
  3637  	for {
  3638  		off1 := v.AuxInt
  3639  		sym := v.Aux
  3640  		mem := v.Args[2]
  3641  		val := v.Args[0]
  3642  		v_1 := v.Args[1]
  3643  		if v_1.Op != OpAMD64ADDQconst {
  3644  			break
  3645  		}
  3646  		off2 := v_1.AuxInt
  3647  		base := v_1.Args[0]
  3648  		if !(is32Bit(off1 + off2)) {
  3649  			break
  3650  		}
  3651  		v.reset(OpAMD64ANDLload)
  3652  		v.AuxInt = off1 + off2
  3653  		v.Aux = sym
  3654  		v.AddArg(val)
  3655  		v.AddArg(base)
  3656  		v.AddArg(mem)
  3657  		return true
  3658  	}
  3659  	// match: (ANDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
  3660  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  3661  	// result: (ANDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  3662  	for {
  3663  		off1 := v.AuxInt
  3664  		sym1 := v.Aux
  3665  		mem := v.Args[2]
  3666  		val := v.Args[0]
  3667  		v_1 := v.Args[1]
  3668  		if v_1.Op != OpAMD64LEAQ {
  3669  			break
  3670  		}
  3671  		off2 := v_1.AuxInt
  3672  		sym2 := v_1.Aux
  3673  		base := v_1.Args[0]
  3674  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  3675  			break
  3676  		}
  3677  		v.reset(OpAMD64ANDLload)
  3678  		v.AuxInt = off1 + off2
  3679  		v.Aux = mergeSym(sym1, sym2)
  3680  		v.AddArg(val)
  3681  		v.AddArg(base)
  3682  		v.AddArg(mem)
  3683  		return true
  3684  	}
  3685  	// match: (ANDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _))
  3686  	// result: (ANDL x (MOVLf2i y))
  3687  	for {
  3688  		off := v.AuxInt
  3689  		sym := v.Aux
  3690  		_ = v.Args[2]
  3691  		x := v.Args[0]
  3692  		ptr := v.Args[1]
  3693  		v_2 := v.Args[2]
  3694  		if v_2.Op != OpAMD64MOVSSstore || v_2.AuxInt != off || v_2.Aux != sym {
  3695  			break
  3696  		}
  3697  		_ = v_2.Args[2]
  3698  		if ptr != v_2.Args[0] {
  3699  			break
  3700  		}
  3701  		y := v_2.Args[1]
  3702  		v.reset(OpAMD64ANDL)
  3703  		v.AddArg(x)
  3704  		v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32)
  3705  		v0.AddArg(y)
  3706  		v.AddArg(v0)
  3707  		return true
  3708  	}
  3709  	return false
  3710  }
  3711  func rewriteValueAMD64_OpAMD64ANDLmodify_0(v *Value) bool {
  3712  	// match: (ANDLmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  3713  	// cond: is32Bit(off1+off2)
  3714  	// result: (ANDLmodify [off1+off2] {sym} base val mem)
  3715  	for {
  3716  		off1 := v.AuxInt
  3717  		sym := v.Aux
  3718  		mem := v.Args[2]
  3719  		v_0 := v.Args[0]
  3720  		if v_0.Op != OpAMD64ADDQconst {
  3721  			break
  3722  		}
  3723  		off2 := v_0.AuxInt
  3724  		base := v_0.Args[0]
  3725  		val := v.Args[1]
  3726  		if !(is32Bit(off1 + off2)) {
  3727  			break
  3728  		}
  3729  		v.reset(OpAMD64ANDLmodify)
  3730  		v.AuxInt = off1 + off2
  3731  		v.Aux = sym
  3732  		v.AddArg(base)
  3733  		v.AddArg(val)
  3734  		v.AddArg(mem)
  3735  		return true
  3736  	}
  3737  	// match: (ANDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  3738  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  3739  	// result: (ANDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  3740  	for {
  3741  		off1 := v.AuxInt
  3742  		sym1 := v.Aux
  3743  		mem := v.Args[2]
  3744  		v_0 := v.Args[0]
  3745  		if v_0.Op != OpAMD64LEAQ {
  3746  			break
  3747  		}
  3748  		off2 := v_0.AuxInt
  3749  		sym2 := v_0.Aux
  3750  		base := v_0.Args[0]
  3751  		val := v.Args[1]
  3752  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  3753  			break
  3754  		}
  3755  		v.reset(OpAMD64ANDLmodify)
  3756  		v.AuxInt = off1 + off2
  3757  		v.Aux = mergeSym(sym1, sym2)
  3758  		v.AddArg(base)
  3759  		v.AddArg(val)
  3760  		v.AddArg(mem)
  3761  		return true
  3762  	}
  3763  	return false
  3764  }
  3765  func rewriteValueAMD64_OpAMD64ANDQ_0(v *Value) bool {
  3766  	// match: (ANDQ (NOTQ (SHLQ (MOVQconst [1]) y)) x)
  3767  	// result: (BTRQ x y)
  3768  	for {
  3769  		x := v.Args[1]
  3770  		v_0 := v.Args[0]
  3771  		if v_0.Op != OpAMD64NOTQ {
  3772  			break
  3773  		}
  3774  		v_0_0 := v_0.Args[0]
  3775  		if v_0_0.Op != OpAMD64SHLQ {
  3776  			break
  3777  		}
  3778  		y := v_0_0.Args[1]
  3779  		v_0_0_0 := v_0_0.Args[0]
  3780  		if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 {
  3781  			break
  3782  		}
  3783  		v.reset(OpAMD64BTRQ)
  3784  		v.AddArg(x)
  3785  		v.AddArg(y)
  3786  		return true
  3787  	}
  3788  	// match: (ANDQ x (NOTQ (SHLQ (MOVQconst [1]) y)))
  3789  	// result: (BTRQ x y)
  3790  	for {
  3791  		_ = v.Args[1]
  3792  		x := v.Args[0]
  3793  		v_1 := v.Args[1]
  3794  		if v_1.Op != OpAMD64NOTQ {
  3795  			break
  3796  		}
  3797  		v_1_0 := v_1.Args[0]
  3798  		if v_1_0.Op != OpAMD64SHLQ {
  3799  			break
  3800  		}
  3801  		y := v_1_0.Args[1]
  3802  		v_1_0_0 := v_1_0.Args[0]
  3803  		if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 {
  3804  			break
  3805  		}
  3806  		v.reset(OpAMD64BTRQ)
  3807  		v.AddArg(x)
  3808  		v.AddArg(y)
  3809  		return true
  3810  	}
  3811  	// match: (ANDQ (MOVQconst [c]) x)
  3812  	// cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128
  3813  	// result: (BTRQconst [log2(^c)] x)
  3814  	for {
  3815  		x := v.Args[1]
  3816  		v_0 := v.Args[0]
  3817  		if v_0.Op != OpAMD64MOVQconst {
  3818  			break
  3819  		}
  3820  		c := v_0.AuxInt
  3821  		if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) {
  3822  			break
  3823  		}
  3824  		v.reset(OpAMD64BTRQconst)
  3825  		v.AuxInt = log2(^c)
  3826  		v.AddArg(x)
  3827  		return true
  3828  	}
  3829  	// match: (ANDQ x (MOVQconst [c]))
  3830  	// cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128
  3831  	// result: (BTRQconst [log2(^c)] x)
  3832  	for {
  3833  		_ = v.Args[1]
  3834  		x := v.Args[0]
  3835  		v_1 := v.Args[1]
  3836  		if v_1.Op != OpAMD64MOVQconst {
  3837  			break
  3838  		}
  3839  		c := v_1.AuxInt
  3840  		if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) {
  3841  			break
  3842  		}
  3843  		v.reset(OpAMD64BTRQconst)
  3844  		v.AuxInt = log2(^c)
  3845  		v.AddArg(x)
  3846  		return true
  3847  	}
  3848  	// match: (ANDQ x (MOVQconst [c]))
  3849  	// cond: is32Bit(c)
  3850  	// result: (ANDQconst [c] x)
  3851  	for {
  3852  		_ = v.Args[1]
  3853  		x := v.Args[0]
  3854  		v_1 := v.Args[1]
  3855  		if v_1.Op != OpAMD64MOVQconst {
  3856  			break
  3857  		}
  3858  		c := v_1.AuxInt
  3859  		if !(is32Bit(c)) {
  3860  			break
  3861  		}
  3862  		v.reset(OpAMD64ANDQconst)
  3863  		v.AuxInt = c
  3864  		v.AddArg(x)
  3865  		return true
  3866  	}
  3867  	// match: (ANDQ (MOVQconst [c]) x)
  3868  	// cond: is32Bit(c)
  3869  	// result: (ANDQconst [c] x)
  3870  	for {
  3871  		x := v.Args[1]
  3872  		v_0 := v.Args[0]
  3873  		if v_0.Op != OpAMD64MOVQconst {
  3874  			break
  3875  		}
  3876  		c := v_0.AuxInt
  3877  		if !(is32Bit(c)) {
  3878  			break
  3879  		}
  3880  		v.reset(OpAMD64ANDQconst)
  3881  		v.AuxInt = c
  3882  		v.AddArg(x)
  3883  		return true
  3884  	}
  3885  	// match: (ANDQ x x)
  3886  	// result: x
  3887  	for {
  3888  		x := v.Args[1]
  3889  		if x != v.Args[0] {
  3890  			break
  3891  		}
  3892  		v.reset(OpCopy)
  3893  		v.Type = x.Type
  3894  		v.AddArg(x)
  3895  		return true
  3896  	}
  3897  	// match: (ANDQ x l:(MOVQload [off] {sym} ptr mem))
  3898  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  3899  	// result: (ANDQload x [off] {sym} ptr mem)
  3900  	for {
  3901  		_ = v.Args[1]
  3902  		x := v.Args[0]
  3903  		l := v.Args[1]
  3904  		if l.Op != OpAMD64MOVQload {
  3905  			break
  3906  		}
  3907  		off := l.AuxInt
  3908  		sym := l.Aux
  3909  		mem := l.Args[1]
  3910  		ptr := l.Args[0]
  3911  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  3912  			break
  3913  		}
  3914  		v.reset(OpAMD64ANDQload)
  3915  		v.AuxInt = off
  3916  		v.Aux = sym
  3917  		v.AddArg(x)
  3918  		v.AddArg(ptr)
  3919  		v.AddArg(mem)
  3920  		return true
  3921  	}
  3922  	// match: (ANDQ l:(MOVQload [off] {sym} ptr mem) x)
  3923  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  3924  	// result: (ANDQload x [off] {sym} ptr mem)
  3925  	for {
  3926  		x := v.Args[1]
  3927  		l := v.Args[0]
  3928  		if l.Op != OpAMD64MOVQload {
  3929  			break
  3930  		}
  3931  		off := l.AuxInt
  3932  		sym := l.Aux
  3933  		mem := l.Args[1]
  3934  		ptr := l.Args[0]
  3935  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  3936  			break
  3937  		}
  3938  		v.reset(OpAMD64ANDQload)
  3939  		v.AuxInt = off
  3940  		v.Aux = sym
  3941  		v.AddArg(x)
  3942  		v.AddArg(ptr)
  3943  		v.AddArg(mem)
  3944  		return true
  3945  	}
  3946  	return false
  3947  }
  3948  func rewriteValueAMD64_OpAMD64ANDQconst_0(v *Value) bool {
  3949  	// match: (ANDQconst [c] x)
  3950  	// cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128
  3951  	// result: (BTRQconst [log2(^c)] x)
  3952  	for {
  3953  		c := v.AuxInt
  3954  		x := v.Args[0]
  3955  		if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) {
  3956  			break
  3957  		}
  3958  		v.reset(OpAMD64BTRQconst)
  3959  		v.AuxInt = log2(^c)
  3960  		v.AddArg(x)
  3961  		return true
  3962  	}
  3963  	// match: (ANDQconst [c] (ANDQconst [d] x))
  3964  	// result: (ANDQconst [c & d] x)
  3965  	for {
  3966  		c := v.AuxInt
  3967  		v_0 := v.Args[0]
  3968  		if v_0.Op != OpAMD64ANDQconst {
  3969  			break
  3970  		}
  3971  		d := v_0.AuxInt
  3972  		x := v_0.Args[0]
  3973  		v.reset(OpAMD64ANDQconst)
  3974  		v.AuxInt = c & d
  3975  		v.AddArg(x)
  3976  		return true
  3977  	}
  3978  	// match: (ANDQconst [c] (BTRQconst [d] x))
  3979  	// result: (ANDQconst [c &^ (1<<uint32(d))] x)
  3980  	for {
  3981  		c := v.AuxInt
  3982  		v_0 := v.Args[0]
  3983  		if v_0.Op != OpAMD64BTRQconst {
  3984  			break
  3985  		}
  3986  		d := v_0.AuxInt
  3987  		x := v_0.Args[0]
  3988  		v.reset(OpAMD64ANDQconst)
  3989  		v.AuxInt = c &^ (1 << uint32(d))
  3990  		v.AddArg(x)
  3991  		return true
  3992  	}
  3993  	// match: (ANDQconst [ 0xFF] x)
  3994  	// result: (MOVBQZX x)
  3995  	for {
  3996  		if v.AuxInt != 0xFF {
  3997  			break
  3998  		}
  3999  		x := v.Args[0]
  4000  		v.reset(OpAMD64MOVBQZX)
  4001  		v.AddArg(x)
  4002  		return true
  4003  	}
  4004  	// match: (ANDQconst [0xFFFF] x)
  4005  	// result: (MOVWQZX x)
  4006  	for {
  4007  		if v.AuxInt != 0xFFFF {
  4008  			break
  4009  		}
  4010  		x := v.Args[0]
  4011  		v.reset(OpAMD64MOVWQZX)
  4012  		v.AddArg(x)
  4013  		return true
  4014  	}
  4015  	// match: (ANDQconst [0xFFFFFFFF] x)
  4016  	// result: (MOVLQZX x)
  4017  	for {
  4018  		if v.AuxInt != 0xFFFFFFFF {
  4019  			break
  4020  		}
  4021  		x := v.Args[0]
  4022  		v.reset(OpAMD64MOVLQZX)
  4023  		v.AddArg(x)
  4024  		return true
  4025  	}
  4026  	// match: (ANDQconst [0] _)
  4027  	// result: (MOVQconst [0])
  4028  	for {
  4029  		if v.AuxInt != 0 {
  4030  			break
  4031  		}
  4032  		v.reset(OpAMD64MOVQconst)
  4033  		v.AuxInt = 0
  4034  		return true
  4035  	}
  4036  	// match: (ANDQconst [-1] x)
  4037  	// result: x
  4038  	for {
  4039  		if v.AuxInt != -1 {
  4040  			break
  4041  		}
  4042  		x := v.Args[0]
  4043  		v.reset(OpCopy)
  4044  		v.Type = x.Type
  4045  		v.AddArg(x)
  4046  		return true
  4047  	}
  4048  	// match: (ANDQconst [c] (MOVQconst [d]))
  4049  	// result: (MOVQconst [c&d])
  4050  	for {
  4051  		c := v.AuxInt
  4052  		v_0 := v.Args[0]
  4053  		if v_0.Op != OpAMD64MOVQconst {
  4054  			break
  4055  		}
  4056  		d := v_0.AuxInt
  4057  		v.reset(OpAMD64MOVQconst)
  4058  		v.AuxInt = c & d
  4059  		return true
  4060  	}
  4061  	return false
  4062  }
  4063  func rewriteValueAMD64_OpAMD64ANDQconstmodify_0(v *Value) bool {
  4064  	// match: (ANDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  4065  	// cond: ValAndOff(valoff1).canAdd(off2)
  4066  	// result: (ANDQconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  4067  	for {
  4068  		valoff1 := v.AuxInt
  4069  		sym := v.Aux
  4070  		mem := v.Args[1]
  4071  		v_0 := v.Args[0]
  4072  		if v_0.Op != OpAMD64ADDQconst {
  4073  			break
  4074  		}
  4075  		off2 := v_0.AuxInt
  4076  		base := v_0.Args[0]
  4077  		if !(ValAndOff(valoff1).canAdd(off2)) {
  4078  			break
  4079  		}
  4080  		v.reset(OpAMD64ANDQconstmodify)
  4081  		v.AuxInt = ValAndOff(valoff1).add(off2)
  4082  		v.Aux = sym
  4083  		v.AddArg(base)
  4084  		v.AddArg(mem)
  4085  		return true
  4086  	}
  4087  	// match: (ANDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  4088  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  4089  	// result: (ANDQconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  4090  	for {
  4091  		valoff1 := v.AuxInt
  4092  		sym1 := v.Aux
  4093  		mem := v.Args[1]
  4094  		v_0 := v.Args[0]
  4095  		if v_0.Op != OpAMD64LEAQ {
  4096  			break
  4097  		}
  4098  		off2 := v_0.AuxInt
  4099  		sym2 := v_0.Aux
  4100  		base := v_0.Args[0]
  4101  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  4102  			break
  4103  		}
  4104  		v.reset(OpAMD64ANDQconstmodify)
  4105  		v.AuxInt = ValAndOff(valoff1).add(off2)
  4106  		v.Aux = mergeSym(sym1, sym2)
  4107  		v.AddArg(base)
  4108  		v.AddArg(mem)
  4109  		return true
  4110  	}
  4111  	return false
  4112  }
  4113  func rewriteValueAMD64_OpAMD64ANDQload_0(v *Value) bool {
  4114  	b := v.Block
  4115  	typ := &b.Func.Config.Types
  4116  	// match: (ANDQload [off1] {sym} val (ADDQconst [off2] base) mem)
  4117  	// cond: is32Bit(off1+off2)
  4118  	// result: (ANDQload [off1+off2] {sym} val base mem)
  4119  	for {
  4120  		off1 := v.AuxInt
  4121  		sym := v.Aux
  4122  		mem := v.Args[2]
  4123  		val := v.Args[0]
  4124  		v_1 := v.Args[1]
  4125  		if v_1.Op != OpAMD64ADDQconst {
  4126  			break
  4127  		}
  4128  		off2 := v_1.AuxInt
  4129  		base := v_1.Args[0]
  4130  		if !(is32Bit(off1 + off2)) {
  4131  			break
  4132  		}
  4133  		v.reset(OpAMD64ANDQload)
  4134  		v.AuxInt = off1 + off2
  4135  		v.Aux = sym
  4136  		v.AddArg(val)
  4137  		v.AddArg(base)
  4138  		v.AddArg(mem)
  4139  		return true
  4140  	}
  4141  	// match: (ANDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
  4142  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4143  	// result: (ANDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  4144  	for {
  4145  		off1 := v.AuxInt
  4146  		sym1 := v.Aux
  4147  		mem := v.Args[2]
  4148  		val := v.Args[0]
  4149  		v_1 := v.Args[1]
  4150  		if v_1.Op != OpAMD64LEAQ {
  4151  			break
  4152  		}
  4153  		off2 := v_1.AuxInt
  4154  		sym2 := v_1.Aux
  4155  		base := v_1.Args[0]
  4156  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4157  			break
  4158  		}
  4159  		v.reset(OpAMD64ANDQload)
  4160  		v.AuxInt = off1 + off2
  4161  		v.Aux = mergeSym(sym1, sym2)
  4162  		v.AddArg(val)
  4163  		v.AddArg(base)
  4164  		v.AddArg(mem)
  4165  		return true
  4166  	}
  4167  	// match: (ANDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _))
  4168  	// result: (ANDQ x (MOVQf2i y))
  4169  	for {
  4170  		off := v.AuxInt
  4171  		sym := v.Aux
  4172  		_ = v.Args[2]
  4173  		x := v.Args[0]
  4174  		ptr := v.Args[1]
  4175  		v_2 := v.Args[2]
  4176  		if v_2.Op != OpAMD64MOVSDstore || v_2.AuxInt != off || v_2.Aux != sym {
  4177  			break
  4178  		}
  4179  		_ = v_2.Args[2]
  4180  		if ptr != v_2.Args[0] {
  4181  			break
  4182  		}
  4183  		y := v_2.Args[1]
  4184  		v.reset(OpAMD64ANDQ)
  4185  		v.AddArg(x)
  4186  		v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64)
  4187  		v0.AddArg(y)
  4188  		v.AddArg(v0)
  4189  		return true
  4190  	}
  4191  	return false
  4192  }
  4193  func rewriteValueAMD64_OpAMD64ANDQmodify_0(v *Value) bool {
  4194  	// match: (ANDQmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  4195  	// cond: is32Bit(off1+off2)
  4196  	// result: (ANDQmodify [off1+off2] {sym} base val mem)
  4197  	for {
  4198  		off1 := v.AuxInt
  4199  		sym := v.Aux
  4200  		mem := v.Args[2]
  4201  		v_0 := v.Args[0]
  4202  		if v_0.Op != OpAMD64ADDQconst {
  4203  			break
  4204  		}
  4205  		off2 := v_0.AuxInt
  4206  		base := v_0.Args[0]
  4207  		val := v.Args[1]
  4208  		if !(is32Bit(off1 + off2)) {
  4209  			break
  4210  		}
  4211  		v.reset(OpAMD64ANDQmodify)
  4212  		v.AuxInt = off1 + off2
  4213  		v.Aux = sym
  4214  		v.AddArg(base)
  4215  		v.AddArg(val)
  4216  		v.AddArg(mem)
  4217  		return true
  4218  	}
  4219  	// match: (ANDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  4220  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4221  	// result: (ANDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  4222  	for {
  4223  		off1 := v.AuxInt
  4224  		sym1 := v.Aux
  4225  		mem := v.Args[2]
  4226  		v_0 := v.Args[0]
  4227  		if v_0.Op != OpAMD64LEAQ {
  4228  			break
  4229  		}
  4230  		off2 := v_0.AuxInt
  4231  		sym2 := v_0.Aux
  4232  		base := v_0.Args[0]
  4233  		val := v.Args[1]
  4234  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4235  			break
  4236  		}
  4237  		v.reset(OpAMD64ANDQmodify)
  4238  		v.AuxInt = off1 + off2
  4239  		v.Aux = mergeSym(sym1, sym2)
  4240  		v.AddArg(base)
  4241  		v.AddArg(val)
  4242  		v.AddArg(mem)
  4243  		return true
  4244  	}
  4245  	return false
  4246  }
  4247  func rewriteValueAMD64_OpAMD64BSFQ_0(v *Value) bool {
  4248  	b := v.Block
  4249  	// match: (BSFQ (ORQconst <t> [1<<8] (MOVBQZX x)))
  4250  	// result: (BSFQ (ORQconst <t> [1<<8] x))
  4251  	for {
  4252  		v_0 := v.Args[0]
  4253  		if v_0.Op != OpAMD64ORQconst {
  4254  			break
  4255  		}
  4256  		t := v_0.Type
  4257  		if v_0.AuxInt != 1<<8 {
  4258  			break
  4259  		}
  4260  		v_0_0 := v_0.Args[0]
  4261  		if v_0_0.Op != OpAMD64MOVBQZX {
  4262  			break
  4263  		}
  4264  		x := v_0_0.Args[0]
  4265  		v.reset(OpAMD64BSFQ)
  4266  		v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t)
  4267  		v0.AuxInt = 1 << 8
  4268  		v0.AddArg(x)
  4269  		v.AddArg(v0)
  4270  		return true
  4271  	}
  4272  	// match: (BSFQ (ORQconst <t> [1<<16] (MOVWQZX x)))
  4273  	// result: (BSFQ (ORQconst <t> [1<<16] x))
  4274  	for {
  4275  		v_0 := v.Args[0]
  4276  		if v_0.Op != OpAMD64ORQconst {
  4277  			break
  4278  		}
  4279  		t := v_0.Type
  4280  		if v_0.AuxInt != 1<<16 {
  4281  			break
  4282  		}
  4283  		v_0_0 := v_0.Args[0]
  4284  		if v_0_0.Op != OpAMD64MOVWQZX {
  4285  			break
  4286  		}
  4287  		x := v_0_0.Args[0]
  4288  		v.reset(OpAMD64BSFQ)
  4289  		v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t)
  4290  		v0.AuxInt = 1 << 16
  4291  		v0.AddArg(x)
  4292  		v.AddArg(v0)
  4293  		return true
  4294  	}
  4295  	return false
  4296  }
  4297  func rewriteValueAMD64_OpAMD64BTCLconst_0(v *Value) bool {
  4298  	// match: (BTCLconst [c] (XORLconst [d] x))
  4299  	// result: (XORLconst [d ^ 1<<uint32(c)] x)
  4300  	for {
  4301  		c := v.AuxInt
  4302  		v_0 := v.Args[0]
  4303  		if v_0.Op != OpAMD64XORLconst {
  4304  			break
  4305  		}
  4306  		d := v_0.AuxInt
  4307  		x := v_0.Args[0]
  4308  		v.reset(OpAMD64XORLconst)
  4309  		v.AuxInt = d ^ 1<<uint32(c)
  4310  		v.AddArg(x)
  4311  		return true
  4312  	}
  4313  	// match: (BTCLconst [c] (BTCLconst [d] x))
  4314  	// result: (XORLconst [1<<uint32(c) ^ 1<<uint32(d)] x)
  4315  	for {
  4316  		c := v.AuxInt
  4317  		v_0 := v.Args[0]
  4318  		if v_0.Op != OpAMD64BTCLconst {
  4319  			break
  4320  		}
  4321  		d := v_0.AuxInt
  4322  		x := v_0.Args[0]
  4323  		v.reset(OpAMD64XORLconst)
  4324  		v.AuxInt = 1<<uint32(c) ^ 1<<uint32(d)
  4325  		v.AddArg(x)
  4326  		return true
  4327  	}
  4328  	// match: (BTCLconst [c] (MOVLconst [d]))
  4329  	// result: (MOVLconst [d^(1<<uint32(c))])
  4330  	for {
  4331  		c := v.AuxInt
  4332  		v_0 := v.Args[0]
  4333  		if v_0.Op != OpAMD64MOVLconst {
  4334  			break
  4335  		}
  4336  		d := v_0.AuxInt
  4337  		v.reset(OpAMD64MOVLconst)
  4338  		v.AuxInt = d ^ (1 << uint32(c))
  4339  		return true
  4340  	}
  4341  	return false
  4342  }
  4343  func rewriteValueAMD64_OpAMD64BTCLconstmodify_0(v *Value) bool {
  4344  	// match: (BTCLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  4345  	// cond: ValAndOff(valoff1).canAdd(off2)
  4346  	// result: (BTCLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  4347  	for {
  4348  		valoff1 := v.AuxInt
  4349  		sym := v.Aux
  4350  		mem := v.Args[1]
  4351  		v_0 := v.Args[0]
  4352  		if v_0.Op != OpAMD64ADDQconst {
  4353  			break
  4354  		}
  4355  		off2 := v_0.AuxInt
  4356  		base := v_0.Args[0]
  4357  		if !(ValAndOff(valoff1).canAdd(off2)) {
  4358  			break
  4359  		}
  4360  		v.reset(OpAMD64BTCLconstmodify)
  4361  		v.AuxInt = ValAndOff(valoff1).add(off2)
  4362  		v.Aux = sym
  4363  		v.AddArg(base)
  4364  		v.AddArg(mem)
  4365  		return true
  4366  	}
  4367  	// match: (BTCLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  4368  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  4369  	// result: (BTCLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  4370  	for {
  4371  		valoff1 := v.AuxInt
  4372  		sym1 := v.Aux
  4373  		mem := v.Args[1]
  4374  		v_0 := v.Args[0]
  4375  		if v_0.Op != OpAMD64LEAQ {
  4376  			break
  4377  		}
  4378  		off2 := v_0.AuxInt
  4379  		sym2 := v_0.Aux
  4380  		base := v_0.Args[0]
  4381  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  4382  			break
  4383  		}
  4384  		v.reset(OpAMD64BTCLconstmodify)
  4385  		v.AuxInt = ValAndOff(valoff1).add(off2)
  4386  		v.Aux = mergeSym(sym1, sym2)
  4387  		v.AddArg(base)
  4388  		v.AddArg(mem)
  4389  		return true
  4390  	}
  4391  	return false
  4392  }
  4393  func rewriteValueAMD64_OpAMD64BTCLmodify_0(v *Value) bool {
  4394  	// match: (BTCLmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  4395  	// cond: is32Bit(off1+off2)
  4396  	// result: (BTCLmodify [off1+off2] {sym} base val mem)
  4397  	for {
  4398  		off1 := v.AuxInt
  4399  		sym := v.Aux
  4400  		mem := v.Args[2]
  4401  		v_0 := v.Args[0]
  4402  		if v_0.Op != OpAMD64ADDQconst {
  4403  			break
  4404  		}
  4405  		off2 := v_0.AuxInt
  4406  		base := v_0.Args[0]
  4407  		val := v.Args[1]
  4408  		if !(is32Bit(off1 + off2)) {
  4409  			break
  4410  		}
  4411  		v.reset(OpAMD64BTCLmodify)
  4412  		v.AuxInt = off1 + off2
  4413  		v.Aux = sym
  4414  		v.AddArg(base)
  4415  		v.AddArg(val)
  4416  		v.AddArg(mem)
  4417  		return true
  4418  	}
  4419  	// match: (BTCLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  4420  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4421  	// result: (BTCLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  4422  	for {
  4423  		off1 := v.AuxInt
  4424  		sym1 := v.Aux
  4425  		mem := v.Args[2]
  4426  		v_0 := v.Args[0]
  4427  		if v_0.Op != OpAMD64LEAQ {
  4428  			break
  4429  		}
  4430  		off2 := v_0.AuxInt
  4431  		sym2 := v_0.Aux
  4432  		base := v_0.Args[0]
  4433  		val := v.Args[1]
  4434  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4435  			break
  4436  		}
  4437  		v.reset(OpAMD64BTCLmodify)
  4438  		v.AuxInt = off1 + off2
  4439  		v.Aux = mergeSym(sym1, sym2)
  4440  		v.AddArg(base)
  4441  		v.AddArg(val)
  4442  		v.AddArg(mem)
  4443  		return true
  4444  	}
  4445  	return false
  4446  }
  4447  func rewriteValueAMD64_OpAMD64BTCQconst_0(v *Value) bool {
  4448  	// match: (BTCQconst [c] (XORQconst [d] x))
  4449  	// result: (XORQconst [d ^ 1<<uint32(c)] x)
  4450  	for {
  4451  		c := v.AuxInt
  4452  		v_0 := v.Args[0]
  4453  		if v_0.Op != OpAMD64XORQconst {
  4454  			break
  4455  		}
  4456  		d := v_0.AuxInt
  4457  		x := v_0.Args[0]
  4458  		v.reset(OpAMD64XORQconst)
  4459  		v.AuxInt = d ^ 1<<uint32(c)
  4460  		v.AddArg(x)
  4461  		return true
  4462  	}
  4463  	// match: (BTCQconst [c] (BTCQconst [d] x))
  4464  	// result: (XORQconst [1<<uint32(c) ^ 1<<uint32(d)] x)
  4465  	for {
  4466  		c := v.AuxInt
  4467  		v_0 := v.Args[0]
  4468  		if v_0.Op != OpAMD64BTCQconst {
  4469  			break
  4470  		}
  4471  		d := v_0.AuxInt
  4472  		x := v_0.Args[0]
  4473  		v.reset(OpAMD64XORQconst)
  4474  		v.AuxInt = 1<<uint32(c) ^ 1<<uint32(d)
  4475  		v.AddArg(x)
  4476  		return true
  4477  	}
  4478  	// match: (BTCQconst [c] (MOVQconst [d]))
  4479  	// result: (MOVQconst [d^(1<<uint32(c))])
  4480  	for {
  4481  		c := v.AuxInt
  4482  		v_0 := v.Args[0]
  4483  		if v_0.Op != OpAMD64MOVQconst {
  4484  			break
  4485  		}
  4486  		d := v_0.AuxInt
  4487  		v.reset(OpAMD64MOVQconst)
  4488  		v.AuxInt = d ^ (1 << uint32(c))
  4489  		return true
  4490  	}
  4491  	return false
  4492  }
  4493  func rewriteValueAMD64_OpAMD64BTCQconstmodify_0(v *Value) bool {
  4494  	// match: (BTCQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  4495  	// cond: ValAndOff(valoff1).canAdd(off2)
  4496  	// result: (BTCQconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  4497  	for {
  4498  		valoff1 := v.AuxInt
  4499  		sym := v.Aux
  4500  		mem := v.Args[1]
  4501  		v_0 := v.Args[0]
  4502  		if v_0.Op != OpAMD64ADDQconst {
  4503  			break
  4504  		}
  4505  		off2 := v_0.AuxInt
  4506  		base := v_0.Args[0]
  4507  		if !(ValAndOff(valoff1).canAdd(off2)) {
  4508  			break
  4509  		}
  4510  		v.reset(OpAMD64BTCQconstmodify)
  4511  		v.AuxInt = ValAndOff(valoff1).add(off2)
  4512  		v.Aux = sym
  4513  		v.AddArg(base)
  4514  		v.AddArg(mem)
  4515  		return true
  4516  	}
  4517  	// match: (BTCQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  4518  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  4519  	// result: (BTCQconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  4520  	for {
  4521  		valoff1 := v.AuxInt
  4522  		sym1 := v.Aux
  4523  		mem := v.Args[1]
  4524  		v_0 := v.Args[0]
  4525  		if v_0.Op != OpAMD64LEAQ {
  4526  			break
  4527  		}
  4528  		off2 := v_0.AuxInt
  4529  		sym2 := v_0.Aux
  4530  		base := v_0.Args[0]
  4531  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  4532  			break
  4533  		}
  4534  		v.reset(OpAMD64BTCQconstmodify)
  4535  		v.AuxInt = ValAndOff(valoff1).add(off2)
  4536  		v.Aux = mergeSym(sym1, sym2)
  4537  		v.AddArg(base)
  4538  		v.AddArg(mem)
  4539  		return true
  4540  	}
  4541  	return false
  4542  }
  4543  func rewriteValueAMD64_OpAMD64BTCQmodify_0(v *Value) bool {
  4544  	// match: (BTCQmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  4545  	// cond: is32Bit(off1+off2)
  4546  	// result: (BTCQmodify [off1+off2] {sym} base val mem)
  4547  	for {
  4548  		off1 := v.AuxInt
  4549  		sym := v.Aux
  4550  		mem := v.Args[2]
  4551  		v_0 := v.Args[0]
  4552  		if v_0.Op != OpAMD64ADDQconst {
  4553  			break
  4554  		}
  4555  		off2 := v_0.AuxInt
  4556  		base := v_0.Args[0]
  4557  		val := v.Args[1]
  4558  		if !(is32Bit(off1 + off2)) {
  4559  			break
  4560  		}
  4561  		v.reset(OpAMD64BTCQmodify)
  4562  		v.AuxInt = off1 + off2
  4563  		v.Aux = sym
  4564  		v.AddArg(base)
  4565  		v.AddArg(val)
  4566  		v.AddArg(mem)
  4567  		return true
  4568  	}
  4569  	// match: (BTCQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  4570  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4571  	// result: (BTCQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  4572  	for {
  4573  		off1 := v.AuxInt
  4574  		sym1 := v.Aux
  4575  		mem := v.Args[2]
  4576  		v_0 := v.Args[0]
  4577  		if v_0.Op != OpAMD64LEAQ {
  4578  			break
  4579  		}
  4580  		off2 := v_0.AuxInt
  4581  		sym2 := v_0.Aux
  4582  		base := v_0.Args[0]
  4583  		val := v.Args[1]
  4584  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4585  			break
  4586  		}
  4587  		v.reset(OpAMD64BTCQmodify)
  4588  		v.AuxInt = off1 + off2
  4589  		v.Aux = mergeSym(sym1, sym2)
  4590  		v.AddArg(base)
  4591  		v.AddArg(val)
  4592  		v.AddArg(mem)
  4593  		return true
  4594  	}
  4595  	return false
  4596  }
  4597  func rewriteValueAMD64_OpAMD64BTLconst_0(v *Value) bool {
  4598  	// match: (BTLconst [c] (SHRQconst [d] x))
  4599  	// cond: (c+d)<64
  4600  	// result: (BTQconst [c+d] x)
  4601  	for {
  4602  		c := v.AuxInt
  4603  		v_0 := v.Args[0]
  4604  		if v_0.Op != OpAMD64SHRQconst {
  4605  			break
  4606  		}
  4607  		d := v_0.AuxInt
  4608  		x := v_0.Args[0]
  4609  		if !((c + d) < 64) {
  4610  			break
  4611  		}
  4612  		v.reset(OpAMD64BTQconst)
  4613  		v.AuxInt = c + d
  4614  		v.AddArg(x)
  4615  		return true
  4616  	}
  4617  	// match: (BTLconst [c] (SHLQconst [d] x))
  4618  	// cond: c>d
  4619  	// result: (BTLconst [c-d] x)
  4620  	for {
  4621  		c := v.AuxInt
  4622  		v_0 := v.Args[0]
  4623  		if v_0.Op != OpAMD64SHLQconst {
  4624  			break
  4625  		}
  4626  		d := v_0.AuxInt
  4627  		x := v_0.Args[0]
  4628  		if !(c > d) {
  4629  			break
  4630  		}
  4631  		v.reset(OpAMD64BTLconst)
  4632  		v.AuxInt = c - d
  4633  		v.AddArg(x)
  4634  		return true
  4635  	}
  4636  	// match: (BTLconst [0] s:(SHRQ x y))
  4637  	// result: (BTQ y x)
  4638  	for {
  4639  		if v.AuxInt != 0 {
  4640  			break
  4641  		}
  4642  		s := v.Args[0]
  4643  		if s.Op != OpAMD64SHRQ {
  4644  			break
  4645  		}
  4646  		y := s.Args[1]
  4647  		x := s.Args[0]
  4648  		v.reset(OpAMD64BTQ)
  4649  		v.AddArg(y)
  4650  		v.AddArg(x)
  4651  		return true
  4652  	}
  4653  	// match: (BTLconst [c] (SHRLconst [d] x))
  4654  	// cond: (c+d)<32
  4655  	// result: (BTLconst [c+d] x)
  4656  	for {
  4657  		c := v.AuxInt
  4658  		v_0 := v.Args[0]
  4659  		if v_0.Op != OpAMD64SHRLconst {
  4660  			break
  4661  		}
  4662  		d := v_0.AuxInt
  4663  		x := v_0.Args[0]
  4664  		if !((c + d) < 32) {
  4665  			break
  4666  		}
  4667  		v.reset(OpAMD64BTLconst)
  4668  		v.AuxInt = c + d
  4669  		v.AddArg(x)
  4670  		return true
  4671  	}
  4672  	// match: (BTLconst [c] (SHLLconst [d] x))
  4673  	// cond: c>d
  4674  	// result: (BTLconst [c-d] x)
  4675  	for {
  4676  		c := v.AuxInt
  4677  		v_0 := v.Args[0]
  4678  		if v_0.Op != OpAMD64SHLLconst {
  4679  			break
  4680  		}
  4681  		d := v_0.AuxInt
  4682  		x := v_0.Args[0]
  4683  		if !(c > d) {
  4684  			break
  4685  		}
  4686  		v.reset(OpAMD64BTLconst)
  4687  		v.AuxInt = c - d
  4688  		v.AddArg(x)
  4689  		return true
  4690  	}
  4691  	// match: (BTLconst [0] s:(SHRL x y))
  4692  	// result: (BTL y x)
  4693  	for {
  4694  		if v.AuxInt != 0 {
  4695  			break
  4696  		}
  4697  		s := v.Args[0]
  4698  		if s.Op != OpAMD64SHRL {
  4699  			break
  4700  		}
  4701  		y := s.Args[1]
  4702  		x := s.Args[0]
  4703  		v.reset(OpAMD64BTL)
  4704  		v.AddArg(y)
  4705  		v.AddArg(x)
  4706  		return true
  4707  	}
  4708  	return false
  4709  }
  4710  func rewriteValueAMD64_OpAMD64BTQconst_0(v *Value) bool {
  4711  	// match: (BTQconst [c] (SHRQconst [d] x))
  4712  	// cond: (c+d)<64
  4713  	// result: (BTQconst [c+d] x)
  4714  	for {
  4715  		c := v.AuxInt
  4716  		v_0 := v.Args[0]
  4717  		if v_0.Op != OpAMD64SHRQconst {
  4718  			break
  4719  		}
  4720  		d := v_0.AuxInt
  4721  		x := v_0.Args[0]
  4722  		if !((c + d) < 64) {
  4723  			break
  4724  		}
  4725  		v.reset(OpAMD64BTQconst)
  4726  		v.AuxInt = c + d
  4727  		v.AddArg(x)
  4728  		return true
  4729  	}
  4730  	// match: (BTQconst [c] (SHLQconst [d] x))
  4731  	// cond: c>d
  4732  	// result: (BTQconst [c-d] x)
  4733  	for {
  4734  		c := v.AuxInt
  4735  		v_0 := v.Args[0]
  4736  		if v_0.Op != OpAMD64SHLQconst {
  4737  			break
  4738  		}
  4739  		d := v_0.AuxInt
  4740  		x := v_0.Args[0]
  4741  		if !(c > d) {
  4742  			break
  4743  		}
  4744  		v.reset(OpAMD64BTQconst)
  4745  		v.AuxInt = c - d
  4746  		v.AddArg(x)
  4747  		return true
  4748  	}
  4749  	// match: (BTQconst [0] s:(SHRQ x y))
  4750  	// result: (BTQ y x)
  4751  	for {
  4752  		if v.AuxInt != 0 {
  4753  			break
  4754  		}
  4755  		s := v.Args[0]
  4756  		if s.Op != OpAMD64SHRQ {
  4757  			break
  4758  		}
  4759  		y := s.Args[1]
  4760  		x := s.Args[0]
  4761  		v.reset(OpAMD64BTQ)
  4762  		v.AddArg(y)
  4763  		v.AddArg(x)
  4764  		return true
  4765  	}
  4766  	return false
  4767  }
  4768  func rewriteValueAMD64_OpAMD64BTRLconst_0(v *Value) bool {
  4769  	// match: (BTRLconst [c] (BTSLconst [c] x))
  4770  	// result: (BTRLconst [c] x)
  4771  	for {
  4772  		c := v.AuxInt
  4773  		v_0 := v.Args[0]
  4774  		if v_0.Op != OpAMD64BTSLconst || v_0.AuxInt != c {
  4775  			break
  4776  		}
  4777  		x := v_0.Args[0]
  4778  		v.reset(OpAMD64BTRLconst)
  4779  		v.AuxInt = c
  4780  		v.AddArg(x)
  4781  		return true
  4782  	}
  4783  	// match: (BTRLconst [c] (BTCLconst [c] x))
  4784  	// result: (BTRLconst [c] x)
  4785  	for {
  4786  		c := v.AuxInt
  4787  		v_0 := v.Args[0]
  4788  		if v_0.Op != OpAMD64BTCLconst || v_0.AuxInt != c {
  4789  			break
  4790  		}
  4791  		x := v_0.Args[0]
  4792  		v.reset(OpAMD64BTRLconst)
  4793  		v.AuxInt = c
  4794  		v.AddArg(x)
  4795  		return true
  4796  	}
  4797  	// match: (BTRLconst [c] (ANDLconst [d] x))
  4798  	// result: (ANDLconst [d &^ (1<<uint32(c))] x)
  4799  	for {
  4800  		c := v.AuxInt
  4801  		v_0 := v.Args[0]
  4802  		if v_0.Op != OpAMD64ANDLconst {
  4803  			break
  4804  		}
  4805  		d := v_0.AuxInt
  4806  		x := v_0.Args[0]
  4807  		v.reset(OpAMD64ANDLconst)
  4808  		v.AuxInt = d &^ (1 << uint32(c))
  4809  		v.AddArg(x)
  4810  		return true
  4811  	}
  4812  	// match: (BTRLconst [c] (BTRLconst [d] x))
  4813  	// result: (ANDLconst [^(1<<uint32(c) | 1<<uint32(d))] x)
  4814  	for {
  4815  		c := v.AuxInt
  4816  		v_0 := v.Args[0]
  4817  		if v_0.Op != OpAMD64BTRLconst {
  4818  			break
  4819  		}
  4820  		d := v_0.AuxInt
  4821  		x := v_0.Args[0]
  4822  		v.reset(OpAMD64ANDLconst)
  4823  		v.AuxInt = ^(1<<uint32(c) | 1<<uint32(d))
  4824  		v.AddArg(x)
  4825  		return true
  4826  	}
  4827  	// match: (BTRLconst [c] (MOVLconst [d]))
  4828  	// result: (MOVLconst [d&^(1<<uint32(c))])
  4829  	for {
  4830  		c := v.AuxInt
  4831  		v_0 := v.Args[0]
  4832  		if v_0.Op != OpAMD64MOVLconst {
  4833  			break
  4834  		}
  4835  		d := v_0.AuxInt
  4836  		v.reset(OpAMD64MOVLconst)
  4837  		v.AuxInt = d &^ (1 << uint32(c))
  4838  		return true
  4839  	}
  4840  	return false
  4841  }
  4842  func rewriteValueAMD64_OpAMD64BTRLconstmodify_0(v *Value) bool {
  4843  	// match: (BTRLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  4844  	// cond: ValAndOff(valoff1).canAdd(off2)
  4845  	// result: (BTRLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  4846  	for {
  4847  		valoff1 := v.AuxInt
  4848  		sym := v.Aux
  4849  		mem := v.Args[1]
  4850  		v_0 := v.Args[0]
  4851  		if v_0.Op != OpAMD64ADDQconst {
  4852  			break
  4853  		}
  4854  		off2 := v_0.AuxInt
  4855  		base := v_0.Args[0]
  4856  		if !(ValAndOff(valoff1).canAdd(off2)) {
  4857  			break
  4858  		}
  4859  		v.reset(OpAMD64BTRLconstmodify)
  4860  		v.AuxInt = ValAndOff(valoff1).add(off2)
  4861  		v.Aux = sym
  4862  		v.AddArg(base)
  4863  		v.AddArg(mem)
  4864  		return true
  4865  	}
  4866  	// match: (BTRLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  4867  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  4868  	// result: (BTRLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  4869  	for {
  4870  		valoff1 := v.AuxInt
  4871  		sym1 := v.Aux
  4872  		mem := v.Args[1]
  4873  		v_0 := v.Args[0]
  4874  		if v_0.Op != OpAMD64LEAQ {
  4875  			break
  4876  		}
  4877  		off2 := v_0.AuxInt
  4878  		sym2 := v_0.Aux
  4879  		base := v_0.Args[0]
  4880  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  4881  			break
  4882  		}
  4883  		v.reset(OpAMD64BTRLconstmodify)
  4884  		v.AuxInt = ValAndOff(valoff1).add(off2)
  4885  		v.Aux = mergeSym(sym1, sym2)
  4886  		v.AddArg(base)
  4887  		v.AddArg(mem)
  4888  		return true
  4889  	}
  4890  	return false
  4891  }
  4892  func rewriteValueAMD64_OpAMD64BTRLmodify_0(v *Value) bool {
  4893  	// match: (BTRLmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  4894  	// cond: is32Bit(off1+off2)
  4895  	// result: (BTRLmodify [off1+off2] {sym} base val mem)
  4896  	for {
  4897  		off1 := v.AuxInt
  4898  		sym := v.Aux
  4899  		mem := v.Args[2]
  4900  		v_0 := v.Args[0]
  4901  		if v_0.Op != OpAMD64ADDQconst {
  4902  			break
  4903  		}
  4904  		off2 := v_0.AuxInt
  4905  		base := v_0.Args[0]
  4906  		val := v.Args[1]
  4907  		if !(is32Bit(off1 + off2)) {
  4908  			break
  4909  		}
  4910  		v.reset(OpAMD64BTRLmodify)
  4911  		v.AuxInt = off1 + off2
  4912  		v.Aux = sym
  4913  		v.AddArg(base)
  4914  		v.AddArg(val)
  4915  		v.AddArg(mem)
  4916  		return true
  4917  	}
  4918  	// match: (BTRLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  4919  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4920  	// result: (BTRLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  4921  	for {
  4922  		off1 := v.AuxInt
  4923  		sym1 := v.Aux
  4924  		mem := v.Args[2]
  4925  		v_0 := v.Args[0]
  4926  		if v_0.Op != OpAMD64LEAQ {
  4927  			break
  4928  		}
  4929  		off2 := v_0.AuxInt
  4930  		sym2 := v_0.Aux
  4931  		base := v_0.Args[0]
  4932  		val := v.Args[1]
  4933  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4934  			break
  4935  		}
  4936  		v.reset(OpAMD64BTRLmodify)
  4937  		v.AuxInt = off1 + off2
  4938  		v.Aux = mergeSym(sym1, sym2)
  4939  		v.AddArg(base)
  4940  		v.AddArg(val)
  4941  		v.AddArg(mem)
  4942  		return true
  4943  	}
  4944  	return false
  4945  }
  4946  func rewriteValueAMD64_OpAMD64BTRQconst_0(v *Value) bool {
  4947  	// match: (BTRQconst [c] (BTSQconst [c] x))
  4948  	// result: (BTRQconst [c] x)
  4949  	for {
  4950  		c := v.AuxInt
  4951  		v_0 := v.Args[0]
  4952  		if v_0.Op != OpAMD64BTSQconst || v_0.AuxInt != c {
  4953  			break
  4954  		}
  4955  		x := v_0.Args[0]
  4956  		v.reset(OpAMD64BTRQconst)
  4957  		v.AuxInt = c
  4958  		v.AddArg(x)
  4959  		return true
  4960  	}
  4961  	// match: (BTRQconst [c] (BTCQconst [c] x))
  4962  	// result: (BTRQconst [c] x)
  4963  	for {
  4964  		c := v.AuxInt
  4965  		v_0 := v.Args[0]
  4966  		if v_0.Op != OpAMD64BTCQconst || v_0.AuxInt != c {
  4967  			break
  4968  		}
  4969  		x := v_0.Args[0]
  4970  		v.reset(OpAMD64BTRQconst)
  4971  		v.AuxInt = c
  4972  		v.AddArg(x)
  4973  		return true
  4974  	}
  4975  	// match: (BTRQconst [c] (ANDQconst [d] x))
  4976  	// result: (ANDQconst [d &^ (1<<uint32(c))] x)
  4977  	for {
  4978  		c := v.AuxInt
  4979  		v_0 := v.Args[0]
  4980  		if v_0.Op != OpAMD64ANDQconst {
  4981  			break
  4982  		}
  4983  		d := v_0.AuxInt
  4984  		x := v_0.Args[0]
  4985  		v.reset(OpAMD64ANDQconst)
  4986  		v.AuxInt = d &^ (1 << uint32(c))
  4987  		v.AddArg(x)
  4988  		return true
  4989  	}
  4990  	// match: (BTRQconst [c] (BTRQconst [d] x))
  4991  	// result: (ANDQconst [^(1<<uint32(c) | 1<<uint32(d))] x)
  4992  	for {
  4993  		c := v.AuxInt
  4994  		v_0 := v.Args[0]
  4995  		if v_0.Op != OpAMD64BTRQconst {
  4996  			break
  4997  		}
  4998  		d := v_0.AuxInt
  4999  		x := v_0.Args[0]
  5000  		v.reset(OpAMD64ANDQconst)
  5001  		v.AuxInt = ^(1<<uint32(c) | 1<<uint32(d))
  5002  		v.AddArg(x)
  5003  		return true
  5004  	}
  5005  	// match: (BTRQconst [c] (MOVQconst [d]))
  5006  	// result: (MOVQconst [d&^(1<<uint32(c))])
  5007  	for {
  5008  		c := v.AuxInt
  5009  		v_0 := v.Args[0]
  5010  		if v_0.Op != OpAMD64MOVQconst {
  5011  			break
  5012  		}
  5013  		d := v_0.AuxInt
  5014  		v.reset(OpAMD64MOVQconst)
  5015  		v.AuxInt = d &^ (1 << uint32(c))
  5016  		return true
  5017  	}
  5018  	return false
  5019  }
  5020  func rewriteValueAMD64_OpAMD64BTRQconstmodify_0(v *Value) bool {
  5021  	// match: (BTRQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  5022  	// cond: ValAndOff(valoff1).canAdd(off2)
  5023  	// result: (BTRQconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  5024  	for {
  5025  		valoff1 := v.AuxInt
  5026  		sym := v.Aux
  5027  		mem := v.Args[1]
  5028  		v_0 := v.Args[0]
  5029  		if v_0.Op != OpAMD64ADDQconst {
  5030  			break
  5031  		}
  5032  		off2 := v_0.AuxInt
  5033  		base := v_0.Args[0]
  5034  		if !(ValAndOff(valoff1).canAdd(off2)) {
  5035  			break
  5036  		}
  5037  		v.reset(OpAMD64BTRQconstmodify)
  5038  		v.AuxInt = ValAndOff(valoff1).add(off2)
  5039  		v.Aux = sym
  5040  		v.AddArg(base)
  5041  		v.AddArg(mem)
  5042  		return true
  5043  	}
  5044  	// match: (BTRQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  5045  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  5046  	// result: (BTRQconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  5047  	for {
  5048  		valoff1 := v.AuxInt
  5049  		sym1 := v.Aux
  5050  		mem := v.Args[1]
  5051  		v_0 := v.Args[0]
  5052  		if v_0.Op != OpAMD64LEAQ {
  5053  			break
  5054  		}
  5055  		off2 := v_0.AuxInt
  5056  		sym2 := v_0.Aux
  5057  		base := v_0.Args[0]
  5058  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  5059  			break
  5060  		}
  5061  		v.reset(OpAMD64BTRQconstmodify)
  5062  		v.AuxInt = ValAndOff(valoff1).add(off2)
  5063  		v.Aux = mergeSym(sym1, sym2)
  5064  		v.AddArg(base)
  5065  		v.AddArg(mem)
  5066  		return true
  5067  	}
  5068  	return false
  5069  }
  5070  func rewriteValueAMD64_OpAMD64BTRQmodify_0(v *Value) bool {
  5071  	// match: (BTRQmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  5072  	// cond: is32Bit(off1+off2)
  5073  	// result: (BTRQmodify [off1+off2] {sym} base val mem)
  5074  	for {
  5075  		off1 := v.AuxInt
  5076  		sym := v.Aux
  5077  		mem := v.Args[2]
  5078  		v_0 := v.Args[0]
  5079  		if v_0.Op != OpAMD64ADDQconst {
  5080  			break
  5081  		}
  5082  		off2 := v_0.AuxInt
  5083  		base := v_0.Args[0]
  5084  		val := v.Args[1]
  5085  		if !(is32Bit(off1 + off2)) {
  5086  			break
  5087  		}
  5088  		v.reset(OpAMD64BTRQmodify)
  5089  		v.AuxInt = off1 + off2
  5090  		v.Aux = sym
  5091  		v.AddArg(base)
  5092  		v.AddArg(val)
  5093  		v.AddArg(mem)
  5094  		return true
  5095  	}
  5096  	// match: (BTRQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  5097  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  5098  	// result: (BTRQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  5099  	for {
  5100  		off1 := v.AuxInt
  5101  		sym1 := v.Aux
  5102  		mem := v.Args[2]
  5103  		v_0 := v.Args[0]
  5104  		if v_0.Op != OpAMD64LEAQ {
  5105  			break
  5106  		}
  5107  		off2 := v_0.AuxInt
  5108  		sym2 := v_0.Aux
  5109  		base := v_0.Args[0]
  5110  		val := v.Args[1]
  5111  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  5112  			break
  5113  		}
  5114  		v.reset(OpAMD64BTRQmodify)
  5115  		v.AuxInt = off1 + off2
  5116  		v.Aux = mergeSym(sym1, sym2)
  5117  		v.AddArg(base)
  5118  		v.AddArg(val)
  5119  		v.AddArg(mem)
  5120  		return true
  5121  	}
  5122  	return false
  5123  }
  5124  func rewriteValueAMD64_OpAMD64BTSLconst_0(v *Value) bool {
  5125  	// match: (BTSLconst [c] (BTRLconst [c] x))
  5126  	// result: (BTSLconst [c] x)
  5127  	for {
  5128  		c := v.AuxInt
  5129  		v_0 := v.Args[0]
  5130  		if v_0.Op != OpAMD64BTRLconst || v_0.AuxInt != c {
  5131  			break
  5132  		}
  5133  		x := v_0.Args[0]
  5134  		v.reset(OpAMD64BTSLconst)
  5135  		v.AuxInt = c
  5136  		v.AddArg(x)
  5137  		return true
  5138  	}
  5139  	// match: (BTSLconst [c] (BTCLconst [c] x))
  5140  	// result: (BTSLconst [c] x)
  5141  	for {
  5142  		c := v.AuxInt
  5143  		v_0 := v.Args[0]
  5144  		if v_0.Op != OpAMD64BTCLconst || v_0.AuxInt != c {
  5145  			break
  5146  		}
  5147  		x := v_0.Args[0]
  5148  		v.reset(OpAMD64BTSLconst)
  5149  		v.AuxInt = c
  5150  		v.AddArg(x)
  5151  		return true
  5152  	}
  5153  	// match: (BTSLconst [c] (ORLconst [d] x))
  5154  	// result: (ORLconst [d | 1<<uint32(c)] x)
  5155  	for {
  5156  		c := v.AuxInt
  5157  		v_0 := v.Args[0]
  5158  		if v_0.Op != OpAMD64ORLconst {
  5159  			break
  5160  		}
  5161  		d := v_0.AuxInt
  5162  		x := v_0.Args[0]
  5163  		v.reset(OpAMD64ORLconst)
  5164  		v.AuxInt = d | 1<<uint32(c)
  5165  		v.AddArg(x)
  5166  		return true
  5167  	}
  5168  	// match: (BTSLconst [c] (BTSLconst [d] x))
  5169  	// result: (ORLconst [1<<uint32(d) | 1<<uint32(c)] x)
  5170  	for {
  5171  		c := v.AuxInt
  5172  		v_0 := v.Args[0]
  5173  		if v_0.Op != OpAMD64BTSLconst {
  5174  			break
  5175  		}
  5176  		d := v_0.AuxInt
  5177  		x := v_0.Args[0]
  5178  		v.reset(OpAMD64ORLconst)
  5179  		v.AuxInt = 1<<uint32(d) | 1<<uint32(c)
  5180  		v.AddArg(x)
  5181  		return true
  5182  	}
  5183  	// match: (BTSLconst [c] (MOVLconst [d]))
  5184  	// result: (MOVLconst [d|(1<<uint32(c))])
  5185  	for {
  5186  		c := v.AuxInt
  5187  		v_0 := v.Args[0]
  5188  		if v_0.Op != OpAMD64MOVLconst {
  5189  			break
  5190  		}
  5191  		d := v_0.AuxInt
  5192  		v.reset(OpAMD64MOVLconst)
  5193  		v.AuxInt = d | (1 << uint32(c))
  5194  		return true
  5195  	}
  5196  	return false
  5197  }
  5198  func rewriteValueAMD64_OpAMD64BTSLconstmodify_0(v *Value) bool {
  5199  	// match: (BTSLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  5200  	// cond: ValAndOff(valoff1).canAdd(off2)
  5201  	// result: (BTSLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  5202  	for {
  5203  		valoff1 := v.AuxInt
  5204  		sym := v.Aux
  5205  		mem := v.Args[1]
  5206  		v_0 := v.Args[0]
  5207  		if v_0.Op != OpAMD64ADDQconst {
  5208  			break
  5209  		}
  5210  		off2 := v_0.AuxInt
  5211  		base := v_0.Args[0]
  5212  		if !(ValAndOff(valoff1).canAdd(off2)) {
  5213  			break
  5214  		}
  5215  		v.reset(OpAMD64BTSLconstmodify)
  5216  		v.AuxInt = ValAndOff(valoff1).add(off2)
  5217  		v.Aux = sym
  5218  		v.AddArg(base)
  5219  		v.AddArg(mem)
  5220  		return true
  5221  	}
  5222  	// match: (BTSLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  5223  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  5224  	// result: (BTSLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  5225  	for {
  5226  		valoff1 := v.AuxInt
  5227  		sym1 := v.Aux
  5228  		mem := v.Args[1]
  5229  		v_0 := v.Args[0]
  5230  		if v_0.Op != OpAMD64LEAQ {
  5231  			break
  5232  		}
  5233  		off2 := v_0.AuxInt
  5234  		sym2 := v_0.Aux
  5235  		base := v_0.Args[0]
  5236  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  5237  			break
  5238  		}
  5239  		v.reset(OpAMD64BTSLconstmodify)
  5240  		v.AuxInt = ValAndOff(valoff1).add(off2)
  5241  		v.Aux = mergeSym(sym1, sym2)
  5242  		v.AddArg(base)
  5243  		v.AddArg(mem)
  5244  		return true
  5245  	}
  5246  	return false
  5247  }
  5248  func rewriteValueAMD64_OpAMD64BTSLmodify_0(v *Value) bool {
  5249  	// match: (BTSLmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  5250  	// cond: is32Bit(off1+off2)
  5251  	// result: (BTSLmodify [off1+off2] {sym} base val mem)
  5252  	for {
  5253  		off1 := v.AuxInt
  5254  		sym := v.Aux
  5255  		mem := v.Args[2]
  5256  		v_0 := v.Args[0]
  5257  		if v_0.Op != OpAMD64ADDQconst {
  5258  			break
  5259  		}
  5260  		off2 := v_0.AuxInt
  5261  		base := v_0.Args[0]
  5262  		val := v.Args[1]
  5263  		if !(is32Bit(off1 + off2)) {
  5264  			break
  5265  		}
  5266  		v.reset(OpAMD64BTSLmodify)
  5267  		v.AuxInt = off1 + off2
  5268  		v.Aux = sym
  5269  		v.AddArg(base)
  5270  		v.AddArg(val)
  5271  		v.AddArg(mem)
  5272  		return true
  5273  	}
  5274  	// match: (BTSLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  5275  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  5276  	// result: (BTSLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  5277  	for {
  5278  		off1 := v.AuxInt
  5279  		sym1 := v.Aux
  5280  		mem := v.Args[2]
  5281  		v_0 := v.Args[0]
  5282  		if v_0.Op != OpAMD64LEAQ {
  5283  			break
  5284  		}
  5285  		off2 := v_0.AuxInt
  5286  		sym2 := v_0.Aux
  5287  		base := v_0.Args[0]
  5288  		val := v.Args[1]
  5289  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  5290  			break
  5291  		}
  5292  		v.reset(OpAMD64BTSLmodify)
  5293  		v.AuxInt = off1 + off2
  5294  		v.Aux = mergeSym(sym1, sym2)
  5295  		v.AddArg(base)
  5296  		v.AddArg(val)
  5297  		v.AddArg(mem)
  5298  		return true
  5299  	}
  5300  	return false
  5301  }
  5302  func rewriteValueAMD64_OpAMD64BTSQconst_0(v *Value) bool {
  5303  	// match: (BTSQconst [c] (BTRQconst [c] x))
  5304  	// result: (BTSQconst [c] x)
  5305  	for {
  5306  		c := v.AuxInt
  5307  		v_0 := v.Args[0]
  5308  		if v_0.Op != OpAMD64BTRQconst || v_0.AuxInt != c {
  5309  			break
  5310  		}
  5311  		x := v_0.Args[0]
  5312  		v.reset(OpAMD64BTSQconst)
  5313  		v.AuxInt = c
  5314  		v.AddArg(x)
  5315  		return true
  5316  	}
  5317  	// match: (BTSQconst [c] (BTCQconst [c] x))
  5318  	// result: (BTSQconst [c] x)
  5319  	for {
  5320  		c := v.AuxInt
  5321  		v_0 := v.Args[0]
  5322  		if v_0.Op != OpAMD64BTCQconst || v_0.AuxInt != c {
  5323  			break
  5324  		}
  5325  		x := v_0.Args[0]
  5326  		v.reset(OpAMD64BTSQconst)
  5327  		v.AuxInt = c
  5328  		v.AddArg(x)
  5329  		return true
  5330  	}
  5331  	// match: (BTSQconst [c] (ORQconst [d] x))
  5332  	// result: (ORQconst [d | 1<<uint32(c)] x)
  5333  	for {
  5334  		c := v.AuxInt
  5335  		v_0 := v.Args[0]
  5336  		if v_0.Op != OpAMD64ORQconst {
  5337  			break
  5338  		}
  5339  		d := v_0.AuxInt
  5340  		x := v_0.Args[0]
  5341  		v.reset(OpAMD64ORQconst)
  5342  		v.AuxInt = d | 1<<uint32(c)
  5343  		v.AddArg(x)
  5344  		return true
  5345  	}
  5346  	// match: (BTSQconst [c] (BTSQconst [d] x))
  5347  	// result: (ORQconst [1<<uint32(d) | 1<<uint32(c)] x)
  5348  	for {
  5349  		c := v.AuxInt
  5350  		v_0 := v.Args[0]
  5351  		if v_0.Op != OpAMD64BTSQconst {
  5352  			break
  5353  		}
  5354  		d := v_0.AuxInt
  5355  		x := v_0.Args[0]
  5356  		v.reset(OpAMD64ORQconst)
  5357  		v.AuxInt = 1<<uint32(d) | 1<<uint32(c)
  5358  		v.AddArg(x)
  5359  		return true
  5360  	}
  5361  	// match: (BTSQconst [c] (MOVQconst [d]))
  5362  	// result: (MOVQconst [d|(1<<uint32(c))])
  5363  	for {
  5364  		c := v.AuxInt
  5365  		v_0 := v.Args[0]
  5366  		if v_0.Op != OpAMD64MOVQconst {
  5367  			break
  5368  		}
  5369  		d := v_0.AuxInt
  5370  		v.reset(OpAMD64MOVQconst)
  5371  		v.AuxInt = d | (1 << uint32(c))
  5372  		return true
  5373  	}
  5374  	return false
  5375  }
  5376  func rewriteValueAMD64_OpAMD64BTSQconstmodify_0(v *Value) bool {
  5377  	// match: (BTSQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  5378  	// cond: ValAndOff(valoff1).canAdd(off2)
  5379  	// result: (BTSQconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  5380  	for {
  5381  		valoff1 := v.AuxInt
  5382  		sym := v.Aux
  5383  		mem := v.Args[1]
  5384  		v_0 := v.Args[0]
  5385  		if v_0.Op != OpAMD64ADDQconst {
  5386  			break
  5387  		}
  5388  		off2 := v_0.AuxInt
  5389  		base := v_0.Args[0]
  5390  		if !(ValAndOff(valoff1).canAdd(off2)) {
  5391  			break
  5392  		}
  5393  		v.reset(OpAMD64BTSQconstmodify)
  5394  		v.AuxInt = ValAndOff(valoff1).add(off2)
  5395  		v.Aux = sym
  5396  		v.AddArg(base)
  5397  		v.AddArg(mem)
  5398  		return true
  5399  	}
  5400  	// match: (BTSQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  5401  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  5402  	// result: (BTSQconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  5403  	for {
  5404  		valoff1 := v.AuxInt
  5405  		sym1 := v.Aux
  5406  		mem := v.Args[1]
  5407  		v_0 := v.Args[0]
  5408  		if v_0.Op != OpAMD64LEAQ {
  5409  			break
  5410  		}
  5411  		off2 := v_0.AuxInt
  5412  		sym2 := v_0.Aux
  5413  		base := v_0.Args[0]
  5414  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  5415  			break
  5416  		}
  5417  		v.reset(OpAMD64BTSQconstmodify)
  5418  		v.AuxInt = ValAndOff(valoff1).add(off2)
  5419  		v.Aux = mergeSym(sym1, sym2)
  5420  		v.AddArg(base)
  5421  		v.AddArg(mem)
  5422  		return true
  5423  	}
  5424  	return false
  5425  }
  5426  func rewriteValueAMD64_OpAMD64BTSQmodify_0(v *Value) bool {
  5427  	// match: (BTSQmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  5428  	// cond: is32Bit(off1+off2)
  5429  	// result: (BTSQmodify [off1+off2] {sym} base val mem)
  5430  	for {
  5431  		off1 := v.AuxInt
  5432  		sym := v.Aux
  5433  		mem := v.Args[2]
  5434  		v_0 := v.Args[0]
  5435  		if v_0.Op != OpAMD64ADDQconst {
  5436  			break
  5437  		}
  5438  		off2 := v_0.AuxInt
  5439  		base := v_0.Args[0]
  5440  		val := v.Args[1]
  5441  		if !(is32Bit(off1 + off2)) {
  5442  			break
  5443  		}
  5444  		v.reset(OpAMD64BTSQmodify)
  5445  		v.AuxInt = off1 + off2
  5446  		v.Aux = sym
  5447  		v.AddArg(base)
  5448  		v.AddArg(val)
  5449  		v.AddArg(mem)
  5450  		return true
  5451  	}
  5452  	// match: (BTSQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  5453  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  5454  	// result: (BTSQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  5455  	for {
  5456  		off1 := v.AuxInt
  5457  		sym1 := v.Aux
  5458  		mem := v.Args[2]
  5459  		v_0 := v.Args[0]
  5460  		if v_0.Op != OpAMD64LEAQ {
  5461  			break
  5462  		}
  5463  		off2 := v_0.AuxInt
  5464  		sym2 := v_0.Aux
  5465  		base := v_0.Args[0]
  5466  		val := v.Args[1]
  5467  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  5468  			break
  5469  		}
  5470  		v.reset(OpAMD64BTSQmodify)
  5471  		v.AuxInt = off1 + off2
  5472  		v.Aux = mergeSym(sym1, sym2)
  5473  		v.AddArg(base)
  5474  		v.AddArg(val)
  5475  		v.AddArg(mem)
  5476  		return true
  5477  	}
  5478  	return false
  5479  }
  5480  func rewriteValueAMD64_OpAMD64CMOVLCC_0(v *Value) bool {
  5481  	// match: (CMOVLCC x y (InvertFlags cond))
  5482  	// result: (CMOVLLS x y cond)
  5483  	for {
  5484  		_ = v.Args[2]
  5485  		x := v.Args[0]
  5486  		y := v.Args[1]
  5487  		v_2 := v.Args[2]
  5488  		if v_2.Op != OpAMD64InvertFlags {
  5489  			break
  5490  		}
  5491  		cond := v_2.Args[0]
  5492  		v.reset(OpAMD64CMOVLLS)
  5493  		v.AddArg(x)
  5494  		v.AddArg(y)
  5495  		v.AddArg(cond)
  5496  		return true
  5497  	}
  5498  	// match: (CMOVLCC _ x (FlagEQ))
  5499  	// result: x
  5500  	for {
  5501  		_ = v.Args[2]
  5502  		x := v.Args[1]
  5503  		v_2 := v.Args[2]
  5504  		if v_2.Op != OpAMD64FlagEQ {
  5505  			break
  5506  		}
  5507  		v.reset(OpCopy)
  5508  		v.Type = x.Type
  5509  		v.AddArg(x)
  5510  		return true
  5511  	}
  5512  	// match: (CMOVLCC _ x (FlagGT_UGT))
  5513  	// result: x
  5514  	for {
  5515  		_ = v.Args[2]
  5516  		x := v.Args[1]
  5517  		v_2 := v.Args[2]
  5518  		if v_2.Op != OpAMD64FlagGT_UGT {
  5519  			break
  5520  		}
  5521  		v.reset(OpCopy)
  5522  		v.Type = x.Type
  5523  		v.AddArg(x)
  5524  		return true
  5525  	}
  5526  	// match: (CMOVLCC y _ (FlagGT_ULT))
  5527  	// result: y
  5528  	for {
  5529  		_ = v.Args[2]
  5530  		y := v.Args[0]
  5531  		v_2 := v.Args[2]
  5532  		if v_2.Op != OpAMD64FlagGT_ULT {
  5533  			break
  5534  		}
  5535  		v.reset(OpCopy)
  5536  		v.Type = y.Type
  5537  		v.AddArg(y)
  5538  		return true
  5539  	}
  5540  	// match: (CMOVLCC y _ (FlagLT_ULT))
  5541  	// result: y
  5542  	for {
  5543  		_ = v.Args[2]
  5544  		y := v.Args[0]
  5545  		v_2 := v.Args[2]
  5546  		if v_2.Op != OpAMD64FlagLT_ULT {
  5547  			break
  5548  		}
  5549  		v.reset(OpCopy)
  5550  		v.Type = y.Type
  5551  		v.AddArg(y)
  5552  		return true
  5553  	}
  5554  	// match: (CMOVLCC _ x (FlagLT_UGT))
  5555  	// result: x
  5556  	for {
  5557  		_ = v.Args[2]
  5558  		x := v.Args[1]
  5559  		v_2 := v.Args[2]
  5560  		if v_2.Op != OpAMD64FlagLT_UGT {
  5561  			break
  5562  		}
  5563  		v.reset(OpCopy)
  5564  		v.Type = x.Type
  5565  		v.AddArg(x)
  5566  		return true
  5567  	}
  5568  	return false
  5569  }
  5570  func rewriteValueAMD64_OpAMD64CMOVLCS_0(v *Value) bool {
  5571  	// match: (CMOVLCS x y (InvertFlags cond))
  5572  	// result: (CMOVLHI x y cond)
  5573  	for {
  5574  		_ = v.Args[2]
  5575  		x := v.Args[0]
  5576  		y := v.Args[1]
  5577  		v_2 := v.Args[2]
  5578  		if v_2.Op != OpAMD64InvertFlags {
  5579  			break
  5580  		}
  5581  		cond := v_2.Args[0]
  5582  		v.reset(OpAMD64CMOVLHI)
  5583  		v.AddArg(x)
  5584  		v.AddArg(y)
  5585  		v.AddArg(cond)
  5586  		return true
  5587  	}
  5588  	// match: (CMOVLCS y _ (FlagEQ))
  5589  	// result: y
  5590  	for {
  5591  		_ = v.Args[2]
  5592  		y := v.Args[0]
  5593  		v_2 := v.Args[2]
  5594  		if v_2.Op != OpAMD64FlagEQ {
  5595  			break
  5596  		}
  5597  		v.reset(OpCopy)
  5598  		v.Type = y.Type
  5599  		v.AddArg(y)
  5600  		return true
  5601  	}
  5602  	// match: (CMOVLCS y _ (FlagGT_UGT))
  5603  	// result: y
  5604  	for {
  5605  		_ = v.Args[2]
  5606  		y := v.Args[0]
  5607  		v_2 := v.Args[2]
  5608  		if v_2.Op != OpAMD64FlagGT_UGT {
  5609  			break
  5610  		}
  5611  		v.reset(OpCopy)
  5612  		v.Type = y.Type
  5613  		v.AddArg(y)
  5614  		return true
  5615  	}
  5616  	// match: (CMOVLCS _ x (FlagGT_ULT))
  5617  	// result: x
  5618  	for {
  5619  		_ = v.Args[2]
  5620  		x := v.Args[1]
  5621  		v_2 := v.Args[2]
  5622  		if v_2.Op != OpAMD64FlagGT_ULT {
  5623  			break
  5624  		}
  5625  		v.reset(OpCopy)
  5626  		v.Type = x.Type
  5627  		v.AddArg(x)
  5628  		return true
  5629  	}
  5630  	// match: (CMOVLCS _ x (FlagLT_ULT))
  5631  	// result: x
  5632  	for {
  5633  		_ = v.Args[2]
  5634  		x := v.Args[1]
  5635  		v_2 := v.Args[2]
  5636  		if v_2.Op != OpAMD64FlagLT_ULT {
  5637  			break
  5638  		}
  5639  		v.reset(OpCopy)
  5640  		v.Type = x.Type
  5641  		v.AddArg(x)
  5642  		return true
  5643  	}
  5644  	// match: (CMOVLCS y _ (FlagLT_UGT))
  5645  	// result: y
  5646  	for {
  5647  		_ = v.Args[2]
  5648  		y := v.Args[0]
  5649  		v_2 := v.Args[2]
  5650  		if v_2.Op != OpAMD64FlagLT_UGT {
  5651  			break
  5652  		}
  5653  		v.reset(OpCopy)
  5654  		v.Type = y.Type
  5655  		v.AddArg(y)
  5656  		return true
  5657  	}
  5658  	return false
  5659  }
  5660  func rewriteValueAMD64_OpAMD64CMOVLEQ_0(v *Value) bool {
  5661  	// match: (CMOVLEQ x y (InvertFlags cond))
  5662  	// result: (CMOVLEQ x y cond)
  5663  	for {
  5664  		_ = v.Args[2]
  5665  		x := v.Args[0]
  5666  		y := v.Args[1]
  5667  		v_2 := v.Args[2]
  5668  		if v_2.Op != OpAMD64InvertFlags {
  5669  			break
  5670  		}
  5671  		cond := v_2.Args[0]
  5672  		v.reset(OpAMD64CMOVLEQ)
  5673  		v.AddArg(x)
  5674  		v.AddArg(y)
  5675  		v.AddArg(cond)
  5676  		return true
  5677  	}
  5678  	// match: (CMOVLEQ _ x (FlagEQ))
  5679  	// result: x
  5680  	for {
  5681  		_ = v.Args[2]
  5682  		x := v.Args[1]
  5683  		v_2 := v.Args[2]
  5684  		if v_2.Op != OpAMD64FlagEQ {
  5685  			break
  5686  		}
  5687  		v.reset(OpCopy)
  5688  		v.Type = x.Type
  5689  		v.AddArg(x)
  5690  		return true
  5691  	}
  5692  	// match: (CMOVLEQ y _ (FlagGT_UGT))
  5693  	// result: y
  5694  	for {
  5695  		_ = v.Args[2]
  5696  		y := v.Args[0]
  5697  		v_2 := v.Args[2]
  5698  		if v_2.Op != OpAMD64FlagGT_UGT {
  5699  			break
  5700  		}
  5701  		v.reset(OpCopy)
  5702  		v.Type = y.Type
  5703  		v.AddArg(y)
  5704  		return true
  5705  	}
  5706  	// match: (CMOVLEQ y _ (FlagGT_ULT))
  5707  	// result: y
  5708  	for {
  5709  		_ = v.Args[2]
  5710  		y := v.Args[0]
  5711  		v_2 := v.Args[2]
  5712  		if v_2.Op != OpAMD64FlagGT_ULT {
  5713  			break
  5714  		}
  5715  		v.reset(OpCopy)
  5716  		v.Type = y.Type
  5717  		v.AddArg(y)
  5718  		return true
  5719  	}
  5720  	// match: (CMOVLEQ y _ (FlagLT_ULT))
  5721  	// result: y
  5722  	for {
  5723  		_ = v.Args[2]
  5724  		y := v.Args[0]
  5725  		v_2 := v.Args[2]
  5726  		if v_2.Op != OpAMD64FlagLT_ULT {
  5727  			break
  5728  		}
  5729  		v.reset(OpCopy)
  5730  		v.Type = y.Type
  5731  		v.AddArg(y)
  5732  		return true
  5733  	}
  5734  	// match: (CMOVLEQ y _ (FlagLT_UGT))
  5735  	// result: y
  5736  	for {
  5737  		_ = v.Args[2]
  5738  		y := v.Args[0]
  5739  		v_2 := v.Args[2]
  5740  		if v_2.Op != OpAMD64FlagLT_UGT {
  5741  			break
  5742  		}
  5743  		v.reset(OpCopy)
  5744  		v.Type = y.Type
  5745  		v.AddArg(y)
  5746  		return true
  5747  	}
  5748  	return false
  5749  }
  5750  func rewriteValueAMD64_OpAMD64CMOVLGE_0(v *Value) bool {
  5751  	// match: (CMOVLGE x y (InvertFlags cond))
  5752  	// result: (CMOVLLE x y cond)
  5753  	for {
  5754  		_ = v.Args[2]
  5755  		x := v.Args[0]
  5756  		y := v.Args[1]
  5757  		v_2 := v.Args[2]
  5758  		if v_2.Op != OpAMD64InvertFlags {
  5759  			break
  5760  		}
  5761  		cond := v_2.Args[0]
  5762  		v.reset(OpAMD64CMOVLLE)
  5763  		v.AddArg(x)
  5764  		v.AddArg(y)
  5765  		v.AddArg(cond)
  5766  		return true
  5767  	}
  5768  	// match: (CMOVLGE _ x (FlagEQ))
  5769  	// result: x
  5770  	for {
  5771  		_ = v.Args[2]
  5772  		x := v.Args[1]
  5773  		v_2 := v.Args[2]
  5774  		if v_2.Op != OpAMD64FlagEQ {
  5775  			break
  5776  		}
  5777  		v.reset(OpCopy)
  5778  		v.Type = x.Type
  5779  		v.AddArg(x)
  5780  		return true
  5781  	}
  5782  	// match: (CMOVLGE _ x (FlagGT_UGT))
  5783  	// result: x
  5784  	for {
  5785  		_ = v.Args[2]
  5786  		x := v.Args[1]
  5787  		v_2 := v.Args[2]
  5788  		if v_2.Op != OpAMD64FlagGT_UGT {
  5789  			break
  5790  		}
  5791  		v.reset(OpCopy)
  5792  		v.Type = x.Type
  5793  		v.AddArg(x)
  5794  		return true
  5795  	}
  5796  	// match: (CMOVLGE _ x (FlagGT_ULT))
  5797  	// result: x
  5798  	for {
  5799  		_ = v.Args[2]
  5800  		x := v.Args[1]
  5801  		v_2 := v.Args[2]
  5802  		if v_2.Op != OpAMD64FlagGT_ULT {
  5803  			break
  5804  		}
  5805  		v.reset(OpCopy)
  5806  		v.Type = x.Type
  5807  		v.AddArg(x)
  5808  		return true
  5809  	}
  5810  	// match: (CMOVLGE y _ (FlagLT_ULT))
  5811  	// result: y
  5812  	for {
  5813  		_ = v.Args[2]
  5814  		y := v.Args[0]
  5815  		v_2 := v.Args[2]
  5816  		if v_2.Op != OpAMD64FlagLT_ULT {
  5817  			break
  5818  		}
  5819  		v.reset(OpCopy)
  5820  		v.Type = y.Type
  5821  		v.AddArg(y)
  5822  		return true
  5823  	}
  5824  	// match: (CMOVLGE y _ (FlagLT_UGT))
  5825  	// result: y
  5826  	for {
  5827  		_ = v.Args[2]
  5828  		y := v.Args[0]
  5829  		v_2 := v.Args[2]
  5830  		if v_2.Op != OpAMD64FlagLT_UGT {
  5831  			break
  5832  		}
  5833  		v.reset(OpCopy)
  5834  		v.Type = y.Type
  5835  		v.AddArg(y)
  5836  		return true
  5837  	}
  5838  	return false
  5839  }
  5840  func rewriteValueAMD64_OpAMD64CMOVLGT_0(v *Value) bool {
  5841  	// match: (CMOVLGT x y (InvertFlags cond))
  5842  	// result: (CMOVLLT x y cond)
  5843  	for {
  5844  		_ = v.Args[2]
  5845  		x := v.Args[0]
  5846  		y := v.Args[1]
  5847  		v_2 := v.Args[2]
  5848  		if v_2.Op != OpAMD64InvertFlags {
  5849  			break
  5850  		}
  5851  		cond := v_2.Args[0]
  5852  		v.reset(OpAMD64CMOVLLT)
  5853  		v.AddArg(x)
  5854  		v.AddArg(y)
  5855  		v.AddArg(cond)
  5856  		return true
  5857  	}
  5858  	// match: (CMOVLGT y _ (FlagEQ))
  5859  	// result: y
  5860  	for {
  5861  		_ = v.Args[2]
  5862  		y := v.Args[0]
  5863  		v_2 := v.Args[2]
  5864  		if v_2.Op != OpAMD64FlagEQ {
  5865  			break
  5866  		}
  5867  		v.reset(OpCopy)
  5868  		v.Type = y.Type
  5869  		v.AddArg(y)
  5870  		return true
  5871  	}
  5872  	// match: (CMOVLGT _ x (FlagGT_UGT))
  5873  	// result: x
  5874  	for {
  5875  		_ = v.Args[2]
  5876  		x := v.Args[1]
  5877  		v_2 := v.Args[2]
  5878  		if v_2.Op != OpAMD64FlagGT_UGT {
  5879  			break
  5880  		}
  5881  		v.reset(OpCopy)
  5882  		v.Type = x.Type
  5883  		v.AddArg(x)
  5884  		return true
  5885  	}
  5886  	// match: (CMOVLGT _ x (FlagGT_ULT))
  5887  	// result: x
  5888  	for {
  5889  		_ = v.Args[2]
  5890  		x := v.Args[1]
  5891  		v_2 := v.Args[2]
  5892  		if v_2.Op != OpAMD64FlagGT_ULT {
  5893  			break
  5894  		}
  5895  		v.reset(OpCopy)
  5896  		v.Type = x.Type
  5897  		v.AddArg(x)
  5898  		return true
  5899  	}
  5900  	// match: (CMOVLGT y _ (FlagLT_ULT))
  5901  	// result: y
  5902  	for {
  5903  		_ = v.Args[2]
  5904  		y := v.Args[0]
  5905  		v_2 := v.Args[2]
  5906  		if v_2.Op != OpAMD64FlagLT_ULT {
  5907  			break
  5908  		}
  5909  		v.reset(OpCopy)
  5910  		v.Type = y.Type
  5911  		v.AddArg(y)
  5912  		return true
  5913  	}
  5914  	// match: (CMOVLGT y _ (FlagLT_UGT))
  5915  	// result: y
  5916  	for {
  5917  		_ = v.Args[2]
  5918  		y := v.Args[0]
  5919  		v_2 := v.Args[2]
  5920  		if v_2.Op != OpAMD64FlagLT_UGT {
  5921  			break
  5922  		}
  5923  		v.reset(OpCopy)
  5924  		v.Type = y.Type
  5925  		v.AddArg(y)
  5926  		return true
  5927  	}
  5928  	return false
  5929  }
  5930  func rewriteValueAMD64_OpAMD64CMOVLHI_0(v *Value) bool {
  5931  	// match: (CMOVLHI x y (InvertFlags cond))
  5932  	// result: (CMOVLCS x y cond)
  5933  	for {
  5934  		_ = v.Args[2]
  5935  		x := v.Args[0]
  5936  		y := v.Args[1]
  5937  		v_2 := v.Args[2]
  5938  		if v_2.Op != OpAMD64InvertFlags {
  5939  			break
  5940  		}
  5941  		cond := v_2.Args[0]
  5942  		v.reset(OpAMD64CMOVLCS)
  5943  		v.AddArg(x)
  5944  		v.AddArg(y)
  5945  		v.AddArg(cond)
  5946  		return true
  5947  	}
  5948  	// match: (CMOVLHI y _ (FlagEQ))
  5949  	// result: y
  5950  	for {
  5951  		_ = v.Args[2]
  5952  		y := v.Args[0]
  5953  		v_2 := v.Args[2]
  5954  		if v_2.Op != OpAMD64FlagEQ {
  5955  			break
  5956  		}
  5957  		v.reset(OpCopy)
  5958  		v.Type = y.Type
  5959  		v.AddArg(y)
  5960  		return true
  5961  	}
  5962  	// match: (CMOVLHI _ x (FlagGT_UGT))
  5963  	// result: x
  5964  	for {
  5965  		_ = v.Args[2]
  5966  		x := v.Args[1]
  5967  		v_2 := v.Args[2]
  5968  		if v_2.Op != OpAMD64FlagGT_UGT {
  5969  			break
  5970  		}
  5971  		v.reset(OpCopy)
  5972  		v.Type = x.Type
  5973  		v.AddArg(x)
  5974  		return true
  5975  	}
  5976  	// match: (CMOVLHI y _ (FlagGT_ULT))
  5977  	// result: y
  5978  	for {
  5979  		_ = v.Args[2]
  5980  		y := v.Args[0]
  5981  		v_2 := v.Args[2]
  5982  		if v_2.Op != OpAMD64FlagGT_ULT {
  5983  			break
  5984  		}
  5985  		v.reset(OpCopy)
  5986  		v.Type = y.Type
  5987  		v.AddArg(y)
  5988  		return true
  5989  	}
  5990  	// match: (CMOVLHI y _ (FlagLT_ULT))
  5991  	// result: y
  5992  	for {
  5993  		_ = v.Args[2]
  5994  		y := v.Args[0]
  5995  		v_2 := v.Args[2]
  5996  		if v_2.Op != OpAMD64FlagLT_ULT {
  5997  			break
  5998  		}
  5999  		v.reset(OpCopy)
  6000  		v.Type = y.Type
  6001  		v.AddArg(y)
  6002  		return true
  6003  	}
  6004  	// match: (CMOVLHI _ x (FlagLT_UGT))
  6005  	// result: x
  6006  	for {
  6007  		_ = v.Args[2]
  6008  		x := v.Args[1]
  6009  		v_2 := v.Args[2]
  6010  		if v_2.Op != OpAMD64FlagLT_UGT {
  6011  			break
  6012  		}
  6013  		v.reset(OpCopy)
  6014  		v.Type = x.Type
  6015  		v.AddArg(x)
  6016  		return true
  6017  	}
  6018  	return false
  6019  }
  6020  func rewriteValueAMD64_OpAMD64CMOVLLE_0(v *Value) bool {
  6021  	// match: (CMOVLLE x y (InvertFlags cond))
  6022  	// result: (CMOVLGE x y cond)
  6023  	for {
  6024  		_ = v.Args[2]
  6025  		x := v.Args[0]
  6026  		y := v.Args[1]
  6027  		v_2 := v.Args[2]
  6028  		if v_2.Op != OpAMD64InvertFlags {
  6029  			break
  6030  		}
  6031  		cond := v_2.Args[0]
  6032  		v.reset(OpAMD64CMOVLGE)
  6033  		v.AddArg(x)
  6034  		v.AddArg(y)
  6035  		v.AddArg(cond)
  6036  		return true
  6037  	}
  6038  	// match: (CMOVLLE _ x (FlagEQ))
  6039  	// result: x
  6040  	for {
  6041  		_ = v.Args[2]
  6042  		x := v.Args[1]
  6043  		v_2 := v.Args[2]
  6044  		if v_2.Op != OpAMD64FlagEQ {
  6045  			break
  6046  		}
  6047  		v.reset(OpCopy)
  6048  		v.Type = x.Type
  6049  		v.AddArg(x)
  6050  		return true
  6051  	}
  6052  	// match: (CMOVLLE y _ (FlagGT_UGT))
  6053  	// result: y
  6054  	for {
  6055  		_ = v.Args[2]
  6056  		y := v.Args[0]
  6057  		v_2 := v.Args[2]
  6058  		if v_2.Op != OpAMD64FlagGT_UGT {
  6059  			break
  6060  		}
  6061  		v.reset(OpCopy)
  6062  		v.Type = y.Type
  6063  		v.AddArg(y)
  6064  		return true
  6065  	}
  6066  	// match: (CMOVLLE y _ (FlagGT_ULT))
  6067  	// result: y
  6068  	for {
  6069  		_ = v.Args[2]
  6070  		y := v.Args[0]
  6071  		v_2 := v.Args[2]
  6072  		if v_2.Op != OpAMD64FlagGT_ULT {
  6073  			break
  6074  		}
  6075  		v.reset(OpCopy)
  6076  		v.Type = y.Type
  6077  		v.AddArg(y)
  6078  		return true
  6079  	}
  6080  	// match: (CMOVLLE _ x (FlagLT_ULT))
  6081  	// result: x
  6082  	for {
  6083  		_ = v.Args[2]
  6084  		x := v.Args[1]
  6085  		v_2 := v.Args[2]
  6086  		if v_2.Op != OpAMD64FlagLT_ULT {
  6087  			break
  6088  		}
  6089  		v.reset(OpCopy)
  6090  		v.Type = x.Type
  6091  		v.AddArg(x)
  6092  		return true
  6093  	}
  6094  	// match: (CMOVLLE _ x (FlagLT_UGT))
  6095  	// result: x
  6096  	for {
  6097  		_ = v.Args[2]
  6098  		x := v.Args[1]
  6099  		v_2 := v.Args[2]
  6100  		if v_2.Op != OpAMD64FlagLT_UGT {
  6101  			break
  6102  		}
  6103  		v.reset(OpCopy)
  6104  		v.Type = x.Type
  6105  		v.AddArg(x)
  6106  		return true
  6107  	}
  6108  	return false
  6109  }
  6110  func rewriteValueAMD64_OpAMD64CMOVLLS_0(v *Value) bool {
  6111  	// match: (CMOVLLS x y (InvertFlags cond))
  6112  	// result: (CMOVLCC x y cond)
  6113  	for {
  6114  		_ = v.Args[2]
  6115  		x := v.Args[0]
  6116  		y := v.Args[1]
  6117  		v_2 := v.Args[2]
  6118  		if v_2.Op != OpAMD64InvertFlags {
  6119  			break
  6120  		}
  6121  		cond := v_2.Args[0]
  6122  		v.reset(OpAMD64CMOVLCC)
  6123  		v.AddArg(x)
  6124  		v.AddArg(y)
  6125  		v.AddArg(cond)
  6126  		return true
  6127  	}
  6128  	// match: (CMOVLLS _ x (FlagEQ))
  6129  	// result: x
  6130  	for {
  6131  		_ = v.Args[2]
  6132  		x := v.Args[1]
  6133  		v_2 := v.Args[2]
  6134  		if v_2.Op != OpAMD64FlagEQ {
  6135  			break
  6136  		}
  6137  		v.reset(OpCopy)
  6138  		v.Type = x.Type
  6139  		v.AddArg(x)
  6140  		return true
  6141  	}
  6142  	// match: (CMOVLLS y _ (FlagGT_UGT))
  6143  	// result: y
  6144  	for {
  6145  		_ = v.Args[2]
  6146  		y := v.Args[0]
  6147  		v_2 := v.Args[2]
  6148  		if v_2.Op != OpAMD64FlagGT_UGT {
  6149  			break
  6150  		}
  6151  		v.reset(OpCopy)
  6152  		v.Type = y.Type
  6153  		v.AddArg(y)
  6154  		return true
  6155  	}
  6156  	// match: (CMOVLLS _ x (FlagGT_ULT))
  6157  	// result: x
  6158  	for {
  6159  		_ = v.Args[2]
  6160  		x := v.Args[1]
  6161  		v_2 := v.Args[2]
  6162  		if v_2.Op != OpAMD64FlagGT_ULT {
  6163  			break
  6164  		}
  6165  		v.reset(OpCopy)
  6166  		v.Type = x.Type
  6167  		v.AddArg(x)
  6168  		return true
  6169  	}
  6170  	// match: (CMOVLLS _ x (FlagLT_ULT))
  6171  	// result: x
  6172  	for {
  6173  		_ = v.Args[2]
  6174  		x := v.Args[1]
  6175  		v_2 := v.Args[2]
  6176  		if v_2.Op != OpAMD64FlagLT_ULT {
  6177  			break
  6178  		}
  6179  		v.reset(OpCopy)
  6180  		v.Type = x.Type
  6181  		v.AddArg(x)
  6182  		return true
  6183  	}
  6184  	// match: (CMOVLLS y _ (FlagLT_UGT))
  6185  	// result: y
  6186  	for {
  6187  		_ = v.Args[2]
  6188  		y := v.Args[0]
  6189  		v_2 := v.Args[2]
  6190  		if v_2.Op != OpAMD64FlagLT_UGT {
  6191  			break
  6192  		}
  6193  		v.reset(OpCopy)
  6194  		v.Type = y.Type
  6195  		v.AddArg(y)
  6196  		return true
  6197  	}
  6198  	return false
  6199  }
  6200  func rewriteValueAMD64_OpAMD64CMOVLLT_0(v *Value) bool {
  6201  	// match: (CMOVLLT x y (InvertFlags cond))
  6202  	// result: (CMOVLGT x y cond)
  6203  	for {
  6204  		_ = v.Args[2]
  6205  		x := v.Args[0]
  6206  		y := v.Args[1]
  6207  		v_2 := v.Args[2]
  6208  		if v_2.Op != OpAMD64InvertFlags {
  6209  			break
  6210  		}
  6211  		cond := v_2.Args[0]
  6212  		v.reset(OpAMD64CMOVLGT)
  6213  		v.AddArg(x)
  6214  		v.AddArg(y)
  6215  		v.AddArg(cond)
  6216  		return true
  6217  	}
  6218  	// match: (CMOVLLT y _ (FlagEQ))
  6219  	// result: y
  6220  	for {
  6221  		_ = v.Args[2]
  6222  		y := v.Args[0]
  6223  		v_2 := v.Args[2]
  6224  		if v_2.Op != OpAMD64FlagEQ {
  6225  			break
  6226  		}
  6227  		v.reset(OpCopy)
  6228  		v.Type = y.Type
  6229  		v.AddArg(y)
  6230  		return true
  6231  	}
  6232  	// match: (CMOVLLT y _ (FlagGT_UGT))
  6233  	// result: y
  6234  	for {
  6235  		_ = v.Args[2]
  6236  		y := v.Args[0]
  6237  		v_2 := v.Args[2]
  6238  		if v_2.Op != OpAMD64FlagGT_UGT {
  6239  			break
  6240  		}
  6241  		v.reset(OpCopy)
  6242  		v.Type = y.Type
  6243  		v.AddArg(y)
  6244  		return true
  6245  	}
  6246  	// match: (CMOVLLT y _ (FlagGT_ULT))
  6247  	// result: y
  6248  	for {
  6249  		_ = v.Args[2]
  6250  		y := v.Args[0]
  6251  		v_2 := v.Args[2]
  6252  		if v_2.Op != OpAMD64FlagGT_ULT {
  6253  			break
  6254  		}
  6255  		v.reset(OpCopy)
  6256  		v.Type = y.Type
  6257  		v.AddArg(y)
  6258  		return true
  6259  	}
  6260  	// match: (CMOVLLT _ x (FlagLT_ULT))
  6261  	// result: x
  6262  	for {
  6263  		_ = v.Args[2]
  6264  		x := v.Args[1]
  6265  		v_2 := v.Args[2]
  6266  		if v_2.Op != OpAMD64FlagLT_ULT {
  6267  			break
  6268  		}
  6269  		v.reset(OpCopy)
  6270  		v.Type = x.Type
  6271  		v.AddArg(x)
  6272  		return true
  6273  	}
  6274  	// match: (CMOVLLT _ x (FlagLT_UGT))
  6275  	// result: x
  6276  	for {
  6277  		_ = v.Args[2]
  6278  		x := v.Args[1]
  6279  		v_2 := v.Args[2]
  6280  		if v_2.Op != OpAMD64FlagLT_UGT {
  6281  			break
  6282  		}
  6283  		v.reset(OpCopy)
  6284  		v.Type = x.Type
  6285  		v.AddArg(x)
  6286  		return true
  6287  	}
  6288  	return false
  6289  }
  6290  func rewriteValueAMD64_OpAMD64CMOVLNE_0(v *Value) bool {
  6291  	// match: (CMOVLNE x y (InvertFlags cond))
  6292  	// result: (CMOVLNE x y cond)
  6293  	for {
  6294  		_ = v.Args[2]
  6295  		x := v.Args[0]
  6296  		y := v.Args[1]
  6297  		v_2 := v.Args[2]
  6298  		if v_2.Op != OpAMD64InvertFlags {
  6299  			break
  6300  		}
  6301  		cond := v_2.Args[0]
  6302  		v.reset(OpAMD64CMOVLNE)
  6303  		v.AddArg(x)
  6304  		v.AddArg(y)
  6305  		v.AddArg(cond)
  6306  		return true
  6307  	}
  6308  	// match: (CMOVLNE y _ (FlagEQ))
  6309  	// result: y
  6310  	for {
  6311  		_ = v.Args[2]
  6312  		y := v.Args[0]
  6313  		v_2 := v.Args[2]
  6314  		if v_2.Op != OpAMD64FlagEQ {
  6315  			break
  6316  		}
  6317  		v.reset(OpCopy)
  6318  		v.Type = y.Type
  6319  		v.AddArg(y)
  6320  		return true
  6321  	}
  6322  	// match: (CMOVLNE _ x (FlagGT_UGT))
  6323  	// result: x
  6324  	for {
  6325  		_ = v.Args[2]
  6326  		x := v.Args[1]
  6327  		v_2 := v.Args[2]
  6328  		if v_2.Op != OpAMD64FlagGT_UGT {
  6329  			break
  6330  		}
  6331  		v.reset(OpCopy)
  6332  		v.Type = x.Type
  6333  		v.AddArg(x)
  6334  		return true
  6335  	}
  6336  	// match: (CMOVLNE _ x (FlagGT_ULT))
  6337  	// result: x
  6338  	for {
  6339  		_ = v.Args[2]
  6340  		x := v.Args[1]
  6341  		v_2 := v.Args[2]
  6342  		if v_2.Op != OpAMD64FlagGT_ULT {
  6343  			break
  6344  		}
  6345  		v.reset(OpCopy)
  6346  		v.Type = x.Type
  6347  		v.AddArg(x)
  6348  		return true
  6349  	}
  6350  	// match: (CMOVLNE _ x (FlagLT_ULT))
  6351  	// result: x
  6352  	for {
  6353  		_ = v.Args[2]
  6354  		x := v.Args[1]
  6355  		v_2 := v.Args[2]
  6356  		if v_2.Op != OpAMD64FlagLT_ULT {
  6357  			break
  6358  		}
  6359  		v.reset(OpCopy)
  6360  		v.Type = x.Type
  6361  		v.AddArg(x)
  6362  		return true
  6363  	}
  6364  	// match: (CMOVLNE _ x (FlagLT_UGT))
  6365  	// result: x
  6366  	for {
  6367  		_ = v.Args[2]
  6368  		x := v.Args[1]
  6369  		v_2 := v.Args[2]
  6370  		if v_2.Op != OpAMD64FlagLT_UGT {
  6371  			break
  6372  		}
  6373  		v.reset(OpCopy)
  6374  		v.Type = x.Type
  6375  		v.AddArg(x)
  6376  		return true
  6377  	}
  6378  	return false
  6379  }
  6380  func rewriteValueAMD64_OpAMD64CMOVQCC_0(v *Value) bool {
  6381  	// match: (CMOVQCC x y (InvertFlags cond))
  6382  	// result: (CMOVQLS x y cond)
  6383  	for {
  6384  		_ = v.Args[2]
  6385  		x := v.Args[0]
  6386  		y := v.Args[1]
  6387  		v_2 := v.Args[2]
  6388  		if v_2.Op != OpAMD64InvertFlags {
  6389  			break
  6390  		}
  6391  		cond := v_2.Args[0]
  6392  		v.reset(OpAMD64CMOVQLS)
  6393  		v.AddArg(x)
  6394  		v.AddArg(y)
  6395  		v.AddArg(cond)
  6396  		return true
  6397  	}
  6398  	// match: (CMOVQCC _ x (FlagEQ))
  6399  	// result: x
  6400  	for {
  6401  		_ = v.Args[2]
  6402  		x := v.Args[1]
  6403  		v_2 := v.Args[2]
  6404  		if v_2.Op != OpAMD64FlagEQ {
  6405  			break
  6406  		}
  6407  		v.reset(OpCopy)
  6408  		v.Type = x.Type
  6409  		v.AddArg(x)
  6410  		return true
  6411  	}
  6412  	// match: (CMOVQCC _ x (FlagGT_UGT))
  6413  	// result: x
  6414  	for {
  6415  		_ = v.Args[2]
  6416  		x := v.Args[1]
  6417  		v_2 := v.Args[2]
  6418  		if v_2.Op != OpAMD64FlagGT_UGT {
  6419  			break
  6420  		}
  6421  		v.reset(OpCopy)
  6422  		v.Type = x.Type
  6423  		v.AddArg(x)
  6424  		return true
  6425  	}
  6426  	// match: (CMOVQCC y _ (FlagGT_ULT))
  6427  	// result: y
  6428  	for {
  6429  		_ = v.Args[2]
  6430  		y := v.Args[0]
  6431  		v_2 := v.Args[2]
  6432  		if v_2.Op != OpAMD64FlagGT_ULT {
  6433  			break
  6434  		}
  6435  		v.reset(OpCopy)
  6436  		v.Type = y.Type
  6437  		v.AddArg(y)
  6438  		return true
  6439  	}
  6440  	// match: (CMOVQCC y _ (FlagLT_ULT))
  6441  	// result: y
  6442  	for {
  6443  		_ = v.Args[2]
  6444  		y := v.Args[0]
  6445  		v_2 := v.Args[2]
  6446  		if v_2.Op != OpAMD64FlagLT_ULT {
  6447  			break
  6448  		}
  6449  		v.reset(OpCopy)
  6450  		v.Type = y.Type
  6451  		v.AddArg(y)
  6452  		return true
  6453  	}
  6454  	// match: (CMOVQCC _ x (FlagLT_UGT))
  6455  	// result: x
  6456  	for {
  6457  		_ = v.Args[2]
  6458  		x := v.Args[1]
  6459  		v_2 := v.Args[2]
  6460  		if v_2.Op != OpAMD64FlagLT_UGT {
  6461  			break
  6462  		}
  6463  		v.reset(OpCopy)
  6464  		v.Type = x.Type
  6465  		v.AddArg(x)
  6466  		return true
  6467  	}
  6468  	return false
  6469  }
  6470  func rewriteValueAMD64_OpAMD64CMOVQCS_0(v *Value) bool {
  6471  	// match: (CMOVQCS x y (InvertFlags cond))
  6472  	// result: (CMOVQHI x y cond)
  6473  	for {
  6474  		_ = v.Args[2]
  6475  		x := v.Args[0]
  6476  		y := v.Args[1]
  6477  		v_2 := v.Args[2]
  6478  		if v_2.Op != OpAMD64InvertFlags {
  6479  			break
  6480  		}
  6481  		cond := v_2.Args[0]
  6482  		v.reset(OpAMD64CMOVQHI)
  6483  		v.AddArg(x)
  6484  		v.AddArg(y)
  6485  		v.AddArg(cond)
  6486  		return true
  6487  	}
  6488  	// match: (CMOVQCS y _ (FlagEQ))
  6489  	// result: y
  6490  	for {
  6491  		_ = v.Args[2]
  6492  		y := v.Args[0]
  6493  		v_2 := v.Args[2]
  6494  		if v_2.Op != OpAMD64FlagEQ {
  6495  			break
  6496  		}
  6497  		v.reset(OpCopy)
  6498  		v.Type = y.Type
  6499  		v.AddArg(y)
  6500  		return true
  6501  	}
  6502  	// match: (CMOVQCS y _ (FlagGT_UGT))
  6503  	// result: y
  6504  	for {
  6505  		_ = v.Args[2]
  6506  		y := v.Args[0]
  6507  		v_2 := v.Args[2]
  6508  		if v_2.Op != OpAMD64FlagGT_UGT {
  6509  			break
  6510  		}
  6511  		v.reset(OpCopy)
  6512  		v.Type = y.Type
  6513  		v.AddArg(y)
  6514  		return true
  6515  	}
  6516  	// match: (CMOVQCS _ x (FlagGT_ULT))
  6517  	// result: x
  6518  	for {
  6519  		_ = v.Args[2]
  6520  		x := v.Args[1]
  6521  		v_2 := v.Args[2]
  6522  		if v_2.Op != OpAMD64FlagGT_ULT {
  6523  			break
  6524  		}
  6525  		v.reset(OpCopy)
  6526  		v.Type = x.Type
  6527  		v.AddArg(x)
  6528  		return true
  6529  	}
  6530  	// match: (CMOVQCS _ x (FlagLT_ULT))
  6531  	// result: x
  6532  	for {
  6533  		_ = v.Args[2]
  6534  		x := v.Args[1]
  6535  		v_2 := v.Args[2]
  6536  		if v_2.Op != OpAMD64FlagLT_ULT {
  6537  			break
  6538  		}
  6539  		v.reset(OpCopy)
  6540  		v.Type = x.Type
  6541  		v.AddArg(x)
  6542  		return true
  6543  	}
  6544  	// match: (CMOVQCS y _ (FlagLT_UGT))
  6545  	// result: y
  6546  	for {
  6547  		_ = v.Args[2]
  6548  		y := v.Args[0]
  6549  		v_2 := v.Args[2]
  6550  		if v_2.Op != OpAMD64FlagLT_UGT {
  6551  			break
  6552  		}
  6553  		v.reset(OpCopy)
  6554  		v.Type = y.Type
  6555  		v.AddArg(y)
  6556  		return true
  6557  	}
  6558  	return false
  6559  }
  6560  func rewriteValueAMD64_OpAMD64CMOVQEQ_0(v *Value) bool {
  6561  	// match: (CMOVQEQ x y (InvertFlags cond))
  6562  	// result: (CMOVQEQ x y cond)
  6563  	for {
  6564  		_ = v.Args[2]
  6565  		x := v.Args[0]
  6566  		y := v.Args[1]
  6567  		v_2 := v.Args[2]
  6568  		if v_2.Op != OpAMD64InvertFlags {
  6569  			break
  6570  		}
  6571  		cond := v_2.Args[0]
  6572  		v.reset(OpAMD64CMOVQEQ)
  6573  		v.AddArg(x)
  6574  		v.AddArg(y)
  6575  		v.AddArg(cond)
  6576  		return true
  6577  	}
  6578  	// match: (CMOVQEQ _ x (FlagEQ))
  6579  	// result: x
  6580  	for {
  6581  		_ = v.Args[2]
  6582  		x := v.Args[1]
  6583  		v_2 := v.Args[2]
  6584  		if v_2.Op != OpAMD64FlagEQ {
  6585  			break
  6586  		}
  6587  		v.reset(OpCopy)
  6588  		v.Type = x.Type
  6589  		v.AddArg(x)
  6590  		return true
  6591  	}
  6592  	// match: (CMOVQEQ y _ (FlagGT_UGT))
  6593  	// result: y
  6594  	for {
  6595  		_ = v.Args[2]
  6596  		y := v.Args[0]
  6597  		v_2 := v.Args[2]
  6598  		if v_2.Op != OpAMD64FlagGT_UGT {
  6599  			break
  6600  		}
  6601  		v.reset(OpCopy)
  6602  		v.Type = y.Type
  6603  		v.AddArg(y)
  6604  		return true
  6605  	}
  6606  	// match: (CMOVQEQ y _ (FlagGT_ULT))
  6607  	// result: y
  6608  	for {
  6609  		_ = v.Args[2]
  6610  		y := v.Args[0]
  6611  		v_2 := v.Args[2]
  6612  		if v_2.Op != OpAMD64FlagGT_ULT {
  6613  			break
  6614  		}
  6615  		v.reset(OpCopy)
  6616  		v.Type = y.Type
  6617  		v.AddArg(y)
  6618  		return true
  6619  	}
  6620  	// match: (CMOVQEQ y _ (FlagLT_ULT))
  6621  	// result: y
  6622  	for {
  6623  		_ = v.Args[2]
  6624  		y := v.Args[0]
  6625  		v_2 := v.Args[2]
  6626  		if v_2.Op != OpAMD64FlagLT_ULT {
  6627  			break
  6628  		}
  6629  		v.reset(OpCopy)
  6630  		v.Type = y.Type
  6631  		v.AddArg(y)
  6632  		return true
  6633  	}
  6634  	// match: (CMOVQEQ y _ (FlagLT_UGT))
  6635  	// result: y
  6636  	for {
  6637  		_ = v.Args[2]
  6638  		y := v.Args[0]
  6639  		v_2 := v.Args[2]
  6640  		if v_2.Op != OpAMD64FlagLT_UGT {
  6641  			break
  6642  		}
  6643  		v.reset(OpCopy)
  6644  		v.Type = y.Type
  6645  		v.AddArg(y)
  6646  		return true
  6647  	}
  6648  	// match: (CMOVQEQ x _ (Select1 (BSFQ (ORQconst [c] _))))
  6649  	// cond: c != 0
  6650  	// result: x
  6651  	for {
  6652  		_ = v.Args[2]
  6653  		x := v.Args[0]
  6654  		v_2 := v.Args[2]
  6655  		if v_2.Op != OpSelect1 {
  6656  			break
  6657  		}
  6658  		v_2_0 := v_2.Args[0]
  6659  		if v_2_0.Op != OpAMD64BSFQ {
  6660  			break
  6661  		}
  6662  		v_2_0_0 := v_2_0.Args[0]
  6663  		if v_2_0_0.Op != OpAMD64ORQconst {
  6664  			break
  6665  		}
  6666  		c := v_2_0_0.AuxInt
  6667  		if !(c != 0) {
  6668  			break
  6669  		}
  6670  		v.reset(OpCopy)
  6671  		v.Type = x.Type
  6672  		v.AddArg(x)
  6673  		return true
  6674  	}
  6675  	return false
  6676  }
  6677  func rewriteValueAMD64_OpAMD64CMOVQGE_0(v *Value) bool {
  6678  	// match: (CMOVQGE x y (InvertFlags cond))
  6679  	// result: (CMOVQLE x y cond)
  6680  	for {
  6681  		_ = v.Args[2]
  6682  		x := v.Args[0]
  6683  		y := v.Args[1]
  6684  		v_2 := v.Args[2]
  6685  		if v_2.Op != OpAMD64InvertFlags {
  6686  			break
  6687  		}
  6688  		cond := v_2.Args[0]
  6689  		v.reset(OpAMD64CMOVQLE)
  6690  		v.AddArg(x)
  6691  		v.AddArg(y)
  6692  		v.AddArg(cond)
  6693  		return true
  6694  	}
  6695  	// match: (CMOVQGE _ x (FlagEQ))
  6696  	// result: x
  6697  	for {
  6698  		_ = v.Args[2]
  6699  		x := v.Args[1]
  6700  		v_2 := v.Args[2]
  6701  		if v_2.Op != OpAMD64FlagEQ {
  6702  			break
  6703  		}
  6704  		v.reset(OpCopy)
  6705  		v.Type = x.Type
  6706  		v.AddArg(x)
  6707  		return true
  6708  	}
  6709  	// match: (CMOVQGE _ x (FlagGT_UGT))
  6710  	// result: x
  6711  	for {
  6712  		_ = v.Args[2]
  6713  		x := v.Args[1]
  6714  		v_2 := v.Args[2]
  6715  		if v_2.Op != OpAMD64FlagGT_UGT {
  6716  			break
  6717  		}
  6718  		v.reset(OpCopy)
  6719  		v.Type = x.Type
  6720  		v.AddArg(x)
  6721  		return true
  6722  	}
  6723  	// match: (CMOVQGE _ x (FlagGT_ULT))
  6724  	// result: x
  6725  	for {
  6726  		_ = v.Args[2]
  6727  		x := v.Args[1]
  6728  		v_2 := v.Args[2]
  6729  		if v_2.Op != OpAMD64FlagGT_ULT {
  6730  			break
  6731  		}
  6732  		v.reset(OpCopy)
  6733  		v.Type = x.Type
  6734  		v.AddArg(x)
  6735  		return true
  6736  	}
  6737  	// match: (CMOVQGE y _ (FlagLT_ULT))
  6738  	// result: y
  6739  	for {
  6740  		_ = v.Args[2]
  6741  		y := v.Args[0]
  6742  		v_2 := v.Args[2]
  6743  		if v_2.Op != OpAMD64FlagLT_ULT {
  6744  			break
  6745  		}
  6746  		v.reset(OpCopy)
  6747  		v.Type = y.Type
  6748  		v.AddArg(y)
  6749  		return true
  6750  	}
  6751  	// match: (CMOVQGE y _ (FlagLT_UGT))
  6752  	// result: y
  6753  	for {
  6754  		_ = v.Args[2]
  6755  		y := v.Args[0]
  6756  		v_2 := v.Args[2]
  6757  		if v_2.Op != OpAMD64FlagLT_UGT {
  6758  			break
  6759  		}
  6760  		v.reset(OpCopy)
  6761  		v.Type = y.Type
  6762  		v.AddArg(y)
  6763  		return true
  6764  	}
  6765  	return false
  6766  }
  6767  func rewriteValueAMD64_OpAMD64CMOVQGT_0(v *Value) bool {
  6768  	// match: (CMOVQGT x y (InvertFlags cond))
  6769  	// result: (CMOVQLT x y cond)
  6770  	for {
  6771  		_ = v.Args[2]
  6772  		x := v.Args[0]
  6773  		y := v.Args[1]
  6774  		v_2 := v.Args[2]
  6775  		if v_2.Op != OpAMD64InvertFlags {
  6776  			break
  6777  		}
  6778  		cond := v_2.Args[0]
  6779  		v.reset(OpAMD64CMOVQLT)
  6780  		v.AddArg(x)
  6781  		v.AddArg(y)
  6782  		v.AddArg(cond)
  6783  		return true
  6784  	}
  6785  	// match: (CMOVQGT y _ (FlagEQ))
  6786  	// result: y
  6787  	for {
  6788  		_ = v.Args[2]
  6789  		y := v.Args[0]
  6790  		v_2 := v.Args[2]
  6791  		if v_2.Op != OpAMD64FlagEQ {
  6792  			break
  6793  		}
  6794  		v.reset(OpCopy)
  6795  		v.Type = y.Type
  6796  		v.AddArg(y)
  6797  		return true
  6798  	}
  6799  	// match: (CMOVQGT _ x (FlagGT_UGT))
  6800  	// result: x
  6801  	for {
  6802  		_ = v.Args[2]
  6803  		x := v.Args[1]
  6804  		v_2 := v.Args[2]
  6805  		if v_2.Op != OpAMD64FlagGT_UGT {
  6806  			break
  6807  		}
  6808  		v.reset(OpCopy)
  6809  		v.Type = x.Type
  6810  		v.AddArg(x)
  6811  		return true
  6812  	}
  6813  	// match: (CMOVQGT _ x (FlagGT_ULT))
  6814  	// result: x
  6815  	for {
  6816  		_ = v.Args[2]
  6817  		x := v.Args[1]
  6818  		v_2 := v.Args[2]
  6819  		if v_2.Op != OpAMD64FlagGT_ULT {
  6820  			break
  6821  		}
  6822  		v.reset(OpCopy)
  6823  		v.Type = x.Type
  6824  		v.AddArg(x)
  6825  		return true
  6826  	}
  6827  	// match: (CMOVQGT y _ (FlagLT_ULT))
  6828  	// result: y
  6829  	for {
  6830  		_ = v.Args[2]
  6831  		y := v.Args[0]
  6832  		v_2 := v.Args[2]
  6833  		if v_2.Op != OpAMD64FlagLT_ULT {
  6834  			break
  6835  		}
  6836  		v.reset(OpCopy)
  6837  		v.Type = y.Type
  6838  		v.AddArg(y)
  6839  		return true
  6840  	}
  6841  	// match: (CMOVQGT y _ (FlagLT_UGT))
  6842  	// result: y
  6843  	for {
  6844  		_ = v.Args[2]
  6845  		y := v.Args[0]
  6846  		v_2 := v.Args[2]
  6847  		if v_2.Op != OpAMD64FlagLT_UGT {
  6848  			break
  6849  		}
  6850  		v.reset(OpCopy)
  6851  		v.Type = y.Type
  6852  		v.AddArg(y)
  6853  		return true
  6854  	}
  6855  	return false
  6856  }
  6857  func rewriteValueAMD64_OpAMD64CMOVQHI_0(v *Value) bool {
  6858  	// match: (CMOVQHI x y (InvertFlags cond))
  6859  	// result: (CMOVQCS x y cond)
  6860  	for {
  6861  		_ = v.Args[2]
  6862  		x := v.Args[0]
  6863  		y := v.Args[1]
  6864  		v_2 := v.Args[2]
  6865  		if v_2.Op != OpAMD64InvertFlags {
  6866  			break
  6867  		}
  6868  		cond := v_2.Args[0]
  6869  		v.reset(OpAMD64CMOVQCS)
  6870  		v.AddArg(x)
  6871  		v.AddArg(y)
  6872  		v.AddArg(cond)
  6873  		return true
  6874  	}
  6875  	// match: (CMOVQHI y _ (FlagEQ))
  6876  	// result: y
  6877  	for {
  6878  		_ = v.Args[2]
  6879  		y := v.Args[0]
  6880  		v_2 := v.Args[2]
  6881  		if v_2.Op != OpAMD64FlagEQ {
  6882  			break
  6883  		}
  6884  		v.reset(OpCopy)
  6885  		v.Type = y.Type
  6886  		v.AddArg(y)
  6887  		return true
  6888  	}
  6889  	// match: (CMOVQHI _ x (FlagGT_UGT))
  6890  	// result: x
  6891  	for {
  6892  		_ = v.Args[2]
  6893  		x := v.Args[1]
  6894  		v_2 := v.Args[2]
  6895  		if v_2.Op != OpAMD64FlagGT_UGT {
  6896  			break
  6897  		}
  6898  		v.reset(OpCopy)
  6899  		v.Type = x.Type
  6900  		v.AddArg(x)
  6901  		return true
  6902  	}
  6903  	// match: (CMOVQHI y _ (FlagGT_ULT))
  6904  	// result: y
  6905  	for {
  6906  		_ = v.Args[2]
  6907  		y := v.Args[0]
  6908  		v_2 := v.Args[2]
  6909  		if v_2.Op != OpAMD64FlagGT_ULT {
  6910  			break
  6911  		}
  6912  		v.reset(OpCopy)
  6913  		v.Type = y.Type
  6914  		v.AddArg(y)
  6915  		return true
  6916  	}
  6917  	// match: (CMOVQHI y _ (FlagLT_ULT))
  6918  	// result: y
  6919  	for {
  6920  		_ = v.Args[2]
  6921  		y := v.Args[0]
  6922  		v_2 := v.Args[2]
  6923  		if v_2.Op != OpAMD64FlagLT_ULT {
  6924  			break
  6925  		}
  6926  		v.reset(OpCopy)
  6927  		v.Type = y.Type
  6928  		v.AddArg(y)
  6929  		return true
  6930  	}
  6931  	// match: (CMOVQHI _ x (FlagLT_UGT))
  6932  	// result: x
  6933  	for {
  6934  		_ = v.Args[2]
  6935  		x := v.Args[1]
  6936  		v_2 := v.Args[2]
  6937  		if v_2.Op != OpAMD64FlagLT_UGT {
  6938  			break
  6939  		}
  6940  		v.reset(OpCopy)
  6941  		v.Type = x.Type
  6942  		v.AddArg(x)
  6943  		return true
  6944  	}
  6945  	return false
  6946  }
  6947  func rewriteValueAMD64_OpAMD64CMOVQLE_0(v *Value) bool {
  6948  	// match: (CMOVQLE x y (InvertFlags cond))
  6949  	// result: (CMOVQGE x y cond)
  6950  	for {
  6951  		_ = v.Args[2]
  6952  		x := v.Args[0]
  6953  		y := v.Args[1]
  6954  		v_2 := v.Args[2]
  6955  		if v_2.Op != OpAMD64InvertFlags {
  6956  			break
  6957  		}
  6958  		cond := v_2.Args[0]
  6959  		v.reset(OpAMD64CMOVQGE)
  6960  		v.AddArg(x)
  6961  		v.AddArg(y)
  6962  		v.AddArg(cond)
  6963  		return true
  6964  	}
  6965  	// match: (CMOVQLE _ x (FlagEQ))
  6966  	// result: x
  6967  	for {
  6968  		_ = v.Args[2]
  6969  		x := v.Args[1]
  6970  		v_2 := v.Args[2]
  6971  		if v_2.Op != OpAMD64FlagEQ {
  6972  			break
  6973  		}
  6974  		v.reset(OpCopy)
  6975  		v.Type = x.Type
  6976  		v.AddArg(x)
  6977  		return true
  6978  	}
  6979  	// match: (CMOVQLE y _ (FlagGT_UGT))
  6980  	// result: y
  6981  	for {
  6982  		_ = v.Args[2]
  6983  		y := v.Args[0]
  6984  		v_2 := v.Args[2]
  6985  		if v_2.Op != OpAMD64FlagGT_UGT {
  6986  			break
  6987  		}
  6988  		v.reset(OpCopy)
  6989  		v.Type = y.Type
  6990  		v.AddArg(y)
  6991  		return true
  6992  	}
  6993  	// match: (CMOVQLE y _ (FlagGT_ULT))
  6994  	// result: y
  6995  	for {
  6996  		_ = v.Args[2]
  6997  		y := v.Args[0]
  6998  		v_2 := v.Args[2]
  6999  		if v_2.Op != OpAMD64FlagGT_ULT {
  7000  			break
  7001  		}
  7002  		v.reset(OpCopy)
  7003  		v.Type = y.Type
  7004  		v.AddArg(y)
  7005  		return true
  7006  	}
  7007  	// match: (CMOVQLE _ x (FlagLT_ULT))
  7008  	// result: x
  7009  	for {
  7010  		_ = v.Args[2]
  7011  		x := v.Args[1]
  7012  		v_2 := v.Args[2]
  7013  		if v_2.Op != OpAMD64FlagLT_ULT {
  7014  			break
  7015  		}
  7016  		v.reset(OpCopy)
  7017  		v.Type = x.Type
  7018  		v.AddArg(x)
  7019  		return true
  7020  	}
  7021  	// match: (CMOVQLE _ x (FlagLT_UGT))
  7022  	// result: x
  7023  	for {
  7024  		_ = v.Args[2]
  7025  		x := v.Args[1]
  7026  		v_2 := v.Args[2]
  7027  		if v_2.Op != OpAMD64FlagLT_UGT {
  7028  			break
  7029  		}
  7030  		v.reset(OpCopy)
  7031  		v.Type = x.Type
  7032  		v.AddArg(x)
  7033  		return true
  7034  	}
  7035  	return false
  7036  }
  7037  func rewriteValueAMD64_OpAMD64CMOVQLS_0(v *Value) bool {
  7038  	// match: (CMOVQLS x y (InvertFlags cond))
  7039  	// result: (CMOVQCC x y cond)
  7040  	for {
  7041  		_ = v.Args[2]
  7042  		x := v.Args[0]
  7043  		y := v.Args[1]
  7044  		v_2 := v.Args[2]
  7045  		if v_2.Op != OpAMD64InvertFlags {
  7046  			break
  7047  		}
  7048  		cond := v_2.Args[0]
  7049  		v.reset(OpAMD64CMOVQCC)
  7050  		v.AddArg(x)
  7051  		v.AddArg(y)
  7052  		v.AddArg(cond)
  7053  		return true
  7054  	}
  7055  	// match: (CMOVQLS _ x (FlagEQ))
  7056  	// result: x
  7057  	for {
  7058  		_ = v.Args[2]
  7059  		x := v.Args[1]
  7060  		v_2 := v.Args[2]
  7061  		if v_2.Op != OpAMD64FlagEQ {
  7062  			break
  7063  		}
  7064  		v.reset(OpCopy)
  7065  		v.Type = x.Type
  7066  		v.AddArg(x)
  7067  		return true
  7068  	}
  7069  	// match: (CMOVQLS y _ (FlagGT_UGT))
  7070  	// result: y
  7071  	for {
  7072  		_ = v.Args[2]
  7073  		y := v.Args[0]
  7074  		v_2 := v.Args[2]
  7075  		if v_2.Op != OpAMD64FlagGT_UGT {
  7076  			break
  7077  		}
  7078  		v.reset(OpCopy)
  7079  		v.Type = y.Type
  7080  		v.AddArg(y)
  7081  		return true
  7082  	}
  7083  	// match: (CMOVQLS _ x (FlagGT_ULT))
  7084  	// result: x
  7085  	for {
  7086  		_ = v.Args[2]
  7087  		x := v.Args[1]
  7088  		v_2 := v.Args[2]
  7089  		if v_2.Op != OpAMD64FlagGT_ULT {
  7090  			break
  7091  		}
  7092  		v.reset(OpCopy)
  7093  		v.Type = x.Type
  7094  		v.AddArg(x)
  7095  		return true
  7096  	}
  7097  	// match: (CMOVQLS _ x (FlagLT_ULT))
  7098  	// result: x
  7099  	for {
  7100  		_ = v.Args[2]
  7101  		x := v.Args[1]
  7102  		v_2 := v.Args[2]
  7103  		if v_2.Op != OpAMD64FlagLT_ULT {
  7104  			break
  7105  		}
  7106  		v.reset(OpCopy)
  7107  		v.Type = x.Type
  7108  		v.AddArg(x)
  7109  		return true
  7110  	}
  7111  	// match: (CMOVQLS y _ (FlagLT_UGT))
  7112  	// result: y
  7113  	for {
  7114  		_ = v.Args[2]
  7115  		y := v.Args[0]
  7116  		v_2 := v.Args[2]
  7117  		if v_2.Op != OpAMD64FlagLT_UGT {
  7118  			break
  7119  		}
  7120  		v.reset(OpCopy)
  7121  		v.Type = y.Type
  7122  		v.AddArg(y)
  7123  		return true
  7124  	}
  7125  	return false
  7126  }
  7127  func rewriteValueAMD64_OpAMD64CMOVQLT_0(v *Value) bool {
  7128  	// match: (CMOVQLT x y (InvertFlags cond))
  7129  	// result: (CMOVQGT x y cond)
  7130  	for {
  7131  		_ = v.Args[2]
  7132  		x := v.Args[0]
  7133  		y := v.Args[1]
  7134  		v_2 := v.Args[2]
  7135  		if v_2.Op != OpAMD64InvertFlags {
  7136  			break
  7137  		}
  7138  		cond := v_2.Args[0]
  7139  		v.reset(OpAMD64CMOVQGT)
  7140  		v.AddArg(x)
  7141  		v.AddArg(y)
  7142  		v.AddArg(cond)
  7143  		return true
  7144  	}
  7145  	// match: (CMOVQLT y _ (FlagEQ))
  7146  	// result: y
  7147  	for {
  7148  		_ = v.Args[2]
  7149  		y := v.Args[0]
  7150  		v_2 := v.Args[2]
  7151  		if v_2.Op != OpAMD64FlagEQ {
  7152  			break
  7153  		}
  7154  		v.reset(OpCopy)
  7155  		v.Type = y.Type
  7156  		v.AddArg(y)
  7157  		return true
  7158  	}
  7159  	// match: (CMOVQLT y _ (FlagGT_UGT))
  7160  	// result: y
  7161  	for {
  7162  		_ = v.Args[2]
  7163  		y := v.Args[0]
  7164  		v_2 := v.Args[2]
  7165  		if v_2.Op != OpAMD64FlagGT_UGT {
  7166  			break
  7167  		}
  7168  		v.reset(OpCopy)
  7169  		v.Type = y.Type
  7170  		v.AddArg(y)
  7171  		return true
  7172  	}
  7173  	// match: (CMOVQLT y _ (FlagGT_ULT))
  7174  	// result: y
  7175  	for {
  7176  		_ = v.Args[2]
  7177  		y := v.Args[0]
  7178  		v_2 := v.Args[2]
  7179  		if v_2.Op != OpAMD64FlagGT_ULT {
  7180  			break
  7181  		}
  7182  		v.reset(OpCopy)
  7183  		v.Type = y.Type
  7184  		v.AddArg(y)
  7185  		return true
  7186  	}
  7187  	// match: (CMOVQLT _ x (FlagLT_ULT))
  7188  	// result: x
  7189  	for {
  7190  		_ = v.Args[2]
  7191  		x := v.Args[1]
  7192  		v_2 := v.Args[2]
  7193  		if v_2.Op != OpAMD64FlagLT_ULT {
  7194  			break
  7195  		}
  7196  		v.reset(OpCopy)
  7197  		v.Type = x.Type
  7198  		v.AddArg(x)
  7199  		return true
  7200  	}
  7201  	// match: (CMOVQLT _ x (FlagLT_UGT))
  7202  	// result: x
  7203  	for {
  7204  		_ = v.Args[2]
  7205  		x := v.Args[1]
  7206  		v_2 := v.Args[2]
  7207  		if v_2.Op != OpAMD64FlagLT_UGT {
  7208  			break
  7209  		}
  7210  		v.reset(OpCopy)
  7211  		v.Type = x.Type
  7212  		v.AddArg(x)
  7213  		return true
  7214  	}
  7215  	return false
  7216  }
  7217  func rewriteValueAMD64_OpAMD64CMOVQNE_0(v *Value) bool {
  7218  	// match: (CMOVQNE x y (InvertFlags cond))
  7219  	// result: (CMOVQNE x y cond)
  7220  	for {
  7221  		_ = v.Args[2]
  7222  		x := v.Args[0]
  7223  		y := v.Args[1]
  7224  		v_2 := v.Args[2]
  7225  		if v_2.Op != OpAMD64InvertFlags {
  7226  			break
  7227  		}
  7228  		cond := v_2.Args[0]
  7229  		v.reset(OpAMD64CMOVQNE)
  7230  		v.AddArg(x)
  7231  		v.AddArg(y)
  7232  		v.AddArg(cond)
  7233  		return true
  7234  	}
  7235  	// match: (CMOVQNE y _ (FlagEQ))
  7236  	// result: y
  7237  	for {
  7238  		_ = v.Args[2]
  7239  		y := v.Args[0]
  7240  		v_2 := v.Args[2]
  7241  		if v_2.Op != OpAMD64FlagEQ {
  7242  			break
  7243  		}
  7244  		v.reset(OpCopy)
  7245  		v.Type = y.Type
  7246  		v.AddArg(y)
  7247  		return true
  7248  	}
  7249  	// match: (CMOVQNE _ x (FlagGT_UGT))
  7250  	// result: x
  7251  	for {
  7252  		_ = v.Args[2]
  7253  		x := v.Args[1]
  7254  		v_2 := v.Args[2]
  7255  		if v_2.Op != OpAMD64FlagGT_UGT {
  7256  			break
  7257  		}
  7258  		v.reset(OpCopy)
  7259  		v.Type = x.Type
  7260  		v.AddArg(x)
  7261  		return true
  7262  	}
  7263  	// match: (CMOVQNE _ x (FlagGT_ULT))
  7264  	// result: x
  7265  	for {
  7266  		_ = v.Args[2]
  7267  		x := v.Args[1]
  7268  		v_2 := v.Args[2]
  7269  		if v_2.Op != OpAMD64FlagGT_ULT {
  7270  			break
  7271  		}
  7272  		v.reset(OpCopy)
  7273  		v.Type = x.Type
  7274  		v.AddArg(x)
  7275  		return true
  7276  	}
  7277  	// match: (CMOVQNE _ x (FlagLT_ULT))
  7278  	// result: x
  7279  	for {
  7280  		_ = v.Args[2]
  7281  		x := v.Args[1]
  7282  		v_2 := v.Args[2]
  7283  		if v_2.Op != OpAMD64FlagLT_ULT {
  7284  			break
  7285  		}
  7286  		v.reset(OpCopy)
  7287  		v.Type = x.Type
  7288  		v.AddArg(x)
  7289  		return true
  7290  	}
  7291  	// match: (CMOVQNE _ x (FlagLT_UGT))
  7292  	// result: x
  7293  	for {
  7294  		_ = v.Args[2]
  7295  		x := v.Args[1]
  7296  		v_2 := v.Args[2]
  7297  		if v_2.Op != OpAMD64FlagLT_UGT {
  7298  			break
  7299  		}
  7300  		v.reset(OpCopy)
  7301  		v.Type = x.Type
  7302  		v.AddArg(x)
  7303  		return true
  7304  	}
  7305  	return false
  7306  }
  7307  func rewriteValueAMD64_OpAMD64CMOVWCC_0(v *Value) bool {
  7308  	// match: (CMOVWCC x y (InvertFlags cond))
  7309  	// result: (CMOVWLS x y cond)
  7310  	for {
  7311  		_ = v.Args[2]
  7312  		x := v.Args[0]
  7313  		y := v.Args[1]
  7314  		v_2 := v.Args[2]
  7315  		if v_2.Op != OpAMD64InvertFlags {
  7316  			break
  7317  		}
  7318  		cond := v_2.Args[0]
  7319  		v.reset(OpAMD64CMOVWLS)
  7320  		v.AddArg(x)
  7321  		v.AddArg(y)
  7322  		v.AddArg(cond)
  7323  		return true
  7324  	}
  7325  	// match: (CMOVWCC _ x (FlagEQ))
  7326  	// result: x
  7327  	for {
  7328  		_ = v.Args[2]
  7329  		x := v.Args[1]
  7330  		v_2 := v.Args[2]
  7331  		if v_2.Op != OpAMD64FlagEQ {
  7332  			break
  7333  		}
  7334  		v.reset(OpCopy)
  7335  		v.Type = x.Type
  7336  		v.AddArg(x)
  7337  		return true
  7338  	}
  7339  	// match: (CMOVWCC _ x (FlagGT_UGT))
  7340  	// result: x
  7341  	for {
  7342  		_ = v.Args[2]
  7343  		x := v.Args[1]
  7344  		v_2 := v.Args[2]
  7345  		if v_2.Op != OpAMD64FlagGT_UGT {
  7346  			break
  7347  		}
  7348  		v.reset(OpCopy)
  7349  		v.Type = x.Type
  7350  		v.AddArg(x)
  7351  		return true
  7352  	}
  7353  	// match: (CMOVWCC y _ (FlagGT_ULT))
  7354  	// result: y
  7355  	for {
  7356  		_ = v.Args[2]
  7357  		y := v.Args[0]
  7358  		v_2 := v.Args[2]
  7359  		if v_2.Op != OpAMD64FlagGT_ULT {
  7360  			break
  7361  		}
  7362  		v.reset(OpCopy)
  7363  		v.Type = y.Type
  7364  		v.AddArg(y)
  7365  		return true
  7366  	}
  7367  	// match: (CMOVWCC y _ (FlagLT_ULT))
  7368  	// result: y
  7369  	for {
  7370  		_ = v.Args[2]
  7371  		y := v.Args[0]
  7372  		v_2 := v.Args[2]
  7373  		if v_2.Op != OpAMD64FlagLT_ULT {
  7374  			break
  7375  		}
  7376  		v.reset(OpCopy)
  7377  		v.Type = y.Type
  7378  		v.AddArg(y)
  7379  		return true
  7380  	}
  7381  	// match: (CMOVWCC _ x (FlagLT_UGT))
  7382  	// result: x
  7383  	for {
  7384  		_ = v.Args[2]
  7385  		x := v.Args[1]
  7386  		v_2 := v.Args[2]
  7387  		if v_2.Op != OpAMD64FlagLT_UGT {
  7388  			break
  7389  		}
  7390  		v.reset(OpCopy)
  7391  		v.Type = x.Type
  7392  		v.AddArg(x)
  7393  		return true
  7394  	}
  7395  	return false
  7396  }
  7397  func rewriteValueAMD64_OpAMD64CMOVWCS_0(v *Value) bool {
  7398  	// match: (CMOVWCS x y (InvertFlags cond))
  7399  	// result: (CMOVWHI x y cond)
  7400  	for {
  7401  		_ = v.Args[2]
  7402  		x := v.Args[0]
  7403  		y := v.Args[1]
  7404  		v_2 := v.Args[2]
  7405  		if v_2.Op != OpAMD64InvertFlags {
  7406  			break
  7407  		}
  7408  		cond := v_2.Args[0]
  7409  		v.reset(OpAMD64CMOVWHI)
  7410  		v.AddArg(x)
  7411  		v.AddArg(y)
  7412  		v.AddArg(cond)
  7413  		return true
  7414  	}
  7415  	// match: (CMOVWCS y _ (FlagEQ))
  7416  	// result: y
  7417  	for {
  7418  		_ = v.Args[2]
  7419  		y := v.Args[0]
  7420  		v_2 := v.Args[2]
  7421  		if v_2.Op != OpAMD64FlagEQ {
  7422  			break
  7423  		}
  7424  		v.reset(OpCopy)
  7425  		v.Type = y.Type
  7426  		v.AddArg(y)
  7427  		return true
  7428  	}
  7429  	// match: (CMOVWCS y _ (FlagGT_UGT))
  7430  	// result: y
  7431  	for {
  7432  		_ = v.Args[2]
  7433  		y := v.Args[0]
  7434  		v_2 := v.Args[2]
  7435  		if v_2.Op != OpAMD64FlagGT_UGT {
  7436  			break
  7437  		}
  7438  		v.reset(OpCopy)
  7439  		v.Type = y.Type
  7440  		v.AddArg(y)
  7441  		return true
  7442  	}
  7443  	// match: (CMOVWCS _ x (FlagGT_ULT))
  7444  	// result: x
  7445  	for {
  7446  		_ = v.Args[2]
  7447  		x := v.Args[1]
  7448  		v_2 := v.Args[2]
  7449  		if v_2.Op != OpAMD64FlagGT_ULT {
  7450  			break
  7451  		}
  7452  		v.reset(OpCopy)
  7453  		v.Type = x.Type
  7454  		v.AddArg(x)
  7455  		return true
  7456  	}
  7457  	// match: (CMOVWCS _ x (FlagLT_ULT))
  7458  	// result: x
  7459  	for {
  7460  		_ = v.Args[2]
  7461  		x := v.Args[1]
  7462  		v_2 := v.Args[2]
  7463  		if v_2.Op != OpAMD64FlagLT_ULT {
  7464  			break
  7465  		}
  7466  		v.reset(OpCopy)
  7467  		v.Type = x.Type
  7468  		v.AddArg(x)
  7469  		return true
  7470  	}
  7471  	// match: (CMOVWCS y _ (FlagLT_UGT))
  7472  	// result: y
  7473  	for {
  7474  		_ = v.Args[2]
  7475  		y := v.Args[0]
  7476  		v_2 := v.Args[2]
  7477  		if v_2.Op != OpAMD64FlagLT_UGT {
  7478  			break
  7479  		}
  7480  		v.reset(OpCopy)
  7481  		v.Type = y.Type
  7482  		v.AddArg(y)
  7483  		return true
  7484  	}
  7485  	return false
  7486  }
  7487  func rewriteValueAMD64_OpAMD64CMOVWEQ_0(v *Value) bool {
  7488  	// match: (CMOVWEQ x y (InvertFlags cond))
  7489  	// result: (CMOVWEQ x y cond)
  7490  	for {
  7491  		_ = v.Args[2]
  7492  		x := v.Args[0]
  7493  		y := v.Args[1]
  7494  		v_2 := v.Args[2]
  7495  		if v_2.Op != OpAMD64InvertFlags {
  7496  			break
  7497  		}
  7498  		cond := v_2.Args[0]
  7499  		v.reset(OpAMD64CMOVWEQ)
  7500  		v.AddArg(x)
  7501  		v.AddArg(y)
  7502  		v.AddArg(cond)
  7503  		return true
  7504  	}
  7505  	// match: (CMOVWEQ _ x (FlagEQ))
  7506  	// result: x
  7507  	for {
  7508  		_ = v.Args[2]
  7509  		x := v.Args[1]
  7510  		v_2 := v.Args[2]
  7511  		if v_2.Op != OpAMD64FlagEQ {
  7512  			break
  7513  		}
  7514  		v.reset(OpCopy)
  7515  		v.Type = x.Type
  7516  		v.AddArg(x)
  7517  		return true
  7518  	}
  7519  	// match: (CMOVWEQ y _ (FlagGT_UGT))
  7520  	// result: y
  7521  	for {
  7522  		_ = v.Args[2]
  7523  		y := v.Args[0]
  7524  		v_2 := v.Args[2]
  7525  		if v_2.Op != OpAMD64FlagGT_UGT {
  7526  			break
  7527  		}
  7528  		v.reset(OpCopy)
  7529  		v.Type = y.Type
  7530  		v.AddArg(y)
  7531  		return true
  7532  	}
  7533  	// match: (CMOVWEQ y _ (FlagGT_ULT))
  7534  	// result: y
  7535  	for {
  7536  		_ = v.Args[2]
  7537  		y := v.Args[0]
  7538  		v_2 := v.Args[2]
  7539  		if v_2.Op != OpAMD64FlagGT_ULT {
  7540  			break
  7541  		}
  7542  		v.reset(OpCopy)
  7543  		v.Type = y.Type
  7544  		v.AddArg(y)
  7545  		return true
  7546  	}
  7547  	// match: (CMOVWEQ y _ (FlagLT_ULT))
  7548  	// result: y
  7549  	for {
  7550  		_ = v.Args[2]
  7551  		y := v.Args[0]
  7552  		v_2 := v.Args[2]
  7553  		if v_2.Op != OpAMD64FlagLT_ULT {
  7554  			break
  7555  		}
  7556  		v.reset(OpCopy)
  7557  		v.Type = y.Type
  7558  		v.AddArg(y)
  7559  		return true
  7560  	}
  7561  	// match: (CMOVWEQ y _ (FlagLT_UGT))
  7562  	// result: y
  7563  	for {
  7564  		_ = v.Args[2]
  7565  		y := v.Args[0]
  7566  		v_2 := v.Args[2]
  7567  		if v_2.Op != OpAMD64FlagLT_UGT {
  7568  			break
  7569  		}
  7570  		v.reset(OpCopy)
  7571  		v.Type = y.Type
  7572  		v.AddArg(y)
  7573  		return true
  7574  	}
  7575  	return false
  7576  }
  7577  func rewriteValueAMD64_OpAMD64CMOVWGE_0(v *Value) bool {
  7578  	// match: (CMOVWGE x y (InvertFlags cond))
  7579  	// result: (CMOVWLE x y cond)
  7580  	for {
  7581  		_ = v.Args[2]
  7582  		x := v.Args[0]
  7583  		y := v.Args[1]
  7584  		v_2 := v.Args[2]
  7585  		if v_2.Op != OpAMD64InvertFlags {
  7586  			break
  7587  		}
  7588  		cond := v_2.Args[0]
  7589  		v.reset(OpAMD64CMOVWLE)
  7590  		v.AddArg(x)
  7591  		v.AddArg(y)
  7592  		v.AddArg(cond)
  7593  		return true
  7594  	}
  7595  	// match: (CMOVWGE _ x (FlagEQ))
  7596  	// result: x
  7597  	for {
  7598  		_ = v.Args[2]
  7599  		x := v.Args[1]
  7600  		v_2 := v.Args[2]
  7601  		if v_2.Op != OpAMD64FlagEQ {
  7602  			break
  7603  		}
  7604  		v.reset(OpCopy)
  7605  		v.Type = x.Type
  7606  		v.AddArg(x)
  7607  		return true
  7608  	}
  7609  	// match: (CMOVWGE _ x (FlagGT_UGT))
  7610  	// result: x
  7611  	for {
  7612  		_ = v.Args[2]
  7613  		x := v.Args[1]
  7614  		v_2 := v.Args[2]
  7615  		if v_2.Op != OpAMD64FlagGT_UGT {
  7616  			break
  7617  		}
  7618  		v.reset(OpCopy)
  7619  		v.Type = x.Type
  7620  		v.AddArg(x)
  7621  		return true
  7622  	}
  7623  	// match: (CMOVWGE _ x (FlagGT_ULT))
  7624  	// result: x
  7625  	for {
  7626  		_ = v.Args[2]
  7627  		x := v.Args[1]
  7628  		v_2 := v.Args[2]
  7629  		if v_2.Op != OpAMD64FlagGT_ULT {
  7630  			break
  7631  		}
  7632  		v.reset(OpCopy)
  7633  		v.Type = x.Type
  7634  		v.AddArg(x)
  7635  		return true
  7636  	}
  7637  	// match: (CMOVWGE y _ (FlagLT_ULT))
  7638  	// result: y
  7639  	for {
  7640  		_ = v.Args[2]
  7641  		y := v.Args[0]
  7642  		v_2 := v.Args[2]
  7643  		if v_2.Op != OpAMD64FlagLT_ULT {
  7644  			break
  7645  		}
  7646  		v.reset(OpCopy)
  7647  		v.Type = y.Type
  7648  		v.AddArg(y)
  7649  		return true
  7650  	}
  7651  	// match: (CMOVWGE y _ (FlagLT_UGT))
  7652  	// result: y
  7653  	for {
  7654  		_ = v.Args[2]
  7655  		y := v.Args[0]
  7656  		v_2 := v.Args[2]
  7657  		if v_2.Op != OpAMD64FlagLT_UGT {
  7658  			break
  7659  		}
  7660  		v.reset(OpCopy)
  7661  		v.Type = y.Type
  7662  		v.AddArg(y)
  7663  		return true
  7664  	}
  7665  	return false
  7666  }
  7667  func rewriteValueAMD64_OpAMD64CMOVWGT_0(v *Value) bool {
  7668  	// match: (CMOVWGT x y (InvertFlags cond))
  7669  	// result: (CMOVWLT x y cond)
  7670  	for {
  7671  		_ = v.Args[2]
  7672  		x := v.Args[0]
  7673  		y := v.Args[1]
  7674  		v_2 := v.Args[2]
  7675  		if v_2.Op != OpAMD64InvertFlags {
  7676  			break
  7677  		}
  7678  		cond := v_2.Args[0]
  7679  		v.reset(OpAMD64CMOVWLT)
  7680  		v.AddArg(x)
  7681  		v.AddArg(y)
  7682  		v.AddArg(cond)
  7683  		return true
  7684  	}
  7685  	// match: (CMOVWGT y _ (FlagEQ))
  7686  	// result: y
  7687  	for {
  7688  		_ = v.Args[2]
  7689  		y := v.Args[0]
  7690  		v_2 := v.Args[2]
  7691  		if v_2.Op != OpAMD64FlagEQ {
  7692  			break
  7693  		}
  7694  		v.reset(OpCopy)
  7695  		v.Type = y.Type
  7696  		v.AddArg(y)
  7697  		return true
  7698  	}
  7699  	// match: (CMOVWGT _ x (FlagGT_UGT))
  7700  	// result: x
  7701  	for {
  7702  		_ = v.Args[2]
  7703  		x := v.Args[1]
  7704  		v_2 := v.Args[2]
  7705  		if v_2.Op != OpAMD64FlagGT_UGT {
  7706  			break
  7707  		}
  7708  		v.reset(OpCopy)
  7709  		v.Type = x.Type
  7710  		v.AddArg(x)
  7711  		return true
  7712  	}
  7713  	// match: (CMOVWGT _ x (FlagGT_ULT))
  7714  	// result: x
  7715  	for {
  7716  		_ = v.Args[2]
  7717  		x := v.Args[1]
  7718  		v_2 := v.Args[2]
  7719  		if v_2.Op != OpAMD64FlagGT_ULT {
  7720  			break
  7721  		}
  7722  		v.reset(OpCopy)
  7723  		v.Type = x.Type
  7724  		v.AddArg(x)
  7725  		return true
  7726  	}
  7727  	// match: (CMOVWGT y _ (FlagLT_ULT))
  7728  	// result: y
  7729  	for {
  7730  		_ = v.Args[2]
  7731  		y := v.Args[0]
  7732  		v_2 := v.Args[2]
  7733  		if v_2.Op != OpAMD64FlagLT_ULT {
  7734  			break
  7735  		}
  7736  		v.reset(OpCopy)
  7737  		v.Type = y.Type
  7738  		v.AddArg(y)
  7739  		return true
  7740  	}
  7741  	// match: (CMOVWGT y _ (FlagLT_UGT))
  7742  	// result: y
  7743  	for {
  7744  		_ = v.Args[2]
  7745  		y := v.Args[0]
  7746  		v_2 := v.Args[2]
  7747  		if v_2.Op != OpAMD64FlagLT_UGT {
  7748  			break
  7749  		}
  7750  		v.reset(OpCopy)
  7751  		v.Type = y.Type
  7752  		v.AddArg(y)
  7753  		return true
  7754  	}
  7755  	return false
  7756  }
  7757  func rewriteValueAMD64_OpAMD64CMOVWHI_0(v *Value) bool {
  7758  	// match: (CMOVWHI x y (InvertFlags cond))
  7759  	// result: (CMOVWCS x y cond)
  7760  	for {
  7761  		_ = v.Args[2]
  7762  		x := v.Args[0]
  7763  		y := v.Args[1]
  7764  		v_2 := v.Args[2]
  7765  		if v_2.Op != OpAMD64InvertFlags {
  7766  			break
  7767  		}
  7768  		cond := v_2.Args[0]
  7769  		v.reset(OpAMD64CMOVWCS)
  7770  		v.AddArg(x)
  7771  		v.AddArg(y)
  7772  		v.AddArg(cond)
  7773  		return true
  7774  	}
  7775  	// match: (CMOVWHI y _ (FlagEQ))
  7776  	// result: y
  7777  	for {
  7778  		_ = v.Args[2]
  7779  		y := v.Args[0]
  7780  		v_2 := v.Args[2]
  7781  		if v_2.Op != OpAMD64FlagEQ {
  7782  			break
  7783  		}
  7784  		v.reset(OpCopy)
  7785  		v.Type = y.Type
  7786  		v.AddArg(y)
  7787  		return true
  7788  	}
  7789  	// match: (CMOVWHI _ x (FlagGT_UGT))
  7790  	// result: x
  7791  	for {
  7792  		_ = v.Args[2]
  7793  		x := v.Args[1]
  7794  		v_2 := v.Args[2]
  7795  		if v_2.Op != OpAMD64FlagGT_UGT {
  7796  			break
  7797  		}
  7798  		v.reset(OpCopy)
  7799  		v.Type = x.Type
  7800  		v.AddArg(x)
  7801  		return true
  7802  	}
  7803  	// match: (CMOVWHI y _ (FlagGT_ULT))
  7804  	// result: y
  7805  	for {
  7806  		_ = v.Args[2]
  7807  		y := v.Args[0]
  7808  		v_2 := v.Args[2]
  7809  		if v_2.Op != OpAMD64FlagGT_ULT {
  7810  			break
  7811  		}
  7812  		v.reset(OpCopy)
  7813  		v.Type = y.Type
  7814  		v.AddArg(y)
  7815  		return true
  7816  	}
  7817  	// match: (CMOVWHI y _ (FlagLT_ULT))
  7818  	// result: y
  7819  	for {
  7820  		_ = v.Args[2]
  7821  		y := v.Args[0]
  7822  		v_2 := v.Args[2]
  7823  		if v_2.Op != OpAMD64FlagLT_ULT {
  7824  			break
  7825  		}
  7826  		v.reset(OpCopy)
  7827  		v.Type = y.Type
  7828  		v.AddArg(y)
  7829  		return true
  7830  	}
  7831  	// match: (CMOVWHI _ x (FlagLT_UGT))
  7832  	// result: x
  7833  	for {
  7834  		_ = v.Args[2]
  7835  		x := v.Args[1]
  7836  		v_2 := v.Args[2]
  7837  		if v_2.Op != OpAMD64FlagLT_UGT {
  7838  			break
  7839  		}
  7840  		v.reset(OpCopy)
  7841  		v.Type = x.Type
  7842  		v.AddArg(x)
  7843  		return true
  7844  	}
  7845  	return false
  7846  }
  7847  func rewriteValueAMD64_OpAMD64CMOVWLE_0(v *Value) bool {
  7848  	// match: (CMOVWLE x y (InvertFlags cond))
  7849  	// result: (CMOVWGE x y cond)
  7850  	for {
  7851  		_ = v.Args[2]
  7852  		x := v.Args[0]
  7853  		y := v.Args[1]
  7854  		v_2 := v.Args[2]
  7855  		if v_2.Op != OpAMD64InvertFlags {
  7856  			break
  7857  		}
  7858  		cond := v_2.Args[0]
  7859  		v.reset(OpAMD64CMOVWGE)
  7860  		v.AddArg(x)
  7861  		v.AddArg(y)
  7862  		v.AddArg(cond)
  7863  		return true
  7864  	}
  7865  	// match: (CMOVWLE _ x (FlagEQ))
  7866  	// result: x
  7867  	for {
  7868  		_ = v.Args[2]
  7869  		x := v.Args[1]
  7870  		v_2 := v.Args[2]
  7871  		if v_2.Op != OpAMD64FlagEQ {
  7872  			break
  7873  		}
  7874  		v.reset(OpCopy)
  7875  		v.Type = x.Type
  7876  		v.AddArg(x)
  7877  		return true
  7878  	}
  7879  	// match: (CMOVWLE y _ (FlagGT_UGT))
  7880  	// result: y
  7881  	for {
  7882  		_ = v.Args[2]
  7883  		y := v.Args[0]
  7884  		v_2 := v.Args[2]
  7885  		if v_2.Op != OpAMD64FlagGT_UGT {
  7886  			break
  7887  		}
  7888  		v.reset(OpCopy)
  7889  		v.Type = y.Type
  7890  		v.AddArg(y)
  7891  		return true
  7892  	}
  7893  	// match: (CMOVWLE y _ (FlagGT_ULT))
  7894  	// result: y
  7895  	for {
  7896  		_ = v.Args[2]
  7897  		y := v.Args[0]
  7898  		v_2 := v.Args[2]
  7899  		if v_2.Op != OpAMD64FlagGT_ULT {
  7900  			break
  7901  		}
  7902  		v.reset(OpCopy)
  7903  		v.Type = y.Type
  7904  		v.AddArg(y)
  7905  		return true
  7906  	}
  7907  	// match: (CMOVWLE _ x (FlagLT_ULT))
  7908  	// result: x
  7909  	for {
  7910  		_ = v.Args[2]
  7911  		x := v.Args[1]
  7912  		v_2 := v.Args[2]
  7913  		if v_2.Op != OpAMD64FlagLT_ULT {
  7914  			break
  7915  		}
  7916  		v.reset(OpCopy)
  7917  		v.Type = x.Type
  7918  		v.AddArg(x)
  7919  		return true
  7920  	}
  7921  	// match: (CMOVWLE _ x (FlagLT_UGT))
  7922  	// result: x
  7923  	for {
  7924  		_ = v.Args[2]
  7925  		x := v.Args[1]
  7926  		v_2 := v.Args[2]
  7927  		if v_2.Op != OpAMD64FlagLT_UGT {
  7928  			break
  7929  		}
  7930  		v.reset(OpCopy)
  7931  		v.Type = x.Type
  7932  		v.AddArg(x)
  7933  		return true
  7934  	}
  7935  	return false
  7936  }
  7937  func rewriteValueAMD64_OpAMD64CMOVWLS_0(v *Value) bool {
  7938  	// match: (CMOVWLS x y (InvertFlags cond))
  7939  	// result: (CMOVWCC x y cond)
  7940  	for {
  7941  		_ = v.Args[2]
  7942  		x := v.Args[0]
  7943  		y := v.Args[1]
  7944  		v_2 := v.Args[2]
  7945  		if v_2.Op != OpAMD64InvertFlags {
  7946  			break
  7947  		}
  7948  		cond := v_2.Args[0]
  7949  		v.reset(OpAMD64CMOVWCC)
  7950  		v.AddArg(x)
  7951  		v.AddArg(y)
  7952  		v.AddArg(cond)
  7953  		return true
  7954  	}
  7955  	// match: (CMOVWLS _ x (FlagEQ))
  7956  	// result: x
  7957  	for {
  7958  		_ = v.Args[2]
  7959  		x := v.Args[1]
  7960  		v_2 := v.Args[2]
  7961  		if v_2.Op != OpAMD64FlagEQ {
  7962  			break
  7963  		}
  7964  		v.reset(OpCopy)
  7965  		v.Type = x.Type
  7966  		v.AddArg(x)
  7967  		return true
  7968  	}
  7969  	// match: (CMOVWLS y _ (FlagGT_UGT))
  7970  	// result: y
  7971  	for {
  7972  		_ = v.Args[2]
  7973  		y := v.Args[0]
  7974  		v_2 := v.Args[2]
  7975  		if v_2.Op != OpAMD64FlagGT_UGT {
  7976  			break
  7977  		}
  7978  		v.reset(OpCopy)
  7979  		v.Type = y.Type
  7980  		v.AddArg(y)
  7981  		return true
  7982  	}
  7983  	// match: (CMOVWLS _ x (FlagGT_ULT))
  7984  	// result: x
  7985  	for {
  7986  		_ = v.Args[2]
  7987  		x := v.Args[1]
  7988  		v_2 := v.Args[2]
  7989  		if v_2.Op != OpAMD64FlagGT_ULT {
  7990  			break
  7991  		}
  7992  		v.reset(OpCopy)
  7993  		v.Type = x.Type
  7994  		v.AddArg(x)
  7995  		return true
  7996  	}
  7997  	// match: (CMOVWLS _ x (FlagLT_ULT))
  7998  	// result: x
  7999  	for {
  8000  		_ = v.Args[2]
  8001  		x := v.Args[1]
  8002  		v_2 := v.Args[2]
  8003  		if v_2.Op != OpAMD64FlagLT_ULT {
  8004  			break
  8005  		}
  8006  		v.reset(OpCopy)
  8007  		v.Type = x.Type
  8008  		v.AddArg(x)
  8009  		return true
  8010  	}
  8011  	// match: (CMOVWLS y _ (FlagLT_UGT))
  8012  	// result: y
  8013  	for {
  8014  		_ = v.Args[2]
  8015  		y := v.Args[0]
  8016  		v_2 := v.Args[2]
  8017  		if v_2.Op != OpAMD64FlagLT_UGT {
  8018  			break
  8019  		}
  8020  		v.reset(OpCopy)
  8021  		v.Type = y.Type
  8022  		v.AddArg(y)
  8023  		return true
  8024  	}
  8025  	return false
  8026  }
  8027  func rewriteValueAMD64_OpAMD64CMOVWLT_0(v *Value) bool {
  8028  	// match: (CMOVWLT x y (InvertFlags cond))
  8029  	// result: (CMOVWGT x y cond)
  8030  	for {
  8031  		_ = v.Args[2]
  8032  		x := v.Args[0]
  8033  		y := v.Args[1]
  8034  		v_2 := v.Args[2]
  8035  		if v_2.Op != OpAMD64InvertFlags {
  8036  			break
  8037  		}
  8038  		cond := v_2.Args[0]
  8039  		v.reset(OpAMD64CMOVWGT)
  8040  		v.AddArg(x)
  8041  		v.AddArg(y)
  8042  		v.AddArg(cond)
  8043  		return true
  8044  	}
  8045  	// match: (CMOVWLT y _ (FlagEQ))
  8046  	// result: y
  8047  	for {
  8048  		_ = v.Args[2]
  8049  		y := v.Args[0]
  8050  		v_2 := v.Args[2]
  8051  		if v_2.Op != OpAMD64FlagEQ {
  8052  			break
  8053  		}
  8054  		v.reset(OpCopy)
  8055  		v.Type = y.Type
  8056  		v.AddArg(y)
  8057  		return true
  8058  	}
  8059  	// match: (CMOVWLT y _ (FlagGT_UGT))
  8060  	// result: y
  8061  	for {
  8062  		_ = v.Args[2]
  8063  		y := v.Args[0]
  8064  		v_2 := v.Args[2]
  8065  		if v_2.Op != OpAMD64FlagGT_UGT {
  8066  			break
  8067  		}
  8068  		v.reset(OpCopy)
  8069  		v.Type = y.Type
  8070  		v.AddArg(y)
  8071  		return true
  8072  	}
  8073  	// match: (CMOVWLT y _ (FlagGT_ULT))
  8074  	// result: y
  8075  	for {
  8076  		_ = v.Args[2]
  8077  		y := v.Args[0]
  8078  		v_2 := v.Args[2]
  8079  		if v_2.Op != OpAMD64FlagGT_ULT {
  8080  			break
  8081  		}
  8082  		v.reset(OpCopy)
  8083  		v.Type = y.Type
  8084  		v.AddArg(y)
  8085  		return true
  8086  	}
  8087  	// match: (CMOVWLT _ x (FlagLT_ULT))
  8088  	// result: x
  8089  	for {
  8090  		_ = v.Args[2]
  8091  		x := v.Args[1]
  8092  		v_2 := v.Args[2]
  8093  		if v_2.Op != OpAMD64FlagLT_ULT {
  8094  			break
  8095  		}
  8096  		v.reset(OpCopy)
  8097  		v.Type = x.Type
  8098  		v.AddArg(x)
  8099  		return true
  8100  	}
  8101  	// match: (CMOVWLT _ x (FlagLT_UGT))
  8102  	// result: x
  8103  	for {
  8104  		_ = v.Args[2]
  8105  		x := v.Args[1]
  8106  		v_2 := v.Args[2]
  8107  		if v_2.Op != OpAMD64FlagLT_UGT {
  8108  			break
  8109  		}
  8110  		v.reset(OpCopy)
  8111  		v.Type = x.Type
  8112  		v.AddArg(x)
  8113  		return true
  8114  	}
  8115  	return false
  8116  }
  8117  func rewriteValueAMD64_OpAMD64CMOVWNE_0(v *Value) bool {
  8118  	// match: (CMOVWNE x y (InvertFlags cond))
  8119  	// result: (CMOVWNE x y cond)
  8120  	for {
  8121  		_ = v.Args[2]
  8122  		x := v.Args[0]
  8123  		y := v.Args[1]
  8124  		v_2 := v.Args[2]
  8125  		if v_2.Op != OpAMD64InvertFlags {
  8126  			break
  8127  		}
  8128  		cond := v_2.Args[0]
  8129  		v.reset(OpAMD64CMOVWNE)
  8130  		v.AddArg(x)
  8131  		v.AddArg(y)
  8132  		v.AddArg(cond)
  8133  		return true
  8134  	}
  8135  	// match: (CMOVWNE y _ (FlagEQ))
  8136  	// result: y
  8137  	for {
  8138  		_ = v.Args[2]
  8139  		y := v.Args[0]
  8140  		v_2 := v.Args[2]
  8141  		if v_2.Op != OpAMD64FlagEQ {
  8142  			break
  8143  		}
  8144  		v.reset(OpCopy)
  8145  		v.Type = y.Type
  8146  		v.AddArg(y)
  8147  		return true
  8148  	}
  8149  	// match: (CMOVWNE _ x (FlagGT_UGT))
  8150  	// result: x
  8151  	for {
  8152  		_ = v.Args[2]
  8153  		x := v.Args[1]
  8154  		v_2 := v.Args[2]
  8155  		if v_2.Op != OpAMD64FlagGT_UGT {
  8156  			break
  8157  		}
  8158  		v.reset(OpCopy)
  8159  		v.Type = x.Type
  8160  		v.AddArg(x)
  8161  		return true
  8162  	}
  8163  	// match: (CMOVWNE _ x (FlagGT_ULT))
  8164  	// result: x
  8165  	for {
  8166  		_ = v.Args[2]
  8167  		x := v.Args[1]
  8168  		v_2 := v.Args[2]
  8169  		if v_2.Op != OpAMD64FlagGT_ULT {
  8170  			break
  8171  		}
  8172  		v.reset(OpCopy)
  8173  		v.Type = x.Type
  8174  		v.AddArg(x)
  8175  		return true
  8176  	}
  8177  	// match: (CMOVWNE _ x (FlagLT_ULT))
  8178  	// result: x
  8179  	for {
  8180  		_ = v.Args[2]
  8181  		x := v.Args[1]
  8182  		v_2 := v.Args[2]
  8183  		if v_2.Op != OpAMD64FlagLT_ULT {
  8184  			break
  8185  		}
  8186  		v.reset(OpCopy)
  8187  		v.Type = x.Type
  8188  		v.AddArg(x)
  8189  		return true
  8190  	}
  8191  	// match: (CMOVWNE _ x (FlagLT_UGT))
  8192  	// result: x
  8193  	for {
  8194  		_ = v.Args[2]
  8195  		x := v.Args[1]
  8196  		v_2 := v.Args[2]
  8197  		if v_2.Op != OpAMD64FlagLT_UGT {
  8198  			break
  8199  		}
  8200  		v.reset(OpCopy)
  8201  		v.Type = x.Type
  8202  		v.AddArg(x)
  8203  		return true
  8204  	}
  8205  	return false
  8206  }
  8207  func rewriteValueAMD64_OpAMD64CMPB_0(v *Value) bool {
  8208  	b := v.Block
  8209  	// match: (CMPB x (MOVLconst [c]))
  8210  	// result: (CMPBconst x [int64(int8(c))])
  8211  	for {
  8212  		_ = v.Args[1]
  8213  		x := v.Args[0]
  8214  		v_1 := v.Args[1]
  8215  		if v_1.Op != OpAMD64MOVLconst {
  8216  			break
  8217  		}
  8218  		c := v_1.AuxInt
  8219  		v.reset(OpAMD64CMPBconst)
  8220  		v.AuxInt = int64(int8(c))
  8221  		v.AddArg(x)
  8222  		return true
  8223  	}
  8224  	// match: (CMPB (MOVLconst [c]) x)
  8225  	// result: (InvertFlags (CMPBconst x [int64(int8(c))]))
  8226  	for {
  8227  		x := v.Args[1]
  8228  		v_0 := v.Args[0]
  8229  		if v_0.Op != OpAMD64MOVLconst {
  8230  			break
  8231  		}
  8232  		c := v_0.AuxInt
  8233  		v.reset(OpAMD64InvertFlags)
  8234  		v0 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
  8235  		v0.AuxInt = int64(int8(c))
  8236  		v0.AddArg(x)
  8237  		v.AddArg(v0)
  8238  		return true
  8239  	}
  8240  	// match: (CMPB l:(MOVBload {sym} [off] ptr mem) x)
  8241  	// cond: canMergeLoad(v, l) && clobber(l)
  8242  	// result: (CMPBload {sym} [off] ptr x mem)
  8243  	for {
  8244  		x := v.Args[1]
  8245  		l := v.Args[0]
  8246  		if l.Op != OpAMD64MOVBload {
  8247  			break
  8248  		}
  8249  		off := l.AuxInt
  8250  		sym := l.Aux
  8251  		mem := l.Args[1]
  8252  		ptr := l.Args[0]
  8253  		if !(canMergeLoad(v, l) && clobber(l)) {
  8254  			break
  8255  		}
  8256  		v.reset(OpAMD64CMPBload)
  8257  		v.AuxInt = off
  8258  		v.Aux = sym
  8259  		v.AddArg(ptr)
  8260  		v.AddArg(x)
  8261  		v.AddArg(mem)
  8262  		return true
  8263  	}
  8264  	// match: (CMPB x l:(MOVBload {sym} [off] ptr mem))
  8265  	// cond: canMergeLoad(v, l) && clobber(l)
  8266  	// result: (InvertFlags (CMPBload {sym} [off] ptr x mem))
  8267  	for {
  8268  		_ = v.Args[1]
  8269  		x := v.Args[0]
  8270  		l := v.Args[1]
  8271  		if l.Op != OpAMD64MOVBload {
  8272  			break
  8273  		}
  8274  		off := l.AuxInt
  8275  		sym := l.Aux
  8276  		mem := l.Args[1]
  8277  		ptr := l.Args[0]
  8278  		if !(canMergeLoad(v, l) && clobber(l)) {
  8279  			break
  8280  		}
  8281  		v.reset(OpAMD64InvertFlags)
  8282  		v0 := b.NewValue0(l.Pos, OpAMD64CMPBload, types.TypeFlags)
  8283  		v0.AuxInt = off
  8284  		v0.Aux = sym
  8285  		v0.AddArg(ptr)
  8286  		v0.AddArg(x)
  8287  		v0.AddArg(mem)
  8288  		v.AddArg(v0)
  8289  		return true
  8290  	}
  8291  	return false
  8292  }
  8293  func rewriteValueAMD64_OpAMD64CMPBconst_0(v *Value) bool {
  8294  	b := v.Block
  8295  	// match: (CMPBconst (MOVLconst [x]) [y])
  8296  	// cond: int8(x)==int8(y)
  8297  	// result: (FlagEQ)
  8298  	for {
  8299  		y := v.AuxInt
  8300  		v_0 := v.Args[0]
  8301  		if v_0.Op != OpAMD64MOVLconst {
  8302  			break
  8303  		}
  8304  		x := v_0.AuxInt
  8305  		if !(int8(x) == int8(y)) {
  8306  			break
  8307  		}
  8308  		v.reset(OpAMD64FlagEQ)
  8309  		return true
  8310  	}
  8311  	// match: (CMPBconst (MOVLconst [x]) [y])
  8312  	// cond: int8(x)<int8(y) && uint8(x)<uint8(y)
  8313  	// result: (FlagLT_ULT)
  8314  	for {
  8315  		y := v.AuxInt
  8316  		v_0 := v.Args[0]
  8317  		if v_0.Op != OpAMD64MOVLconst {
  8318  			break
  8319  		}
  8320  		x := v_0.AuxInt
  8321  		if !(int8(x) < int8(y) && uint8(x) < uint8(y)) {
  8322  			break
  8323  		}
  8324  		v.reset(OpAMD64FlagLT_ULT)
  8325  		return true
  8326  	}
  8327  	// match: (CMPBconst (MOVLconst [x]) [y])
  8328  	// cond: int8(x)<int8(y) && uint8(x)>uint8(y)
  8329  	// result: (FlagLT_UGT)
  8330  	for {
  8331  		y := v.AuxInt
  8332  		v_0 := v.Args[0]
  8333  		if v_0.Op != OpAMD64MOVLconst {
  8334  			break
  8335  		}
  8336  		x := v_0.AuxInt
  8337  		if !(int8(x) < int8(y) && uint8(x) > uint8(y)) {
  8338  			break
  8339  		}
  8340  		v.reset(OpAMD64FlagLT_UGT)
  8341  		return true
  8342  	}
  8343  	// match: (CMPBconst (MOVLconst [x]) [y])
  8344  	// cond: int8(x)>int8(y) && uint8(x)<uint8(y)
  8345  	// result: (FlagGT_ULT)
  8346  	for {
  8347  		y := v.AuxInt
  8348  		v_0 := v.Args[0]
  8349  		if v_0.Op != OpAMD64MOVLconst {
  8350  			break
  8351  		}
  8352  		x := v_0.AuxInt
  8353  		if !(int8(x) > int8(y) && uint8(x) < uint8(y)) {
  8354  			break
  8355  		}
  8356  		v.reset(OpAMD64FlagGT_ULT)
  8357  		return true
  8358  	}
  8359  	// match: (CMPBconst (MOVLconst [x]) [y])
  8360  	// cond: int8(x)>int8(y) && uint8(x)>uint8(y)
  8361  	// result: (FlagGT_UGT)
  8362  	for {
  8363  		y := v.AuxInt
  8364  		v_0 := v.Args[0]
  8365  		if v_0.Op != OpAMD64MOVLconst {
  8366  			break
  8367  		}
  8368  		x := v_0.AuxInt
  8369  		if !(int8(x) > int8(y) && uint8(x) > uint8(y)) {
  8370  			break
  8371  		}
  8372  		v.reset(OpAMD64FlagGT_UGT)
  8373  		return true
  8374  	}
  8375  	// match: (CMPBconst (ANDLconst _ [m]) [n])
  8376  	// cond: 0 <= int8(m) && int8(m) < int8(n)
  8377  	// result: (FlagLT_ULT)
  8378  	for {
  8379  		n := v.AuxInt
  8380  		v_0 := v.Args[0]
  8381  		if v_0.Op != OpAMD64ANDLconst {
  8382  			break
  8383  		}
  8384  		m := v_0.AuxInt
  8385  		if !(0 <= int8(m) && int8(m) < int8(n)) {
  8386  			break
  8387  		}
  8388  		v.reset(OpAMD64FlagLT_ULT)
  8389  		return true
  8390  	}
  8391  	// match: (CMPBconst (ANDL x y) [0])
  8392  	// result: (TESTB x y)
  8393  	for {
  8394  		if v.AuxInt != 0 {
  8395  			break
  8396  		}
  8397  		v_0 := v.Args[0]
  8398  		if v_0.Op != OpAMD64ANDL {
  8399  			break
  8400  		}
  8401  		y := v_0.Args[1]
  8402  		x := v_0.Args[0]
  8403  		v.reset(OpAMD64TESTB)
  8404  		v.AddArg(x)
  8405  		v.AddArg(y)
  8406  		return true
  8407  	}
  8408  	// match: (CMPBconst (ANDLconst [c] x) [0])
  8409  	// result: (TESTBconst [int64(int8(c))] x)
  8410  	for {
  8411  		if v.AuxInt != 0 {
  8412  			break
  8413  		}
  8414  		v_0 := v.Args[0]
  8415  		if v_0.Op != OpAMD64ANDLconst {
  8416  			break
  8417  		}
  8418  		c := v_0.AuxInt
  8419  		x := v_0.Args[0]
  8420  		v.reset(OpAMD64TESTBconst)
  8421  		v.AuxInt = int64(int8(c))
  8422  		v.AddArg(x)
  8423  		return true
  8424  	}
  8425  	// match: (CMPBconst x [0])
  8426  	// result: (TESTB x x)
  8427  	for {
  8428  		if v.AuxInt != 0 {
  8429  			break
  8430  		}
  8431  		x := v.Args[0]
  8432  		v.reset(OpAMD64TESTB)
  8433  		v.AddArg(x)
  8434  		v.AddArg(x)
  8435  		return true
  8436  	}
  8437  	// match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c])
  8438  	// cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l)
  8439  	// result: @l.Block (CMPBconstload {sym} [makeValAndOff(c,off)] ptr mem)
  8440  	for {
  8441  		c := v.AuxInt
  8442  		l := v.Args[0]
  8443  		if l.Op != OpAMD64MOVBload {
  8444  			break
  8445  		}
  8446  		off := l.AuxInt
  8447  		sym := l.Aux
  8448  		mem := l.Args[1]
  8449  		ptr := l.Args[0]
  8450  		if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) {
  8451  			break
  8452  		}
  8453  		b = l.Block
  8454  		v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags)
  8455  		v.reset(OpCopy)
  8456  		v.AddArg(v0)
  8457  		v0.AuxInt = makeValAndOff(c, off)
  8458  		v0.Aux = sym
  8459  		v0.AddArg(ptr)
  8460  		v0.AddArg(mem)
  8461  		return true
  8462  	}
  8463  	return false
  8464  }
  8465  func rewriteValueAMD64_OpAMD64CMPBconstload_0(v *Value) bool {
  8466  	// match: (CMPBconstload [valoff1] {sym} (ADDQconst [off2] base) mem)
  8467  	// cond: ValAndOff(valoff1).canAdd(off2)
  8468  	// result: (CMPBconstload [ValAndOff(valoff1).add(off2)] {sym} base mem)
  8469  	for {
  8470  		valoff1 := v.AuxInt
  8471  		sym := v.Aux
  8472  		mem := v.Args[1]
  8473  		v_0 := v.Args[0]
  8474  		if v_0.Op != OpAMD64ADDQconst {
  8475  			break
  8476  		}
  8477  		off2 := v_0.AuxInt
  8478  		base := v_0.Args[0]
  8479  		if !(ValAndOff(valoff1).canAdd(off2)) {
  8480  			break
  8481  		}
  8482  		v.reset(OpAMD64CMPBconstload)
  8483  		v.AuxInt = ValAndOff(valoff1).add(off2)
  8484  		v.Aux = sym
  8485  		v.AddArg(base)
  8486  		v.AddArg(mem)
  8487  		return true
  8488  	}
  8489  	// match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  8490  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  8491  	// result: (CMPBconstload [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  8492  	for {
  8493  		valoff1 := v.AuxInt
  8494  		sym1 := v.Aux
  8495  		mem := v.Args[1]
  8496  		v_0 := v.Args[0]
  8497  		if v_0.Op != OpAMD64LEAQ {
  8498  			break
  8499  		}
  8500  		off2 := v_0.AuxInt
  8501  		sym2 := v_0.Aux
  8502  		base := v_0.Args[0]
  8503  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  8504  			break
  8505  		}
  8506  		v.reset(OpAMD64CMPBconstload)
  8507  		v.AuxInt = ValAndOff(valoff1).add(off2)
  8508  		v.Aux = mergeSym(sym1, sym2)
  8509  		v.AddArg(base)
  8510  		v.AddArg(mem)
  8511  		return true
  8512  	}
  8513  	return false
  8514  }
  8515  func rewriteValueAMD64_OpAMD64CMPBload_0(v *Value) bool {
  8516  	// match: (CMPBload [off1] {sym} (ADDQconst [off2] base) val mem)
  8517  	// cond: is32Bit(off1+off2)
  8518  	// result: (CMPBload [off1+off2] {sym} base val mem)
  8519  	for {
  8520  		off1 := v.AuxInt
  8521  		sym := v.Aux
  8522  		mem := v.Args[2]
  8523  		v_0 := v.Args[0]
  8524  		if v_0.Op != OpAMD64ADDQconst {
  8525  			break
  8526  		}
  8527  		off2 := v_0.AuxInt
  8528  		base := v_0.Args[0]
  8529  		val := v.Args[1]
  8530  		if !(is32Bit(off1 + off2)) {
  8531  			break
  8532  		}
  8533  		v.reset(OpAMD64CMPBload)
  8534  		v.AuxInt = off1 + off2
  8535  		v.Aux = sym
  8536  		v.AddArg(base)
  8537  		v.AddArg(val)
  8538  		v.AddArg(mem)
  8539  		return true
  8540  	}
  8541  	// match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  8542  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  8543  	// result: (CMPBload [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  8544  	for {
  8545  		off1 := v.AuxInt
  8546  		sym1 := v.Aux
  8547  		mem := v.Args[2]
  8548  		v_0 := v.Args[0]
  8549  		if v_0.Op != OpAMD64LEAQ {
  8550  			break
  8551  		}
  8552  		off2 := v_0.AuxInt
  8553  		sym2 := v_0.Aux
  8554  		base := v_0.Args[0]
  8555  		val := v.Args[1]
  8556  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  8557  			break
  8558  		}
  8559  		v.reset(OpAMD64CMPBload)
  8560  		v.AuxInt = off1 + off2
  8561  		v.Aux = mergeSym(sym1, sym2)
  8562  		v.AddArg(base)
  8563  		v.AddArg(val)
  8564  		v.AddArg(mem)
  8565  		return true
  8566  	}
  8567  	// match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem)
  8568  	// cond: validValAndOff(int64(int8(c)),off)
  8569  	// result: (CMPBconstload {sym} [makeValAndOff(int64(int8(c)),off)] ptr mem)
  8570  	for {
  8571  		off := v.AuxInt
  8572  		sym := v.Aux
  8573  		mem := v.Args[2]
  8574  		ptr := v.Args[0]
  8575  		v_1 := v.Args[1]
  8576  		if v_1.Op != OpAMD64MOVLconst {
  8577  			break
  8578  		}
  8579  		c := v_1.AuxInt
  8580  		if !(validValAndOff(int64(int8(c)), off)) {
  8581  			break
  8582  		}
  8583  		v.reset(OpAMD64CMPBconstload)
  8584  		v.AuxInt = makeValAndOff(int64(int8(c)), off)
  8585  		v.Aux = sym
  8586  		v.AddArg(ptr)
  8587  		v.AddArg(mem)
  8588  		return true
  8589  	}
  8590  	return false
  8591  }
  8592  func rewriteValueAMD64_OpAMD64CMPL_0(v *Value) bool {
  8593  	b := v.Block
  8594  	// match: (CMPL x (MOVLconst [c]))
  8595  	// result: (CMPLconst x [c])
  8596  	for {
  8597  		_ = v.Args[1]
  8598  		x := v.Args[0]
  8599  		v_1 := v.Args[1]
  8600  		if v_1.Op != OpAMD64MOVLconst {
  8601  			break
  8602  		}
  8603  		c := v_1.AuxInt
  8604  		v.reset(OpAMD64CMPLconst)
  8605  		v.AuxInt = c
  8606  		v.AddArg(x)
  8607  		return true
  8608  	}
  8609  	// match: (CMPL (MOVLconst [c]) x)
  8610  	// result: (InvertFlags (CMPLconst x [c]))
  8611  	for {
  8612  		x := v.Args[1]
  8613  		v_0 := v.Args[0]
  8614  		if v_0.Op != OpAMD64MOVLconst {
  8615  			break
  8616  		}
  8617  		c := v_0.AuxInt
  8618  		v.reset(OpAMD64InvertFlags)
  8619  		v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
  8620  		v0.AuxInt = c
  8621  		v0.AddArg(x)
  8622  		v.AddArg(v0)
  8623  		return true
  8624  	}
  8625  	// match: (CMPL l:(MOVLload {sym} [off] ptr mem) x)
  8626  	// cond: canMergeLoad(v, l) && clobber(l)
  8627  	// result: (CMPLload {sym} [off] ptr x mem)
  8628  	for {
  8629  		x := v.Args[1]
  8630  		l := v.Args[0]
  8631  		if l.Op != OpAMD64MOVLload {
  8632  			break
  8633  		}
  8634  		off := l.AuxInt
  8635  		sym := l.Aux
  8636  		mem := l.Args[1]
  8637  		ptr := l.Args[0]
  8638  		if !(canMergeLoad(v, l) && clobber(l)) {
  8639  			break
  8640  		}
  8641  		v.reset(OpAMD64CMPLload)
  8642  		v.AuxInt = off
  8643  		v.Aux = sym
  8644  		v.AddArg(ptr)
  8645  		v.AddArg(x)
  8646  		v.AddArg(mem)
  8647  		return true
  8648  	}
  8649  	// match: (CMPL x l:(MOVLload {sym} [off] ptr mem))
  8650  	// cond: canMergeLoad(v, l) && clobber(l)
  8651  	// result: (InvertFlags (CMPLload {sym} [off] ptr x mem))
  8652  	for {
  8653  		_ = v.Args[1]
  8654  		x := v.Args[0]
  8655  		l := v.Args[1]
  8656  		if l.Op != OpAMD64MOVLload {
  8657  			break
  8658  		}
  8659  		off := l.AuxInt
  8660  		sym := l.Aux
  8661  		mem := l.Args[1]
  8662  		ptr := l.Args[0]
  8663  		if !(canMergeLoad(v, l) && clobber(l)) {
  8664  			break
  8665  		}
  8666  		v.reset(OpAMD64InvertFlags)
  8667  		v0 := b.NewValue0(l.Pos, OpAMD64CMPLload, types.TypeFlags)
  8668  		v0.AuxInt = off
  8669  		v0.Aux = sym
  8670  		v0.AddArg(ptr)
  8671  		v0.AddArg(x)
  8672  		v0.AddArg(mem)
  8673  		v.AddArg(v0)
  8674  		return true
  8675  	}
  8676  	return false
  8677  }
  8678  func rewriteValueAMD64_OpAMD64CMPLconst_0(v *Value) bool {
  8679  	// match: (CMPLconst (MOVLconst [x]) [y])
  8680  	// cond: int32(x)==int32(y)
  8681  	// result: (FlagEQ)
  8682  	for {
  8683  		y := v.AuxInt
  8684  		v_0 := v.Args[0]
  8685  		if v_0.Op != OpAMD64MOVLconst {
  8686  			break
  8687  		}
  8688  		x := v_0.AuxInt
  8689  		if !(int32(x) == int32(y)) {
  8690  			break
  8691  		}
  8692  		v.reset(OpAMD64FlagEQ)
  8693  		return true
  8694  	}
  8695  	// match: (CMPLconst (MOVLconst [x]) [y])
  8696  	// cond: int32(x)<int32(y) && uint32(x)<uint32(y)
  8697  	// result: (FlagLT_ULT)
  8698  	for {
  8699  		y := v.AuxInt
  8700  		v_0 := v.Args[0]
  8701  		if v_0.Op != OpAMD64MOVLconst {
  8702  			break
  8703  		}
  8704  		x := v_0.AuxInt
  8705  		if !(int32(x) < int32(y) && uint32(x) < uint32(y)) {
  8706  			break
  8707  		}
  8708  		v.reset(OpAMD64FlagLT_ULT)
  8709  		return true
  8710  	}
  8711  	// match: (CMPLconst (MOVLconst [x]) [y])
  8712  	// cond: int32(x)<int32(y) && uint32(x)>uint32(y)
  8713  	// result: (FlagLT_UGT)
  8714  	for {
  8715  		y := v.AuxInt
  8716  		v_0 := v.Args[0]
  8717  		if v_0.Op != OpAMD64MOVLconst {
  8718  			break
  8719  		}
  8720  		x := v_0.AuxInt
  8721  		if !(int32(x) < int32(y) && uint32(x) > uint32(y)) {
  8722  			break
  8723  		}
  8724  		v.reset(OpAMD64FlagLT_UGT)
  8725  		return true
  8726  	}
  8727  	// match: (CMPLconst (MOVLconst [x]) [y])
  8728  	// cond: int32(x)>int32(y) && uint32(x)<uint32(y)
  8729  	// result: (FlagGT_ULT)
  8730  	for {
  8731  		y := v.AuxInt
  8732  		v_0 := v.Args[0]
  8733  		if v_0.Op != OpAMD64MOVLconst {
  8734  			break
  8735  		}
  8736  		x := v_0.AuxInt
  8737  		if !(int32(x) > int32(y) && uint32(x) < uint32(y)) {
  8738  			break
  8739  		}
  8740  		v.reset(OpAMD64FlagGT_ULT)
  8741  		return true
  8742  	}
  8743  	// match: (CMPLconst (MOVLconst [x]) [y])
  8744  	// cond: int32(x)>int32(y) && uint32(x)>uint32(y)
  8745  	// result: (FlagGT_UGT)
  8746  	for {
  8747  		y := v.AuxInt
  8748  		v_0 := v.Args[0]
  8749  		if v_0.Op != OpAMD64MOVLconst {
  8750  			break
  8751  		}
  8752  		x := v_0.AuxInt
  8753  		if !(int32(x) > int32(y) && uint32(x) > uint32(y)) {
  8754  			break
  8755  		}
  8756  		v.reset(OpAMD64FlagGT_UGT)
  8757  		return true
  8758  	}
  8759  	// match: (CMPLconst (SHRLconst _ [c]) [n])
  8760  	// cond: 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n)
  8761  	// result: (FlagLT_ULT)
  8762  	for {
  8763  		n := v.AuxInt
  8764  		v_0 := v.Args[0]
  8765  		if v_0.Op != OpAMD64SHRLconst {
  8766  			break
  8767  		}
  8768  		c := v_0.AuxInt
  8769  		if !(0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n)) {
  8770  			break
  8771  		}
  8772  		v.reset(OpAMD64FlagLT_ULT)
  8773  		return true
  8774  	}
  8775  	// match: (CMPLconst (ANDLconst _ [m]) [n])
  8776  	// cond: 0 <= int32(m) && int32(m) < int32(n)
  8777  	// result: (FlagLT_ULT)
  8778  	for {
  8779  		n := v.AuxInt
  8780  		v_0 := v.Args[0]
  8781  		if v_0.Op != OpAMD64ANDLconst {
  8782  			break
  8783  		}
  8784  		m := v_0.AuxInt
  8785  		if !(0 <= int32(m) && int32(m) < int32(n)) {
  8786  			break
  8787  		}
  8788  		v.reset(OpAMD64FlagLT_ULT)
  8789  		return true
  8790  	}
  8791  	// match: (CMPLconst (ANDL x y) [0])
  8792  	// result: (TESTL x y)
  8793  	for {
  8794  		if v.AuxInt != 0 {
  8795  			break
  8796  		}
  8797  		v_0 := v.Args[0]
  8798  		if v_0.Op != OpAMD64ANDL {
  8799  			break
  8800  		}
  8801  		y := v_0.Args[1]
  8802  		x := v_0.Args[0]
  8803  		v.reset(OpAMD64TESTL)
  8804  		v.AddArg(x)
  8805  		v.AddArg(y)
  8806  		return true
  8807  	}
  8808  	// match: (CMPLconst (ANDLconst [c] x) [0])
  8809  	// result: (TESTLconst [c] x)
  8810  	for {
  8811  		if v.AuxInt != 0 {
  8812  			break
  8813  		}
  8814  		v_0 := v.Args[0]
  8815  		if v_0.Op != OpAMD64ANDLconst {
  8816  			break
  8817  		}
  8818  		c := v_0.AuxInt
  8819  		x := v_0.Args[0]
  8820  		v.reset(OpAMD64TESTLconst)
  8821  		v.AuxInt = c
  8822  		v.AddArg(x)
  8823  		return true
  8824  	}
  8825  	// match: (CMPLconst x [0])
  8826  	// result: (TESTL x x)
  8827  	for {
  8828  		if v.AuxInt != 0 {
  8829  			break
  8830  		}
  8831  		x := v.Args[0]
  8832  		v.reset(OpAMD64TESTL)
  8833  		v.AddArg(x)
  8834  		v.AddArg(x)
  8835  		return true
  8836  	}
  8837  	return false
  8838  }
  8839  func rewriteValueAMD64_OpAMD64CMPLconst_10(v *Value) bool {
  8840  	b := v.Block
  8841  	// match: (CMPLconst l:(MOVLload {sym} [off] ptr mem) [c])
  8842  	// cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l)
  8843  	// result: @l.Block (CMPLconstload {sym} [makeValAndOff(c,off)] ptr mem)
  8844  	for {
  8845  		c := v.AuxInt
  8846  		l := v.Args[0]
  8847  		if l.Op != OpAMD64MOVLload {
  8848  			break
  8849  		}
  8850  		off := l.AuxInt
  8851  		sym := l.Aux
  8852  		mem := l.Args[1]
  8853  		ptr := l.Args[0]
  8854  		if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) {
  8855  			break
  8856  		}
  8857  		b = l.Block
  8858  		v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags)
  8859  		v.reset(OpCopy)
  8860  		v.AddArg(v0)
  8861  		v0.AuxInt = makeValAndOff(c, off)
  8862  		v0.Aux = sym
  8863  		v0.AddArg(ptr)
  8864  		v0.AddArg(mem)
  8865  		return true
  8866  	}
  8867  	return false
  8868  }
  8869  func rewriteValueAMD64_OpAMD64CMPLconstload_0(v *Value) bool {
  8870  	// match: (CMPLconstload [valoff1] {sym} (ADDQconst [off2] base) mem)
  8871  	// cond: ValAndOff(valoff1).canAdd(off2)
  8872  	// result: (CMPLconstload [ValAndOff(valoff1).add(off2)] {sym} base mem)
  8873  	for {
  8874  		valoff1 := v.AuxInt
  8875  		sym := v.Aux
  8876  		mem := v.Args[1]
  8877  		v_0 := v.Args[0]
  8878  		if v_0.Op != OpAMD64ADDQconst {
  8879  			break
  8880  		}
  8881  		off2 := v_0.AuxInt
  8882  		base := v_0.Args[0]
  8883  		if !(ValAndOff(valoff1).canAdd(off2)) {
  8884  			break
  8885  		}
  8886  		v.reset(OpAMD64CMPLconstload)
  8887  		v.AuxInt = ValAndOff(valoff1).add(off2)
  8888  		v.Aux = sym
  8889  		v.AddArg(base)
  8890  		v.AddArg(mem)
  8891  		return true
  8892  	}
  8893  	// match: (CMPLconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  8894  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  8895  	// result: (CMPLconstload [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  8896  	for {
  8897  		valoff1 := v.AuxInt
  8898  		sym1 := v.Aux
  8899  		mem := v.Args[1]
  8900  		v_0 := v.Args[0]
  8901  		if v_0.Op != OpAMD64LEAQ {
  8902  			break
  8903  		}
  8904  		off2 := v_0.AuxInt
  8905  		sym2 := v_0.Aux
  8906  		base := v_0.Args[0]
  8907  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  8908  			break
  8909  		}
  8910  		v.reset(OpAMD64CMPLconstload)
  8911  		v.AuxInt = ValAndOff(valoff1).add(off2)
  8912  		v.Aux = mergeSym(sym1, sym2)
  8913  		v.AddArg(base)
  8914  		v.AddArg(mem)
  8915  		return true
  8916  	}
  8917  	return false
  8918  }
  8919  func rewriteValueAMD64_OpAMD64CMPLload_0(v *Value) bool {
  8920  	// match: (CMPLload [off1] {sym} (ADDQconst [off2] base) val mem)
  8921  	// cond: is32Bit(off1+off2)
  8922  	// result: (CMPLload [off1+off2] {sym} base val mem)
  8923  	for {
  8924  		off1 := v.AuxInt
  8925  		sym := v.Aux
  8926  		mem := v.Args[2]
  8927  		v_0 := v.Args[0]
  8928  		if v_0.Op != OpAMD64ADDQconst {
  8929  			break
  8930  		}
  8931  		off2 := v_0.AuxInt
  8932  		base := v_0.Args[0]
  8933  		val := v.Args[1]
  8934  		if !(is32Bit(off1 + off2)) {
  8935  			break
  8936  		}
  8937  		v.reset(OpAMD64CMPLload)
  8938  		v.AuxInt = off1 + off2
  8939  		v.Aux = sym
  8940  		v.AddArg(base)
  8941  		v.AddArg(val)
  8942  		v.AddArg(mem)
  8943  		return true
  8944  	}
  8945  	// match: (CMPLload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  8946  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  8947  	// result: (CMPLload [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  8948  	for {
  8949  		off1 := v.AuxInt
  8950  		sym1 := v.Aux
  8951  		mem := v.Args[2]
  8952  		v_0 := v.Args[0]
  8953  		if v_0.Op != OpAMD64LEAQ {
  8954  			break
  8955  		}
  8956  		off2 := v_0.AuxInt
  8957  		sym2 := v_0.Aux
  8958  		base := v_0.Args[0]
  8959  		val := v.Args[1]
  8960  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  8961  			break
  8962  		}
  8963  		v.reset(OpAMD64CMPLload)
  8964  		v.AuxInt = off1 + off2
  8965  		v.Aux = mergeSym(sym1, sym2)
  8966  		v.AddArg(base)
  8967  		v.AddArg(val)
  8968  		v.AddArg(mem)
  8969  		return true
  8970  	}
  8971  	// match: (CMPLload {sym} [off] ptr (MOVLconst [c]) mem)
  8972  	// cond: validValAndOff(c,off)
  8973  	// result: (CMPLconstload {sym} [makeValAndOff(c,off)] ptr mem)
  8974  	for {
  8975  		off := v.AuxInt
  8976  		sym := v.Aux
  8977  		mem := v.Args[2]
  8978  		ptr := v.Args[0]
  8979  		v_1 := v.Args[1]
  8980  		if v_1.Op != OpAMD64MOVLconst {
  8981  			break
  8982  		}
  8983  		c := v_1.AuxInt
  8984  		if !(validValAndOff(c, off)) {
  8985  			break
  8986  		}
  8987  		v.reset(OpAMD64CMPLconstload)
  8988  		v.AuxInt = makeValAndOff(c, off)
  8989  		v.Aux = sym
  8990  		v.AddArg(ptr)
  8991  		v.AddArg(mem)
  8992  		return true
  8993  	}
  8994  	return false
  8995  }
  8996  func rewriteValueAMD64_OpAMD64CMPQ_0(v *Value) bool {
  8997  	b := v.Block
  8998  	// match: (CMPQ x (MOVQconst [c]))
  8999  	// cond: is32Bit(c)
  9000  	// result: (CMPQconst x [c])
  9001  	for {
  9002  		_ = v.Args[1]
  9003  		x := v.Args[0]
  9004  		v_1 := v.Args[1]
  9005  		if v_1.Op != OpAMD64MOVQconst {
  9006  			break
  9007  		}
  9008  		c := v_1.AuxInt
  9009  		if !(is32Bit(c)) {
  9010  			break
  9011  		}
  9012  		v.reset(OpAMD64CMPQconst)
  9013  		v.AuxInt = c
  9014  		v.AddArg(x)
  9015  		return true
  9016  	}
  9017  	// match: (CMPQ (MOVQconst [c]) x)
  9018  	// cond: is32Bit(c)
  9019  	// result: (InvertFlags (CMPQconst x [c]))
  9020  	for {
  9021  		x := v.Args[1]
  9022  		v_0 := v.Args[0]
  9023  		if v_0.Op != OpAMD64MOVQconst {
  9024  			break
  9025  		}
  9026  		c := v_0.AuxInt
  9027  		if !(is32Bit(c)) {
  9028  			break
  9029  		}
  9030  		v.reset(OpAMD64InvertFlags)
  9031  		v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
  9032  		v0.AuxInt = c
  9033  		v0.AddArg(x)
  9034  		v.AddArg(v0)
  9035  		return true
  9036  	}
  9037  	// match: (CMPQ l:(MOVQload {sym} [off] ptr mem) x)
  9038  	// cond: canMergeLoad(v, l) && clobber(l)
  9039  	// result: (CMPQload {sym} [off] ptr x mem)
  9040  	for {
  9041  		x := v.Args[1]
  9042  		l := v.Args[0]
  9043  		if l.Op != OpAMD64MOVQload {
  9044  			break
  9045  		}
  9046  		off := l.AuxInt
  9047  		sym := l.Aux
  9048  		mem := l.Args[1]
  9049  		ptr := l.Args[0]
  9050  		if !(canMergeLoad(v, l) && clobber(l)) {
  9051  			break
  9052  		}
  9053  		v.reset(OpAMD64CMPQload)
  9054  		v.AuxInt = off
  9055  		v.Aux = sym
  9056  		v.AddArg(ptr)
  9057  		v.AddArg(x)
  9058  		v.AddArg(mem)
  9059  		return true
  9060  	}
  9061  	// match: (CMPQ x l:(MOVQload {sym} [off] ptr mem))
  9062  	// cond: canMergeLoad(v, l) && clobber(l)
  9063  	// result: (InvertFlags (CMPQload {sym} [off] ptr x mem))
  9064  	for {
  9065  		_ = v.Args[1]
  9066  		x := v.Args[0]
  9067  		l := v.Args[1]
  9068  		if l.Op != OpAMD64MOVQload {
  9069  			break
  9070  		}
  9071  		off := l.AuxInt
  9072  		sym := l.Aux
  9073  		mem := l.Args[1]
  9074  		ptr := l.Args[0]
  9075  		if !(canMergeLoad(v, l) && clobber(l)) {
  9076  			break
  9077  		}
  9078  		v.reset(OpAMD64InvertFlags)
  9079  		v0 := b.NewValue0(l.Pos, OpAMD64CMPQload, types.TypeFlags)
  9080  		v0.AuxInt = off
  9081  		v0.Aux = sym
  9082  		v0.AddArg(ptr)
  9083  		v0.AddArg(x)
  9084  		v0.AddArg(mem)
  9085  		v.AddArg(v0)
  9086  		return true
  9087  	}
  9088  	return false
  9089  }
  9090  func rewriteValueAMD64_OpAMD64CMPQconst_0(v *Value) bool {
  9091  	// match: (CMPQconst (NEGQ (ADDQconst [-16] (ANDQconst [15] _))) [32])
  9092  	// result: (FlagLT_ULT)
  9093  	for {
  9094  		if v.AuxInt != 32 {
  9095  			break
  9096  		}
  9097  		v_0 := v.Args[0]
  9098  		if v_0.Op != OpAMD64NEGQ {
  9099  			break
  9100  		}
  9101  		v_0_0 := v_0.Args[0]
  9102  		if v_0_0.Op != OpAMD64ADDQconst || v_0_0.AuxInt != -16 {
  9103  			break
  9104  		}
  9105  		v_0_0_0 := v_0_0.Args[0]
  9106  		if v_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0.AuxInt != 15 {
  9107  			break
  9108  		}
  9109  		v.reset(OpAMD64FlagLT_ULT)
  9110  		return true
  9111  	}
  9112  	// match: (CMPQconst (NEGQ (ADDQconst [ -8] (ANDQconst [7] _))) [32])
  9113  	// result: (FlagLT_ULT)
  9114  	for {
  9115  		if v.AuxInt != 32 {
  9116  			break
  9117  		}
  9118  		v_0 := v.Args[0]
  9119  		if v_0.Op != OpAMD64NEGQ {
  9120  			break
  9121  		}
  9122  		v_0_0 := v_0.Args[0]
  9123  		if v_0_0.Op != OpAMD64ADDQconst || v_0_0.AuxInt != -8 {
  9124  			break
  9125  		}
  9126  		v_0_0_0 := v_0_0.Args[0]
  9127  		if v_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0.AuxInt != 7 {
  9128  			break
  9129  		}
  9130  		v.reset(OpAMD64FlagLT_ULT)
  9131  		return true
  9132  	}
  9133  	// match: (CMPQconst (MOVQconst [x]) [y])
  9134  	// cond: x==y
  9135  	// result: (FlagEQ)
  9136  	for {
  9137  		y := v.AuxInt
  9138  		v_0 := v.Args[0]
  9139  		if v_0.Op != OpAMD64MOVQconst {
  9140  			break
  9141  		}
  9142  		x := v_0.AuxInt
  9143  		if !(x == y) {
  9144  			break
  9145  		}
  9146  		v.reset(OpAMD64FlagEQ)
  9147  		return true
  9148  	}
  9149  	// match: (CMPQconst (MOVQconst [x]) [y])
  9150  	// cond: x<y && uint64(x)<uint64(y)
  9151  	// result: (FlagLT_ULT)
  9152  	for {
  9153  		y := v.AuxInt
  9154  		v_0 := v.Args[0]
  9155  		if v_0.Op != OpAMD64MOVQconst {
  9156  			break
  9157  		}
  9158  		x := v_0.AuxInt
  9159  		if !(x < y && uint64(x) < uint64(y)) {
  9160  			break
  9161  		}
  9162  		v.reset(OpAMD64FlagLT_ULT)
  9163  		return true
  9164  	}
  9165  	// match: (CMPQconst (MOVQconst [x]) [y])
  9166  	// cond: x<y && uint64(x)>uint64(y)
  9167  	// result: (FlagLT_UGT)
  9168  	for {
  9169  		y := v.AuxInt
  9170  		v_0 := v.Args[0]
  9171  		if v_0.Op != OpAMD64MOVQconst {
  9172  			break
  9173  		}
  9174  		x := v_0.AuxInt
  9175  		if !(x < y && uint64(x) > uint64(y)) {
  9176  			break
  9177  		}
  9178  		v.reset(OpAMD64FlagLT_UGT)
  9179  		return true
  9180  	}
  9181  	// match: (CMPQconst (MOVQconst [x]) [y])
  9182  	// cond: x>y && uint64(x)<uint64(y)
  9183  	// result: (FlagGT_ULT)
  9184  	for {
  9185  		y := v.AuxInt
  9186  		v_0 := v.Args[0]
  9187  		if v_0.Op != OpAMD64MOVQconst {
  9188  			break
  9189  		}
  9190  		x := v_0.AuxInt
  9191  		if !(x > y && uint64(x) < uint64(y)) {
  9192  			break
  9193  		}
  9194  		v.reset(OpAMD64FlagGT_ULT)
  9195  		return true
  9196  	}
  9197  	// match: (CMPQconst (MOVQconst [x]) [y])
  9198  	// cond: x>y && uint64(x)>uint64(y)
  9199  	// result: (FlagGT_UGT)
  9200  	for {
  9201  		y := v.AuxInt
  9202  		v_0 := v.Args[0]
  9203  		if v_0.Op != OpAMD64MOVQconst {
  9204  			break
  9205  		}
  9206  		x := v_0.AuxInt
  9207  		if !(x > y && uint64(x) > uint64(y)) {
  9208  			break
  9209  		}
  9210  		v.reset(OpAMD64FlagGT_UGT)
  9211  		return true
  9212  	}
  9213  	// match: (CMPQconst (MOVBQZX _) [c])
  9214  	// cond: 0xFF < c
  9215  	// result: (FlagLT_ULT)
  9216  	for {
  9217  		c := v.AuxInt
  9218  		v_0 := v.Args[0]
  9219  		if v_0.Op != OpAMD64MOVBQZX || !(0xFF < c) {
  9220  			break
  9221  		}
  9222  		v.reset(OpAMD64FlagLT_ULT)
  9223  		return true
  9224  	}
  9225  	// match: (CMPQconst (MOVWQZX _) [c])
  9226  	// cond: 0xFFFF < c
  9227  	// result: (FlagLT_ULT)
  9228  	for {
  9229  		c := v.AuxInt
  9230  		v_0 := v.Args[0]
  9231  		if v_0.Op != OpAMD64MOVWQZX || !(0xFFFF < c) {
  9232  			break
  9233  		}
  9234  		v.reset(OpAMD64FlagLT_ULT)
  9235  		return true
  9236  	}
  9237  	// match: (CMPQconst (MOVLQZX _) [c])
  9238  	// cond: 0xFFFFFFFF < c
  9239  	// result: (FlagLT_ULT)
  9240  	for {
  9241  		c := v.AuxInt
  9242  		v_0 := v.Args[0]
  9243  		if v_0.Op != OpAMD64MOVLQZX || !(0xFFFFFFFF < c) {
  9244  			break
  9245  		}
  9246  		v.reset(OpAMD64FlagLT_ULT)
  9247  		return true
  9248  	}
  9249  	return false
  9250  }
  9251  func rewriteValueAMD64_OpAMD64CMPQconst_10(v *Value) bool {
  9252  	b := v.Block
  9253  	// match: (CMPQconst (SHRQconst _ [c]) [n])
  9254  	// cond: 0 <= n && 0 < c && c <= 64 && (1<<uint64(64-c)) <= uint64(n)
  9255  	// result: (FlagLT_ULT)
  9256  	for {
  9257  		n := v.AuxInt
  9258  		v_0 := v.Args[0]
  9259  		if v_0.Op != OpAMD64SHRQconst {
  9260  			break
  9261  		}
  9262  		c := v_0.AuxInt
  9263  		if !(0 <= n && 0 < c && c <= 64 && (1<<uint64(64-c)) <= uint64(n)) {
  9264  			break
  9265  		}
  9266  		v.reset(OpAMD64FlagLT_ULT)
  9267  		return true
  9268  	}
  9269  	// match: (CMPQconst (ANDQconst _ [m]) [n])
  9270  	// cond: 0 <= m && m < n
  9271  	// result: (FlagLT_ULT)
  9272  	for {
  9273  		n := v.AuxInt
  9274  		v_0 := v.Args[0]
  9275  		if v_0.Op != OpAMD64ANDQconst {
  9276  			break
  9277  		}
  9278  		m := v_0.AuxInt
  9279  		if !(0 <= m && m < n) {
  9280  			break
  9281  		}
  9282  		v.reset(OpAMD64FlagLT_ULT)
  9283  		return true
  9284  	}
  9285  	// match: (CMPQconst (ANDLconst _ [m]) [n])
  9286  	// cond: 0 <= m && m < n
  9287  	// result: (FlagLT_ULT)
  9288  	for {
  9289  		n := v.AuxInt
  9290  		v_0 := v.Args[0]
  9291  		if v_0.Op != OpAMD64ANDLconst {
  9292  			break
  9293  		}
  9294  		m := v_0.AuxInt
  9295  		if !(0 <= m && m < n) {
  9296  			break
  9297  		}
  9298  		v.reset(OpAMD64FlagLT_ULT)
  9299  		return true
  9300  	}
  9301  	// match: (CMPQconst (ANDQ x y) [0])
  9302  	// result: (TESTQ x y)
  9303  	for {
  9304  		if v.AuxInt != 0 {
  9305  			break
  9306  		}
  9307  		v_0 := v.Args[0]
  9308  		if v_0.Op != OpAMD64ANDQ {
  9309  			break
  9310  		}
  9311  		y := v_0.Args[1]
  9312  		x := v_0.Args[0]
  9313  		v.reset(OpAMD64TESTQ)
  9314  		v.AddArg(x)
  9315  		v.AddArg(y)
  9316  		return true
  9317  	}
  9318  	// match: (CMPQconst (ANDQconst [c] x) [0])
  9319  	// result: (TESTQconst [c] x)
  9320  	for {
  9321  		if v.AuxInt != 0 {
  9322  			break
  9323  		}
  9324  		v_0 := v.Args[0]
  9325  		if v_0.Op != OpAMD64ANDQconst {
  9326  			break
  9327  		}
  9328  		c := v_0.AuxInt
  9329  		x := v_0.Args[0]
  9330  		v.reset(OpAMD64TESTQconst)
  9331  		v.AuxInt = c
  9332  		v.AddArg(x)
  9333  		return true
  9334  	}
  9335  	// match: (CMPQconst x [0])
  9336  	// result: (TESTQ x x)
  9337  	for {
  9338  		if v.AuxInt != 0 {
  9339  			break
  9340  		}
  9341  		x := v.Args[0]
  9342  		v.reset(OpAMD64TESTQ)
  9343  		v.AddArg(x)
  9344  		v.AddArg(x)
  9345  		return true
  9346  	}
  9347  	// match: (CMPQconst l:(MOVQload {sym} [off] ptr mem) [c])
  9348  	// cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l)
  9349  	// result: @l.Block (CMPQconstload {sym} [makeValAndOff(c,off)] ptr mem)
  9350  	for {
  9351  		c := v.AuxInt
  9352  		l := v.Args[0]
  9353  		if l.Op != OpAMD64MOVQload {
  9354  			break
  9355  		}
  9356  		off := l.AuxInt
  9357  		sym := l.Aux
  9358  		mem := l.Args[1]
  9359  		ptr := l.Args[0]
  9360  		if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) {
  9361  			break
  9362  		}
  9363  		b = l.Block
  9364  		v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags)
  9365  		v.reset(OpCopy)
  9366  		v.AddArg(v0)
  9367  		v0.AuxInt = makeValAndOff(c, off)
  9368  		v0.Aux = sym
  9369  		v0.AddArg(ptr)
  9370  		v0.AddArg(mem)
  9371  		return true
  9372  	}
  9373  	return false
  9374  }
  9375  func rewriteValueAMD64_OpAMD64CMPQconstload_0(v *Value) bool {
  9376  	// match: (CMPQconstload [valoff1] {sym} (ADDQconst [off2] base) mem)
  9377  	// cond: ValAndOff(valoff1).canAdd(off2)
  9378  	// result: (CMPQconstload [ValAndOff(valoff1).add(off2)] {sym} base mem)
  9379  	for {
  9380  		valoff1 := v.AuxInt
  9381  		sym := v.Aux
  9382  		mem := v.Args[1]
  9383  		v_0 := v.Args[0]
  9384  		if v_0.Op != OpAMD64ADDQconst {
  9385  			break
  9386  		}
  9387  		off2 := v_0.AuxInt
  9388  		base := v_0.Args[0]
  9389  		if !(ValAndOff(valoff1).canAdd(off2)) {
  9390  			break
  9391  		}
  9392  		v.reset(OpAMD64CMPQconstload)
  9393  		v.AuxInt = ValAndOff(valoff1).add(off2)
  9394  		v.Aux = sym
  9395  		v.AddArg(base)
  9396  		v.AddArg(mem)
  9397  		return true
  9398  	}
  9399  	// match: (CMPQconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  9400  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  9401  	// result: (CMPQconstload [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  9402  	for {
  9403  		valoff1 := v.AuxInt
  9404  		sym1 := v.Aux
  9405  		mem := v.Args[1]
  9406  		v_0 := v.Args[0]
  9407  		if v_0.Op != OpAMD64LEAQ {
  9408  			break
  9409  		}
  9410  		off2 := v_0.AuxInt
  9411  		sym2 := v_0.Aux
  9412  		base := v_0.Args[0]
  9413  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  9414  			break
  9415  		}
  9416  		v.reset(OpAMD64CMPQconstload)
  9417  		v.AuxInt = ValAndOff(valoff1).add(off2)
  9418  		v.Aux = mergeSym(sym1, sym2)
  9419  		v.AddArg(base)
  9420  		v.AddArg(mem)
  9421  		return true
  9422  	}
  9423  	return false
  9424  }
  9425  func rewriteValueAMD64_OpAMD64CMPQload_0(v *Value) bool {
  9426  	// match: (CMPQload [off1] {sym} (ADDQconst [off2] base) val mem)
  9427  	// cond: is32Bit(off1+off2)
  9428  	// result: (CMPQload [off1+off2] {sym} base val mem)
  9429  	for {
  9430  		off1 := v.AuxInt
  9431  		sym := v.Aux
  9432  		mem := v.Args[2]
  9433  		v_0 := v.Args[0]
  9434  		if v_0.Op != OpAMD64ADDQconst {
  9435  			break
  9436  		}
  9437  		off2 := v_0.AuxInt
  9438  		base := v_0.Args[0]
  9439  		val := v.Args[1]
  9440  		if !(is32Bit(off1 + off2)) {
  9441  			break
  9442  		}
  9443  		v.reset(OpAMD64CMPQload)
  9444  		v.AuxInt = off1 + off2
  9445  		v.Aux = sym
  9446  		v.AddArg(base)
  9447  		v.AddArg(val)
  9448  		v.AddArg(mem)
  9449  		return true
  9450  	}
  9451  	// match: (CMPQload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  9452  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  9453  	// result: (CMPQload [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  9454  	for {
  9455  		off1 := v.AuxInt
  9456  		sym1 := v.Aux
  9457  		mem := v.Args[2]
  9458  		v_0 := v.Args[0]
  9459  		if v_0.Op != OpAMD64LEAQ {
  9460  			break
  9461  		}
  9462  		off2 := v_0.AuxInt
  9463  		sym2 := v_0.Aux
  9464  		base := v_0.Args[0]
  9465  		val := v.Args[1]
  9466  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  9467  			break
  9468  		}
  9469  		v.reset(OpAMD64CMPQload)
  9470  		v.AuxInt = off1 + off2
  9471  		v.Aux = mergeSym(sym1, sym2)
  9472  		v.AddArg(base)
  9473  		v.AddArg(val)
  9474  		v.AddArg(mem)
  9475  		return true
  9476  	}
  9477  	// match: (CMPQload {sym} [off] ptr (MOVQconst [c]) mem)
  9478  	// cond: validValAndOff(c,off)
  9479  	// result: (CMPQconstload {sym} [makeValAndOff(c,off)] ptr mem)
  9480  	for {
  9481  		off := v.AuxInt
  9482  		sym := v.Aux
  9483  		mem := v.Args[2]
  9484  		ptr := v.Args[0]
  9485  		v_1 := v.Args[1]
  9486  		if v_1.Op != OpAMD64MOVQconst {
  9487  			break
  9488  		}
  9489  		c := v_1.AuxInt
  9490  		if !(validValAndOff(c, off)) {
  9491  			break
  9492  		}
  9493  		v.reset(OpAMD64CMPQconstload)
  9494  		v.AuxInt = makeValAndOff(c, off)
  9495  		v.Aux = sym
  9496  		v.AddArg(ptr)
  9497  		v.AddArg(mem)
  9498  		return true
  9499  	}
  9500  	return false
  9501  }
  9502  func rewriteValueAMD64_OpAMD64CMPW_0(v *Value) bool {
  9503  	b := v.Block
  9504  	// match: (CMPW x (MOVLconst [c]))
  9505  	// result: (CMPWconst x [int64(int16(c))])
  9506  	for {
  9507  		_ = v.Args[1]
  9508  		x := v.Args[0]
  9509  		v_1 := v.Args[1]
  9510  		if v_1.Op != OpAMD64MOVLconst {
  9511  			break
  9512  		}
  9513  		c := v_1.AuxInt
  9514  		v.reset(OpAMD64CMPWconst)
  9515  		v.AuxInt = int64(int16(c))
  9516  		v.AddArg(x)
  9517  		return true
  9518  	}
  9519  	// match: (CMPW (MOVLconst [c]) x)
  9520  	// result: (InvertFlags (CMPWconst x [int64(int16(c))]))
  9521  	for {
  9522  		x := v.Args[1]
  9523  		v_0 := v.Args[0]
  9524  		if v_0.Op != OpAMD64MOVLconst {
  9525  			break
  9526  		}
  9527  		c := v_0.AuxInt
  9528  		v.reset(OpAMD64InvertFlags)
  9529  		v0 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
  9530  		v0.AuxInt = int64(int16(c))
  9531  		v0.AddArg(x)
  9532  		v.AddArg(v0)
  9533  		return true
  9534  	}
  9535  	// match: (CMPW l:(MOVWload {sym} [off] ptr mem) x)
  9536  	// cond: canMergeLoad(v, l) && clobber(l)
  9537  	// result: (CMPWload {sym} [off] ptr x mem)
  9538  	for {
  9539  		x := v.Args[1]
  9540  		l := v.Args[0]
  9541  		if l.Op != OpAMD64MOVWload {
  9542  			break
  9543  		}
  9544  		off := l.AuxInt
  9545  		sym := l.Aux
  9546  		mem := l.Args[1]
  9547  		ptr := l.Args[0]
  9548  		if !(canMergeLoad(v, l) && clobber(l)) {
  9549  			break
  9550  		}
  9551  		v.reset(OpAMD64CMPWload)
  9552  		v.AuxInt = off
  9553  		v.Aux = sym
  9554  		v.AddArg(ptr)
  9555  		v.AddArg(x)
  9556  		v.AddArg(mem)
  9557  		return true
  9558  	}
  9559  	// match: (CMPW x l:(MOVWload {sym} [off] ptr mem))
  9560  	// cond: canMergeLoad(v, l) && clobber(l)
  9561  	// result: (InvertFlags (CMPWload {sym} [off] ptr x mem))
  9562  	for {
  9563  		_ = v.Args[1]
  9564  		x := v.Args[0]
  9565  		l := v.Args[1]
  9566  		if l.Op != OpAMD64MOVWload {
  9567  			break
  9568  		}
  9569  		off := l.AuxInt
  9570  		sym := l.Aux
  9571  		mem := l.Args[1]
  9572  		ptr := l.Args[0]
  9573  		if !(canMergeLoad(v, l) && clobber(l)) {
  9574  			break
  9575  		}
  9576  		v.reset(OpAMD64InvertFlags)
  9577  		v0 := b.NewValue0(l.Pos, OpAMD64CMPWload, types.TypeFlags)
  9578  		v0.AuxInt = off
  9579  		v0.Aux = sym
  9580  		v0.AddArg(ptr)
  9581  		v0.AddArg(x)
  9582  		v0.AddArg(mem)
  9583  		v.AddArg(v0)
  9584  		return true
  9585  	}
  9586  	return false
  9587  }
  9588  func rewriteValueAMD64_OpAMD64CMPWconst_0(v *Value) bool {
  9589  	b := v.Block
  9590  	// match: (CMPWconst (MOVLconst [x]) [y])
  9591  	// cond: int16(x)==int16(y)
  9592  	// result: (FlagEQ)
  9593  	for {
  9594  		y := v.AuxInt
  9595  		v_0 := v.Args[0]
  9596  		if v_0.Op != OpAMD64MOVLconst {
  9597  			break
  9598  		}
  9599  		x := v_0.AuxInt
  9600  		if !(int16(x) == int16(y)) {
  9601  			break
  9602  		}
  9603  		v.reset(OpAMD64FlagEQ)
  9604  		return true
  9605  	}
  9606  	// match: (CMPWconst (MOVLconst [x]) [y])
  9607  	// cond: int16(x)<int16(y) && uint16(x)<uint16(y)
  9608  	// result: (FlagLT_ULT)
  9609  	for {
  9610  		y := v.AuxInt
  9611  		v_0 := v.Args[0]
  9612  		if v_0.Op != OpAMD64MOVLconst {
  9613  			break
  9614  		}
  9615  		x := v_0.AuxInt
  9616  		if !(int16(x) < int16(y) && uint16(x) < uint16(y)) {
  9617  			break
  9618  		}
  9619  		v.reset(OpAMD64FlagLT_ULT)
  9620  		return true
  9621  	}
  9622  	// match: (CMPWconst (MOVLconst [x]) [y])
  9623  	// cond: int16(x)<int16(y) && uint16(x)>uint16(y)
  9624  	// result: (FlagLT_UGT)
  9625  	for {
  9626  		y := v.AuxInt
  9627  		v_0 := v.Args[0]
  9628  		if v_0.Op != OpAMD64MOVLconst {
  9629  			break
  9630  		}
  9631  		x := v_0.AuxInt
  9632  		if !(int16(x) < int16(y) && uint16(x) > uint16(y)) {
  9633  			break
  9634  		}
  9635  		v.reset(OpAMD64FlagLT_UGT)
  9636  		return true
  9637  	}
  9638  	// match: (CMPWconst (MOVLconst [x]) [y])
  9639  	// cond: int16(x)>int16(y) && uint16(x)<uint16(y)
  9640  	// result: (FlagGT_ULT)
  9641  	for {
  9642  		y := v.AuxInt
  9643  		v_0 := v.Args[0]
  9644  		if v_0.Op != OpAMD64MOVLconst {
  9645  			break
  9646  		}
  9647  		x := v_0.AuxInt
  9648  		if !(int16(x) > int16(y) && uint16(x) < uint16(y)) {
  9649  			break
  9650  		}
  9651  		v.reset(OpAMD64FlagGT_ULT)
  9652  		return true
  9653  	}
  9654  	// match: (CMPWconst (MOVLconst [x]) [y])
  9655  	// cond: int16(x)>int16(y) && uint16(x)>uint16(y)
  9656  	// result: (FlagGT_UGT)
  9657  	for {
  9658  		y := v.AuxInt
  9659  		v_0 := v.Args[0]
  9660  		if v_0.Op != OpAMD64MOVLconst {
  9661  			break
  9662  		}
  9663  		x := v_0.AuxInt
  9664  		if !(int16(x) > int16(y) && uint16(x) > uint16(y)) {
  9665  			break
  9666  		}
  9667  		v.reset(OpAMD64FlagGT_UGT)
  9668  		return true
  9669  	}
  9670  	// match: (CMPWconst (ANDLconst _ [m]) [n])
  9671  	// cond: 0 <= int16(m) && int16(m) < int16(n)
  9672  	// result: (FlagLT_ULT)
  9673  	for {
  9674  		n := v.AuxInt
  9675  		v_0 := v.Args[0]
  9676  		if v_0.Op != OpAMD64ANDLconst {
  9677  			break
  9678  		}
  9679  		m := v_0.AuxInt
  9680  		if !(0 <= int16(m) && int16(m) < int16(n)) {
  9681  			break
  9682  		}
  9683  		v.reset(OpAMD64FlagLT_ULT)
  9684  		return true
  9685  	}
  9686  	// match: (CMPWconst (ANDL x y) [0])
  9687  	// result: (TESTW x y)
  9688  	for {
  9689  		if v.AuxInt != 0 {
  9690  			break
  9691  		}
  9692  		v_0 := v.Args[0]
  9693  		if v_0.Op != OpAMD64ANDL {
  9694  			break
  9695  		}
  9696  		y := v_0.Args[1]
  9697  		x := v_0.Args[0]
  9698  		v.reset(OpAMD64TESTW)
  9699  		v.AddArg(x)
  9700  		v.AddArg(y)
  9701  		return true
  9702  	}
  9703  	// match: (CMPWconst (ANDLconst [c] x) [0])
  9704  	// result: (TESTWconst [int64(int16(c))] x)
  9705  	for {
  9706  		if v.AuxInt != 0 {
  9707  			break
  9708  		}
  9709  		v_0 := v.Args[0]
  9710  		if v_0.Op != OpAMD64ANDLconst {
  9711  			break
  9712  		}
  9713  		c := v_0.AuxInt
  9714  		x := v_0.Args[0]
  9715  		v.reset(OpAMD64TESTWconst)
  9716  		v.AuxInt = int64(int16(c))
  9717  		v.AddArg(x)
  9718  		return true
  9719  	}
  9720  	// match: (CMPWconst x [0])
  9721  	// result: (TESTW x x)
  9722  	for {
  9723  		if v.AuxInt != 0 {
  9724  			break
  9725  		}
  9726  		x := v.Args[0]
  9727  		v.reset(OpAMD64TESTW)
  9728  		v.AddArg(x)
  9729  		v.AddArg(x)
  9730  		return true
  9731  	}
  9732  	// match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c])
  9733  	// cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l)
  9734  	// result: @l.Block (CMPWconstload {sym} [makeValAndOff(c,off)] ptr mem)
  9735  	for {
  9736  		c := v.AuxInt
  9737  		l := v.Args[0]
  9738  		if l.Op != OpAMD64MOVWload {
  9739  			break
  9740  		}
  9741  		off := l.AuxInt
  9742  		sym := l.Aux
  9743  		mem := l.Args[1]
  9744  		ptr := l.Args[0]
  9745  		if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) {
  9746  			break
  9747  		}
  9748  		b = l.Block
  9749  		v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags)
  9750  		v.reset(OpCopy)
  9751  		v.AddArg(v0)
  9752  		v0.AuxInt = makeValAndOff(c, off)
  9753  		v0.Aux = sym
  9754  		v0.AddArg(ptr)
  9755  		v0.AddArg(mem)
  9756  		return true
  9757  	}
  9758  	return false
  9759  }
  9760  func rewriteValueAMD64_OpAMD64CMPWconstload_0(v *Value) bool {
  9761  	// match: (CMPWconstload [valoff1] {sym} (ADDQconst [off2] base) mem)
  9762  	// cond: ValAndOff(valoff1).canAdd(off2)
  9763  	// result: (CMPWconstload [ValAndOff(valoff1).add(off2)] {sym} base mem)
  9764  	for {
  9765  		valoff1 := v.AuxInt
  9766  		sym := v.Aux
  9767  		mem := v.Args[1]
  9768  		v_0 := v.Args[0]
  9769  		if v_0.Op != OpAMD64ADDQconst {
  9770  			break
  9771  		}
  9772  		off2 := v_0.AuxInt
  9773  		base := v_0.Args[0]
  9774  		if !(ValAndOff(valoff1).canAdd(off2)) {
  9775  			break
  9776  		}
  9777  		v.reset(OpAMD64CMPWconstload)
  9778  		v.AuxInt = ValAndOff(valoff1).add(off2)
  9779  		v.Aux = sym
  9780  		v.AddArg(base)
  9781  		v.AddArg(mem)
  9782  		return true
  9783  	}
  9784  	// match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  9785  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  9786  	// result: (CMPWconstload [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  9787  	for {
  9788  		valoff1 := v.AuxInt
  9789  		sym1 := v.Aux
  9790  		mem := v.Args[1]
  9791  		v_0 := v.Args[0]
  9792  		if v_0.Op != OpAMD64LEAQ {
  9793  			break
  9794  		}
  9795  		off2 := v_0.AuxInt
  9796  		sym2 := v_0.Aux
  9797  		base := v_0.Args[0]
  9798  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  9799  			break
  9800  		}
  9801  		v.reset(OpAMD64CMPWconstload)
  9802  		v.AuxInt = ValAndOff(valoff1).add(off2)
  9803  		v.Aux = mergeSym(sym1, sym2)
  9804  		v.AddArg(base)
  9805  		v.AddArg(mem)
  9806  		return true
  9807  	}
  9808  	return false
  9809  }
  9810  func rewriteValueAMD64_OpAMD64CMPWload_0(v *Value) bool {
  9811  	// match: (CMPWload [off1] {sym} (ADDQconst [off2] base) val mem)
  9812  	// cond: is32Bit(off1+off2)
  9813  	// result: (CMPWload [off1+off2] {sym} base val mem)
  9814  	for {
  9815  		off1 := v.AuxInt
  9816  		sym := v.Aux
  9817  		mem := v.Args[2]
  9818  		v_0 := v.Args[0]
  9819  		if v_0.Op != OpAMD64ADDQconst {
  9820  			break
  9821  		}
  9822  		off2 := v_0.AuxInt
  9823  		base := v_0.Args[0]
  9824  		val := v.Args[1]
  9825  		if !(is32Bit(off1 + off2)) {
  9826  			break
  9827  		}
  9828  		v.reset(OpAMD64CMPWload)
  9829  		v.AuxInt = off1 + off2
  9830  		v.Aux = sym
  9831  		v.AddArg(base)
  9832  		v.AddArg(val)
  9833  		v.AddArg(mem)
  9834  		return true
  9835  	}
  9836  	// match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  9837  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  9838  	// result: (CMPWload [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  9839  	for {
  9840  		off1 := v.AuxInt
  9841  		sym1 := v.Aux
  9842  		mem := v.Args[2]
  9843  		v_0 := v.Args[0]
  9844  		if v_0.Op != OpAMD64LEAQ {
  9845  			break
  9846  		}
  9847  		off2 := v_0.AuxInt
  9848  		sym2 := v_0.Aux
  9849  		base := v_0.Args[0]
  9850  		val := v.Args[1]
  9851  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  9852  			break
  9853  		}
  9854  		v.reset(OpAMD64CMPWload)
  9855  		v.AuxInt = off1 + off2
  9856  		v.Aux = mergeSym(sym1, sym2)
  9857  		v.AddArg(base)
  9858  		v.AddArg(val)
  9859  		v.AddArg(mem)
  9860  		return true
  9861  	}
  9862  	// match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem)
  9863  	// cond: validValAndOff(int64(int16(c)),off)
  9864  	// result: (CMPWconstload {sym} [makeValAndOff(int64(int16(c)),off)] ptr mem)
  9865  	for {
  9866  		off := v.AuxInt
  9867  		sym := v.Aux
  9868  		mem := v.Args[2]
  9869  		ptr := v.Args[0]
  9870  		v_1 := v.Args[1]
  9871  		if v_1.Op != OpAMD64MOVLconst {
  9872  			break
  9873  		}
  9874  		c := v_1.AuxInt
  9875  		if !(validValAndOff(int64(int16(c)), off)) {
  9876  			break
  9877  		}
  9878  		v.reset(OpAMD64CMPWconstload)
  9879  		v.AuxInt = makeValAndOff(int64(int16(c)), off)
  9880  		v.Aux = sym
  9881  		v.AddArg(ptr)
  9882  		v.AddArg(mem)
  9883  		return true
  9884  	}
  9885  	return false
  9886  }
  9887  func rewriteValueAMD64_OpAMD64CMPXCHGLlock_0(v *Value) bool {
  9888  	// match: (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem)
  9889  	// cond: is32Bit(off1+off2)
  9890  	// result: (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem)
  9891  	for {
  9892  		off1 := v.AuxInt
  9893  		sym := v.Aux
  9894  		mem := v.Args[3]
  9895  		v_0 := v.Args[0]
  9896  		if v_0.Op != OpAMD64ADDQconst {
  9897  			break
  9898  		}
  9899  		off2 := v_0.AuxInt
  9900  		ptr := v_0.Args[0]
  9901  		old := v.Args[1]
  9902  		new_ := v.Args[2]
  9903  		if !(is32Bit(off1 + off2)) {
  9904  			break
  9905  		}
  9906  		v.reset(OpAMD64CMPXCHGLlock)
  9907  		v.AuxInt = off1 + off2
  9908  		v.Aux = sym
  9909  		v.AddArg(ptr)
  9910  		v.AddArg(old)
  9911  		v.AddArg(new_)
  9912  		v.AddArg(mem)
  9913  		return true
  9914  	}
  9915  	return false
  9916  }
  9917  func rewriteValueAMD64_OpAMD64CMPXCHGQlock_0(v *Value) bool {
  9918  	// match: (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem)
  9919  	// cond: is32Bit(off1+off2)
  9920  	// result: (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem)
  9921  	for {
  9922  		off1 := v.AuxInt
  9923  		sym := v.Aux
  9924  		mem := v.Args[3]
  9925  		v_0 := v.Args[0]
  9926  		if v_0.Op != OpAMD64ADDQconst {
  9927  			break
  9928  		}
  9929  		off2 := v_0.AuxInt
  9930  		ptr := v_0.Args[0]
  9931  		old := v.Args[1]
  9932  		new_ := v.Args[2]
  9933  		if !(is32Bit(off1 + off2)) {
  9934  			break
  9935  		}
  9936  		v.reset(OpAMD64CMPXCHGQlock)
  9937  		v.AuxInt = off1 + off2
  9938  		v.Aux = sym
  9939  		v.AddArg(ptr)
  9940  		v.AddArg(old)
  9941  		v.AddArg(new_)
  9942  		v.AddArg(mem)
  9943  		return true
  9944  	}
  9945  	return false
  9946  }
  9947  func rewriteValueAMD64_OpAMD64DIVSD_0(v *Value) bool {
  9948  	// match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem))
  9949  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  9950  	// result: (DIVSDload x [off] {sym} ptr mem)
  9951  	for {
  9952  		_ = v.Args[1]
  9953  		x := v.Args[0]
  9954  		l := v.Args[1]
  9955  		if l.Op != OpAMD64MOVSDload {
  9956  			break
  9957  		}
  9958  		off := l.AuxInt
  9959  		sym := l.Aux
  9960  		mem := l.Args[1]
  9961  		ptr := l.Args[0]
  9962  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  9963  			break
  9964  		}
  9965  		v.reset(OpAMD64DIVSDload)
  9966  		v.AuxInt = off
  9967  		v.Aux = sym
  9968  		v.AddArg(x)
  9969  		v.AddArg(ptr)
  9970  		v.AddArg(mem)
  9971  		return true
  9972  	}
  9973  	return false
  9974  }
  9975  func rewriteValueAMD64_OpAMD64DIVSDload_0(v *Value) bool {
  9976  	// match: (DIVSDload [off1] {sym} val (ADDQconst [off2] base) mem)
  9977  	// cond: is32Bit(off1+off2)
  9978  	// result: (DIVSDload [off1+off2] {sym} val base mem)
  9979  	for {
  9980  		off1 := v.AuxInt
  9981  		sym := v.Aux
  9982  		mem := v.Args[2]
  9983  		val := v.Args[0]
  9984  		v_1 := v.Args[1]
  9985  		if v_1.Op != OpAMD64ADDQconst {
  9986  			break
  9987  		}
  9988  		off2 := v_1.AuxInt
  9989  		base := v_1.Args[0]
  9990  		if !(is32Bit(off1 + off2)) {
  9991  			break
  9992  		}
  9993  		v.reset(OpAMD64DIVSDload)
  9994  		v.AuxInt = off1 + off2
  9995  		v.Aux = sym
  9996  		v.AddArg(val)
  9997  		v.AddArg(base)
  9998  		v.AddArg(mem)
  9999  		return true
 10000  	}
 10001  	// match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
 10002  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10003  	// result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
 10004  	for {
 10005  		off1 := v.AuxInt
 10006  		sym1 := v.Aux
 10007  		mem := v.Args[2]
 10008  		val := v.Args[0]
 10009  		v_1 := v.Args[1]
 10010  		if v_1.Op != OpAMD64LEAQ {
 10011  			break
 10012  		}
 10013  		off2 := v_1.AuxInt
 10014  		sym2 := v_1.Aux
 10015  		base := v_1.Args[0]
 10016  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10017  			break
 10018  		}
 10019  		v.reset(OpAMD64DIVSDload)
 10020  		v.AuxInt = off1 + off2
 10021  		v.Aux = mergeSym(sym1, sym2)
 10022  		v.AddArg(val)
 10023  		v.AddArg(base)
 10024  		v.AddArg(mem)
 10025  		return true
 10026  	}
 10027  	return false
 10028  }
 10029  func rewriteValueAMD64_OpAMD64DIVSS_0(v *Value) bool {
 10030  	// match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem))
 10031  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
 10032  	// result: (DIVSSload x [off] {sym} ptr mem)
 10033  	for {
 10034  		_ = v.Args[1]
 10035  		x := v.Args[0]
 10036  		l := v.Args[1]
 10037  		if l.Op != OpAMD64MOVSSload {
 10038  			break
 10039  		}
 10040  		off := l.AuxInt
 10041  		sym := l.Aux
 10042  		mem := l.Args[1]
 10043  		ptr := l.Args[0]
 10044  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
 10045  			break
 10046  		}
 10047  		v.reset(OpAMD64DIVSSload)
 10048  		v.AuxInt = off
 10049  		v.Aux = sym
 10050  		v.AddArg(x)
 10051  		v.AddArg(ptr)
 10052  		v.AddArg(mem)
 10053  		return true
 10054  	}
 10055  	return false
 10056  }
 10057  func rewriteValueAMD64_OpAMD64DIVSSload_0(v *Value) bool {
 10058  	// match: (DIVSSload [off1] {sym} val (ADDQconst [off2] base) mem)
 10059  	// cond: is32Bit(off1+off2)
 10060  	// result: (DIVSSload [off1+off2] {sym} val base mem)
 10061  	for {
 10062  		off1 := v.AuxInt
 10063  		sym := v.Aux
 10064  		mem := v.Args[2]
 10065  		val := v.Args[0]
 10066  		v_1 := v.Args[1]
 10067  		if v_1.Op != OpAMD64ADDQconst {
 10068  			break
 10069  		}
 10070  		off2 := v_1.AuxInt
 10071  		base := v_1.Args[0]
 10072  		if !(is32Bit(off1 + off2)) {
 10073  			break
 10074  		}
 10075  		v.reset(OpAMD64DIVSSload)
 10076  		v.AuxInt = off1 + off2
 10077  		v.Aux = sym
 10078  		v.AddArg(val)
 10079  		v.AddArg(base)
 10080  		v.AddArg(mem)
 10081  		return true
 10082  	}
 10083  	// match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
 10084  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10085  	// result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
 10086  	for {
 10087  		off1 := v.AuxInt
 10088  		sym1 := v.Aux
 10089  		mem := v.Args[2]
 10090  		val := v.Args[0]
 10091  		v_1 := v.Args[1]
 10092  		if v_1.Op != OpAMD64LEAQ {
 10093  			break
 10094  		}
 10095  		off2 := v_1.AuxInt
 10096  		sym2 := v_1.Aux
 10097  		base := v_1.Args[0]
 10098  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10099  			break
 10100  		}
 10101  		v.reset(OpAMD64DIVSSload)
 10102  		v.AuxInt = off1 + off2
 10103  		v.Aux = mergeSym(sym1, sym2)
 10104  		v.AddArg(val)
 10105  		v.AddArg(base)
 10106  		v.AddArg(mem)
 10107  		return true
 10108  	}
 10109  	return false
 10110  }
 10111  func rewriteValueAMD64_OpAMD64HMULL_0(v *Value) bool {
 10112  	// match: (HMULL x y)
 10113  	// cond: !x.rematerializeable() && y.rematerializeable()
 10114  	// result: (HMULL y x)
 10115  	for {
 10116  		y := v.Args[1]
 10117  		x := v.Args[0]
 10118  		if !(!x.rematerializeable() && y.rematerializeable()) {
 10119  			break
 10120  		}
 10121  		v.reset(OpAMD64HMULL)
 10122  		v.AddArg(y)
 10123  		v.AddArg(x)
 10124  		return true
 10125  	}
 10126  	return false
 10127  }
 10128  func rewriteValueAMD64_OpAMD64HMULLU_0(v *Value) bool {
 10129  	// match: (HMULLU x y)
 10130  	// cond: !x.rematerializeable() && y.rematerializeable()
 10131  	// result: (HMULLU y x)
 10132  	for {
 10133  		y := v.Args[1]
 10134  		x := v.Args[0]
 10135  		if !(!x.rematerializeable() && y.rematerializeable()) {
 10136  			break
 10137  		}
 10138  		v.reset(OpAMD64HMULLU)
 10139  		v.AddArg(y)
 10140  		v.AddArg(x)
 10141  		return true
 10142  	}
 10143  	return false
 10144  }
 10145  func rewriteValueAMD64_OpAMD64HMULQ_0(v *Value) bool {
 10146  	// match: (HMULQ x y)
 10147  	// cond: !x.rematerializeable() && y.rematerializeable()
 10148  	// result: (HMULQ y x)
 10149  	for {
 10150  		y := v.Args[1]
 10151  		x := v.Args[0]
 10152  		if !(!x.rematerializeable() && y.rematerializeable()) {
 10153  			break
 10154  		}
 10155  		v.reset(OpAMD64HMULQ)
 10156  		v.AddArg(y)
 10157  		v.AddArg(x)
 10158  		return true
 10159  	}
 10160  	return false
 10161  }
 10162  func rewriteValueAMD64_OpAMD64HMULQU_0(v *Value) bool {
 10163  	// match: (HMULQU x y)
 10164  	// cond: !x.rematerializeable() && y.rematerializeable()
 10165  	// result: (HMULQU y x)
 10166  	for {
 10167  		y := v.Args[1]
 10168  		x := v.Args[0]
 10169  		if !(!x.rematerializeable() && y.rematerializeable()) {
 10170  			break
 10171  		}
 10172  		v.reset(OpAMD64HMULQU)
 10173  		v.AddArg(y)
 10174  		v.AddArg(x)
 10175  		return true
 10176  	}
 10177  	return false
 10178  }
 10179  func rewriteValueAMD64_OpAMD64LEAL_0(v *Value) bool {
 10180  	// match: (LEAL [c] {s} (ADDLconst [d] x))
 10181  	// cond: is32Bit(c+d)
 10182  	// result: (LEAL [c+d] {s} x)
 10183  	for {
 10184  		c := v.AuxInt
 10185  		s := v.Aux
 10186  		v_0 := v.Args[0]
 10187  		if v_0.Op != OpAMD64ADDLconst {
 10188  			break
 10189  		}
 10190  		d := v_0.AuxInt
 10191  		x := v_0.Args[0]
 10192  		if !(is32Bit(c + d)) {
 10193  			break
 10194  		}
 10195  		v.reset(OpAMD64LEAL)
 10196  		v.AuxInt = c + d
 10197  		v.Aux = s
 10198  		v.AddArg(x)
 10199  		return true
 10200  	}
 10201  	// match: (LEAL [c] {s} (ADDL x y))
 10202  	// cond: x.Op != OpSB && y.Op != OpSB
 10203  	// result: (LEAL1 [c] {s} x y)
 10204  	for {
 10205  		c := v.AuxInt
 10206  		s := v.Aux
 10207  		v_0 := v.Args[0]
 10208  		if v_0.Op != OpAMD64ADDL {
 10209  			break
 10210  		}
 10211  		y := v_0.Args[1]
 10212  		x := v_0.Args[0]
 10213  		if !(x.Op != OpSB && y.Op != OpSB) {
 10214  			break
 10215  		}
 10216  		v.reset(OpAMD64LEAL1)
 10217  		v.AuxInt = c
 10218  		v.Aux = s
 10219  		v.AddArg(x)
 10220  		v.AddArg(y)
 10221  		return true
 10222  	}
 10223  	return false
 10224  }
 10225  func rewriteValueAMD64_OpAMD64LEAL1_0(v *Value) bool {
 10226  	// match: (LEAL1 [c] {s} (ADDLconst [d] x) y)
 10227  	// cond: is32Bit(c+d) && x.Op != OpSB
 10228  	// result: (LEAL1 [c+d] {s} x y)
 10229  	for {
 10230  		c := v.AuxInt
 10231  		s := v.Aux
 10232  		y := v.Args[1]
 10233  		v_0 := v.Args[0]
 10234  		if v_0.Op != OpAMD64ADDLconst {
 10235  			break
 10236  		}
 10237  		d := v_0.AuxInt
 10238  		x := v_0.Args[0]
 10239  		if !(is32Bit(c+d) && x.Op != OpSB) {
 10240  			break
 10241  		}
 10242  		v.reset(OpAMD64LEAL1)
 10243  		v.AuxInt = c + d
 10244  		v.Aux = s
 10245  		v.AddArg(x)
 10246  		v.AddArg(y)
 10247  		return true
 10248  	}
 10249  	// match: (LEAL1 [c] {s} y (ADDLconst [d] x))
 10250  	// cond: is32Bit(c+d) && x.Op != OpSB
 10251  	// result: (LEAL1 [c+d] {s} x y)
 10252  	for {
 10253  		c := v.AuxInt
 10254  		s := v.Aux
 10255  		_ = v.Args[1]
 10256  		y := v.Args[0]
 10257  		v_1 := v.Args[1]
 10258  		if v_1.Op != OpAMD64ADDLconst {
 10259  			break
 10260  		}
 10261  		d := v_1.AuxInt
 10262  		x := v_1.Args[0]
 10263  		if !(is32Bit(c+d) && x.Op != OpSB) {
 10264  			break
 10265  		}
 10266  		v.reset(OpAMD64LEAL1)
 10267  		v.AuxInt = c + d
 10268  		v.Aux = s
 10269  		v.AddArg(x)
 10270  		v.AddArg(y)
 10271  		return true
 10272  	}
 10273  	// match: (LEAL1 [c] {s} x (SHLLconst [1] y))
 10274  	// result: (LEAL2 [c] {s} x y)
 10275  	for {
 10276  		c := v.AuxInt
 10277  		s := v.Aux
 10278  		_ = v.Args[1]
 10279  		x := v.Args[0]
 10280  		v_1 := v.Args[1]
 10281  		if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 {
 10282  			break
 10283  		}
 10284  		y := v_1.Args[0]
 10285  		v.reset(OpAMD64LEAL2)
 10286  		v.AuxInt = c
 10287  		v.Aux = s
 10288  		v.AddArg(x)
 10289  		v.AddArg(y)
 10290  		return true
 10291  	}
 10292  	// match: (LEAL1 [c] {s} (SHLLconst [1] y) x)
 10293  	// result: (LEAL2 [c] {s} x y)
 10294  	for {
 10295  		c := v.AuxInt
 10296  		s := v.Aux
 10297  		x := v.Args[1]
 10298  		v_0 := v.Args[0]
 10299  		if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 {
 10300  			break
 10301  		}
 10302  		y := v_0.Args[0]
 10303  		v.reset(OpAMD64LEAL2)
 10304  		v.AuxInt = c
 10305  		v.Aux = s
 10306  		v.AddArg(x)
 10307  		v.AddArg(y)
 10308  		return true
 10309  	}
 10310  	// match: (LEAL1 [c] {s} x (SHLLconst [2] y))
 10311  	// result: (LEAL4 [c] {s} x y)
 10312  	for {
 10313  		c := v.AuxInt
 10314  		s := v.Aux
 10315  		_ = v.Args[1]
 10316  		x := v.Args[0]
 10317  		v_1 := v.Args[1]
 10318  		if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 {
 10319  			break
 10320  		}
 10321  		y := v_1.Args[0]
 10322  		v.reset(OpAMD64LEAL4)
 10323  		v.AuxInt = c
 10324  		v.Aux = s
 10325  		v.AddArg(x)
 10326  		v.AddArg(y)
 10327  		return true
 10328  	}
 10329  	// match: (LEAL1 [c] {s} (SHLLconst [2] y) x)
 10330  	// result: (LEAL4 [c] {s} x y)
 10331  	for {
 10332  		c := v.AuxInt
 10333  		s := v.Aux
 10334  		x := v.Args[1]
 10335  		v_0 := v.Args[0]
 10336  		if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 2 {
 10337  			break
 10338  		}
 10339  		y := v_0.Args[0]
 10340  		v.reset(OpAMD64LEAL4)
 10341  		v.AuxInt = c
 10342  		v.Aux = s
 10343  		v.AddArg(x)
 10344  		v.AddArg(y)
 10345  		return true
 10346  	}
 10347  	// match: (LEAL1 [c] {s} x (SHLLconst [3] y))
 10348  	// result: (LEAL8 [c] {s} x y)
 10349  	for {
 10350  		c := v.AuxInt
 10351  		s := v.Aux
 10352  		_ = v.Args[1]
 10353  		x := v.Args[0]
 10354  		v_1 := v.Args[1]
 10355  		if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 {
 10356  			break
 10357  		}
 10358  		y := v_1.Args[0]
 10359  		v.reset(OpAMD64LEAL8)
 10360  		v.AuxInt = c
 10361  		v.Aux = s
 10362  		v.AddArg(x)
 10363  		v.AddArg(y)
 10364  		return true
 10365  	}
 10366  	// match: (LEAL1 [c] {s} (SHLLconst [3] y) x)
 10367  	// result: (LEAL8 [c] {s} x y)
 10368  	for {
 10369  		c := v.AuxInt
 10370  		s := v.Aux
 10371  		x := v.Args[1]
 10372  		v_0 := v.Args[0]
 10373  		if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 3 {
 10374  			break
 10375  		}
 10376  		y := v_0.Args[0]
 10377  		v.reset(OpAMD64LEAL8)
 10378  		v.AuxInt = c
 10379  		v.Aux = s
 10380  		v.AddArg(x)
 10381  		v.AddArg(y)
 10382  		return true
 10383  	}
 10384  	return false
 10385  }
 10386  func rewriteValueAMD64_OpAMD64LEAL2_0(v *Value) bool {
 10387  	// match: (LEAL2 [c] {s} (ADDLconst [d] x) y)
 10388  	// cond: is32Bit(c+d) && x.Op != OpSB
 10389  	// result: (LEAL2 [c+d] {s} x y)
 10390  	for {
 10391  		c := v.AuxInt
 10392  		s := v.Aux
 10393  		y := v.Args[1]
 10394  		v_0 := v.Args[0]
 10395  		if v_0.Op != OpAMD64ADDLconst {
 10396  			break
 10397  		}
 10398  		d := v_0.AuxInt
 10399  		x := v_0.Args[0]
 10400  		if !(is32Bit(c+d) && x.Op != OpSB) {
 10401  			break
 10402  		}
 10403  		v.reset(OpAMD64LEAL2)
 10404  		v.AuxInt = c + d
 10405  		v.Aux = s
 10406  		v.AddArg(x)
 10407  		v.AddArg(y)
 10408  		return true
 10409  	}
 10410  	// match: (LEAL2 [c] {s} x (ADDLconst [d] y))
 10411  	// cond: is32Bit(c+2*d) && y.Op != OpSB
 10412  	// result: (LEAL2 [c+2*d] {s} x y)
 10413  	for {
 10414  		c := v.AuxInt
 10415  		s := v.Aux
 10416  		_ = v.Args[1]
 10417  		x := v.Args[0]
 10418  		v_1 := v.Args[1]
 10419  		if v_1.Op != OpAMD64ADDLconst {
 10420  			break
 10421  		}
 10422  		d := v_1.AuxInt
 10423  		y := v_1.Args[0]
 10424  		if !(is32Bit(c+2*d) && y.Op != OpSB) {
 10425  			break
 10426  		}
 10427  		v.reset(OpAMD64LEAL2)
 10428  		v.AuxInt = c + 2*d
 10429  		v.Aux = s
 10430  		v.AddArg(x)
 10431  		v.AddArg(y)
 10432  		return true
 10433  	}
 10434  	// match: (LEAL2 [c] {s} x (SHLLconst [1] y))
 10435  	// result: (LEAL4 [c] {s} x y)
 10436  	for {
 10437  		c := v.AuxInt
 10438  		s := v.Aux
 10439  		_ = v.Args[1]
 10440  		x := v.Args[0]
 10441  		v_1 := v.Args[1]
 10442  		if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 {
 10443  			break
 10444  		}
 10445  		y := v_1.Args[0]
 10446  		v.reset(OpAMD64LEAL4)
 10447  		v.AuxInt = c
 10448  		v.Aux = s
 10449  		v.AddArg(x)
 10450  		v.AddArg(y)
 10451  		return true
 10452  	}
 10453  	// match: (LEAL2 [c] {s} x (SHLLconst [2] y))
 10454  	// result: (LEAL8 [c] {s} x y)
 10455  	for {
 10456  		c := v.AuxInt
 10457  		s := v.Aux
 10458  		_ = v.Args[1]
 10459  		x := v.Args[0]
 10460  		v_1 := v.Args[1]
 10461  		if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 {
 10462  			break
 10463  		}
 10464  		y := v_1.Args[0]
 10465  		v.reset(OpAMD64LEAL8)
 10466  		v.AuxInt = c
 10467  		v.Aux = s
 10468  		v.AddArg(x)
 10469  		v.AddArg(y)
 10470  		return true
 10471  	}
 10472  	return false
 10473  }
 10474  func rewriteValueAMD64_OpAMD64LEAL4_0(v *Value) bool {
 10475  	// match: (LEAL4 [c] {s} (ADDLconst [d] x) y)
 10476  	// cond: is32Bit(c+d) && x.Op != OpSB
 10477  	// result: (LEAL4 [c+d] {s} x y)
 10478  	for {
 10479  		c := v.AuxInt
 10480  		s := v.Aux
 10481  		y := v.Args[1]
 10482  		v_0 := v.Args[0]
 10483  		if v_0.Op != OpAMD64ADDLconst {
 10484  			break
 10485  		}
 10486  		d := v_0.AuxInt
 10487  		x := v_0.Args[0]
 10488  		if !(is32Bit(c+d) && x.Op != OpSB) {
 10489  			break
 10490  		}
 10491  		v.reset(OpAMD64LEAL4)
 10492  		v.AuxInt = c + d
 10493  		v.Aux = s
 10494  		v.AddArg(x)
 10495  		v.AddArg(y)
 10496  		return true
 10497  	}
 10498  	// match: (LEAL4 [c] {s} x (ADDLconst [d] y))
 10499  	// cond: is32Bit(c+4*d) && y.Op != OpSB
 10500  	// result: (LEAL4 [c+4*d] {s} x y)
 10501  	for {
 10502  		c := v.AuxInt
 10503  		s := v.Aux
 10504  		_ = v.Args[1]
 10505  		x := v.Args[0]
 10506  		v_1 := v.Args[1]
 10507  		if v_1.Op != OpAMD64ADDLconst {
 10508  			break
 10509  		}
 10510  		d := v_1.AuxInt
 10511  		y := v_1.Args[0]
 10512  		if !(is32Bit(c+4*d) && y.Op != OpSB) {
 10513  			break
 10514  		}
 10515  		v.reset(OpAMD64LEAL4)
 10516  		v.AuxInt = c + 4*d
 10517  		v.Aux = s
 10518  		v.AddArg(x)
 10519  		v.AddArg(y)
 10520  		return true
 10521  	}
 10522  	// match: (LEAL4 [c] {s} x (SHLLconst [1] y))
 10523  	// result: (LEAL8 [c] {s} x y)
 10524  	for {
 10525  		c := v.AuxInt
 10526  		s := v.Aux
 10527  		_ = v.Args[1]
 10528  		x := v.Args[0]
 10529  		v_1 := v.Args[1]
 10530  		if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 {
 10531  			break
 10532  		}
 10533  		y := v_1.Args[0]
 10534  		v.reset(OpAMD64LEAL8)
 10535  		v.AuxInt = c
 10536  		v.Aux = s
 10537  		v.AddArg(x)
 10538  		v.AddArg(y)
 10539  		return true
 10540  	}
 10541  	return false
 10542  }
 10543  func rewriteValueAMD64_OpAMD64LEAL8_0(v *Value) bool {
 10544  	// match: (LEAL8 [c] {s} (ADDLconst [d] x) y)
 10545  	// cond: is32Bit(c+d) && x.Op != OpSB
 10546  	// result: (LEAL8 [c+d] {s} x y)
 10547  	for {
 10548  		c := v.AuxInt
 10549  		s := v.Aux
 10550  		y := v.Args[1]
 10551  		v_0 := v.Args[0]
 10552  		if v_0.Op != OpAMD64ADDLconst {
 10553  			break
 10554  		}
 10555  		d := v_0.AuxInt
 10556  		x := v_0.Args[0]
 10557  		if !(is32Bit(c+d) && x.Op != OpSB) {
 10558  			break
 10559  		}
 10560  		v.reset(OpAMD64LEAL8)
 10561  		v.AuxInt = c + d
 10562  		v.Aux = s
 10563  		v.AddArg(x)
 10564  		v.AddArg(y)
 10565  		return true
 10566  	}
 10567  	// match: (LEAL8 [c] {s} x (ADDLconst [d] y))
 10568  	// cond: is32Bit(c+8*d) && y.Op != OpSB
 10569  	// result: (LEAL8 [c+8*d] {s} x y)
 10570  	for {
 10571  		c := v.AuxInt
 10572  		s := v.Aux
 10573  		_ = v.Args[1]
 10574  		x := v.Args[0]
 10575  		v_1 := v.Args[1]
 10576  		if v_1.Op != OpAMD64ADDLconst {
 10577  			break
 10578  		}
 10579  		d := v_1.AuxInt
 10580  		y := v_1.Args[0]
 10581  		if !(is32Bit(c+8*d) && y.Op != OpSB) {
 10582  			break
 10583  		}
 10584  		v.reset(OpAMD64LEAL8)
 10585  		v.AuxInt = c + 8*d
 10586  		v.Aux = s
 10587  		v.AddArg(x)
 10588  		v.AddArg(y)
 10589  		return true
 10590  	}
 10591  	return false
 10592  }
 10593  func rewriteValueAMD64_OpAMD64LEAQ_0(v *Value) bool {
 10594  	// match: (LEAQ [c] {s} (ADDQconst [d] x))
 10595  	// cond: is32Bit(c+d)
 10596  	// result: (LEAQ [c+d] {s} x)
 10597  	for {
 10598  		c := v.AuxInt
 10599  		s := v.Aux
 10600  		v_0 := v.Args[0]
 10601  		if v_0.Op != OpAMD64ADDQconst {
 10602  			break
 10603  		}
 10604  		d := v_0.AuxInt
 10605  		x := v_0.Args[0]
 10606  		if !(is32Bit(c + d)) {
 10607  			break
 10608  		}
 10609  		v.reset(OpAMD64LEAQ)
 10610  		v.AuxInt = c + d
 10611  		v.Aux = s
 10612  		v.AddArg(x)
 10613  		return true
 10614  	}
 10615  	// match: (LEAQ [c] {s} (ADDQ x y))
 10616  	// cond: x.Op != OpSB && y.Op != OpSB
 10617  	// result: (LEAQ1 [c] {s} x y)
 10618  	for {
 10619  		c := v.AuxInt
 10620  		s := v.Aux
 10621  		v_0 := v.Args[0]
 10622  		if v_0.Op != OpAMD64ADDQ {
 10623  			break
 10624  		}
 10625  		y := v_0.Args[1]
 10626  		x := v_0.Args[0]
 10627  		if !(x.Op != OpSB && y.Op != OpSB) {
 10628  			break
 10629  		}
 10630  		v.reset(OpAMD64LEAQ1)
 10631  		v.AuxInt = c
 10632  		v.Aux = s
 10633  		v.AddArg(x)
 10634  		v.AddArg(y)
 10635  		return true
 10636  	}
 10637  	// match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x))
 10638  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10639  	// result: (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x)
 10640  	for {
 10641  		off1 := v.AuxInt
 10642  		sym1 := v.Aux
 10643  		v_0 := v.Args[0]
 10644  		if v_0.Op != OpAMD64LEAQ {
 10645  			break
 10646  		}
 10647  		off2 := v_0.AuxInt
 10648  		sym2 := v_0.Aux
 10649  		x := v_0.Args[0]
 10650  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10651  			break
 10652  		}
 10653  		v.reset(OpAMD64LEAQ)
 10654  		v.AuxInt = off1 + off2
 10655  		v.Aux = mergeSym(sym1, sym2)
 10656  		v.AddArg(x)
 10657  		return true
 10658  	}
 10659  	// match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y))
 10660  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10661  	// result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y)
 10662  	for {
 10663  		off1 := v.AuxInt
 10664  		sym1 := v.Aux
 10665  		v_0 := v.Args[0]
 10666  		if v_0.Op != OpAMD64LEAQ1 {
 10667  			break
 10668  		}
 10669  		off2 := v_0.AuxInt
 10670  		sym2 := v_0.Aux
 10671  		y := v_0.Args[1]
 10672  		x := v_0.Args[0]
 10673  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10674  			break
 10675  		}
 10676  		v.reset(OpAMD64LEAQ1)
 10677  		v.AuxInt = off1 + off2
 10678  		v.Aux = mergeSym(sym1, sym2)
 10679  		v.AddArg(x)
 10680  		v.AddArg(y)
 10681  		return true
 10682  	}
 10683  	// match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y))
 10684  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10685  	// result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y)
 10686  	for {
 10687  		off1 := v.AuxInt
 10688  		sym1 := v.Aux
 10689  		v_0 := v.Args[0]
 10690  		if v_0.Op != OpAMD64LEAQ2 {
 10691  			break
 10692  		}
 10693  		off2 := v_0.AuxInt
 10694  		sym2 := v_0.Aux
 10695  		y := v_0.Args[1]
 10696  		x := v_0.Args[0]
 10697  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10698  			break
 10699  		}
 10700  		v.reset(OpAMD64LEAQ2)
 10701  		v.AuxInt = off1 + off2
 10702  		v.Aux = mergeSym(sym1, sym2)
 10703  		v.AddArg(x)
 10704  		v.AddArg(y)
 10705  		return true
 10706  	}
 10707  	// match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y))
 10708  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10709  	// result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y)
 10710  	for {
 10711  		off1 := v.AuxInt
 10712  		sym1 := v.Aux
 10713  		v_0 := v.Args[0]
 10714  		if v_0.Op != OpAMD64LEAQ4 {
 10715  			break
 10716  		}
 10717  		off2 := v_0.AuxInt
 10718  		sym2 := v_0.Aux
 10719  		y := v_0.Args[1]
 10720  		x := v_0.Args[0]
 10721  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10722  			break
 10723  		}
 10724  		v.reset(OpAMD64LEAQ4)
 10725  		v.AuxInt = off1 + off2
 10726  		v.Aux = mergeSym(sym1, sym2)
 10727  		v.AddArg(x)
 10728  		v.AddArg(y)
 10729  		return true
 10730  	}
 10731  	// match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y))
 10732  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10733  	// result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y)
 10734  	for {
 10735  		off1 := v.AuxInt
 10736  		sym1 := v.Aux
 10737  		v_0 := v.Args[0]
 10738  		if v_0.Op != OpAMD64LEAQ8 {
 10739  			break
 10740  		}
 10741  		off2 := v_0.AuxInt
 10742  		sym2 := v_0.Aux
 10743  		y := v_0.Args[1]
 10744  		x := v_0.Args[0]
 10745  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10746  			break
 10747  		}
 10748  		v.reset(OpAMD64LEAQ8)
 10749  		v.AuxInt = off1 + off2
 10750  		v.Aux = mergeSym(sym1, sym2)
 10751  		v.AddArg(x)
 10752  		v.AddArg(y)
 10753  		return true
 10754  	}
 10755  	return false
 10756  }
 10757  func rewriteValueAMD64_OpAMD64LEAQ1_0(v *Value) bool {
 10758  	// match: (LEAQ1 [c] {s} (ADDQconst [d] x) y)
 10759  	// cond: is32Bit(c+d) && x.Op != OpSB
 10760  	// result: (LEAQ1 [c+d] {s} x y)
 10761  	for {
 10762  		c := v.AuxInt
 10763  		s := v.Aux
 10764  		y := v.Args[1]
 10765  		v_0 := v.Args[0]
 10766  		if v_0.Op != OpAMD64ADDQconst {
 10767  			break
 10768  		}
 10769  		d := v_0.AuxInt
 10770  		x := v_0.Args[0]
 10771  		if !(is32Bit(c+d) && x.Op != OpSB) {
 10772  			break
 10773  		}
 10774  		v.reset(OpAMD64LEAQ1)
 10775  		v.AuxInt = c + d
 10776  		v.Aux = s
 10777  		v.AddArg(x)
 10778  		v.AddArg(y)
 10779  		return true
 10780  	}
 10781  	// match: (LEAQ1 [c] {s} y (ADDQconst [d] x))
 10782  	// cond: is32Bit(c+d) && x.Op != OpSB
 10783  	// result: (LEAQ1 [c+d] {s} x y)
 10784  	for {
 10785  		c := v.AuxInt
 10786  		s := v.Aux
 10787  		_ = v.Args[1]
 10788  		y := v.Args[0]
 10789  		v_1 := v.Args[1]
 10790  		if v_1.Op != OpAMD64ADDQconst {
 10791  			break
 10792  		}
 10793  		d := v_1.AuxInt
 10794  		x := v_1.Args[0]
 10795  		if !(is32Bit(c+d) && x.Op != OpSB) {
 10796  			break
 10797  		}
 10798  		v.reset(OpAMD64LEAQ1)
 10799  		v.AuxInt = c + d
 10800  		v.Aux = s
 10801  		v.AddArg(x)
 10802  		v.AddArg(y)
 10803  		return true
 10804  	}
 10805  	// match: (LEAQ1 [c] {s} x (SHLQconst [1] y))
 10806  	// result: (LEAQ2 [c] {s} x y)
 10807  	for {
 10808  		c := v.AuxInt
 10809  		s := v.Aux
 10810  		_ = v.Args[1]
 10811  		x := v.Args[0]
 10812  		v_1 := v.Args[1]
 10813  		if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 {
 10814  			break
 10815  		}
 10816  		y := v_1.Args[0]
 10817  		v.reset(OpAMD64LEAQ2)
 10818  		v.AuxInt = c
 10819  		v.Aux = s
 10820  		v.AddArg(x)
 10821  		v.AddArg(y)
 10822  		return true
 10823  	}
 10824  	// match: (LEAQ1 [c] {s} (SHLQconst [1] y) x)
 10825  	// result: (LEAQ2 [c] {s} x y)
 10826  	for {
 10827  		c := v.AuxInt
 10828  		s := v.Aux
 10829  		x := v.Args[1]
 10830  		v_0 := v.Args[0]
 10831  		if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 {
 10832  			break
 10833  		}
 10834  		y := v_0.Args[0]
 10835  		v.reset(OpAMD64LEAQ2)
 10836  		v.AuxInt = c
 10837  		v.Aux = s
 10838  		v.AddArg(x)
 10839  		v.AddArg(y)
 10840  		return true
 10841  	}
 10842  	// match: (LEAQ1 [c] {s} x (SHLQconst [2] y))
 10843  	// result: (LEAQ4 [c] {s} x y)
 10844  	for {
 10845  		c := v.AuxInt
 10846  		s := v.Aux
 10847  		_ = v.Args[1]
 10848  		x := v.Args[0]
 10849  		v_1 := v.Args[1]
 10850  		if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 {
 10851  			break
 10852  		}
 10853  		y := v_1.Args[0]
 10854  		v.reset(OpAMD64LEAQ4)
 10855  		v.AuxInt = c
 10856  		v.Aux = s
 10857  		v.AddArg(x)
 10858  		v.AddArg(y)
 10859  		return true
 10860  	}
 10861  	// match: (LEAQ1 [c] {s} (SHLQconst [2] y) x)
 10862  	// result: (LEAQ4 [c] {s} x y)
 10863  	for {
 10864  		c := v.AuxInt
 10865  		s := v.Aux
 10866  		x := v.Args[1]
 10867  		v_0 := v.Args[0]
 10868  		if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 2 {
 10869  			break
 10870  		}
 10871  		y := v_0.Args[0]
 10872  		v.reset(OpAMD64LEAQ4)
 10873  		v.AuxInt = c
 10874  		v.Aux = s
 10875  		v.AddArg(x)
 10876  		v.AddArg(y)
 10877  		return true
 10878  	}
 10879  	// match: (LEAQ1 [c] {s} x (SHLQconst [3] y))
 10880  	// result: (LEAQ8 [c] {s} x y)
 10881  	for {
 10882  		c := v.AuxInt
 10883  		s := v.Aux
 10884  		_ = v.Args[1]
 10885  		x := v.Args[0]
 10886  		v_1 := v.Args[1]
 10887  		if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 {
 10888  			break
 10889  		}
 10890  		y := v_1.Args[0]
 10891  		v.reset(OpAMD64LEAQ8)
 10892  		v.AuxInt = c
 10893  		v.Aux = s
 10894  		v.AddArg(x)
 10895  		v.AddArg(y)
 10896  		return true
 10897  	}
 10898  	// match: (LEAQ1 [c] {s} (SHLQconst [3] y) x)
 10899  	// result: (LEAQ8 [c] {s} x y)
 10900  	for {
 10901  		c := v.AuxInt
 10902  		s := v.Aux
 10903  		x := v.Args[1]
 10904  		v_0 := v.Args[0]
 10905  		if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 {
 10906  			break
 10907  		}
 10908  		y := v_0.Args[0]
 10909  		v.reset(OpAMD64LEAQ8)
 10910  		v.AuxInt = c
 10911  		v.Aux = s
 10912  		v.AddArg(x)
 10913  		v.AddArg(y)
 10914  		return true
 10915  	}
 10916  	// match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y)
 10917  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
 10918  	// result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y)
 10919  	for {
 10920  		off1 := v.AuxInt
 10921  		sym1 := v.Aux
 10922  		y := v.Args[1]
 10923  		v_0 := v.Args[0]
 10924  		if v_0.Op != OpAMD64LEAQ {
 10925  			break
 10926  		}
 10927  		off2 := v_0.AuxInt
 10928  		sym2 := v_0.Aux
 10929  		x := v_0.Args[0]
 10930  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
 10931  			break
 10932  		}
 10933  		v.reset(OpAMD64LEAQ1)
 10934  		v.AuxInt = off1 + off2
 10935  		v.Aux = mergeSym(sym1, sym2)
 10936  		v.AddArg(x)
 10937  		v.AddArg(y)
 10938  		return true
 10939  	}
 10940  	// match: (LEAQ1 [off1] {sym1} y (LEAQ [off2] {sym2} x))
 10941  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
 10942  	// result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y)
 10943  	for {
 10944  		off1 := v.AuxInt
 10945  		sym1 := v.Aux
 10946  		_ = v.Args[1]
 10947  		y := v.Args[0]
 10948  		v_1 := v.Args[1]
 10949  		if v_1.Op != OpAMD64LEAQ {
 10950  			break
 10951  		}
 10952  		off2 := v_1.AuxInt
 10953  		sym2 := v_1.Aux
 10954  		x := v_1.Args[0]
 10955  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
 10956  			break
 10957  		}
 10958  		v.reset(OpAMD64LEAQ1)
 10959  		v.AuxInt = off1 + off2
 10960  		v.Aux = mergeSym(sym1, sym2)
 10961  		v.AddArg(x)
 10962  		v.AddArg(y)
 10963  		return true
 10964  	}
 10965  	return false
 10966  }
 10967  func rewriteValueAMD64_OpAMD64LEAQ2_0(v *Value) bool {
 10968  	// match: (LEAQ2 [c] {s} (ADDQconst [d] x) y)
 10969  	// cond: is32Bit(c+d) && x.Op != OpSB
 10970  	// result: (LEAQ2 [c+d] {s} x y)
 10971  	for {
 10972  		c := v.AuxInt
 10973  		s := v.Aux
 10974  		y := v.Args[1]
 10975  		v_0 := v.Args[0]
 10976  		if v_0.Op != OpAMD64ADDQconst {
 10977  			break
 10978  		}
 10979  		d := v_0.AuxInt
 10980  		x := v_0.Args[0]
 10981  		if !(is32Bit(c+d) && x.Op != OpSB) {
 10982  			break
 10983  		}
 10984  		v.reset(OpAMD64LEAQ2)
 10985  		v.AuxInt = c + d
 10986  		v.Aux = s
 10987  		v.AddArg(x)
 10988  		v.AddArg(y)
 10989  		return true
 10990  	}
 10991  	// match: (LEAQ2 [c] {s} x (ADDQconst [d] y))
 10992  	// cond: is32Bit(c+2*d) && y.Op != OpSB
 10993  	// result: (LEAQ2 [c+2*d] {s} x y)
 10994  	for {
 10995  		c := v.AuxInt
 10996  		s := v.Aux
 10997  		_ = v.Args[1]
 10998  		x := v.Args[0]
 10999  		v_1 := v.Args[1]
 11000  		if v_1.Op != OpAMD64ADDQconst {
 11001  			break
 11002  		}
 11003  		d := v_1.AuxInt
 11004  		y := v_1.Args[0]
 11005  		if !(is32Bit(c+2*d) && y.Op != OpSB) {
 11006  			break
 11007  		}
 11008  		v.reset(OpAMD64LEAQ2)
 11009  		v.AuxInt = c + 2*d
 11010  		v.Aux = s
 11011  		v.AddArg(x)
 11012  		v.AddArg(y)
 11013  		return true
 11014  	}
 11015  	// match: (LEAQ2 [c] {s} x (SHLQconst [1] y))
 11016  	// result: (LEAQ4 [c] {s} x y)
 11017  	for {
 11018  		c := v.AuxInt
 11019  		s := v.Aux
 11020  		_ = v.Args[1]
 11021  		x := v.Args[0]
 11022  		v_1 := v.Args[1]
 11023  		if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 {
 11024  			break
 11025  		}
 11026  		y := v_1.Args[0]
 11027  		v.reset(OpAMD64LEAQ4)
 11028  		v.AuxInt = c
 11029  		v.Aux = s
 11030  		v.AddArg(x)
 11031  		v.AddArg(y)
 11032  		return true
 11033  	}
 11034  	// match: (LEAQ2 [c] {s} x (SHLQconst [2] y))
 11035  	// result: (LEAQ8 [c] {s} x y)
 11036  	for {
 11037  		c := v.AuxInt
 11038  		s := v.Aux
 11039  		_ = v.Args[1]
 11040  		x := v.Args[0]
 11041  		v_1 := v.Args[1]
 11042  		if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 {
 11043  			break
 11044  		}
 11045  		y := v_1.Args[0]
 11046  		v.reset(OpAMD64LEAQ8)
 11047  		v.AuxInt = c
 11048  		v.Aux = s
 11049  		v.AddArg(x)
 11050  		v.AddArg(y)
 11051  		return true
 11052  	}
 11053  	// match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y)
 11054  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
 11055  	// result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y)
 11056  	for {
 11057  		off1 := v.AuxInt
 11058  		sym1 := v.Aux
 11059  		y := v.Args[1]
 11060  		v_0 := v.Args[0]
 11061  		if v_0.Op != OpAMD64LEAQ {
 11062  			break
 11063  		}
 11064  		off2 := v_0.AuxInt
 11065  		sym2 := v_0.Aux
 11066  		x := v_0.Args[0]
 11067  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
 11068  			break
 11069  		}
 11070  		v.reset(OpAMD64LEAQ2)
 11071  		v.AuxInt = off1 + off2
 11072  		v.Aux = mergeSym(sym1, sym2)
 11073  		v.AddArg(x)
 11074  		v.AddArg(y)
 11075  		return true
 11076  	}
 11077  	return false
 11078  }
 11079  func rewriteValueAMD64_OpAMD64LEAQ4_0(v *Value) bool {
 11080  	// match: (LEAQ4 [c] {s} (ADDQconst [d] x) y)
 11081  	// cond: is32Bit(c+d) && x.Op != OpSB
 11082  	// result: (LEAQ4 [c+d] {s} x y)
 11083  	for {
 11084  		c := v.AuxInt
 11085  		s := v.Aux
 11086  		y := v.Args[1]
 11087  		v_0 := v.Args[0]
 11088  		if v_0.Op != OpAMD64ADDQconst {
 11089  			break
 11090  		}
 11091  		d := v_0.AuxInt
 11092  		x := v_0.Args[0]
 11093  		if !(is32Bit(c+d) && x.Op != OpSB) {
 11094  			break
 11095  		}
 11096  		v.reset(OpAMD64LEAQ4)
 11097  		v.AuxInt = c + d
 11098  		v.Aux = s
 11099  		v.AddArg(x)
 11100  		v.AddArg(y)
 11101  		return true
 11102  	}
 11103  	// match: (LEAQ4 [c] {s} x (ADDQconst [d] y))
 11104  	// cond: is32Bit(c+4*d) && y.Op != OpSB
 11105  	// result: (LEAQ4 [c+4*d] {s} x y)
 11106  	for {
 11107  		c := v.AuxInt
 11108  		s := v.Aux
 11109  		_ = v.Args[1]
 11110  		x := v.Args[0]
 11111  		v_1 := v.Args[1]
 11112  		if v_1.Op != OpAMD64ADDQconst {
 11113  			break
 11114  		}
 11115  		d := v_1.AuxInt
 11116  		y := v_1.Args[0]
 11117  		if !(is32Bit(c+4*d) && y.Op != OpSB) {
 11118  			break
 11119  		}
 11120  		v.reset(OpAMD64LEAQ4)
 11121  		v.AuxInt = c + 4*d
 11122  		v.Aux = s
 11123  		v.AddArg(x)
 11124  		v.AddArg(y)
 11125  		return true
 11126  	}
 11127  	// match: (LEAQ4 [c] {s} x (SHLQconst [1] y))
 11128  	// result: (LEAQ8 [c] {s} x y)
 11129  	for {
 11130  		c := v.AuxInt
 11131  		s := v.Aux
 11132  		_ = v.Args[1]
 11133  		x := v.Args[0]
 11134  		v_1 := v.Args[1]
 11135  		if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 {
 11136  			break
 11137  		}
 11138  		y := v_1.Args[0]
 11139  		v.reset(OpAMD64LEAQ8)
 11140  		v.AuxInt = c
 11141  		v.Aux = s
 11142  		v.AddArg(x)
 11143  		v.AddArg(y)
 11144  		return true
 11145  	}
 11146  	// match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y)
 11147  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
 11148  	// result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y)
 11149  	for {
 11150  		off1 := v.AuxInt
 11151  		sym1 := v.Aux
 11152  		y := v.Args[1]
 11153  		v_0 := v.Args[0]
 11154  		if v_0.Op != OpAMD64LEAQ {
 11155  			break
 11156  		}
 11157  		off2 := v_0.AuxInt
 11158  		sym2 := v_0.Aux
 11159  		x := v_0.Args[0]
 11160  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
 11161  			break
 11162  		}
 11163  		v.reset(OpAMD64LEAQ4)
 11164  		v.AuxInt = off1 + off2
 11165  		v.Aux = mergeSym(sym1, sym2)
 11166  		v.AddArg(x)
 11167  		v.AddArg(y)
 11168  		return true
 11169  	}
 11170  	return false
 11171  }
 11172  func rewriteValueAMD64_OpAMD64LEAQ8_0(v *Value) bool {
 11173  	// match: (LEAQ8 [c] {s} (ADDQconst [d] x) y)
 11174  	// cond: is32Bit(c+d) && x.Op != OpSB
 11175  	// result: (LEAQ8 [c+d] {s} x y)
 11176  	for {
 11177  		c := v.AuxInt
 11178  		s := v.Aux
 11179  		y := v.Args[1]
 11180  		v_0 := v.Args[0]
 11181  		if v_0.Op != OpAMD64ADDQconst {
 11182  			break
 11183  		}
 11184  		d := v_0.AuxInt
 11185  		x := v_0.Args[0]
 11186  		if !(is32Bit(c+d) && x.Op != OpSB) {
 11187  			break
 11188  		}
 11189  		v.reset(OpAMD64LEAQ8)
 11190  		v.AuxInt = c + d
 11191  		v.Aux = s
 11192  		v.AddArg(x)
 11193  		v.AddArg(y)
 11194  		return true
 11195  	}
 11196  	// match: (LEAQ8 [c] {s} x (ADDQconst [d] y))
 11197  	// cond: is32Bit(c+8*d) && y.Op != OpSB
 11198  	// result: (LEAQ8 [c+8*d] {s} x y)
 11199  	for {
 11200  		c := v.AuxInt
 11201  		s := v.Aux
 11202  		_ = v.Args[1]
 11203  		x := v.Args[0]
 11204  		v_1 := v.Args[1]
 11205  		if v_1.Op != OpAMD64ADDQconst {
 11206  			break
 11207  		}
 11208  		d := v_1.AuxInt
 11209  		y := v_1.Args[0]
 11210  		if !(is32Bit(c+8*d) && y.Op != OpSB) {
 11211  			break
 11212  		}
 11213  		v.reset(OpAMD64LEAQ8)
 11214  		v.AuxInt = c + 8*d
 11215  		v.Aux = s
 11216  		v.AddArg(x)
 11217  		v.AddArg(y)
 11218  		return true
 11219  	}
 11220  	// match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y)
 11221  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
 11222  	// result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y)
 11223  	for {
 11224  		off1 := v.AuxInt
 11225  		sym1 := v.Aux
 11226  		y := v.Args[1]
 11227  		v_0 := v.Args[0]
 11228  		if v_0.Op != OpAMD64LEAQ {
 11229  			break
 11230  		}
 11231  		off2 := v_0.AuxInt
 11232  		sym2 := v_0.Aux
 11233  		x := v_0.Args[0]
 11234  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
 11235  			break
 11236  		}
 11237  		v.reset(OpAMD64LEAQ8)
 11238  		v.AuxInt = off1 + off2
 11239  		v.Aux = mergeSym(sym1, sym2)
 11240  		v.AddArg(x)
 11241  		v.AddArg(y)
 11242  		return true
 11243  	}
 11244  	return false
 11245  }
 11246  func rewriteValueAMD64_OpAMD64MOVBQSX_0(v *Value) bool {
 11247  	b := v.Block
 11248  	// match: (MOVBQSX x:(MOVBload [off] {sym} ptr mem))
 11249  	// cond: x.Uses == 1 && clobber(x)
 11250  	// result: @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
 11251  	for {
 11252  		x := v.Args[0]
 11253  		if x.Op != OpAMD64MOVBload {
 11254  			break
 11255  		}
 11256  		off := x.AuxInt
 11257  		sym := x.Aux
 11258  		mem := x.Args[1]
 11259  		ptr := x.Args[0]
 11260  		if !(x.Uses == 1 && clobber(x)) {
 11261  			break
 11262  		}
 11263  		b = x.Block
 11264  		v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type)
 11265  		v.reset(OpCopy)
 11266  		v.AddArg(v0)
 11267  		v0.AuxInt = off
 11268  		v0.Aux = sym
 11269  		v0.AddArg(ptr)
 11270  		v0.AddArg(mem)
 11271  		return true
 11272  	}
 11273  	// match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem))
 11274  	// cond: x.Uses == 1 && clobber(x)
 11275  	// result: @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
 11276  	for {
 11277  		x := v.Args[0]
 11278  		if x.Op != OpAMD64MOVWload {
 11279  			break
 11280  		}
 11281  		off := x.AuxInt
 11282  		sym := x.Aux
 11283  		mem := x.Args[1]
 11284  		ptr := x.Args[0]
 11285  		if !(x.Uses == 1 && clobber(x)) {
 11286  			break
 11287  		}
 11288  		b = x.Block
 11289  		v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type)
 11290  		v.reset(OpCopy)
 11291  		v.AddArg(v0)
 11292  		v0.AuxInt = off
 11293  		v0.Aux = sym
 11294  		v0.AddArg(ptr)
 11295  		v0.AddArg(mem)
 11296  		return true
 11297  	}
 11298  	// match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem))
 11299  	// cond: x.Uses == 1 && clobber(x)
 11300  	// result: @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
 11301  	for {
 11302  		x := v.Args[0]
 11303  		if x.Op != OpAMD64MOVLload {
 11304  			break
 11305  		}
 11306  		off := x.AuxInt
 11307  		sym := x.Aux
 11308  		mem := x.Args[1]
 11309  		ptr := x.Args[0]
 11310  		if !(x.Uses == 1 && clobber(x)) {
 11311  			break
 11312  		}
 11313  		b = x.Block
 11314  		v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type)
 11315  		v.reset(OpCopy)
 11316  		v.AddArg(v0)
 11317  		v0.AuxInt = off
 11318  		v0.Aux = sym
 11319  		v0.AddArg(ptr)
 11320  		v0.AddArg(mem)
 11321  		return true
 11322  	}
 11323  	// match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem))
 11324  	// cond: x.Uses == 1 && clobber(x)
 11325  	// result: @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
 11326  	for {
 11327  		x := v.Args[0]
 11328  		if x.Op != OpAMD64MOVQload {
 11329  			break
 11330  		}
 11331  		off := x.AuxInt
 11332  		sym := x.Aux
 11333  		mem := x.Args[1]
 11334  		ptr := x.Args[0]
 11335  		if !(x.Uses == 1 && clobber(x)) {
 11336  			break
 11337  		}
 11338  		b = x.Block
 11339  		v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type)
 11340  		v.reset(OpCopy)
 11341  		v.AddArg(v0)
 11342  		v0.AuxInt = off
 11343  		v0.Aux = sym
 11344  		v0.AddArg(ptr)
 11345  		v0.AddArg(mem)
 11346  		return true
 11347  	}
 11348  	// match: (MOVBQSX (ANDLconst [c] x))
 11349  	// cond: c & 0x80 == 0
 11350  	// result: (ANDLconst [c & 0x7f] x)
 11351  	for {
 11352  		v_0 := v.Args[0]
 11353  		if v_0.Op != OpAMD64ANDLconst {
 11354  			break
 11355  		}
 11356  		c := v_0.AuxInt
 11357  		x := v_0.Args[0]
 11358  		if !(c&0x80 == 0) {
 11359  			break
 11360  		}
 11361  		v.reset(OpAMD64ANDLconst)
 11362  		v.AuxInt = c & 0x7f
 11363  		v.AddArg(x)
 11364  		return true
 11365  	}
 11366  	// match: (MOVBQSX (MOVBQSX x))
 11367  	// result: (MOVBQSX x)
 11368  	for {
 11369  		v_0 := v.Args[0]
 11370  		if v_0.Op != OpAMD64MOVBQSX {
 11371  			break
 11372  		}
 11373  		x := v_0.Args[0]
 11374  		v.reset(OpAMD64MOVBQSX)
 11375  		v.AddArg(x)
 11376  		return true
 11377  	}
 11378  	return false
 11379  }
 11380  func rewriteValueAMD64_OpAMD64MOVBQSXload_0(v *Value) bool {
 11381  	// match: (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _))
 11382  	// cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
 11383  	// result: (MOVBQSX x)
 11384  	for {
 11385  		off := v.AuxInt
 11386  		sym := v.Aux
 11387  		_ = v.Args[1]
 11388  		ptr := v.Args[0]
 11389  		v_1 := v.Args[1]
 11390  		if v_1.Op != OpAMD64MOVBstore {
 11391  			break
 11392  		}
 11393  		off2 := v_1.AuxInt
 11394  		sym2 := v_1.Aux
 11395  		_ = v_1.Args[2]
 11396  		ptr2 := v_1.Args[0]
 11397  		x := v_1.Args[1]
 11398  		if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
 11399  			break
 11400  		}
 11401  		v.reset(OpAMD64MOVBQSX)
 11402  		v.AddArg(x)
 11403  		return true
 11404  	}
 11405  	// match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
 11406  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 11407  	// result: (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem)
 11408  	for {
 11409  		off1 := v.AuxInt
 11410  		sym1 := v.Aux
 11411  		mem := v.Args[1]
 11412  		v_0 := v.Args[0]
 11413  		if v_0.Op != OpAMD64LEAQ {
 11414  			break
 11415  		}
 11416  		off2 := v_0.AuxInt
 11417  		sym2 := v_0.Aux
 11418  		base := v_0.Args[0]
 11419  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 11420  			break
 11421  		}
 11422  		v.reset(OpAMD64MOVBQSXload)
 11423  		v.AuxInt = off1 + off2
 11424  		v.Aux = mergeSym(sym1, sym2)
 11425  		v.AddArg(base)
 11426  		v.AddArg(mem)
 11427  		return true
 11428  	}
 11429  	return false
 11430  }
 11431  func rewriteValueAMD64_OpAMD64MOVBQZX_0(v *Value) bool {
 11432  	b := v.Block
 11433  	// match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem))
 11434  	// cond: x.Uses == 1 && clobber(x)
 11435  	// result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
 11436  	for {
 11437  		x := v.Args[0]
 11438  		if x.Op != OpAMD64MOVBload {
 11439  			break
 11440  		}
 11441  		off := x.AuxInt
 11442  		sym := x.Aux
 11443  		mem := x.Args[1]
 11444  		ptr := x.Args[0]
 11445  		if !(x.Uses == 1 && clobber(x)) {
 11446  			break
 11447  		}
 11448  		b = x.Block
 11449  		v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type)
 11450  		v.reset(OpCopy)
 11451  		v.AddArg(v0)
 11452  		v0.AuxInt = off
 11453  		v0.Aux = sym
 11454  		v0.AddArg(ptr)
 11455  		v0.AddArg(mem)
 11456  		return true
 11457  	}
 11458  	// match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem))
 11459  	// cond: x.Uses == 1 && clobber(x)
 11460  	// result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
 11461  	for {
 11462  		x := v.Args[0]
 11463  		if x.Op != OpAMD64MOVWload {
 11464  			break
 11465  		}
 11466  		off := x.AuxInt
 11467  		sym := x.Aux
 11468  		mem := x.Args[1]
 11469  		ptr := x.Args[0]
 11470  		if !(x.Uses == 1 && clobber(x)) {
 11471  			break
 11472  		}
 11473  		b = x.Block
 11474  		v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type)
 11475  		v.reset(OpCopy)
 11476  		v.AddArg(v0)
 11477  		v0.AuxInt = off
 11478  		v0.Aux = sym
 11479  		v0.AddArg(ptr)
 11480  		v0.AddArg(mem)
 11481  		return true
 11482  	}
 11483  	// match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem))
 11484  	// cond: x.Uses == 1 && clobber(x)
 11485  	// result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
 11486  	for {
 11487  		x := v.Args[0]
 11488  		if x.Op != OpAMD64MOVLload {
 11489  			break
 11490  		}
 11491  		off := x.AuxInt
 11492  		sym := x.Aux
 11493  		mem := x.Args[1]
 11494  		ptr := x.Args[0]
 11495  		if !(x.Uses == 1 && clobber(x)) {
 11496  			break
 11497  		}
 11498  		b = x.Block
 11499  		v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type)
 11500  		v.reset(OpCopy)
 11501  		v.AddArg(v0)
 11502  		v0.AuxInt = off
 11503  		v0.Aux = sym
 11504  		v0.AddArg(ptr)
 11505  		v0.AddArg(mem)
 11506  		return true
 11507  	}
 11508  	// match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem))
 11509  	// cond: x.Uses == 1 && clobber(x)
 11510  	// result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
 11511  	for {
 11512  		x := v.Args[0]
 11513  		if x.Op != OpAMD64MOVQload {
 11514  			break
 11515  		}
 11516  		off := x.AuxInt
 11517  		sym := x.Aux
 11518  		mem := x.Args[1]
 11519  		ptr := x.Args[0]
 11520  		if !(x.Uses == 1 && clobber(x)) {
 11521  			break
 11522  		}
 11523  		b = x.Block
 11524  		v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type)
 11525  		v.reset(OpCopy)
 11526  		v.AddArg(v0)
 11527  		v0.AuxInt = off
 11528  		v0.Aux = sym
 11529  		v0.AddArg(ptr)
 11530  		v0.AddArg(mem)
 11531  		return true
 11532  	}
 11533  	// match: (MOVBQZX x)
 11534  	// cond: zeroUpper56Bits(x,3)
 11535  	// result: x
 11536  	for {
 11537  		x := v.Args[0]
 11538  		if !(zeroUpper56Bits(x, 3)) {
 11539  			break
 11540  		}
 11541  		v.reset(OpCopy)
 11542  		v.Type = x.Type
 11543  		v.AddArg(x)
 11544  		return true
 11545  	}
 11546  	// match: (MOVBQZX x:(MOVBloadidx1 [off] {sym} ptr idx mem))
 11547  	// cond: x.Uses == 1 && clobber(x)
 11548  	// result: @x.Block (MOVBloadidx1 <v.Type> [off] {sym} ptr idx mem)
 11549  	for {
 11550  		x := v.Args[0]
 11551  		if x.Op != OpAMD64MOVBloadidx1 {
 11552  			break
 11553  		}
 11554  		off := x.AuxInt
 11555  		sym := x.Aux
 11556  		mem := x.Args[2]
 11557  		ptr := x.Args[0]
 11558  		idx := x.Args[1]
 11559  		if !(x.Uses == 1 && clobber(x)) {
 11560  			break
 11561  		}
 11562  		b = x.Block
 11563  		v0 := b.NewValue0(v.Pos, OpAMD64MOVBloadidx1, v.Type)
 11564  		v.reset(OpCopy)
 11565  		v.AddArg(v0)
 11566  		v0.AuxInt = off
 11567  		v0.Aux = sym
 11568  		v0.AddArg(ptr)
 11569  		v0.AddArg(idx)
 11570  		v0.AddArg(mem)
 11571  		return true
 11572  	}
 11573  	// match: (MOVBQZX (ANDLconst [c] x))
 11574  	// result: (ANDLconst [c & 0xff] x)
 11575  	for {
 11576  		v_0 := v.Args[0]
 11577  		if v_0.Op != OpAMD64ANDLconst {
 11578  			break
 11579  		}
 11580  		c := v_0.AuxInt
 11581  		x := v_0.Args[0]
 11582  		v.reset(OpAMD64ANDLconst)
 11583  		v.AuxInt = c & 0xff
 11584  		v.AddArg(x)
 11585  		return true
 11586  	}
 11587  	// match: (MOVBQZX (MOVBQZX x))
 11588  	// result: (MOVBQZX x)
 11589  	for {
 11590  		v_0 := v.Args[0]
 11591  		if v_0.Op != OpAMD64MOVBQZX {
 11592  			break
 11593  		}
 11594  		x := v_0.Args[0]
 11595  		v.reset(OpAMD64MOVBQZX)
 11596  		v.AddArg(x)
 11597  		return true
 11598  	}
 11599  	return false
 11600  }
 11601  func rewriteValueAMD64_OpAMD64MOVBatomicload_0(v *Value) bool {
 11602  	// match: (MOVBatomicload [off1] {sym} (ADDQconst [off2] ptr) mem)
 11603  	// cond: is32Bit(off1+off2)
 11604  	// result: (MOVBatomicload [off1+off2] {sym} ptr mem)
 11605  	for {
 11606  		off1 := v.AuxInt
 11607  		sym := v.Aux
 11608  		mem := v.Args[1]
 11609  		v_0 := v.Args[0]
 11610  		if v_0.Op != OpAMD64ADDQconst {
 11611  			break
 11612  		}
 11613  		off2 := v_0.AuxInt
 11614  		ptr := v_0.Args[0]
 11615  		if !(is32Bit(off1 + off2)) {
 11616  			break
 11617  		}
 11618  		v.reset(OpAMD64MOVBatomicload)
 11619  		v.AuxInt = off1 + off2
 11620  		v.Aux = sym
 11621  		v.AddArg(ptr)
 11622  		v.AddArg(mem)
 11623  		return true
 11624  	}
 11625  	// match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem)
 11626  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 11627  	// result: (MOVBatomicload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
 11628  	for {
 11629  		off1 := v.AuxInt
 11630  		sym1 := v.Aux
 11631  		mem := v.Args[1]
 11632  		v_0 := v.Args[0]
 11633  		if v_0.Op != OpAMD64LEAQ {
 11634  			break
 11635  		}
 11636  		off2 := v_0.AuxInt
 11637  		sym2 := v_0.Aux
 11638  		ptr := v_0.Args[0]
 11639  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 11640  			break
 11641  		}
 11642  		v.reset(OpAMD64MOVBatomicload)
 11643  		v.AuxInt = off1 + off2
 11644  		v.Aux = mergeSym(sym1, sym2)
 11645  		v.AddArg(ptr)
 11646  		v.AddArg(mem)
 11647  		return true
 11648  	}
 11649  	return false
 11650  }
 11651  func rewriteValueAMD64_OpAMD64MOVBload_0(v *Value) bool {
 11652  	// match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _))
 11653  	// cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
 11654  	// result: (MOVBQZX x)
 11655  	for {
 11656  		off := v.AuxInt
 11657  		sym := v.Aux
 11658  		_ = v.Args[1]
 11659  		ptr := v.Args[0]
 11660  		v_1 := v.Args[1]
 11661  		if v_1.Op != OpAMD64MOVBstore {
 11662  			break
 11663  		}
 11664  		off2 := v_1.AuxInt
 11665  		sym2 := v_1.Aux
 11666  		_ = v_1.Args[2]
 11667  		ptr2 := v_1.Args[0]
 11668  		x := v_1.Args[1]
 11669  		if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
 11670  			break
 11671  		}
 11672  		v.reset(OpAMD64MOVBQZX)
 11673  		v.AddArg(x)
 11674  		return true
 11675  	}
 11676  	// match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem)
 11677  	// cond: is32Bit(off1+off2)
 11678  	// result: (MOVBload [off1+off2] {sym} ptr mem)
 11679  	for {
 11680  		off1 := v.AuxInt
 11681  		sym := v.Aux
 11682  		mem := v.Args[1]
 11683  		v_0 := v.Args[0]
 11684  		if v_0.Op != OpAMD64ADDQconst {
 11685  			break
 11686  		}
 11687  		off2 := v_0.AuxInt
 11688  		ptr := v_0.Args[0]
 11689  		if !(is32Bit(off1 + off2)) {
 11690  			break
 11691  		}
 11692  		v.reset(OpAMD64MOVBload)
 11693  		v.AuxInt = off1 + off2
 11694  		v.Aux = sym
 11695  		v.AddArg(ptr)
 11696  		v.AddArg(mem)
 11697  		return true
 11698  	}
 11699  	// match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
 11700  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 11701  	// result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem)
 11702  	for {
 11703  		off1 := v.AuxInt
 11704  		sym1 := v.Aux
 11705  		mem := v.Args[1]
 11706  		v_0 := v.Args[0]
 11707  		if v_0.Op != OpAMD64LEAQ {
 11708  			break
 11709  		}
 11710  		off2 := v_0.AuxInt
 11711  		sym2 := v_0.Aux
 11712  		base := v_0.Args[0]
 11713  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 11714  			break
 11715  		}
 11716  		v.reset(OpAMD64MOVBload)
 11717  		v.AuxInt = off1 + off2
 11718  		v.Aux = mergeSym(sym1, sym2)
 11719  		v.AddArg(base)
 11720  		v.AddArg(mem)
 11721  		return true
 11722  	}
 11723  	// match: (MOVBload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem)
 11724  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 11725  	// result: (MOVBloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
 11726  	for {
 11727  		off1 := v.AuxInt
 11728  		sym1 := v.Aux
 11729  		mem := v.Args[1]
 11730  		v_0 := v.Args[0]
 11731  		if v_0.Op != OpAMD64LEAQ1 {
 11732  			break
 11733  		}
 11734  		off2 := v_0.AuxInt
 11735  		sym2 := v_0.Aux
 11736  		idx := v_0.Args[1]
 11737  		ptr := v_0.Args[0]
 11738  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 11739  			break
 11740  		}
 11741  		v.reset(OpAMD64MOVBloadidx1)
 11742  		v.AuxInt = off1 + off2
 11743  		v.Aux = mergeSym(sym1, sym2)
 11744  		v.AddArg(ptr)
 11745  		v.AddArg(idx)
 11746  		v.AddArg(mem)
 11747  		return true
 11748  	}
 11749  	// match: (MOVBload [off] {sym} (ADDQ ptr idx) mem)
 11750  	// cond: ptr.Op != OpSB
 11751  	// result: (MOVBloadidx1 [off] {sym} ptr idx mem)
 11752  	for {
 11753  		off := v.AuxInt
 11754  		sym := v.Aux
 11755  		mem := v.Args[1]
 11756  		v_0 := v.Args[0]
 11757  		if v_0.Op != OpAMD64ADDQ {
 11758  			break
 11759  		}
 11760  		idx := v_0.Args[1]
 11761  		ptr := v_0.Args[0]
 11762  		if !(ptr.Op != OpSB) {
 11763  			break
 11764  		}
 11765  		v.reset(OpAMD64MOVBloadidx1)
 11766  		v.AuxInt = off
 11767  		v.Aux = sym
 11768  		v.AddArg(ptr)
 11769  		v.AddArg(idx)
 11770  		v.AddArg(mem)
 11771  		return true
 11772  	}
 11773  	// match: (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
 11774  	// cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2)
 11775  	// result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem)
 11776  	for {
 11777  		off1 := v.AuxInt
 11778  		sym1 := v.Aux
 11779  		mem := v.Args[1]
 11780  		v_0 := v.Args[0]
 11781  		if v_0.Op != OpAMD64LEAL {
 11782  			break
 11783  		}
 11784  		off2 := v_0.AuxInt
 11785  		sym2 := v_0.Aux
 11786  		base := v_0.Args[0]
 11787  		if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) {
 11788  			break
 11789  		}
 11790  		v.reset(OpAMD64MOVBload)
 11791  		v.AuxInt = off1 + off2
 11792  		v.Aux = mergeSym(sym1, sym2)
 11793  		v.AddArg(base)
 11794  		v.AddArg(mem)
 11795  		return true
 11796  	}
 11797  	// match: (MOVBload [off1] {sym} (ADDLconst [off2] ptr) mem)
 11798  	// cond: is32Bit(off1+off2)
 11799  	// result: (MOVBload [off1+off2] {sym} ptr mem)
 11800  	for {
 11801  		off1 := v.AuxInt
 11802  		sym := v.Aux
 11803  		mem := v.Args[1]
 11804  		v_0 := v.Args[0]
 11805  		if v_0.Op != OpAMD64ADDLconst {
 11806  			break
 11807  		}
 11808  		off2 := v_0.AuxInt
 11809  		ptr := v_0.Args[0]
 11810  		if !(is32Bit(off1 + off2)) {
 11811  			break
 11812  		}
 11813  		v.reset(OpAMD64MOVBload)
 11814  		v.AuxInt = off1 + off2
 11815  		v.Aux = sym
 11816  		v.AddArg(ptr)
 11817  		v.AddArg(mem)
 11818  		return true
 11819  	}
 11820  	// match: (MOVBload [off] {sym} (SB) _)
 11821  	// cond: symIsRO(sym)
 11822  	// result: (MOVLconst [int64(read8(sym, off))])
 11823  	for {
 11824  		off := v.AuxInt
 11825  		sym := v.Aux
 11826  		_ = v.Args[1]
 11827  		v_0 := v.Args[0]
 11828  		if v_0.Op != OpSB || !(symIsRO(sym)) {
 11829  			break
 11830  		}
 11831  		v.reset(OpAMD64MOVLconst)
 11832  		v.AuxInt = int64(read8(sym, off))
 11833  		return true
 11834  	}
 11835  	return false
 11836  }
 11837  func rewriteValueAMD64_OpAMD64MOVBloadidx1_0(v *Value) bool {
 11838  	// match: (MOVBloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem)
 11839  	// cond: is32Bit(c+d)
 11840  	// result: (MOVBloadidx1 [c+d] {sym} ptr idx mem)
 11841  	for {
 11842  		c := v.AuxInt
 11843  		sym := v.Aux
 11844  		mem := v.Args[2]
 11845  		v_0 := v.Args[0]
 11846  		if v_0.Op != OpAMD64ADDQconst {
 11847  			break
 11848  		}
 11849  		d := v_0.AuxInt
 11850  		ptr := v_0.Args[0]
 11851  		idx := v.Args[1]
 11852  		if !(is32Bit(c + d)) {
 11853  			break
 11854  		}
 11855  		v.reset(OpAMD64MOVBloadidx1)
 11856  		v.AuxInt = c + d
 11857  		v.Aux = sym
 11858  		v.AddArg(ptr)
 11859  		v.AddArg(idx)
 11860  		v.AddArg(mem)
 11861  		return true
 11862  	}
 11863  	// match: (MOVBloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem)
 11864  	// cond: is32Bit(c+d)
 11865  	// result: (MOVBloadidx1 [c+d] {sym} ptr idx mem)
 11866  	for {
 11867  		c := v.AuxInt
 11868  		sym := v.Aux
 11869  		mem := v.Args[2]
 11870  		idx := v.Args[0]
 11871  		v_1 := v.Args[1]
 11872  		if v_1.Op != OpAMD64ADDQconst {
 11873  			break
 11874  		}
 11875  		d := v_1.AuxInt
 11876  		ptr := v_1.Args[0]
 11877  		if !(is32Bit(c + d)) {
 11878  			break
 11879  		}
 11880  		v.reset(OpAMD64MOVBloadidx1)
 11881  		v.AuxInt = c + d
 11882  		v.Aux = sym
 11883  		v.AddArg(ptr)
 11884  		v.AddArg(idx)
 11885  		v.AddArg(mem)
 11886  		return true
 11887  	}
 11888  	// match: (MOVBloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem)
 11889  	// cond: is32Bit(c+d)
 11890  	// result: (MOVBloadidx1 [c+d] {sym} ptr idx mem)
 11891  	for {
 11892  		c := v.AuxInt
 11893  		sym := v.Aux
 11894  		mem := v.Args[2]
 11895  		ptr := v.Args[0]
 11896  		v_1 := v.Args[1]
 11897  		if v_1.Op != OpAMD64ADDQconst {
 11898  			break
 11899  		}
 11900  		d := v_1.AuxInt
 11901  		idx := v_1.Args[0]
 11902  		if !(is32Bit(c + d)) {
 11903  			break
 11904  		}
 11905  		v.reset(OpAMD64MOVBloadidx1)
 11906  		v.AuxInt = c + d
 11907  		v.Aux = sym
 11908  		v.AddArg(ptr)
 11909  		v.AddArg(idx)
 11910  		v.AddArg(mem)
 11911  		return true
 11912  	}
 11913  	// match: (MOVBloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem)
 11914  	// cond: is32Bit(c+d)
 11915  	// result: (MOVBloadidx1 [c+d] {sym} ptr idx mem)
 11916  	for {
 11917  		c := v.AuxInt
 11918  		sym := v.Aux
 11919  		mem := v.Args[2]
 11920  		v_0 := v.Args[0]
 11921  		if v_0.Op != OpAMD64ADDQconst {
 11922  			break
 11923  		}
 11924  		d := v_0.AuxInt
 11925  		idx := v_0.Args[0]
 11926  		ptr := v.Args[1]
 11927  		if !(is32Bit(c + d)) {
 11928  			break
 11929  		}
 11930  		v.reset(OpAMD64MOVBloadidx1)
 11931  		v.AuxInt = c + d
 11932  		v.Aux = sym
 11933  		v.AddArg(ptr)
 11934  		v.AddArg(idx)
 11935  		v.AddArg(mem)
 11936  		return true
 11937  	}
 11938  	// match: (MOVBloadidx1 [i] {s} p (MOVQconst [c]) mem)
 11939  	// cond: is32Bit(i+c)
 11940  	// result: (MOVBload [i+c] {s} p mem)
 11941  	for {
 11942  		i := v.AuxInt
 11943  		s := v.Aux
 11944  		mem := v.Args[2]
 11945  		p := v.Args[0]
 11946  		v_1 := v.Args[1]
 11947  		if v_1.Op != OpAMD64MOVQconst {
 11948  			break
 11949  		}
 11950  		c := v_1.AuxInt
 11951  		if !(is32Bit(i + c)) {
 11952  			break
 11953  		}
 11954  		v.reset(OpAMD64MOVBload)
 11955  		v.AuxInt = i + c
 11956  		v.Aux = s
 11957  		v.AddArg(p)
 11958  		v.AddArg(mem)
 11959  		return true
 11960  	}
 11961  	// match: (MOVBloadidx1 [i] {s} (MOVQconst [c]) p mem)
 11962  	// cond: is32Bit(i+c)
 11963  	// result: (MOVBload [i+c] {s} p mem)
 11964  	for {
 11965  		i := v.AuxInt
 11966  		s := v.Aux
 11967  		mem := v.Args[2]
 11968  		v_0 := v.Args[0]
 11969  		if v_0.Op != OpAMD64MOVQconst {
 11970  			break
 11971  		}
 11972  		c := v_0.AuxInt
 11973  		p := v.Args[1]
 11974  		if !(is32Bit(i + c)) {
 11975  			break
 11976  		}
 11977  		v.reset(OpAMD64MOVBload)
 11978  		v.AuxInt = i + c
 11979  		v.Aux = s
 11980  		v.AddArg(p)
 11981  		v.AddArg(mem)
 11982  		return true
 11983  	}
 11984  	return false
 11985  }
 11986  func rewriteValueAMD64_OpAMD64MOVBstore_0(v *Value) bool {
 11987  	// match: (MOVBstore [off] {sym} ptr y:(SETL x) mem)
 11988  	// cond: y.Uses == 1
 11989  	// result: (SETLstore [off] {sym} ptr x mem)
 11990  	for {
 11991  		off := v.AuxInt
 11992  		sym := v.Aux
 11993  		mem := v.Args[2]
 11994  		ptr := v.Args[0]
 11995  		y := v.Args[1]
 11996  		if y.Op != OpAMD64SETL {
 11997  			break
 11998  		}
 11999  		x := y.Args[0]
 12000  		if !(y.Uses == 1) {
 12001  			break
 12002  		}
 12003  		v.reset(OpAMD64SETLstore)
 12004  		v.AuxInt = off
 12005  		v.Aux = sym
 12006  		v.AddArg(ptr)
 12007  		v.AddArg(x)
 12008  		v.AddArg(mem)
 12009  		return true
 12010  	}
 12011  	// match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem)
 12012  	// cond: y.Uses == 1
 12013  	// result: (SETLEstore [off] {sym} ptr x mem)
 12014  	for {
 12015  		off := v.AuxInt
 12016  		sym := v.Aux
 12017  		mem := v.Args[2]
 12018  		ptr := v.Args[0]
 12019  		y := v.Args[1]
 12020  		if y.Op != OpAMD64SETLE {
 12021  			break
 12022  		}
 12023  		x := y.Args[0]
 12024  		if !(y.Uses == 1) {
 12025  			break
 12026  		}
 12027  		v.reset(OpAMD64SETLEstore)
 12028  		v.AuxInt = off
 12029  		v.Aux = sym
 12030  		v.AddArg(ptr)
 12031  		v.AddArg(x)
 12032  		v.AddArg(mem)
 12033  		return true
 12034  	}
 12035  	// match: (MOVBstore [off] {sym} ptr y:(SETG x) mem)
 12036  	// cond: y.Uses == 1
 12037  	// result: (SETGstore [off] {sym} ptr x mem)
 12038  	for {
 12039  		off := v.AuxInt
 12040  		sym := v.Aux
 12041  		mem := v.Args[2]
 12042  		ptr := v.Args[0]
 12043  		y := v.Args[1]
 12044  		if y.Op != OpAMD64SETG {
 12045  			break
 12046  		}
 12047  		x := y.Args[0]
 12048  		if !(y.Uses == 1) {
 12049  			break
 12050  		}
 12051  		v.reset(OpAMD64SETGstore)
 12052  		v.AuxInt = off
 12053  		v.Aux = sym
 12054  		v.AddArg(ptr)
 12055  		v.AddArg(x)
 12056  		v.AddArg(mem)
 12057  		return true
 12058  	}
 12059  	// match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem)
 12060  	// cond: y.Uses == 1
 12061  	// result: (SETGEstore [off] {sym} ptr x mem)
 12062  	for {
 12063  		off := v.AuxInt
 12064  		sym := v.Aux
 12065  		mem := v.Args[2]
 12066  		ptr := v.Args[0]
 12067  		y := v.Args[1]
 12068  		if y.Op != OpAMD64SETGE {
 12069  			break
 12070  		}
 12071  		x := y.Args[0]
 12072  		if !(y.Uses == 1) {
 12073  			break
 12074  		}
 12075  		v.reset(OpAMD64SETGEstore)
 12076  		v.AuxInt = off
 12077  		v.Aux = sym
 12078  		v.AddArg(ptr)
 12079  		v.AddArg(x)
 12080  		v.AddArg(mem)
 12081  		return true
 12082  	}
 12083  	// match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem)
 12084  	// cond: y.Uses == 1
 12085  	// result: (SETEQstore [off] {sym} ptr x mem)
 12086  	for {
 12087  		off := v.AuxInt
 12088  		sym := v.Aux
 12089  		mem := v.Args[2]
 12090  		ptr := v.Args[0]
 12091  		y := v.Args[1]
 12092  		if y.Op != OpAMD64SETEQ {
 12093  			break
 12094  		}
 12095  		x := y.Args[0]
 12096  		if !(y.Uses == 1) {
 12097  			break
 12098  		}
 12099  		v.reset(OpAMD64SETEQstore)
 12100  		v.AuxInt = off
 12101  		v.Aux = sym
 12102  		v.AddArg(ptr)
 12103  		v.AddArg(x)
 12104  		v.AddArg(mem)
 12105  		return true
 12106  	}
 12107  	// match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem)
 12108  	// cond: y.Uses == 1
 12109  	// result: (SETNEstore [off] {sym} ptr x mem)
 12110  	for {
 12111  		off := v.AuxInt
 12112  		sym := v.Aux
 12113  		mem := v.Args[2]
 12114  		ptr := v.Args[0]
 12115  		y := v.Args[1]
 12116  		if y.Op != OpAMD64SETNE {
 12117  			break
 12118  		}
 12119  		x := y.Args[0]
 12120  		if !(y.Uses == 1) {
 12121  			break
 12122  		}
 12123  		v.reset(OpAMD64SETNEstore)
 12124  		v.AuxInt = off
 12125  		v.Aux = sym
 12126  		v.AddArg(ptr)
 12127  		v.AddArg(x)
 12128  		v.AddArg(mem)
 12129  		return true
 12130  	}
 12131  	// match: (MOVBstore [off] {sym} ptr y:(SETB x) mem)
 12132  	// cond: y.Uses == 1
 12133  	// result: (SETBstore [off] {sym} ptr x mem)
 12134  	for {
 12135  		off := v.AuxInt
 12136  		sym := v.Aux
 12137  		mem := v.Args[2]
 12138  		ptr := v.Args[0]
 12139  		y := v.Args[1]
 12140  		if y.Op != OpAMD64SETB {
 12141  			break
 12142  		}
 12143  		x := y.Args[0]
 12144  		if !(y.Uses == 1) {
 12145  			break
 12146  		}
 12147  		v.reset(OpAMD64SETBstore)
 12148  		v.AuxInt = off
 12149  		v.Aux = sym
 12150  		v.AddArg(ptr)
 12151  		v.AddArg(x)
 12152  		v.AddArg(mem)
 12153  		return true
 12154  	}
 12155  	// match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem)
 12156  	// cond: y.Uses == 1
 12157  	// result: (SETBEstore [off] {sym} ptr x mem)
 12158  	for {
 12159  		off := v.AuxInt
 12160  		sym := v.Aux
 12161  		mem := v.Args[2]
 12162  		ptr := v.Args[0]
 12163  		y := v.Args[1]
 12164  		if y.Op != OpAMD64SETBE {
 12165  			break
 12166  		}
 12167  		x := y.Args[0]
 12168  		if !(y.Uses == 1) {
 12169  			break
 12170  		}
 12171  		v.reset(OpAMD64SETBEstore)
 12172  		v.AuxInt = off
 12173  		v.Aux = sym
 12174  		v.AddArg(ptr)
 12175  		v.AddArg(x)
 12176  		v.AddArg(mem)
 12177  		return true
 12178  	}
 12179  	// match: (MOVBstore [off] {sym} ptr y:(SETA x) mem)
 12180  	// cond: y.Uses == 1
 12181  	// result: (SETAstore [off] {sym} ptr x mem)
 12182  	for {
 12183  		off := v.AuxInt
 12184  		sym := v.Aux
 12185  		mem := v.Args[2]
 12186  		ptr := v.Args[0]
 12187  		y := v.Args[1]
 12188  		if y.Op != OpAMD64SETA {
 12189  			break
 12190  		}
 12191  		x := y.Args[0]
 12192  		if !(y.Uses == 1) {
 12193  			break
 12194  		}
 12195  		v.reset(OpAMD64SETAstore)
 12196  		v.AuxInt = off
 12197  		v.Aux = sym
 12198  		v.AddArg(ptr)
 12199  		v.AddArg(x)
 12200  		v.AddArg(mem)
 12201  		return true
 12202  	}
 12203  	// match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem)
 12204  	// cond: y.Uses == 1
 12205  	// result: (SETAEstore [off] {sym} ptr x mem)
 12206  	for {
 12207  		off := v.AuxInt
 12208  		sym := v.Aux
 12209  		mem := v.Args[2]
 12210  		ptr := v.Args[0]
 12211  		y := v.Args[1]
 12212  		if y.Op != OpAMD64SETAE {
 12213  			break
 12214  		}
 12215  		x := y.Args[0]
 12216  		if !(y.Uses == 1) {
 12217  			break
 12218  		}
 12219  		v.reset(OpAMD64SETAEstore)
 12220  		v.AuxInt = off
 12221  		v.Aux = sym
 12222  		v.AddArg(ptr)
 12223  		v.AddArg(x)
 12224  		v.AddArg(mem)
 12225  		return true
 12226  	}
 12227  	return false
 12228  }
 12229  func rewriteValueAMD64_OpAMD64MOVBstore_10(v *Value) bool {
 12230  	b := v.Block
 12231  	// match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem)
 12232  	// result: (MOVBstore [off] {sym} ptr x mem)
 12233  	for {
 12234  		off := v.AuxInt
 12235  		sym := v.Aux
 12236  		mem := v.Args[2]
 12237  		ptr := v.Args[0]
 12238  		v_1 := v.Args[1]
 12239  		if v_1.Op != OpAMD64MOVBQSX {
 12240  			break
 12241  		}
 12242  		x := v_1.Args[0]
 12243  		v.reset(OpAMD64MOVBstore)
 12244  		v.AuxInt = off
 12245  		v.Aux = sym
 12246  		v.AddArg(ptr)
 12247  		v.AddArg(x)
 12248  		v.AddArg(mem)
 12249  		return true
 12250  	}
 12251  	// match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem)
 12252  	// result: (MOVBstore [off] {sym} ptr x mem)
 12253  	for {
 12254  		off := v.AuxInt
 12255  		sym := v.Aux
 12256  		mem := v.Args[2]
 12257  		ptr := v.Args[0]
 12258  		v_1 := v.Args[1]
 12259  		if v_1.Op != OpAMD64MOVBQZX {
 12260  			break
 12261  		}
 12262  		x := v_1.Args[0]
 12263  		v.reset(OpAMD64MOVBstore)
 12264  		v.AuxInt = off
 12265  		v.Aux = sym
 12266  		v.AddArg(ptr)
 12267  		v.AddArg(x)
 12268  		v.AddArg(mem)
 12269  		return true
 12270  	}
 12271  	// match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem)
 12272  	// cond: is32Bit(off1+off2)
 12273  	// result: (MOVBstore [off1+off2] {sym} ptr val mem)
 12274  	for {
 12275  		off1 := v.AuxInt
 12276  		sym := v.Aux
 12277  		mem := v.Args[2]
 12278  		v_0 := v.Args[0]
 12279  		if v_0.Op != OpAMD64ADDQconst {
 12280  			break
 12281  		}
 12282  		off2 := v_0.AuxInt
 12283  		ptr := v_0.Args[0]
 12284  		val := v.Args[1]
 12285  		if !(is32Bit(off1 + off2)) {
 12286  			break
 12287  		}
 12288  		v.reset(OpAMD64MOVBstore)
 12289  		v.AuxInt = off1 + off2
 12290  		v.Aux = sym
 12291  		v.AddArg(ptr)
 12292  		v.AddArg(val)
 12293  		v.AddArg(mem)
 12294  		return true
 12295  	}
 12296  	// match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem)
 12297  	// cond: validOff(off)
 12298  	// result: (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem)
 12299  	for {
 12300  		off := v.AuxInt
 12301  		sym := v.Aux
 12302  		mem := v.Args[2]
 12303  		ptr := v.Args[0]
 12304  		v_1 := v.Args[1]
 12305  		if v_1.Op != OpAMD64MOVLconst {
 12306  			break
 12307  		}
 12308  		c := v_1.AuxInt
 12309  		if !(validOff(off)) {
 12310  			break
 12311  		}
 12312  		v.reset(OpAMD64MOVBstoreconst)
 12313  		v.AuxInt = makeValAndOff(int64(int8(c)), off)
 12314  		v.Aux = sym
 12315  		v.AddArg(ptr)
 12316  		v.AddArg(mem)
 12317  		return true
 12318  	}
 12319  	// match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem)
 12320  	// cond: validOff(off)
 12321  	// result: (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem)
 12322  	for {
 12323  		off := v.AuxInt
 12324  		sym := v.Aux
 12325  		mem := v.Args[2]
 12326  		ptr := v.Args[0]
 12327  		v_1 := v.Args[1]
 12328  		if v_1.Op != OpAMD64MOVQconst {
 12329  			break
 12330  		}
 12331  		c := v_1.AuxInt
 12332  		if !(validOff(off)) {
 12333  			break
 12334  		}
 12335  		v.reset(OpAMD64MOVBstoreconst)
 12336  		v.AuxInt = makeValAndOff(int64(int8(c)), off)
 12337  		v.Aux = sym
 12338  		v.AddArg(ptr)
 12339  		v.AddArg(mem)
 12340  		return true
 12341  	}
 12342  	// match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
 12343  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 12344  	// result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
 12345  	for {
 12346  		off1 := v.AuxInt
 12347  		sym1 := v.Aux
 12348  		mem := v.Args[2]
 12349  		v_0 := v.Args[0]
 12350  		if v_0.Op != OpAMD64LEAQ {
 12351  			break
 12352  		}
 12353  		off2 := v_0.AuxInt
 12354  		sym2 := v_0.Aux
 12355  		base := v_0.Args[0]
 12356  		val := v.Args[1]
 12357  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 12358  			break
 12359  		}
 12360  		v.reset(OpAMD64MOVBstore)
 12361  		v.AuxInt = off1 + off2
 12362  		v.Aux = mergeSym(sym1, sym2)
 12363  		v.AddArg(base)
 12364  		v.AddArg(val)
 12365  		v.AddArg(mem)
 12366  		return true
 12367  	}
 12368  	// match: (MOVBstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem)
 12369  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 12370  	// result: (MOVBstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
 12371  	for {
 12372  		off1 := v.AuxInt
 12373  		sym1 := v.Aux
 12374  		mem := v.Args[2]
 12375  		v_0 := v.Args[0]
 12376  		if v_0.Op != OpAMD64LEAQ1 {
 12377  			break
 12378  		}
 12379  		off2 := v_0.AuxInt
 12380  		sym2 := v_0.Aux
 12381  		idx := v_0.Args[1]
 12382  		ptr := v_0.Args[0]
 12383  		val := v.Args[1]
 12384  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 12385  			break
 12386  		}
 12387  		v.reset(OpAMD64MOVBstoreidx1)
 12388  		v.AuxInt = off1 + off2
 12389  		v.Aux = mergeSym(sym1, sym2)
 12390  		v.AddArg(ptr)
 12391  		v.AddArg(idx)
 12392  		v.AddArg(val)
 12393  		v.AddArg(mem)
 12394  		return true
 12395  	}
 12396  	// match: (MOVBstore [off] {sym} (ADDQ ptr idx) val mem)
 12397  	// cond: ptr.Op != OpSB
 12398  	// result: (MOVBstoreidx1 [off] {sym} ptr idx val mem)
 12399  	for {
 12400  		off := v.AuxInt
 12401  		sym := v.Aux
 12402  		mem := v.Args[2]
 12403  		v_0 := v.Args[0]
 12404  		if v_0.Op != OpAMD64ADDQ {
 12405  			break
 12406  		}
 12407  		idx := v_0.Args[1]
 12408  		ptr := v_0.Args[0]
 12409  		val := v.Args[1]
 12410  		if !(ptr.Op != OpSB) {
 12411  			break
 12412  		}
 12413  		v.reset(OpAMD64MOVBstoreidx1)
 12414  		v.AuxInt = off
 12415  		v.Aux = sym
 12416  		v.AddArg(ptr)
 12417  		v.AddArg(idx)
 12418  		v.AddArg(val)
 12419  		v.AddArg(mem)
 12420  		return true
 12421  	}
 12422  	// match: (MOVBstore [i] {s} p w x0:(MOVBstore [i-1] {s} p (SHRWconst [8] w) mem))
 12423  	// cond: x0.Uses == 1 && clobber(x0)
 12424  	// result: (MOVWstore [i-1] {s} p (ROLWconst <w.Type> [8] w) mem)
 12425  	for {
 12426  		i := v.AuxInt
 12427  		s := v.Aux
 12428  		_ = v.Args[2]
 12429  		p := v.Args[0]
 12430  		w := v.Args[1]
 12431  		x0 := v.Args[2]
 12432  		if x0.Op != OpAMD64MOVBstore || x0.AuxInt != i-1 || x0.Aux != s {
 12433  			break
 12434  		}
 12435  		mem := x0.Args[2]
 12436  		if p != x0.Args[0] {
 12437  			break
 12438  		}
 12439  		x0_1 := x0.Args[1]
 12440  		if x0_1.Op != OpAMD64SHRWconst || x0_1.AuxInt != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && clobber(x0)) {
 12441  			break
 12442  		}
 12443  		v.reset(OpAMD64MOVWstore)
 12444  		v.AuxInt = i - 1
 12445  		v.Aux = s
 12446  		v.AddArg(p)
 12447  		v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type)
 12448  		v0.AuxInt = 8
 12449  		v0.AddArg(w)
 12450  		v.AddArg(v0)
 12451  		v.AddArg(mem)
 12452  		return true
 12453  	}
 12454  	// match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem))))
 12455  	// cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)
 12456  	// result: (MOVLstore [i-3] {s} p (BSWAPL <w.Type> w) mem)
 12457  	for {
 12458  		i := v.AuxInt
 12459  		s := v.Aux
 12460  		_ = v.Args[2]
 12461  		p := v.Args[0]
 12462  		w := v.Args[1]
 12463  		x2 := v.Args[2]
 12464  		if x2.Op != OpAMD64MOVBstore || x2.AuxInt != i-1 || x2.Aux != s {
 12465  			break
 12466  		}
 12467  		_ = x2.Args[2]
 12468  		if p != x2.Args[0] {
 12469  			break
 12470  		}
 12471  		x2_1 := x2.Args[1]
 12472  		if x2_1.Op != OpAMD64SHRLconst || x2_1.AuxInt != 8 || w != x2_1.Args[0] {
 12473  			break
 12474  		}
 12475  		x1 := x2.Args[2]
 12476  		if x1.Op != OpAMD64MOVBstore || x1.AuxInt != i-2 || x1.Aux != s {
 12477  			break
 12478  		}
 12479  		_ = x1.Args[2]
 12480  		if p != x1.Args[0] {
 12481  			break
 12482  		}
 12483  		x1_1 := x1.Args[1]
 12484  		if x1_1.Op != OpAMD64SHRLconst || x1_1.AuxInt != 16 || w != x1_1.Args[0] {
 12485  			break
 12486  		}
 12487  		x0 := x1.Args[2]
 12488  		if x0.Op != OpAMD64MOVBstore || x0.AuxInt != i-3 || x0.Aux != s {
 12489  			break
 12490  		}
 12491  		mem := x0.Args[2]
 12492  		if p != x0.Args[0] {
 12493  			break
 12494  		}
 12495  		x0_1 := x0.Args[1]
 12496  		if x0_1.Op != OpAMD64SHRLconst || x0_1.AuxInt != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) {
 12497  			break
 12498  		}
 12499  		v.reset(OpAMD64MOVLstore)
 12500  		v.AuxInt = i - 3
 12501  		v.Aux = s
 12502  		v.AddArg(p)
 12503  		v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type)
 12504  		v0.AddArg(w)
 12505  		v.AddArg(v0)
 12506  		v.AddArg(mem)
 12507  		return true
 12508  	}
 12509  	return false
 12510  }
 12511  func rewriteValueAMD64_OpAMD64MOVBstore_20(v *Value) bool {
 12512  	b := v.Block
 12513  	typ := &b.Func.Config.Types
 12514  	// match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem))))))))
 12515  	// cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)
 12516  	// result: (MOVQstore [i-7] {s} p (BSWAPQ <w.Type> w) mem)
 12517  	for {
 12518  		i := v.AuxInt
 12519  		s := v.Aux
 12520  		_ = v.Args[2]
 12521  		p := v.Args[0]
 12522  		w := v.Args[1]
 12523  		x6 := v.Args[2]
 12524  		if x6.Op != OpAMD64MOVBstore || x6.AuxInt != i-1 || x6.Aux != s {
 12525  			break
 12526  		}
 12527  		_ = x6.Args[2]
 12528  		if p != x6.Args[0] {
 12529  			break
 12530  		}
 12531  		x6_1 := x6.Args[1]
 12532  		if x6_1.Op != OpAMD64SHRQconst || x6_1.AuxInt != 8 || w != x6_1.Args[0] {
 12533  			break
 12534  		}
 12535  		x5 := x6.Args[2]
 12536  		if x5.Op != OpAMD64MOVBstore || x5.AuxInt != i-2 || x5.Aux != s {
 12537  			break
 12538  		}
 12539  		_ = x5.Args[2]
 12540  		if p != x5.Args[0] {
 12541  			break
 12542  		}
 12543  		x5_1 := x5.Args[1]
 12544  		if x5_1.Op != OpAMD64SHRQconst || x5_1.AuxInt != 16 || w != x5_1.Args[0] {
 12545  			break
 12546  		}
 12547  		x4 := x5.Args[2]
 12548  		if x4.Op != OpAMD64MOVBstore || x4.AuxInt != i-3 || x4.Aux != s {
 12549  			break
 12550  		}
 12551  		_ = x4.Args[2]
 12552  		if p != x4.Args[0] {
 12553  			break
 12554  		}
 12555  		x4_1 := x4.Args[1]
 12556  		if x4_1.Op != OpAMD64SHRQconst || x4_1.AuxInt != 24 || w != x4_1.Args[0] {
 12557  			break
 12558  		}
 12559  		x3 := x4.Args[2]
 12560  		if x3.Op != OpAMD64MOVBstore || x3.AuxInt != i-4 || x3.Aux != s {
 12561  			break
 12562  		}
 12563  		_ = x3.Args[2]
 12564  		if p != x3.Args[0] {
 12565  			break
 12566  		}
 12567  		x3_1 := x3.Args[1]
 12568  		if x3_1.Op != OpAMD64SHRQconst || x3_1.AuxInt != 32 || w != x3_1.Args[0] {
 12569  			break
 12570  		}
 12571  		x2 := x3.Args[2]
 12572  		if x2.Op != OpAMD64MOVBstore || x2.AuxInt != i-5 || x2.Aux != s {
 12573  			break
 12574  		}
 12575  		_ = x2.Args[2]
 12576  		if p != x2.Args[0] {
 12577  			break
 12578  		}
 12579  		x2_1 := x2.Args[1]
 12580  		if x2_1.Op != OpAMD64SHRQconst || x2_1.AuxInt != 40 || w != x2_1.Args[0] {
 12581  			break
 12582  		}
 12583  		x1 := x2.Args[2]
 12584  		if x1.Op != OpAMD64MOVBstore || x1.AuxInt != i-6 || x1.Aux != s {
 12585  			break
 12586  		}
 12587  		_ = x1.Args[2]
 12588  		if p != x1.Args[0] {
 12589  			break
 12590  		}
 12591  		x1_1 := x1.Args[1]
 12592  		if x1_1.Op != OpAMD64SHRQconst || x1_1.AuxInt != 48 || w != x1_1.Args[0] {
 12593  			break
 12594  		}
 12595  		x0 := x1.Args[2]
 12596  		if x0.Op != OpAMD64MOVBstore || x0.AuxInt != i-7 || x0.Aux != s {
 12597  			break
 12598  		}
 12599  		mem := x0.Args[2]
 12600  		if p != x0.Args[0] {
 12601  			break
 12602  		}
 12603  		x0_1 := x0.Args[1]
 12604  		if x0_1.Op != OpAMD64SHRQconst || x0_1.AuxInt != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) {
 12605  			break
 12606  		}
 12607  		v.reset(OpAMD64MOVQstore)
 12608  		v.AuxInt = i - 7
 12609  		v.Aux = s
 12610  		v.AddArg(p)
 12611  		v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type)
 12612  		v0.AddArg(w)
 12613  		v.AddArg(v0)
 12614  		v.AddArg(mem)
 12615  		return true
 12616  	}
 12617  	// match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem))
 12618  	// cond: x.Uses == 1 && clobber(x)
 12619  	// result: (MOVWstore [i-1] {s} p w mem)
 12620  	for {
 12621  		i := v.AuxInt
 12622  		s := v.Aux
 12623  		_ = v.Args[2]
 12624  		p := v.Args[0]
 12625  		v_1 := v.Args[1]
 12626  		if v_1.Op != OpAMD64SHRWconst || v_1.AuxInt != 8 {
 12627  			break
 12628  		}
 12629  		w := v_1.Args[0]
 12630  		x := v.Args[2]
 12631  		if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s {
 12632  			break
 12633  		}
 12634  		mem := x.Args[2]
 12635  		if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) {
 12636  			break
 12637  		}
 12638  		v.reset(OpAMD64MOVWstore)
 12639  		v.AuxInt = i - 1
 12640  		v.Aux = s
 12641  		v.AddArg(p)
 12642  		v.AddArg(w)
 12643  		v.AddArg(mem)
 12644  		return true
 12645  	}
 12646  	// match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem))
 12647  	// cond: x.Uses == 1 && clobber(x)
 12648  	// result: (MOVWstore [i-1] {s} p w mem)
 12649  	for {
 12650  		i := v.AuxInt
 12651  		s := v.Aux
 12652  		_ = v.Args[2]
 12653  		p := v.Args[0]
 12654  		v_1 := v.Args[1]
 12655  		if v_1.Op != OpAMD64SHRLconst || v_1.AuxInt != 8 {
 12656  			break
 12657  		}
 12658  		w := v_1.Args[0]
 12659  		x := v.Args[2]
 12660  		if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s {
 12661  			break
 12662  		}
 12663  		mem := x.Args[2]
 12664  		if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) {
 12665  			break
 12666  		}
 12667  		v.reset(OpAMD64MOVWstore)
 12668  		v.AuxInt = i - 1
 12669  		v.Aux = s
 12670  		v.AddArg(p)
 12671  		v.AddArg(w)
 12672  		v.AddArg(mem)
 12673  		return true
 12674  	}
 12675  	// match: (MOVBstore [i] {s} p (SHRQconst [8] w) x:(MOVBstore [i-1] {s} p w mem))
 12676  	// cond: x.Uses == 1 && clobber(x)
 12677  	// result: (MOVWstore [i-1] {s} p w mem)
 12678  	for {
 12679  		i := v.AuxInt
 12680  		s := v.Aux
 12681  		_ = v.Args[2]
 12682  		p := v.Args[0]
 12683  		v_1 := v.Args[1]
 12684  		if v_1.Op != OpAMD64SHRQconst || v_1.AuxInt != 8 {
 12685  			break
 12686  		}
 12687  		w := v_1.Args[0]
 12688  		x := v.Args[2]
 12689  		if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s {
 12690  			break
 12691  		}
 12692  		mem := x.Args[2]
 12693  		if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) {
 12694  			break
 12695  		}
 12696  		v.reset(OpAMD64MOVWstore)
 12697  		v.AuxInt = i - 1
 12698  		v.Aux = s
 12699  		v.AddArg(p)
 12700  		v.AddArg(w)
 12701  		v.AddArg(mem)
 12702  		return true
 12703  	}
 12704  	// match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRWconst [8] w) mem))
 12705  	// cond: x.Uses == 1 && clobber(x)
 12706  	// result: (MOVWstore [i] {s} p w mem)
 12707  	for {
 12708  		i := v.AuxInt
 12709  		s := v.Aux
 12710  		_ = v.Args[2]
 12711  		p := v.Args[0]
 12712  		w := v.Args[1]
 12713  		x := v.Args[2]
 12714  		if x.Op != OpAMD64MOVBstore || x.AuxInt != i+1 || x.Aux != s {
 12715  			break
 12716  		}
 12717  		mem := x.Args[2]
 12718  		if p != x.Args[0] {
 12719  			break
 12720  		}
 12721  		x_1 := x.Args[1]
 12722  		if x_1.Op != OpAMD64SHRWconst || x_1.AuxInt != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) {
 12723  			break
 12724  		}
 12725  		v.reset(OpAMD64MOVWstore)
 12726  		v.AuxInt = i
 12727  		v.Aux = s
 12728  		v.AddArg(p)
 12729  		v.AddArg(w)
 12730  		v.AddArg(mem)
 12731  		return true
 12732  	}
 12733  	// match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRLconst [8] w) mem))
 12734  	// cond: x.Uses == 1 && clobber(x)
 12735  	// result: (MOVWstore [i] {s} p w mem)
 12736  	for {
 12737  		i := v.AuxInt
 12738  		s := v.Aux
 12739  		_ = v.Args[2]
 12740  		p := v.Args[0]
 12741  		w := v.Args[1]
 12742  		x := v.Args[2]
 12743  		if x.Op != OpAMD64MOVBstore || x.AuxInt != i+1 || x.Aux != s {
 12744  			break
 12745  		}
 12746  		mem := x.Args[2]
 12747  		if p != x.Args[0] {
 12748  			break
 12749  		}
 12750  		x_1 := x.Args[1]
 12751  		if x_1.Op != OpAMD64SHRLconst || x_1.AuxInt != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) {
 12752  			break
 12753  		}
 12754  		v.reset(OpAMD64MOVWstore)
 12755  		v.AuxInt = i
 12756  		v.Aux = s
 12757  		v.AddArg(p)
 12758  		v.AddArg(w)
 12759  		v.AddArg(mem)
 12760  		return true
 12761  	}
 12762  	// match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRQconst [8] w) mem))
 12763  	// cond: x.Uses == 1 && clobber(x)
 12764  	// result: (MOVWstore [i] {s} p w mem)
 12765  	for {
 12766  		i := v.AuxInt
 12767  		s := v.Aux
 12768  		_ = v.Args[2]
 12769  		p := v.Args[0]
 12770  		w := v.Args[1]
 12771  		x := v.Args[2]
 12772  		if x.Op != OpAMD64MOVBstore || x.AuxInt != i+1 || x.Aux != s {
 12773  			break
 12774  		}
 12775  		mem := x.Args[2]
 12776  		if p != x.Args[0] {
 12777  			break
 12778  		}
 12779  		x_1 := x.Args[1]
 12780  		if x_1.Op != OpAMD64SHRQconst || x_1.AuxInt != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) {
 12781  			break
 12782  		}
 12783  		v.reset(OpAMD64MOVWstore)
 12784  		v.AuxInt = i
 12785  		v.Aux = s
 12786  		v.AddArg(p)
 12787  		v.AddArg(w)
 12788  		v.AddArg(mem)
 12789  		return true
 12790  	}
 12791  	// match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem))
 12792  	// cond: x.Uses == 1 && clobber(x)
 12793  	// result: (MOVWstore [i-1] {s} p w0 mem)
 12794  	for {
 12795  		i := v.AuxInt
 12796  		s := v.Aux
 12797  		_ = v.Args[2]
 12798  		p := v.Args[0]
 12799  		v_1 := v.Args[1]
 12800  		if v_1.Op != OpAMD64SHRLconst {
 12801  			break
 12802  		}
 12803  		j := v_1.AuxInt
 12804  		w := v_1.Args[0]
 12805  		x := v.Args[2]
 12806  		if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s {
 12807  			break
 12808  		}
 12809  		mem := x.Args[2]
 12810  		if p != x.Args[0] {
 12811  			break
 12812  		}
 12813  		w0 := x.Args[1]
 12814  		if w0.Op != OpAMD64SHRLconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) {
 12815  			break
 12816  		}
 12817  		v.reset(OpAMD64MOVWstore)
 12818  		v.AuxInt = i - 1
 12819  		v.Aux = s
 12820  		v.AddArg(p)
 12821  		v.AddArg(w0)
 12822  		v.AddArg(mem)
 12823  		return true
 12824  	}
 12825  	// match: (MOVBstore [i] {s} p (SHRQconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRQconst [j-8] w) mem))
 12826  	// cond: x.Uses == 1 && clobber(x)
 12827  	// result: (MOVWstore [i-1] {s} p w0 mem)
 12828  	for {
 12829  		i := v.AuxInt
 12830  		s := v.Aux
 12831  		_ = v.Args[2]
 12832  		p := v.Args[0]
 12833  		v_1 := v.Args[1]
 12834  		if v_1.Op != OpAMD64SHRQconst {
 12835  			break
 12836  		}
 12837  		j := v_1.AuxInt
 12838  		w := v_1.Args[0]
 12839  		x := v.Args[2]
 12840  		if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s {
 12841  			break
 12842  		}
 12843  		mem := x.Args[2]
 12844  		if p != x.Args[0] {
 12845  			break
 12846  		}
 12847  		w0 := x.Args[1]
 12848  		if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) {
 12849  			break
 12850  		}
 12851  		v.reset(OpAMD64MOVWstore)
 12852  		v.AuxInt = i - 1
 12853  		v.Aux = s
 12854  		v.AddArg(p)
 12855  		v.AddArg(w0)
 12856  		v.AddArg(mem)
 12857  		return true
 12858  	}
 12859  	// match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem))
 12860  	// cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2)
 12861  	// result: (MOVWstore [i-1] {s} p (MOVWload [j-1] {s2} p2 mem) mem)
 12862  	for {
 12863  		i := v.AuxInt
 12864  		s := v.Aux
 12865  		_ = v.Args[2]
 12866  		p := v.Args[0]
 12867  		x1 := v.Args[1]
 12868  		if x1.Op != OpAMD64MOVBload {
 12869  			break
 12870  		}
 12871  		j := x1.AuxInt
 12872  		s2 := x1.Aux
 12873  		mem := x1.Args[1]
 12874  		p2 := x1.Args[0]
 12875  		mem2 := v.Args[2]
 12876  		if mem2.Op != OpAMD64MOVBstore || mem2.AuxInt != i-1 || mem2.Aux != s {
 12877  			break
 12878  		}
 12879  		_ = mem2.Args[2]
 12880  		if p != mem2.Args[0] {
 12881  			break
 12882  		}
 12883  		x2 := mem2.Args[1]
 12884  		if x2.Op != OpAMD64MOVBload || x2.AuxInt != j-1 || x2.Aux != s2 {
 12885  			break
 12886  		}
 12887  		_ = x2.Args[1]
 12888  		if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2)) {
 12889  			break
 12890  		}
 12891  		v.reset(OpAMD64MOVWstore)
 12892  		v.AuxInt = i - 1
 12893  		v.Aux = s
 12894  		v.AddArg(p)
 12895  		v0 := b.NewValue0(x2.Pos, OpAMD64MOVWload, typ.UInt16)
 12896  		v0.AuxInt = j - 1
 12897  		v0.Aux = s2
 12898  		v0.AddArg(p2)
 12899  		v0.AddArg(mem)
 12900  		v.AddArg(v0)
 12901  		v.AddArg(mem)
 12902  		return true
 12903  	}
 12904  	return false
 12905  }
 12906  func rewriteValueAMD64_OpAMD64MOVBstore_30(v *Value) bool {
 12907  	// match: (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
 12908  	// cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2)
 12909  	// result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
 12910  	for {
 12911  		off1 := v.AuxInt
 12912  		sym1 := v.Aux
 12913  		mem := v.Args[2]
 12914  		v_0 := v.Args[0]
 12915  		if v_0.Op != OpAMD64LEAL {
 12916  			break
 12917  		}
 12918  		off2 := v_0.AuxInt
 12919  		sym2 := v_0.Aux
 12920  		base := v_0.Args[0]
 12921  		val := v.Args[1]
 12922  		if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) {
 12923  			break
 12924  		}
 12925  		v.reset(OpAMD64MOVBstore)
 12926  		v.AuxInt = off1 + off2
 12927  		v.Aux = mergeSym(sym1, sym2)
 12928  		v.AddArg(base)
 12929  		v.AddArg(val)
 12930  		v.AddArg(mem)
 12931  		return true
 12932  	}
 12933  	// match: (MOVBstore [off1] {sym} (ADDLconst [off2] ptr) val mem)
 12934  	// cond: is32Bit(off1+off2)
 12935  	// result: (MOVBstore [off1+off2] {sym} ptr val mem)
 12936  	for {
 12937  		off1 := v.AuxInt
 12938  		sym := v.Aux
 12939  		mem := v.Args[2]
 12940  		v_0 := v.Args[0]
 12941  		if v_0.Op != OpAMD64ADDLconst {
 12942  			break
 12943  		}
 12944  		off2 := v_0.AuxInt
 12945  		ptr := v_0.Args[0]
 12946  		val := v.Args[1]
 12947  		if !(is32Bit(off1 + off2)) {
 12948  			break
 12949  		}
 12950  		v.reset(OpAMD64MOVBstore)
 12951  		v.AuxInt = off1 + off2
 12952  		v.Aux = sym
 12953  		v.AddArg(ptr)
 12954  		v.AddArg(val)
 12955  		v.AddArg(mem)
 12956  		return true
 12957  	}
 12958  	return false
 12959  }
 12960  func rewriteValueAMD64_OpAMD64MOVBstoreconst_0(v *Value) bool {
 12961  	// match: (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem)
 12962  	// cond: ValAndOff(sc).canAdd(off)
 12963  	// result: (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem)
 12964  	for {
 12965  		sc := v.AuxInt
 12966  		s := v.Aux
 12967  		mem := v.Args[1]
 12968  		v_0 := v.Args[0]
 12969  		if v_0.Op != OpAMD64ADDQconst {
 12970  			break
 12971  		}
 12972  		off := v_0.AuxInt
 12973  		ptr := v_0.Args[0]
 12974  		if !(ValAndOff(sc).canAdd(off)) {
 12975  			break
 12976  		}
 12977  		v.reset(OpAMD64MOVBstoreconst)
 12978  		v.AuxInt = ValAndOff(sc).add(off)
 12979  		v.Aux = s
 12980  		v.AddArg(ptr)
 12981  		v.AddArg(mem)
 12982  		return true
 12983  	}
 12984  	// match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem)
 12985  	// cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)
 12986  	// result: (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem)
 12987  	for {
 12988  		sc := v.AuxInt
 12989  		sym1 := v.Aux
 12990  		mem := v.Args[1]
 12991  		v_0 := v.Args[0]
 12992  		if v_0.Op != OpAMD64LEAQ {
 12993  			break
 12994  		}
 12995  		off := v_0.AuxInt
 12996  		sym2 := v_0.Aux
 12997  		ptr := v_0.Args[0]
 12998  		if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) {
 12999  			break
 13000  		}
 13001  		v.reset(OpAMD64MOVBstoreconst)
 13002  		v.AuxInt = ValAndOff(sc).add(off)
 13003  		v.Aux = mergeSym(sym1, sym2)
 13004  		v.AddArg(ptr)
 13005  		v.AddArg(mem)
 13006  		return true
 13007  	}
 13008  	// match: (MOVBstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem)
 13009  	// cond: canMergeSym(sym1, sym2)
 13010  	// result: (MOVBstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem)
 13011  	for {
 13012  		x := v.AuxInt
 13013  		sym1 := v.Aux
 13014  		mem := v.Args[1]
 13015  		v_0 := v.Args[0]
 13016  		if v_0.Op != OpAMD64LEAQ1 {
 13017  			break
 13018  		}
 13019  		off := v_0.AuxInt
 13020  		sym2 := v_0.Aux
 13021  		idx := v_0.Args[1]
 13022  		ptr := v_0.Args[0]
 13023  		if !(canMergeSym(sym1, sym2)) {
 13024  			break
 13025  		}
 13026  		v.reset(OpAMD64MOVBstoreconstidx1)
 13027  		v.AuxInt = ValAndOff(x).add(off)
 13028  		v.Aux = mergeSym(sym1, sym2)
 13029  		v.AddArg(ptr)
 13030  		v.AddArg(idx)
 13031  		v.AddArg(mem)
 13032  		return true
 13033  	}
 13034  	// match: (MOVBstoreconst [x] {sym} (ADDQ ptr idx) mem)
 13035  	// result: (MOVBstoreconstidx1 [x] {sym} ptr idx mem)
 13036  	for {
 13037  		x := v.AuxInt
 13038  		sym := v.Aux
 13039  		mem := v.Args[1]
 13040  		v_0 := v.Args[0]
 13041  		if v_0.Op != OpAMD64ADDQ {
 13042  			break
 13043  		}
 13044  		idx := v_0.Args[1]
 13045  		ptr := v_0.Args[0]
 13046  		v.reset(OpAMD64MOVBstoreconstidx1)
 13047  		v.AuxInt = x
 13048  		v.Aux = sym
 13049  		v.AddArg(ptr)
 13050  		v.AddArg(idx)
 13051  		v.AddArg(mem)
 13052  		return true
 13053  	}
 13054  	// match: (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem))
 13055  	// cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x)
 13056  	// result: (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem)
 13057  	for {
 13058  		c := v.AuxInt
 13059  		s := v.Aux
 13060  		_ = v.Args[1]
 13061  		p := v.Args[0]
 13062  		x := v.Args[1]
 13063  		if x.Op != OpAMD64MOVBstoreconst {
 13064  			break
 13065  		}
 13066  		a := x.AuxInt
 13067  		if x.Aux != s {
 13068  			break
 13069  		}
 13070  		mem := x.Args[1]
 13071  		if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) {
 13072  			break
 13073  		}
 13074  		v.reset(OpAMD64MOVWstoreconst)
 13075  		v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off())
 13076  		v.Aux = s
 13077  		v.AddArg(p)
 13078  		v.AddArg(mem)
 13079  		return true
 13080  	}
 13081  	// match: (MOVBstoreconst [a] {s} p x:(MOVBstoreconst [c] {s} p mem))
 13082  	// cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x)
 13083  	// result: (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem)
 13084  	for {
 13085  		a := v.AuxInt
 13086  		s := v.Aux
 13087  		_ = v.Args[1]
 13088  		p := v.Args[0]
 13089  		x := v.Args[1]
 13090  		if x.Op != OpAMD64MOVBstoreconst {
 13091  			break
 13092  		}
 13093  		c := x.AuxInt
 13094  		if x.Aux != s {
 13095  			break
 13096  		}
 13097  		mem := x.Args[1]
 13098  		if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) {
 13099  			break
 13100  		}
 13101  		v.reset(OpAMD64MOVWstoreconst)
 13102  		v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off())
 13103  		v.Aux = s
 13104  		v.AddArg(p)
 13105  		v.AddArg(mem)
 13106  		return true
 13107  	}
 13108  	// match: (MOVBstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem)
 13109  	// cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)
 13110  	// result: (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem)
 13111  	for {
 13112  		sc := v.AuxInt
 13113  		sym1 := v.Aux
 13114  		mem := v.Args[1]
 13115  		v_0 := v.Args[0]
 13116  		if v_0.Op != OpAMD64LEAL {
 13117  			break
 13118  		}
 13119  		off := v_0.AuxInt
 13120  		sym2 := v_0.Aux
 13121  		ptr := v_0.Args[0]
 13122  		if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) {
 13123  			break
 13124  		}
 13125  		v.reset(OpAMD64MOVBstoreconst)
 13126  		v.AuxInt = ValAndOff(sc).add(off)
 13127  		v.Aux = mergeSym(sym1, sym2)
 13128  		v.AddArg(ptr)
 13129  		v.AddArg(mem)
 13130  		return true
 13131  	}
 13132  	// match: (MOVBstoreconst [sc] {s} (ADDLconst [off] ptr) mem)
 13133  	// cond: ValAndOff(sc).canAdd(off)
 13134  	// result: (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem)
 13135  	for {
 13136  		sc := v.AuxInt
 13137  		s := v.Aux
 13138  		mem := v.Args[1]
 13139  		v_0 := v.Args[0]
 13140  		if v_0.Op != OpAMD64ADDLconst {
 13141  			break
 13142  		}
 13143  		off := v_0.AuxInt
 13144  		ptr := v_0.Args[0]
 13145  		if !(ValAndOff(sc).canAdd(off)) {
 13146  			break
 13147  		}
 13148  		v.reset(OpAMD64MOVBstoreconst)
 13149  		v.AuxInt = ValAndOff(sc).add(off)
 13150  		v.Aux = s
 13151  		v.AddArg(ptr)
 13152  		v.AddArg(mem)
 13153  		return true
 13154  	}
 13155  	return false
 13156  }
 13157  func rewriteValueAMD64_OpAMD64MOVBstoreconstidx1_0(v *Value) bool {
 13158  	// match: (MOVBstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem)
 13159  	// cond: ValAndOff(x).canAdd(c)
 13160  	// result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem)
 13161  	for {
 13162  		x := v.AuxInt
 13163  		sym := v.Aux
 13164  		mem := v.Args[2]
 13165  		v_0 := v.Args[0]
 13166  		if v_0.Op != OpAMD64ADDQconst {
 13167  			break
 13168  		}
 13169  		c := v_0.AuxInt
 13170  		ptr := v_0.Args[0]
 13171  		idx := v.Args[1]
 13172  		if !(ValAndOff(x).canAdd(c)) {
 13173  			break
 13174  		}
 13175  		v.reset(OpAMD64MOVBstoreconstidx1)
 13176  		v.AuxInt = ValAndOff(x).add(c)
 13177  		v.Aux = sym
 13178  		v.AddArg(ptr)
 13179  		v.AddArg(idx)
 13180  		v.AddArg(mem)
 13181  		return true
 13182  	}
 13183  	// match: (MOVBstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem)
 13184  	// cond: ValAndOff(x).canAdd(c)
 13185  	// result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem)
 13186  	for {
 13187  		x := v.AuxInt
 13188  		sym := v.Aux
 13189  		mem := v.Args[2]
 13190  		ptr := v.Args[0]
 13191  		v_1 := v.Args[1]
 13192  		if v_1.Op != OpAMD64ADDQconst {
 13193  			break
 13194  		}
 13195  		c := v_1.AuxInt
 13196  		idx := v_1.Args[0]
 13197  		if !(ValAndOff(x).canAdd(c)) {
 13198  			break
 13199  		}
 13200  		v.reset(OpAMD64MOVBstoreconstidx1)
 13201  		v.AuxInt = ValAndOff(x).add(c)
 13202  		v.Aux = sym
 13203  		v.AddArg(ptr)
 13204  		v.AddArg(idx)
 13205  		v.AddArg(mem)
 13206  		return true
 13207  	}
 13208  	// match: (MOVBstoreconstidx1 [c] {s} p i x:(MOVBstoreconstidx1 [a] {s} p i mem))
 13209  	// cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x)
 13210  	// result: (MOVWstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p i mem)
 13211  	for {
 13212  		c := v.AuxInt
 13213  		s := v.Aux
 13214  		_ = v.Args[2]
 13215  		p := v.Args[0]
 13216  		i := v.Args[1]
 13217  		x := v.Args[2]
 13218  		if x.Op != OpAMD64MOVBstoreconstidx1 {
 13219  			break
 13220  		}
 13221  		a := x.AuxInt
 13222  		if x.Aux != s {
 13223  			break
 13224  		}
 13225  		mem := x.Args[2]
 13226  		if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) {
 13227  			break
 13228  		}
 13229  		v.reset(OpAMD64MOVWstoreconstidx1)
 13230  		v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off())
 13231  		v.Aux = s
 13232  		v.AddArg(p)
 13233  		v.AddArg(i)
 13234  		v.AddArg(mem)
 13235  		return true
 13236  	}
 13237  	return false
 13238  }
 13239  func rewriteValueAMD64_OpAMD64MOVBstoreidx1_0(v *Value) bool {
 13240  	b := v.Block
 13241  	// match: (MOVBstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem)
 13242  	// cond: is32Bit(c+d)
 13243  	// result: (MOVBstoreidx1 [c+d] {sym} ptr idx val mem)
 13244  	for {
 13245  		c := v.AuxInt
 13246  		sym := v.Aux
 13247  		mem := v.Args[3]
 13248  		v_0 := v.Args[0]
 13249  		if v_0.Op != OpAMD64ADDQconst {
 13250  			break
 13251  		}
 13252  		d := v_0.AuxInt
 13253  		ptr := v_0.Args[0]
 13254  		idx := v.Args[1]
 13255  		val := v.Args[2]
 13256  		if !(is32Bit(c + d)) {
 13257  			break
 13258  		}
 13259  		v.reset(OpAMD64MOVBstoreidx1)
 13260  		v.AuxInt = c + d
 13261  		v.Aux = sym
 13262  		v.AddArg(ptr)
 13263  		v.AddArg(idx)
 13264  		v.AddArg(val)
 13265  		v.AddArg(mem)
 13266  		return true
 13267  	}
 13268  	// match: (MOVBstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem)
 13269  	// cond: is32Bit(c+d)
 13270  	// result: (MOVBstoreidx1 [c+d] {sym} ptr idx val mem)
 13271  	for {
 13272  		c := v.AuxInt
 13273  		sym := v.Aux
 13274  		mem := v.Args[3]
 13275  		ptr := v.Args[0]
 13276  		v_1 := v.Args[1]
 13277  		if v_1.Op != OpAMD64ADDQconst {
 13278  			break
 13279  		}
 13280  		d := v_1.AuxInt
 13281  		idx := v_1.Args[0]
 13282  		val := v.Args[2]
 13283  		if !(is32Bit(c + d)) {
 13284  			break
 13285  		}
 13286  		v.reset(OpAMD64MOVBstoreidx1)
 13287  		v.AuxInt = c + d
 13288  		v.Aux = sym
 13289  		v.AddArg(ptr)
 13290  		v.AddArg(idx)
 13291  		v.AddArg(val)
 13292  		v.AddArg(mem)
 13293  		return true
 13294  	}
 13295  	// match: (MOVBstoreidx1 [i] {s} p idx w x0:(MOVBstoreidx1 [i-1] {s} p idx (SHRWconst [8] w) mem))
 13296  	// cond: x0.Uses == 1 && clobber(x0)
 13297  	// result: (MOVWstoreidx1 [i-1] {s} p idx (ROLWconst <w.Type> [8] w) mem)
 13298  	for {
 13299  		i := v.AuxInt
 13300  		s := v.Aux
 13301  		_ = v.Args[3]
 13302  		p := v.Args[0]
 13303  		idx := v.Args[1]
 13304  		w := v.Args[2]
 13305  		x0 := v.Args[3]
 13306  		if x0.Op != OpAMD64MOVBstoreidx1 || x0.AuxInt != i-1 || x0.Aux != s {
 13307  			break
 13308  		}
 13309  		mem := x0.Args[3]
 13310  		if p != x0.Args[0] || idx != x0.Args[1] {
 13311  			break
 13312  		}
 13313  		x0_2 := x0.Args[2]
 13314  		if x0_2.Op != OpAMD64SHRWconst || x0_2.AuxInt != 8 || w != x0_2.Args[0] || !(x0.Uses == 1 && clobber(x0)) {
 13315  			break
 13316  		}
 13317  		v.reset(OpAMD64MOVWstoreidx1)
 13318  		v.AuxInt = i - 1
 13319  		v.Aux = s
 13320  		v.AddArg(p)
 13321  		v.AddArg(idx)
 13322  		v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, w.Type)
 13323  		v0.AuxInt = 8
 13324  		v0.AddArg(w)
 13325  		v.AddArg(v0)
 13326  		v.AddArg(mem)
 13327  		return true
 13328  	}
 13329  	// match: (MOVBstoreidx1 [i] {s} p idx w x2:(MOVBstoreidx1 [i-1] {s} p idx (SHRLconst [8] w) x1:(MOVBstoreidx1 [i-2] {s} p idx (SHRLconst [16] w) x0:(MOVBstoreidx1 [i-3] {s} p idx (SHRLconst [24] w) mem))))
 13330  	// cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)
 13331  	// result: (MOVLstoreidx1 [i-3] {s} p idx (BSWAPL <w.Type> w) mem)
 13332  	for {
 13333  		i := v.AuxInt
 13334  		s := v.Aux
 13335  		_ = v.Args[3]
 13336  		p := v.Args[0]
 13337  		idx := v.Args[1]
 13338  		w := v.Args[2]
 13339  		x2 := v.Args[3]
 13340  		if x2.Op != OpAMD64MOVBstoreidx1 || x2.AuxInt != i-1 || x2.Aux != s {
 13341  			break
 13342  		}
 13343  		_ = x2.Args[3]
 13344  		if p != x2.Args[0] || idx != x2.Args[1] {
 13345  			break
 13346  		}
 13347  		x2_2 := x2.Args[2]
 13348  		if x2_2.Op != OpAMD64SHRLconst || x2_2.AuxInt != 8 || w != x2_2.Args[0] {
 13349  			break
 13350  		}
 13351  		x1 := x2.Args[3]
 13352  		if x1.Op != OpAMD64MOVBstoreidx1 || x1.AuxInt != i-2 || x1.Aux != s {
 13353  			break
 13354  		}
 13355  		_ = x1.Args[3]
 13356  		if p != x1.Args[0] || idx != x1.Args[1] {
 13357  			break
 13358  		}
 13359  		x1_2 := x1.Args[2]
 13360  		if x1_2.Op != OpAMD64SHRLconst || x1_2.AuxInt != 16 || w != x1_2.Args[0] {
 13361  			break
 13362  		}
 13363  		x0 := x1.Args[3]
 13364  		if x0.Op != OpAMD64MOVBstoreidx1 || x0.AuxInt != i-3 || x0.Aux != s {
 13365  			break
 13366  		}
 13367  		mem := x0.Args[3]
 13368  		if p != x0.Args[0] || idx != x0.Args[1] {