Source file src/cmd/compile/internal/ssa/rewriteAMD64.go

Documentation: cmd/compile/internal/ssa

     1  // Code generated from gen/AMD64.rules; DO NOT EDIT.
     2  // generated with: cd gen; go run *.go
     3  
     4  package ssa
     5  
     6  import "fmt"
     7  import "math"
     8  import "cmd/internal/obj"
     9  import "cmd/internal/objabi"
    10  import "cmd/compile/internal/types"
    11  
    12  var _ = fmt.Println   // in case not otherwise used
    13  var _ = math.MinInt8  // in case not otherwise used
    14  var _ = obj.ANOP      // in case not otherwise used
    15  var _ = objabi.GOROOT // in case not otherwise used
    16  var _ = types.TypeMem // in case not otherwise used
    17  
    18  func rewriteValueAMD64(v *Value) bool {
    19  	switch v.Op {
    20  	case OpAMD64ADCQ:
    21  		return rewriteValueAMD64_OpAMD64ADCQ_0(v)
    22  	case OpAMD64ADCQconst:
    23  		return rewriteValueAMD64_OpAMD64ADCQconst_0(v)
    24  	case OpAMD64ADDL:
    25  		return rewriteValueAMD64_OpAMD64ADDL_0(v) || rewriteValueAMD64_OpAMD64ADDL_10(v) || rewriteValueAMD64_OpAMD64ADDL_20(v)
    26  	case OpAMD64ADDLconst:
    27  		return rewriteValueAMD64_OpAMD64ADDLconst_0(v) || rewriteValueAMD64_OpAMD64ADDLconst_10(v)
    28  	case OpAMD64ADDLconstmodify:
    29  		return rewriteValueAMD64_OpAMD64ADDLconstmodify_0(v)
    30  	case OpAMD64ADDLload:
    31  		return rewriteValueAMD64_OpAMD64ADDLload_0(v)
    32  	case OpAMD64ADDLmodify:
    33  		return rewriteValueAMD64_OpAMD64ADDLmodify_0(v)
    34  	case OpAMD64ADDQ:
    35  		return rewriteValueAMD64_OpAMD64ADDQ_0(v) || rewriteValueAMD64_OpAMD64ADDQ_10(v) || rewriteValueAMD64_OpAMD64ADDQ_20(v)
    36  	case OpAMD64ADDQcarry:
    37  		return rewriteValueAMD64_OpAMD64ADDQcarry_0(v)
    38  	case OpAMD64ADDQconst:
    39  		return rewriteValueAMD64_OpAMD64ADDQconst_0(v) || rewriteValueAMD64_OpAMD64ADDQconst_10(v)
    40  	case OpAMD64ADDQconstmodify:
    41  		return rewriteValueAMD64_OpAMD64ADDQconstmodify_0(v)
    42  	case OpAMD64ADDQload:
    43  		return rewriteValueAMD64_OpAMD64ADDQload_0(v)
    44  	case OpAMD64ADDQmodify:
    45  		return rewriteValueAMD64_OpAMD64ADDQmodify_0(v)
    46  	case OpAMD64ADDSD:
    47  		return rewriteValueAMD64_OpAMD64ADDSD_0(v)
    48  	case OpAMD64ADDSDload:
    49  		return rewriteValueAMD64_OpAMD64ADDSDload_0(v)
    50  	case OpAMD64ADDSS:
    51  		return rewriteValueAMD64_OpAMD64ADDSS_0(v)
    52  	case OpAMD64ADDSSload:
    53  		return rewriteValueAMD64_OpAMD64ADDSSload_0(v)
    54  	case OpAMD64ANDL:
    55  		return rewriteValueAMD64_OpAMD64ANDL_0(v)
    56  	case OpAMD64ANDLconst:
    57  		return rewriteValueAMD64_OpAMD64ANDLconst_0(v)
    58  	case OpAMD64ANDLconstmodify:
    59  		return rewriteValueAMD64_OpAMD64ANDLconstmodify_0(v)
    60  	case OpAMD64ANDLload:
    61  		return rewriteValueAMD64_OpAMD64ANDLload_0(v)
    62  	case OpAMD64ANDLmodify:
    63  		return rewriteValueAMD64_OpAMD64ANDLmodify_0(v)
    64  	case OpAMD64ANDQ:
    65  		return rewriteValueAMD64_OpAMD64ANDQ_0(v)
    66  	case OpAMD64ANDQconst:
    67  		return rewriteValueAMD64_OpAMD64ANDQconst_0(v)
    68  	case OpAMD64ANDQconstmodify:
    69  		return rewriteValueAMD64_OpAMD64ANDQconstmodify_0(v)
    70  	case OpAMD64ANDQload:
    71  		return rewriteValueAMD64_OpAMD64ANDQload_0(v)
    72  	case OpAMD64ANDQmodify:
    73  		return rewriteValueAMD64_OpAMD64ANDQmodify_0(v)
    74  	case OpAMD64BSFQ:
    75  		return rewriteValueAMD64_OpAMD64BSFQ_0(v)
    76  	case OpAMD64BTCLconst:
    77  		return rewriteValueAMD64_OpAMD64BTCLconst_0(v)
    78  	case OpAMD64BTCLconstmodify:
    79  		return rewriteValueAMD64_OpAMD64BTCLconstmodify_0(v)
    80  	case OpAMD64BTCLmodify:
    81  		return rewriteValueAMD64_OpAMD64BTCLmodify_0(v)
    82  	case OpAMD64BTCQconst:
    83  		return rewriteValueAMD64_OpAMD64BTCQconst_0(v)
    84  	case OpAMD64BTCQconstmodify:
    85  		return rewriteValueAMD64_OpAMD64BTCQconstmodify_0(v)
    86  	case OpAMD64BTCQmodify:
    87  		return rewriteValueAMD64_OpAMD64BTCQmodify_0(v)
    88  	case OpAMD64BTLconst:
    89  		return rewriteValueAMD64_OpAMD64BTLconst_0(v)
    90  	case OpAMD64BTQconst:
    91  		return rewriteValueAMD64_OpAMD64BTQconst_0(v)
    92  	case OpAMD64BTRLconst:
    93  		return rewriteValueAMD64_OpAMD64BTRLconst_0(v)
    94  	case OpAMD64BTRLconstmodify:
    95  		return rewriteValueAMD64_OpAMD64BTRLconstmodify_0(v)
    96  	case OpAMD64BTRLmodify:
    97  		return rewriteValueAMD64_OpAMD64BTRLmodify_0(v)
    98  	case OpAMD64BTRQconst:
    99  		return rewriteValueAMD64_OpAMD64BTRQconst_0(v)
   100  	case OpAMD64BTRQconstmodify:
   101  		return rewriteValueAMD64_OpAMD64BTRQconstmodify_0(v)
   102  	case OpAMD64BTRQmodify:
   103  		return rewriteValueAMD64_OpAMD64BTRQmodify_0(v)
   104  	case OpAMD64BTSLconst:
   105  		return rewriteValueAMD64_OpAMD64BTSLconst_0(v)
   106  	case OpAMD64BTSLconstmodify:
   107  		return rewriteValueAMD64_OpAMD64BTSLconstmodify_0(v)
   108  	case OpAMD64BTSLmodify:
   109  		return rewriteValueAMD64_OpAMD64BTSLmodify_0(v)
   110  	case OpAMD64BTSQconst:
   111  		return rewriteValueAMD64_OpAMD64BTSQconst_0(v)
   112  	case OpAMD64BTSQconstmodify:
   113  		return rewriteValueAMD64_OpAMD64BTSQconstmodify_0(v)
   114  	case OpAMD64BTSQmodify:
   115  		return rewriteValueAMD64_OpAMD64BTSQmodify_0(v)
   116  	case OpAMD64CMOVLCC:
   117  		return rewriteValueAMD64_OpAMD64CMOVLCC_0(v)
   118  	case OpAMD64CMOVLCS:
   119  		return rewriteValueAMD64_OpAMD64CMOVLCS_0(v)
   120  	case OpAMD64CMOVLEQ:
   121  		return rewriteValueAMD64_OpAMD64CMOVLEQ_0(v)
   122  	case OpAMD64CMOVLGE:
   123  		return rewriteValueAMD64_OpAMD64CMOVLGE_0(v)
   124  	case OpAMD64CMOVLGT:
   125  		return rewriteValueAMD64_OpAMD64CMOVLGT_0(v)
   126  	case OpAMD64CMOVLHI:
   127  		return rewriteValueAMD64_OpAMD64CMOVLHI_0(v)
   128  	case OpAMD64CMOVLLE:
   129  		return rewriteValueAMD64_OpAMD64CMOVLLE_0(v)
   130  	case OpAMD64CMOVLLS:
   131  		return rewriteValueAMD64_OpAMD64CMOVLLS_0(v)
   132  	case OpAMD64CMOVLLT:
   133  		return rewriteValueAMD64_OpAMD64CMOVLLT_0(v)
   134  	case OpAMD64CMOVLNE:
   135  		return rewriteValueAMD64_OpAMD64CMOVLNE_0(v)
   136  	case OpAMD64CMOVQCC:
   137  		return rewriteValueAMD64_OpAMD64CMOVQCC_0(v)
   138  	case OpAMD64CMOVQCS:
   139  		return rewriteValueAMD64_OpAMD64CMOVQCS_0(v)
   140  	case OpAMD64CMOVQEQ:
   141  		return rewriteValueAMD64_OpAMD64CMOVQEQ_0(v)
   142  	case OpAMD64CMOVQGE:
   143  		return rewriteValueAMD64_OpAMD64CMOVQGE_0(v)
   144  	case OpAMD64CMOVQGT:
   145  		return rewriteValueAMD64_OpAMD64CMOVQGT_0(v)
   146  	case OpAMD64CMOVQHI:
   147  		return rewriteValueAMD64_OpAMD64CMOVQHI_0(v)
   148  	case OpAMD64CMOVQLE:
   149  		return rewriteValueAMD64_OpAMD64CMOVQLE_0(v)
   150  	case OpAMD64CMOVQLS:
   151  		return rewriteValueAMD64_OpAMD64CMOVQLS_0(v)
   152  	case OpAMD64CMOVQLT:
   153  		return rewriteValueAMD64_OpAMD64CMOVQLT_0(v)
   154  	case OpAMD64CMOVQNE:
   155  		return rewriteValueAMD64_OpAMD64CMOVQNE_0(v)
   156  	case OpAMD64CMOVWCC:
   157  		return rewriteValueAMD64_OpAMD64CMOVWCC_0(v)
   158  	case OpAMD64CMOVWCS:
   159  		return rewriteValueAMD64_OpAMD64CMOVWCS_0(v)
   160  	case OpAMD64CMOVWEQ:
   161  		return rewriteValueAMD64_OpAMD64CMOVWEQ_0(v)
   162  	case OpAMD64CMOVWGE:
   163  		return rewriteValueAMD64_OpAMD64CMOVWGE_0(v)
   164  	case OpAMD64CMOVWGT:
   165  		return rewriteValueAMD64_OpAMD64CMOVWGT_0(v)
   166  	case OpAMD64CMOVWHI:
   167  		return rewriteValueAMD64_OpAMD64CMOVWHI_0(v)
   168  	case OpAMD64CMOVWLE:
   169  		return rewriteValueAMD64_OpAMD64CMOVWLE_0(v)
   170  	case OpAMD64CMOVWLS:
   171  		return rewriteValueAMD64_OpAMD64CMOVWLS_0(v)
   172  	case OpAMD64CMOVWLT:
   173  		return rewriteValueAMD64_OpAMD64CMOVWLT_0(v)
   174  	case OpAMD64CMOVWNE:
   175  		return rewriteValueAMD64_OpAMD64CMOVWNE_0(v)
   176  	case OpAMD64CMPB:
   177  		return rewriteValueAMD64_OpAMD64CMPB_0(v)
   178  	case OpAMD64CMPBconst:
   179  		return rewriteValueAMD64_OpAMD64CMPBconst_0(v)
   180  	case OpAMD64CMPBconstload:
   181  		return rewriteValueAMD64_OpAMD64CMPBconstload_0(v)
   182  	case OpAMD64CMPBload:
   183  		return rewriteValueAMD64_OpAMD64CMPBload_0(v)
   184  	case OpAMD64CMPL:
   185  		return rewriteValueAMD64_OpAMD64CMPL_0(v)
   186  	case OpAMD64CMPLconst:
   187  		return rewriteValueAMD64_OpAMD64CMPLconst_0(v) || rewriteValueAMD64_OpAMD64CMPLconst_10(v)
   188  	case OpAMD64CMPLconstload:
   189  		return rewriteValueAMD64_OpAMD64CMPLconstload_0(v)
   190  	case OpAMD64CMPLload:
   191  		return rewriteValueAMD64_OpAMD64CMPLload_0(v)
   192  	case OpAMD64CMPQ:
   193  		return rewriteValueAMD64_OpAMD64CMPQ_0(v)
   194  	case OpAMD64CMPQconst:
   195  		return rewriteValueAMD64_OpAMD64CMPQconst_0(v) || rewriteValueAMD64_OpAMD64CMPQconst_10(v)
   196  	case OpAMD64CMPQconstload:
   197  		return rewriteValueAMD64_OpAMD64CMPQconstload_0(v)
   198  	case OpAMD64CMPQload:
   199  		return rewriteValueAMD64_OpAMD64CMPQload_0(v)
   200  	case OpAMD64CMPW:
   201  		return rewriteValueAMD64_OpAMD64CMPW_0(v)
   202  	case OpAMD64CMPWconst:
   203  		return rewriteValueAMD64_OpAMD64CMPWconst_0(v)
   204  	case OpAMD64CMPWconstload:
   205  		return rewriteValueAMD64_OpAMD64CMPWconstload_0(v)
   206  	case OpAMD64CMPWload:
   207  		return rewriteValueAMD64_OpAMD64CMPWload_0(v)
   208  	case OpAMD64CMPXCHGLlock:
   209  		return rewriteValueAMD64_OpAMD64CMPXCHGLlock_0(v)
   210  	case OpAMD64CMPXCHGQlock:
   211  		return rewriteValueAMD64_OpAMD64CMPXCHGQlock_0(v)
   212  	case OpAMD64DIVSD:
   213  		return rewriteValueAMD64_OpAMD64DIVSD_0(v)
   214  	case OpAMD64DIVSDload:
   215  		return rewriteValueAMD64_OpAMD64DIVSDload_0(v)
   216  	case OpAMD64DIVSS:
   217  		return rewriteValueAMD64_OpAMD64DIVSS_0(v)
   218  	case OpAMD64DIVSSload:
   219  		return rewriteValueAMD64_OpAMD64DIVSSload_0(v)
   220  	case OpAMD64HMULL:
   221  		return rewriteValueAMD64_OpAMD64HMULL_0(v)
   222  	case OpAMD64HMULLU:
   223  		return rewriteValueAMD64_OpAMD64HMULLU_0(v)
   224  	case OpAMD64HMULQ:
   225  		return rewriteValueAMD64_OpAMD64HMULQ_0(v)
   226  	case OpAMD64HMULQU:
   227  		return rewriteValueAMD64_OpAMD64HMULQU_0(v)
   228  	case OpAMD64LEAL:
   229  		return rewriteValueAMD64_OpAMD64LEAL_0(v)
   230  	case OpAMD64LEAL1:
   231  		return rewriteValueAMD64_OpAMD64LEAL1_0(v)
   232  	case OpAMD64LEAL2:
   233  		return rewriteValueAMD64_OpAMD64LEAL2_0(v)
   234  	case OpAMD64LEAL4:
   235  		return rewriteValueAMD64_OpAMD64LEAL4_0(v)
   236  	case OpAMD64LEAL8:
   237  		return rewriteValueAMD64_OpAMD64LEAL8_0(v)
   238  	case OpAMD64LEAQ:
   239  		return rewriteValueAMD64_OpAMD64LEAQ_0(v)
   240  	case OpAMD64LEAQ1:
   241  		return rewriteValueAMD64_OpAMD64LEAQ1_0(v)
   242  	case OpAMD64LEAQ2:
   243  		return rewriteValueAMD64_OpAMD64LEAQ2_0(v)
   244  	case OpAMD64LEAQ4:
   245  		return rewriteValueAMD64_OpAMD64LEAQ4_0(v)
   246  	case OpAMD64LEAQ8:
   247  		return rewriteValueAMD64_OpAMD64LEAQ8_0(v)
   248  	case OpAMD64MOVBQSX:
   249  		return rewriteValueAMD64_OpAMD64MOVBQSX_0(v)
   250  	case OpAMD64MOVBQSXload:
   251  		return rewriteValueAMD64_OpAMD64MOVBQSXload_0(v)
   252  	case OpAMD64MOVBQZX:
   253  		return rewriteValueAMD64_OpAMD64MOVBQZX_0(v)
   254  	case OpAMD64MOVBatomicload:
   255  		return rewriteValueAMD64_OpAMD64MOVBatomicload_0(v)
   256  	case OpAMD64MOVBload:
   257  		return rewriteValueAMD64_OpAMD64MOVBload_0(v)
   258  	case OpAMD64MOVBloadidx1:
   259  		return rewriteValueAMD64_OpAMD64MOVBloadidx1_0(v)
   260  	case OpAMD64MOVBstore:
   261  		return rewriteValueAMD64_OpAMD64MOVBstore_0(v) || rewriteValueAMD64_OpAMD64MOVBstore_10(v) || rewriteValueAMD64_OpAMD64MOVBstore_20(v) || rewriteValueAMD64_OpAMD64MOVBstore_30(v)
   262  	case OpAMD64MOVBstoreconst:
   263  		return rewriteValueAMD64_OpAMD64MOVBstoreconst_0(v)
   264  	case OpAMD64MOVBstoreconstidx1:
   265  		return rewriteValueAMD64_OpAMD64MOVBstoreconstidx1_0(v)
   266  	case OpAMD64MOVBstoreidx1:
   267  		return rewriteValueAMD64_OpAMD64MOVBstoreidx1_0(v) || rewriteValueAMD64_OpAMD64MOVBstoreidx1_10(v)
   268  	case OpAMD64MOVLQSX:
   269  		return rewriteValueAMD64_OpAMD64MOVLQSX_0(v)
   270  	case OpAMD64MOVLQSXload:
   271  		return rewriteValueAMD64_OpAMD64MOVLQSXload_0(v)
   272  	case OpAMD64MOVLQZX:
   273  		return rewriteValueAMD64_OpAMD64MOVLQZX_0(v)
   274  	case OpAMD64MOVLatomicload:
   275  		return rewriteValueAMD64_OpAMD64MOVLatomicload_0(v)
   276  	case OpAMD64MOVLf2i:
   277  		return rewriteValueAMD64_OpAMD64MOVLf2i_0(v)
   278  	case OpAMD64MOVLi2f:
   279  		return rewriteValueAMD64_OpAMD64MOVLi2f_0(v)
   280  	case OpAMD64MOVLload:
   281  		return rewriteValueAMD64_OpAMD64MOVLload_0(v) || rewriteValueAMD64_OpAMD64MOVLload_10(v)
   282  	case OpAMD64MOVLloadidx1:
   283  		return rewriteValueAMD64_OpAMD64MOVLloadidx1_0(v)
   284  	case OpAMD64MOVLloadidx4:
   285  		return rewriteValueAMD64_OpAMD64MOVLloadidx4_0(v)
   286  	case OpAMD64MOVLloadidx8:
   287  		return rewriteValueAMD64_OpAMD64MOVLloadidx8_0(v)
   288  	case OpAMD64MOVLstore:
   289  		return rewriteValueAMD64_OpAMD64MOVLstore_0(v) || rewriteValueAMD64_OpAMD64MOVLstore_10(v) || rewriteValueAMD64_OpAMD64MOVLstore_20(v) || rewriteValueAMD64_OpAMD64MOVLstore_30(v)
   290  	case OpAMD64MOVLstoreconst:
   291  		return rewriteValueAMD64_OpAMD64MOVLstoreconst_0(v)
   292  	case OpAMD64MOVLstoreconstidx1:
   293  		return rewriteValueAMD64_OpAMD64MOVLstoreconstidx1_0(v)
   294  	case OpAMD64MOVLstoreconstidx4:
   295  		return rewriteValueAMD64_OpAMD64MOVLstoreconstidx4_0(v)
   296  	case OpAMD64MOVLstoreidx1:
   297  		return rewriteValueAMD64_OpAMD64MOVLstoreidx1_0(v)
   298  	case OpAMD64MOVLstoreidx4:
   299  		return rewriteValueAMD64_OpAMD64MOVLstoreidx4_0(v)
   300  	case OpAMD64MOVLstoreidx8:
   301  		return rewriteValueAMD64_OpAMD64MOVLstoreidx8_0(v)
   302  	case OpAMD64MOVOload:
   303  		return rewriteValueAMD64_OpAMD64MOVOload_0(v)
   304  	case OpAMD64MOVOstore:
   305  		return rewriteValueAMD64_OpAMD64MOVOstore_0(v)
   306  	case OpAMD64MOVQatomicload:
   307  		return rewriteValueAMD64_OpAMD64MOVQatomicload_0(v)
   308  	case OpAMD64MOVQf2i:
   309  		return rewriteValueAMD64_OpAMD64MOVQf2i_0(v)
   310  	case OpAMD64MOVQi2f:
   311  		return rewriteValueAMD64_OpAMD64MOVQi2f_0(v)
   312  	case OpAMD64MOVQload:
   313  		return rewriteValueAMD64_OpAMD64MOVQload_0(v)
   314  	case OpAMD64MOVQloadidx1:
   315  		return rewriteValueAMD64_OpAMD64MOVQloadidx1_0(v)
   316  	case OpAMD64MOVQloadidx8:
   317  		return rewriteValueAMD64_OpAMD64MOVQloadidx8_0(v)
   318  	case OpAMD64MOVQstore:
   319  		return rewriteValueAMD64_OpAMD64MOVQstore_0(v) || rewriteValueAMD64_OpAMD64MOVQstore_10(v) || rewriteValueAMD64_OpAMD64MOVQstore_20(v) || rewriteValueAMD64_OpAMD64MOVQstore_30(v)
   320  	case OpAMD64MOVQstoreconst:
   321  		return rewriteValueAMD64_OpAMD64MOVQstoreconst_0(v)
   322  	case OpAMD64MOVQstoreconstidx1:
   323  		return rewriteValueAMD64_OpAMD64MOVQstoreconstidx1_0(v)
   324  	case OpAMD64MOVQstoreconstidx8:
   325  		return rewriteValueAMD64_OpAMD64MOVQstoreconstidx8_0(v)
   326  	case OpAMD64MOVQstoreidx1:
   327  		return rewriteValueAMD64_OpAMD64MOVQstoreidx1_0(v)
   328  	case OpAMD64MOVQstoreidx8:
   329  		return rewriteValueAMD64_OpAMD64MOVQstoreidx8_0(v)
   330  	case OpAMD64MOVSDload:
   331  		return rewriteValueAMD64_OpAMD64MOVSDload_0(v)
   332  	case OpAMD64MOVSDloadidx1:
   333  		return rewriteValueAMD64_OpAMD64MOVSDloadidx1_0(v)
   334  	case OpAMD64MOVSDloadidx8:
   335  		return rewriteValueAMD64_OpAMD64MOVSDloadidx8_0(v)
   336  	case OpAMD64MOVSDstore:
   337  		return rewriteValueAMD64_OpAMD64MOVSDstore_0(v)
   338  	case OpAMD64MOVSDstoreidx1:
   339  		return rewriteValueAMD64_OpAMD64MOVSDstoreidx1_0(v)
   340  	case OpAMD64MOVSDstoreidx8:
   341  		return rewriteValueAMD64_OpAMD64MOVSDstoreidx8_0(v)
   342  	case OpAMD64MOVSSload:
   343  		return rewriteValueAMD64_OpAMD64MOVSSload_0(v)
   344  	case OpAMD64MOVSSloadidx1:
   345  		return rewriteValueAMD64_OpAMD64MOVSSloadidx1_0(v)
   346  	case OpAMD64MOVSSloadidx4:
   347  		return rewriteValueAMD64_OpAMD64MOVSSloadidx4_0(v)
   348  	case OpAMD64MOVSSstore:
   349  		return rewriteValueAMD64_OpAMD64MOVSSstore_0(v)
   350  	case OpAMD64MOVSSstoreidx1:
   351  		return rewriteValueAMD64_OpAMD64MOVSSstoreidx1_0(v)
   352  	case OpAMD64MOVSSstoreidx4:
   353  		return rewriteValueAMD64_OpAMD64MOVSSstoreidx4_0(v)
   354  	case OpAMD64MOVWQSX:
   355  		return rewriteValueAMD64_OpAMD64MOVWQSX_0(v)
   356  	case OpAMD64MOVWQSXload:
   357  		return rewriteValueAMD64_OpAMD64MOVWQSXload_0(v)
   358  	case OpAMD64MOVWQZX:
   359  		return rewriteValueAMD64_OpAMD64MOVWQZX_0(v)
   360  	case OpAMD64MOVWload:
   361  		return rewriteValueAMD64_OpAMD64MOVWload_0(v)
   362  	case OpAMD64MOVWloadidx1:
   363  		return rewriteValueAMD64_OpAMD64MOVWloadidx1_0(v)
   364  	case OpAMD64MOVWloadidx2:
   365  		return rewriteValueAMD64_OpAMD64MOVWloadidx2_0(v)
   366  	case OpAMD64MOVWstore:
   367  		return rewriteValueAMD64_OpAMD64MOVWstore_0(v) || rewriteValueAMD64_OpAMD64MOVWstore_10(v)
   368  	case OpAMD64MOVWstoreconst:
   369  		return rewriteValueAMD64_OpAMD64MOVWstoreconst_0(v)
   370  	case OpAMD64MOVWstoreconstidx1:
   371  		return rewriteValueAMD64_OpAMD64MOVWstoreconstidx1_0(v)
   372  	case OpAMD64MOVWstoreconstidx2:
   373  		return rewriteValueAMD64_OpAMD64MOVWstoreconstidx2_0(v)
   374  	case OpAMD64MOVWstoreidx1:
   375  		return rewriteValueAMD64_OpAMD64MOVWstoreidx1_0(v)
   376  	case OpAMD64MOVWstoreidx2:
   377  		return rewriteValueAMD64_OpAMD64MOVWstoreidx2_0(v)
   378  	case OpAMD64MULL:
   379  		return rewriteValueAMD64_OpAMD64MULL_0(v)
   380  	case OpAMD64MULLconst:
   381  		return rewriteValueAMD64_OpAMD64MULLconst_0(v) || rewriteValueAMD64_OpAMD64MULLconst_10(v) || rewriteValueAMD64_OpAMD64MULLconst_20(v) || rewriteValueAMD64_OpAMD64MULLconst_30(v)
   382  	case OpAMD64MULQ:
   383  		return rewriteValueAMD64_OpAMD64MULQ_0(v)
   384  	case OpAMD64MULQconst:
   385  		return rewriteValueAMD64_OpAMD64MULQconst_0(v) || rewriteValueAMD64_OpAMD64MULQconst_10(v) || rewriteValueAMD64_OpAMD64MULQconst_20(v) || rewriteValueAMD64_OpAMD64MULQconst_30(v)
   386  	case OpAMD64MULSD:
   387  		return rewriteValueAMD64_OpAMD64MULSD_0(v)
   388  	case OpAMD64MULSDload:
   389  		return rewriteValueAMD64_OpAMD64MULSDload_0(v)
   390  	case OpAMD64MULSS:
   391  		return rewriteValueAMD64_OpAMD64MULSS_0(v)
   392  	case OpAMD64MULSSload:
   393  		return rewriteValueAMD64_OpAMD64MULSSload_0(v)
   394  	case OpAMD64NEGL:
   395  		return rewriteValueAMD64_OpAMD64NEGL_0(v)
   396  	case OpAMD64NEGQ:
   397  		return rewriteValueAMD64_OpAMD64NEGQ_0(v)
   398  	case OpAMD64NOTL:
   399  		return rewriteValueAMD64_OpAMD64NOTL_0(v)
   400  	case OpAMD64NOTQ:
   401  		return rewriteValueAMD64_OpAMD64NOTQ_0(v)
   402  	case OpAMD64ORL:
   403  		return rewriteValueAMD64_OpAMD64ORL_0(v) || rewriteValueAMD64_OpAMD64ORL_10(v) || rewriteValueAMD64_OpAMD64ORL_20(v) || rewriteValueAMD64_OpAMD64ORL_30(v) || rewriteValueAMD64_OpAMD64ORL_40(v) || rewriteValueAMD64_OpAMD64ORL_50(v) || rewriteValueAMD64_OpAMD64ORL_60(v) || rewriteValueAMD64_OpAMD64ORL_70(v) || rewriteValueAMD64_OpAMD64ORL_80(v) || rewriteValueAMD64_OpAMD64ORL_90(v) || rewriteValueAMD64_OpAMD64ORL_100(v) || rewriteValueAMD64_OpAMD64ORL_110(v) || rewriteValueAMD64_OpAMD64ORL_120(v) || rewriteValueAMD64_OpAMD64ORL_130(v)
   404  	case OpAMD64ORLconst:
   405  		return rewriteValueAMD64_OpAMD64ORLconst_0(v)
   406  	case OpAMD64ORLconstmodify:
   407  		return rewriteValueAMD64_OpAMD64ORLconstmodify_0(v)
   408  	case OpAMD64ORLload:
   409  		return rewriteValueAMD64_OpAMD64ORLload_0(v)
   410  	case OpAMD64ORLmodify:
   411  		return rewriteValueAMD64_OpAMD64ORLmodify_0(v)
   412  	case OpAMD64ORQ:
   413  		return rewriteValueAMD64_OpAMD64ORQ_0(v) || rewriteValueAMD64_OpAMD64ORQ_10(v) || rewriteValueAMD64_OpAMD64ORQ_20(v) || rewriteValueAMD64_OpAMD64ORQ_30(v) || rewriteValueAMD64_OpAMD64ORQ_40(v) || rewriteValueAMD64_OpAMD64ORQ_50(v) || rewriteValueAMD64_OpAMD64ORQ_60(v) || rewriteValueAMD64_OpAMD64ORQ_70(v) || rewriteValueAMD64_OpAMD64ORQ_80(v) || rewriteValueAMD64_OpAMD64ORQ_90(v) || rewriteValueAMD64_OpAMD64ORQ_100(v) || rewriteValueAMD64_OpAMD64ORQ_110(v) || rewriteValueAMD64_OpAMD64ORQ_120(v) || rewriteValueAMD64_OpAMD64ORQ_130(v) || rewriteValueAMD64_OpAMD64ORQ_140(v) || rewriteValueAMD64_OpAMD64ORQ_150(v) || rewriteValueAMD64_OpAMD64ORQ_160(v)
   414  	case OpAMD64ORQconst:
   415  		return rewriteValueAMD64_OpAMD64ORQconst_0(v)
   416  	case OpAMD64ORQconstmodify:
   417  		return rewriteValueAMD64_OpAMD64ORQconstmodify_0(v)
   418  	case OpAMD64ORQload:
   419  		return rewriteValueAMD64_OpAMD64ORQload_0(v)
   420  	case OpAMD64ORQmodify:
   421  		return rewriteValueAMD64_OpAMD64ORQmodify_0(v)
   422  	case OpAMD64ROLB:
   423  		return rewriteValueAMD64_OpAMD64ROLB_0(v)
   424  	case OpAMD64ROLBconst:
   425  		return rewriteValueAMD64_OpAMD64ROLBconst_0(v)
   426  	case OpAMD64ROLL:
   427  		return rewriteValueAMD64_OpAMD64ROLL_0(v)
   428  	case OpAMD64ROLLconst:
   429  		return rewriteValueAMD64_OpAMD64ROLLconst_0(v)
   430  	case OpAMD64ROLQ:
   431  		return rewriteValueAMD64_OpAMD64ROLQ_0(v)
   432  	case OpAMD64ROLQconst:
   433  		return rewriteValueAMD64_OpAMD64ROLQconst_0(v)
   434  	case OpAMD64ROLW:
   435  		return rewriteValueAMD64_OpAMD64ROLW_0(v)
   436  	case OpAMD64ROLWconst:
   437  		return rewriteValueAMD64_OpAMD64ROLWconst_0(v)
   438  	case OpAMD64RORB:
   439  		return rewriteValueAMD64_OpAMD64RORB_0(v)
   440  	case OpAMD64RORL:
   441  		return rewriteValueAMD64_OpAMD64RORL_0(v)
   442  	case OpAMD64RORQ:
   443  		return rewriteValueAMD64_OpAMD64RORQ_0(v)
   444  	case OpAMD64RORW:
   445  		return rewriteValueAMD64_OpAMD64RORW_0(v)
   446  	case OpAMD64SARB:
   447  		return rewriteValueAMD64_OpAMD64SARB_0(v)
   448  	case OpAMD64SARBconst:
   449  		return rewriteValueAMD64_OpAMD64SARBconst_0(v)
   450  	case OpAMD64SARL:
   451  		return rewriteValueAMD64_OpAMD64SARL_0(v)
   452  	case OpAMD64SARLconst:
   453  		return rewriteValueAMD64_OpAMD64SARLconst_0(v)
   454  	case OpAMD64SARQ:
   455  		return rewriteValueAMD64_OpAMD64SARQ_0(v)
   456  	case OpAMD64SARQconst:
   457  		return rewriteValueAMD64_OpAMD64SARQconst_0(v)
   458  	case OpAMD64SARW:
   459  		return rewriteValueAMD64_OpAMD64SARW_0(v)
   460  	case OpAMD64SARWconst:
   461  		return rewriteValueAMD64_OpAMD64SARWconst_0(v)
   462  	case OpAMD64SBBLcarrymask:
   463  		return rewriteValueAMD64_OpAMD64SBBLcarrymask_0(v)
   464  	case OpAMD64SBBQ:
   465  		return rewriteValueAMD64_OpAMD64SBBQ_0(v)
   466  	case OpAMD64SBBQcarrymask:
   467  		return rewriteValueAMD64_OpAMD64SBBQcarrymask_0(v)
   468  	case OpAMD64SBBQconst:
   469  		return rewriteValueAMD64_OpAMD64SBBQconst_0(v)
   470  	case OpAMD64SETA:
   471  		return rewriteValueAMD64_OpAMD64SETA_0(v)
   472  	case OpAMD64SETAE:
   473  		return rewriteValueAMD64_OpAMD64SETAE_0(v)
   474  	case OpAMD64SETAEstore:
   475  		return rewriteValueAMD64_OpAMD64SETAEstore_0(v)
   476  	case OpAMD64SETAstore:
   477  		return rewriteValueAMD64_OpAMD64SETAstore_0(v)
   478  	case OpAMD64SETB:
   479  		return rewriteValueAMD64_OpAMD64SETB_0(v)
   480  	case OpAMD64SETBE:
   481  		return rewriteValueAMD64_OpAMD64SETBE_0(v)
   482  	case OpAMD64SETBEstore:
   483  		return rewriteValueAMD64_OpAMD64SETBEstore_0(v)
   484  	case OpAMD64SETBstore:
   485  		return rewriteValueAMD64_OpAMD64SETBstore_0(v)
   486  	case OpAMD64SETEQ:
   487  		return rewriteValueAMD64_OpAMD64SETEQ_0(v) || rewriteValueAMD64_OpAMD64SETEQ_10(v) || rewriteValueAMD64_OpAMD64SETEQ_20(v)
   488  	case OpAMD64SETEQstore:
   489  		return rewriteValueAMD64_OpAMD64SETEQstore_0(v) || rewriteValueAMD64_OpAMD64SETEQstore_10(v) || rewriteValueAMD64_OpAMD64SETEQstore_20(v)
   490  	case OpAMD64SETG:
   491  		return rewriteValueAMD64_OpAMD64SETG_0(v)
   492  	case OpAMD64SETGE:
   493  		return rewriteValueAMD64_OpAMD64SETGE_0(v)
   494  	case OpAMD64SETGEstore:
   495  		return rewriteValueAMD64_OpAMD64SETGEstore_0(v)
   496  	case OpAMD64SETGstore:
   497  		return rewriteValueAMD64_OpAMD64SETGstore_0(v)
   498  	case OpAMD64SETL:
   499  		return rewriteValueAMD64_OpAMD64SETL_0(v)
   500  	case OpAMD64SETLE:
   501  		return rewriteValueAMD64_OpAMD64SETLE_0(v)
   502  	case OpAMD64SETLEstore:
   503  		return rewriteValueAMD64_OpAMD64SETLEstore_0(v)
   504  	case OpAMD64SETLstore:
   505  		return rewriteValueAMD64_OpAMD64SETLstore_0(v)
   506  	case OpAMD64SETNE:
   507  		return rewriteValueAMD64_OpAMD64SETNE_0(v) || rewriteValueAMD64_OpAMD64SETNE_10(v) || rewriteValueAMD64_OpAMD64SETNE_20(v)
   508  	case OpAMD64SETNEstore:
   509  		return rewriteValueAMD64_OpAMD64SETNEstore_0(v) || rewriteValueAMD64_OpAMD64SETNEstore_10(v) || rewriteValueAMD64_OpAMD64SETNEstore_20(v)
   510  	case OpAMD64SHLL:
   511  		return rewriteValueAMD64_OpAMD64SHLL_0(v)
   512  	case OpAMD64SHLLconst:
   513  		return rewriteValueAMD64_OpAMD64SHLLconst_0(v)
   514  	case OpAMD64SHLQ:
   515  		return rewriteValueAMD64_OpAMD64SHLQ_0(v)
   516  	case OpAMD64SHLQconst:
   517  		return rewriteValueAMD64_OpAMD64SHLQconst_0(v)
   518  	case OpAMD64SHRB:
   519  		return rewriteValueAMD64_OpAMD64SHRB_0(v)
   520  	case OpAMD64SHRBconst:
   521  		return rewriteValueAMD64_OpAMD64SHRBconst_0(v)
   522  	case OpAMD64SHRL:
   523  		return rewriteValueAMD64_OpAMD64SHRL_0(v)
   524  	case OpAMD64SHRLconst:
   525  		return rewriteValueAMD64_OpAMD64SHRLconst_0(v)
   526  	case OpAMD64SHRQ:
   527  		return rewriteValueAMD64_OpAMD64SHRQ_0(v)
   528  	case OpAMD64SHRQconst:
   529  		return rewriteValueAMD64_OpAMD64SHRQconst_0(v)
   530  	case OpAMD64SHRW:
   531  		return rewriteValueAMD64_OpAMD64SHRW_0(v)
   532  	case OpAMD64SHRWconst:
   533  		return rewriteValueAMD64_OpAMD64SHRWconst_0(v)
   534  	case OpAMD64SUBL:
   535  		return rewriteValueAMD64_OpAMD64SUBL_0(v)
   536  	case OpAMD64SUBLconst:
   537  		return rewriteValueAMD64_OpAMD64SUBLconst_0(v)
   538  	case OpAMD64SUBLload:
   539  		return rewriteValueAMD64_OpAMD64SUBLload_0(v)
   540  	case OpAMD64SUBLmodify:
   541  		return rewriteValueAMD64_OpAMD64SUBLmodify_0(v)
   542  	case OpAMD64SUBQ:
   543  		return rewriteValueAMD64_OpAMD64SUBQ_0(v)
   544  	case OpAMD64SUBQborrow:
   545  		return rewriteValueAMD64_OpAMD64SUBQborrow_0(v)
   546  	case OpAMD64SUBQconst:
   547  		return rewriteValueAMD64_OpAMD64SUBQconst_0(v)
   548  	case OpAMD64SUBQload:
   549  		return rewriteValueAMD64_OpAMD64SUBQload_0(v)
   550  	case OpAMD64SUBQmodify:
   551  		return rewriteValueAMD64_OpAMD64SUBQmodify_0(v)
   552  	case OpAMD64SUBSD:
   553  		return rewriteValueAMD64_OpAMD64SUBSD_0(v)
   554  	case OpAMD64SUBSDload:
   555  		return rewriteValueAMD64_OpAMD64SUBSDload_0(v)
   556  	case OpAMD64SUBSS:
   557  		return rewriteValueAMD64_OpAMD64SUBSS_0(v)
   558  	case OpAMD64SUBSSload:
   559  		return rewriteValueAMD64_OpAMD64SUBSSload_0(v)
   560  	case OpAMD64TESTB:
   561  		return rewriteValueAMD64_OpAMD64TESTB_0(v)
   562  	case OpAMD64TESTBconst:
   563  		return rewriteValueAMD64_OpAMD64TESTBconst_0(v)
   564  	case OpAMD64TESTL:
   565  		return rewriteValueAMD64_OpAMD64TESTL_0(v)
   566  	case OpAMD64TESTLconst:
   567  		return rewriteValueAMD64_OpAMD64TESTLconst_0(v)
   568  	case OpAMD64TESTQ:
   569  		return rewriteValueAMD64_OpAMD64TESTQ_0(v)
   570  	case OpAMD64TESTQconst:
   571  		return rewriteValueAMD64_OpAMD64TESTQconst_0(v)
   572  	case OpAMD64TESTW:
   573  		return rewriteValueAMD64_OpAMD64TESTW_0(v)
   574  	case OpAMD64TESTWconst:
   575  		return rewriteValueAMD64_OpAMD64TESTWconst_0(v)
   576  	case OpAMD64XADDLlock:
   577  		return rewriteValueAMD64_OpAMD64XADDLlock_0(v)
   578  	case OpAMD64XADDQlock:
   579  		return rewriteValueAMD64_OpAMD64XADDQlock_0(v)
   580  	case OpAMD64XCHGL:
   581  		return rewriteValueAMD64_OpAMD64XCHGL_0(v)
   582  	case OpAMD64XCHGQ:
   583  		return rewriteValueAMD64_OpAMD64XCHGQ_0(v)
   584  	case OpAMD64XORL:
   585  		return rewriteValueAMD64_OpAMD64XORL_0(v) || rewriteValueAMD64_OpAMD64XORL_10(v)
   586  	case OpAMD64XORLconst:
   587  		return rewriteValueAMD64_OpAMD64XORLconst_0(v) || rewriteValueAMD64_OpAMD64XORLconst_10(v)
   588  	case OpAMD64XORLconstmodify:
   589  		return rewriteValueAMD64_OpAMD64XORLconstmodify_0(v)
   590  	case OpAMD64XORLload:
   591  		return rewriteValueAMD64_OpAMD64XORLload_0(v)
   592  	case OpAMD64XORLmodify:
   593  		return rewriteValueAMD64_OpAMD64XORLmodify_0(v)
   594  	case OpAMD64XORQ:
   595  		return rewriteValueAMD64_OpAMD64XORQ_0(v) || rewriteValueAMD64_OpAMD64XORQ_10(v)
   596  	case OpAMD64XORQconst:
   597  		return rewriteValueAMD64_OpAMD64XORQconst_0(v)
   598  	case OpAMD64XORQconstmodify:
   599  		return rewriteValueAMD64_OpAMD64XORQconstmodify_0(v)
   600  	case OpAMD64XORQload:
   601  		return rewriteValueAMD64_OpAMD64XORQload_0(v)
   602  	case OpAMD64XORQmodify:
   603  		return rewriteValueAMD64_OpAMD64XORQmodify_0(v)
   604  	case OpAdd16:
   605  		return rewriteValueAMD64_OpAdd16_0(v)
   606  	case OpAdd32:
   607  		return rewriteValueAMD64_OpAdd32_0(v)
   608  	case OpAdd32F:
   609  		return rewriteValueAMD64_OpAdd32F_0(v)
   610  	case OpAdd64:
   611  		return rewriteValueAMD64_OpAdd64_0(v)
   612  	case OpAdd64F:
   613  		return rewriteValueAMD64_OpAdd64F_0(v)
   614  	case OpAdd8:
   615  		return rewriteValueAMD64_OpAdd8_0(v)
   616  	case OpAddPtr:
   617  		return rewriteValueAMD64_OpAddPtr_0(v)
   618  	case OpAddr:
   619  		return rewriteValueAMD64_OpAddr_0(v)
   620  	case OpAnd16:
   621  		return rewriteValueAMD64_OpAnd16_0(v)
   622  	case OpAnd32:
   623  		return rewriteValueAMD64_OpAnd32_0(v)
   624  	case OpAnd64:
   625  		return rewriteValueAMD64_OpAnd64_0(v)
   626  	case OpAnd8:
   627  		return rewriteValueAMD64_OpAnd8_0(v)
   628  	case OpAndB:
   629  		return rewriteValueAMD64_OpAndB_0(v)
   630  	case OpAtomicAdd32:
   631  		return rewriteValueAMD64_OpAtomicAdd32_0(v)
   632  	case OpAtomicAdd64:
   633  		return rewriteValueAMD64_OpAtomicAdd64_0(v)
   634  	case OpAtomicAnd8:
   635  		return rewriteValueAMD64_OpAtomicAnd8_0(v)
   636  	case OpAtomicCompareAndSwap32:
   637  		return rewriteValueAMD64_OpAtomicCompareAndSwap32_0(v)
   638  	case OpAtomicCompareAndSwap64:
   639  		return rewriteValueAMD64_OpAtomicCompareAndSwap64_0(v)
   640  	case OpAtomicExchange32:
   641  		return rewriteValueAMD64_OpAtomicExchange32_0(v)
   642  	case OpAtomicExchange64:
   643  		return rewriteValueAMD64_OpAtomicExchange64_0(v)
   644  	case OpAtomicLoad32:
   645  		return rewriteValueAMD64_OpAtomicLoad32_0(v)
   646  	case OpAtomicLoad64:
   647  		return rewriteValueAMD64_OpAtomicLoad64_0(v)
   648  	case OpAtomicLoad8:
   649  		return rewriteValueAMD64_OpAtomicLoad8_0(v)
   650  	case OpAtomicLoadPtr:
   651  		return rewriteValueAMD64_OpAtomicLoadPtr_0(v)
   652  	case OpAtomicOr8:
   653  		return rewriteValueAMD64_OpAtomicOr8_0(v)
   654  	case OpAtomicStore32:
   655  		return rewriteValueAMD64_OpAtomicStore32_0(v)
   656  	case OpAtomicStore64:
   657  		return rewriteValueAMD64_OpAtomicStore64_0(v)
   658  	case OpAtomicStorePtrNoWB:
   659  		return rewriteValueAMD64_OpAtomicStorePtrNoWB_0(v)
   660  	case OpAvg64u:
   661  		return rewriteValueAMD64_OpAvg64u_0(v)
   662  	case OpBitLen16:
   663  		return rewriteValueAMD64_OpBitLen16_0(v)
   664  	case OpBitLen32:
   665  		return rewriteValueAMD64_OpBitLen32_0(v)
   666  	case OpBitLen64:
   667  		return rewriteValueAMD64_OpBitLen64_0(v)
   668  	case OpBitLen8:
   669  		return rewriteValueAMD64_OpBitLen8_0(v)
   670  	case OpBswap32:
   671  		return rewriteValueAMD64_OpBswap32_0(v)
   672  	case OpBswap64:
   673  		return rewriteValueAMD64_OpBswap64_0(v)
   674  	case OpCeil:
   675  		return rewriteValueAMD64_OpCeil_0(v)
   676  	case OpClosureCall:
   677  		return rewriteValueAMD64_OpClosureCall_0(v)
   678  	case OpCom16:
   679  		return rewriteValueAMD64_OpCom16_0(v)
   680  	case OpCom32:
   681  		return rewriteValueAMD64_OpCom32_0(v)
   682  	case OpCom64:
   683  		return rewriteValueAMD64_OpCom64_0(v)
   684  	case OpCom8:
   685  		return rewriteValueAMD64_OpCom8_0(v)
   686  	case OpCondSelect:
   687  		return rewriteValueAMD64_OpCondSelect_0(v) || rewriteValueAMD64_OpCondSelect_10(v) || rewriteValueAMD64_OpCondSelect_20(v) || rewriteValueAMD64_OpCondSelect_30(v) || rewriteValueAMD64_OpCondSelect_40(v)
   688  	case OpConst16:
   689  		return rewriteValueAMD64_OpConst16_0(v)
   690  	case OpConst32:
   691  		return rewriteValueAMD64_OpConst32_0(v)
   692  	case OpConst32F:
   693  		return rewriteValueAMD64_OpConst32F_0(v)
   694  	case OpConst64:
   695  		return rewriteValueAMD64_OpConst64_0(v)
   696  	case OpConst64F:
   697  		return rewriteValueAMD64_OpConst64F_0(v)
   698  	case OpConst8:
   699  		return rewriteValueAMD64_OpConst8_0(v)
   700  	case OpConstBool:
   701  		return rewriteValueAMD64_OpConstBool_0(v)
   702  	case OpConstNil:
   703  		return rewriteValueAMD64_OpConstNil_0(v)
   704  	case OpCtz16:
   705  		return rewriteValueAMD64_OpCtz16_0(v)
   706  	case OpCtz16NonZero:
   707  		return rewriteValueAMD64_OpCtz16NonZero_0(v)
   708  	case OpCtz32:
   709  		return rewriteValueAMD64_OpCtz32_0(v)
   710  	case OpCtz32NonZero:
   711  		return rewriteValueAMD64_OpCtz32NonZero_0(v)
   712  	case OpCtz64:
   713  		return rewriteValueAMD64_OpCtz64_0(v)
   714  	case OpCtz64NonZero:
   715  		return rewriteValueAMD64_OpCtz64NonZero_0(v)
   716  	case OpCtz8:
   717  		return rewriteValueAMD64_OpCtz8_0(v)
   718  	case OpCtz8NonZero:
   719  		return rewriteValueAMD64_OpCtz8NonZero_0(v)
   720  	case OpCvt32Fto32:
   721  		return rewriteValueAMD64_OpCvt32Fto32_0(v)
   722  	case OpCvt32Fto64:
   723  		return rewriteValueAMD64_OpCvt32Fto64_0(v)
   724  	case OpCvt32Fto64F:
   725  		return rewriteValueAMD64_OpCvt32Fto64F_0(v)
   726  	case OpCvt32to32F:
   727  		return rewriteValueAMD64_OpCvt32to32F_0(v)
   728  	case OpCvt32to64F:
   729  		return rewriteValueAMD64_OpCvt32to64F_0(v)
   730  	case OpCvt64Fto32:
   731  		return rewriteValueAMD64_OpCvt64Fto32_0(v)
   732  	case OpCvt64Fto32F:
   733  		return rewriteValueAMD64_OpCvt64Fto32F_0(v)
   734  	case OpCvt64Fto64:
   735  		return rewriteValueAMD64_OpCvt64Fto64_0(v)
   736  	case OpCvt64to32F:
   737  		return rewriteValueAMD64_OpCvt64to32F_0(v)
   738  	case OpCvt64to64F:
   739  		return rewriteValueAMD64_OpCvt64to64F_0(v)
   740  	case OpDiv128u:
   741  		return rewriteValueAMD64_OpDiv128u_0(v)
   742  	case OpDiv16:
   743  		return rewriteValueAMD64_OpDiv16_0(v)
   744  	case OpDiv16u:
   745  		return rewriteValueAMD64_OpDiv16u_0(v)
   746  	case OpDiv32:
   747  		return rewriteValueAMD64_OpDiv32_0(v)
   748  	case OpDiv32F:
   749  		return rewriteValueAMD64_OpDiv32F_0(v)
   750  	case OpDiv32u:
   751  		return rewriteValueAMD64_OpDiv32u_0(v)
   752  	case OpDiv64:
   753  		return rewriteValueAMD64_OpDiv64_0(v)
   754  	case OpDiv64F:
   755  		return rewriteValueAMD64_OpDiv64F_0(v)
   756  	case OpDiv64u:
   757  		return rewriteValueAMD64_OpDiv64u_0(v)
   758  	case OpDiv8:
   759  		return rewriteValueAMD64_OpDiv8_0(v)
   760  	case OpDiv8u:
   761  		return rewriteValueAMD64_OpDiv8u_0(v)
   762  	case OpEq16:
   763  		return rewriteValueAMD64_OpEq16_0(v)
   764  	case OpEq32:
   765  		return rewriteValueAMD64_OpEq32_0(v)
   766  	case OpEq32F:
   767  		return rewriteValueAMD64_OpEq32F_0(v)
   768  	case OpEq64:
   769  		return rewriteValueAMD64_OpEq64_0(v)
   770  	case OpEq64F:
   771  		return rewriteValueAMD64_OpEq64F_0(v)
   772  	case OpEq8:
   773  		return rewriteValueAMD64_OpEq8_0(v)
   774  	case OpEqB:
   775  		return rewriteValueAMD64_OpEqB_0(v)
   776  	case OpEqPtr:
   777  		return rewriteValueAMD64_OpEqPtr_0(v)
   778  	case OpFloor:
   779  		return rewriteValueAMD64_OpFloor_0(v)
   780  	case OpGeq16:
   781  		return rewriteValueAMD64_OpGeq16_0(v)
   782  	case OpGeq16U:
   783  		return rewriteValueAMD64_OpGeq16U_0(v)
   784  	case OpGeq32:
   785  		return rewriteValueAMD64_OpGeq32_0(v)
   786  	case OpGeq32F:
   787  		return rewriteValueAMD64_OpGeq32F_0(v)
   788  	case OpGeq32U:
   789  		return rewriteValueAMD64_OpGeq32U_0(v)
   790  	case OpGeq64:
   791  		return rewriteValueAMD64_OpGeq64_0(v)
   792  	case OpGeq64F:
   793  		return rewriteValueAMD64_OpGeq64F_0(v)
   794  	case OpGeq64U:
   795  		return rewriteValueAMD64_OpGeq64U_0(v)
   796  	case OpGeq8:
   797  		return rewriteValueAMD64_OpGeq8_0(v)
   798  	case OpGeq8U:
   799  		return rewriteValueAMD64_OpGeq8U_0(v)
   800  	case OpGetCallerPC:
   801  		return rewriteValueAMD64_OpGetCallerPC_0(v)
   802  	case OpGetCallerSP:
   803  		return rewriteValueAMD64_OpGetCallerSP_0(v)
   804  	case OpGetClosurePtr:
   805  		return rewriteValueAMD64_OpGetClosurePtr_0(v)
   806  	case OpGetG:
   807  		return rewriteValueAMD64_OpGetG_0(v)
   808  	case OpGreater16:
   809  		return rewriteValueAMD64_OpGreater16_0(v)
   810  	case OpGreater16U:
   811  		return rewriteValueAMD64_OpGreater16U_0(v)
   812  	case OpGreater32:
   813  		return rewriteValueAMD64_OpGreater32_0(v)
   814  	case OpGreater32F:
   815  		return rewriteValueAMD64_OpGreater32F_0(v)
   816  	case OpGreater32U:
   817  		return rewriteValueAMD64_OpGreater32U_0(v)
   818  	case OpGreater64:
   819  		return rewriteValueAMD64_OpGreater64_0(v)
   820  	case OpGreater64F:
   821  		return rewriteValueAMD64_OpGreater64F_0(v)
   822  	case OpGreater64U:
   823  		return rewriteValueAMD64_OpGreater64U_0(v)
   824  	case OpGreater8:
   825  		return rewriteValueAMD64_OpGreater8_0(v)
   826  	case OpGreater8U:
   827  		return rewriteValueAMD64_OpGreater8U_0(v)
   828  	case OpHmul32:
   829  		return rewriteValueAMD64_OpHmul32_0(v)
   830  	case OpHmul32u:
   831  		return rewriteValueAMD64_OpHmul32u_0(v)
   832  	case OpHmul64:
   833  		return rewriteValueAMD64_OpHmul64_0(v)
   834  	case OpHmul64u:
   835  		return rewriteValueAMD64_OpHmul64u_0(v)
   836  	case OpInt64Hi:
   837  		return rewriteValueAMD64_OpInt64Hi_0(v)
   838  	case OpInt64Lo:
   839  		return rewriteValueAMD64_OpInt64Lo_0(v)
   840  	case OpInterCall:
   841  		return rewriteValueAMD64_OpInterCall_0(v)
   842  	case OpIsInBounds:
   843  		return rewriteValueAMD64_OpIsInBounds_0(v)
   844  	case OpIsNonNil:
   845  		return rewriteValueAMD64_OpIsNonNil_0(v)
   846  	case OpIsSliceInBounds:
   847  		return rewriteValueAMD64_OpIsSliceInBounds_0(v)
   848  	case OpLeq16:
   849  		return rewriteValueAMD64_OpLeq16_0(v)
   850  	case OpLeq16U:
   851  		return rewriteValueAMD64_OpLeq16U_0(v)
   852  	case OpLeq32:
   853  		return rewriteValueAMD64_OpLeq32_0(v)
   854  	case OpLeq32F:
   855  		return rewriteValueAMD64_OpLeq32F_0(v)
   856  	case OpLeq32U:
   857  		return rewriteValueAMD64_OpLeq32U_0(v)
   858  	case OpLeq64:
   859  		return rewriteValueAMD64_OpLeq64_0(v)
   860  	case OpLeq64F:
   861  		return rewriteValueAMD64_OpLeq64F_0(v)
   862  	case OpLeq64U:
   863  		return rewriteValueAMD64_OpLeq64U_0(v)
   864  	case OpLeq8:
   865  		return rewriteValueAMD64_OpLeq8_0(v)
   866  	case OpLeq8U:
   867  		return rewriteValueAMD64_OpLeq8U_0(v)
   868  	case OpLess16:
   869  		return rewriteValueAMD64_OpLess16_0(v)
   870  	case OpLess16U:
   871  		return rewriteValueAMD64_OpLess16U_0(v)
   872  	case OpLess32:
   873  		return rewriteValueAMD64_OpLess32_0(v)
   874  	case OpLess32F:
   875  		return rewriteValueAMD64_OpLess32F_0(v)
   876  	case OpLess32U:
   877  		return rewriteValueAMD64_OpLess32U_0(v)
   878  	case OpLess64:
   879  		return rewriteValueAMD64_OpLess64_0(v)
   880  	case OpLess64F:
   881  		return rewriteValueAMD64_OpLess64F_0(v)
   882  	case OpLess64U:
   883  		return rewriteValueAMD64_OpLess64U_0(v)
   884  	case OpLess8:
   885  		return rewriteValueAMD64_OpLess8_0(v)
   886  	case OpLess8U:
   887  		return rewriteValueAMD64_OpLess8U_0(v)
   888  	case OpLoad:
   889  		return rewriteValueAMD64_OpLoad_0(v)
   890  	case OpLocalAddr:
   891  		return rewriteValueAMD64_OpLocalAddr_0(v)
   892  	case OpLsh16x16:
   893  		return rewriteValueAMD64_OpLsh16x16_0(v)
   894  	case OpLsh16x32:
   895  		return rewriteValueAMD64_OpLsh16x32_0(v)
   896  	case OpLsh16x64:
   897  		return rewriteValueAMD64_OpLsh16x64_0(v)
   898  	case OpLsh16x8:
   899  		return rewriteValueAMD64_OpLsh16x8_0(v)
   900  	case OpLsh32x16:
   901  		return rewriteValueAMD64_OpLsh32x16_0(v)
   902  	case OpLsh32x32:
   903  		return rewriteValueAMD64_OpLsh32x32_0(v)
   904  	case OpLsh32x64:
   905  		return rewriteValueAMD64_OpLsh32x64_0(v)
   906  	case OpLsh32x8:
   907  		return rewriteValueAMD64_OpLsh32x8_0(v)
   908  	case OpLsh64x16:
   909  		return rewriteValueAMD64_OpLsh64x16_0(v)
   910  	case OpLsh64x32:
   911  		return rewriteValueAMD64_OpLsh64x32_0(v)
   912  	case OpLsh64x64:
   913  		return rewriteValueAMD64_OpLsh64x64_0(v)
   914  	case OpLsh64x8:
   915  		return rewriteValueAMD64_OpLsh64x8_0(v)
   916  	case OpLsh8x16:
   917  		return rewriteValueAMD64_OpLsh8x16_0(v)
   918  	case OpLsh8x32:
   919  		return rewriteValueAMD64_OpLsh8x32_0(v)
   920  	case OpLsh8x64:
   921  		return rewriteValueAMD64_OpLsh8x64_0(v)
   922  	case OpLsh8x8:
   923  		return rewriteValueAMD64_OpLsh8x8_0(v)
   924  	case OpMod16:
   925  		return rewriteValueAMD64_OpMod16_0(v)
   926  	case OpMod16u:
   927  		return rewriteValueAMD64_OpMod16u_0(v)
   928  	case OpMod32:
   929  		return rewriteValueAMD64_OpMod32_0(v)
   930  	case OpMod32u:
   931  		return rewriteValueAMD64_OpMod32u_0(v)
   932  	case OpMod64:
   933  		return rewriteValueAMD64_OpMod64_0(v)
   934  	case OpMod64u:
   935  		return rewriteValueAMD64_OpMod64u_0(v)
   936  	case OpMod8:
   937  		return rewriteValueAMD64_OpMod8_0(v)
   938  	case OpMod8u:
   939  		return rewriteValueAMD64_OpMod8u_0(v)
   940  	case OpMove:
   941  		return rewriteValueAMD64_OpMove_0(v) || rewriteValueAMD64_OpMove_10(v) || rewriteValueAMD64_OpMove_20(v)
   942  	case OpMul16:
   943  		return rewriteValueAMD64_OpMul16_0(v)
   944  	case OpMul32:
   945  		return rewriteValueAMD64_OpMul32_0(v)
   946  	case OpMul32F:
   947  		return rewriteValueAMD64_OpMul32F_0(v)
   948  	case OpMul64:
   949  		return rewriteValueAMD64_OpMul64_0(v)
   950  	case OpMul64F:
   951  		return rewriteValueAMD64_OpMul64F_0(v)
   952  	case OpMul64uhilo:
   953  		return rewriteValueAMD64_OpMul64uhilo_0(v)
   954  	case OpMul8:
   955  		return rewriteValueAMD64_OpMul8_0(v)
   956  	case OpNeg16:
   957  		return rewriteValueAMD64_OpNeg16_0(v)
   958  	case OpNeg32:
   959  		return rewriteValueAMD64_OpNeg32_0(v)
   960  	case OpNeg32F:
   961  		return rewriteValueAMD64_OpNeg32F_0(v)
   962  	case OpNeg64:
   963  		return rewriteValueAMD64_OpNeg64_0(v)
   964  	case OpNeg64F:
   965  		return rewriteValueAMD64_OpNeg64F_0(v)
   966  	case OpNeg8:
   967  		return rewriteValueAMD64_OpNeg8_0(v)
   968  	case OpNeq16:
   969  		return rewriteValueAMD64_OpNeq16_0(v)
   970  	case OpNeq32:
   971  		return rewriteValueAMD64_OpNeq32_0(v)
   972  	case OpNeq32F:
   973  		return rewriteValueAMD64_OpNeq32F_0(v)
   974  	case OpNeq64:
   975  		return rewriteValueAMD64_OpNeq64_0(v)
   976  	case OpNeq64F:
   977  		return rewriteValueAMD64_OpNeq64F_0(v)
   978  	case OpNeq8:
   979  		return rewriteValueAMD64_OpNeq8_0(v)
   980  	case OpNeqB:
   981  		return rewriteValueAMD64_OpNeqB_0(v)
   982  	case OpNeqPtr:
   983  		return rewriteValueAMD64_OpNeqPtr_0(v)
   984  	case OpNilCheck:
   985  		return rewriteValueAMD64_OpNilCheck_0(v)
   986  	case OpNot:
   987  		return rewriteValueAMD64_OpNot_0(v)
   988  	case OpOffPtr:
   989  		return rewriteValueAMD64_OpOffPtr_0(v)
   990  	case OpOr16:
   991  		return rewriteValueAMD64_OpOr16_0(v)
   992  	case OpOr32:
   993  		return rewriteValueAMD64_OpOr32_0(v)
   994  	case OpOr64:
   995  		return rewriteValueAMD64_OpOr64_0(v)
   996  	case OpOr8:
   997  		return rewriteValueAMD64_OpOr8_0(v)
   998  	case OpOrB:
   999  		return rewriteValueAMD64_OpOrB_0(v)
  1000  	case OpPanicBounds:
  1001  		return rewriteValueAMD64_OpPanicBounds_0(v)
  1002  	case OpPanicExtend:
  1003  		return rewriteValueAMD64_OpPanicExtend_0(v)
  1004  	case OpPopCount16:
  1005  		return rewriteValueAMD64_OpPopCount16_0(v)
  1006  	case OpPopCount32:
  1007  		return rewriteValueAMD64_OpPopCount32_0(v)
  1008  	case OpPopCount64:
  1009  		return rewriteValueAMD64_OpPopCount64_0(v)
  1010  	case OpPopCount8:
  1011  		return rewriteValueAMD64_OpPopCount8_0(v)
  1012  	case OpRotateLeft16:
  1013  		return rewriteValueAMD64_OpRotateLeft16_0(v)
  1014  	case OpRotateLeft32:
  1015  		return rewriteValueAMD64_OpRotateLeft32_0(v)
  1016  	case OpRotateLeft64:
  1017  		return rewriteValueAMD64_OpRotateLeft64_0(v)
  1018  	case OpRotateLeft8:
  1019  		return rewriteValueAMD64_OpRotateLeft8_0(v)
  1020  	case OpRound32F:
  1021  		return rewriteValueAMD64_OpRound32F_0(v)
  1022  	case OpRound64F:
  1023  		return rewriteValueAMD64_OpRound64F_0(v)
  1024  	case OpRoundToEven:
  1025  		return rewriteValueAMD64_OpRoundToEven_0(v)
  1026  	case OpRsh16Ux16:
  1027  		return rewriteValueAMD64_OpRsh16Ux16_0(v)
  1028  	case OpRsh16Ux32:
  1029  		return rewriteValueAMD64_OpRsh16Ux32_0(v)
  1030  	case OpRsh16Ux64:
  1031  		return rewriteValueAMD64_OpRsh16Ux64_0(v)
  1032  	case OpRsh16Ux8:
  1033  		return rewriteValueAMD64_OpRsh16Ux8_0(v)
  1034  	case OpRsh16x16:
  1035  		return rewriteValueAMD64_OpRsh16x16_0(v)
  1036  	case OpRsh16x32:
  1037  		return rewriteValueAMD64_OpRsh16x32_0(v)
  1038  	case OpRsh16x64:
  1039  		return rewriteValueAMD64_OpRsh16x64_0(v)
  1040  	case OpRsh16x8:
  1041  		return rewriteValueAMD64_OpRsh16x8_0(v)
  1042  	case OpRsh32Ux16:
  1043  		return rewriteValueAMD64_OpRsh32Ux16_0(v)
  1044  	case OpRsh32Ux32:
  1045  		return rewriteValueAMD64_OpRsh32Ux32_0(v)
  1046  	case OpRsh32Ux64:
  1047  		return rewriteValueAMD64_OpRsh32Ux64_0(v)
  1048  	case OpRsh32Ux8:
  1049  		return rewriteValueAMD64_OpRsh32Ux8_0(v)
  1050  	case OpRsh32x16:
  1051  		return rewriteValueAMD64_OpRsh32x16_0(v)
  1052  	case OpRsh32x32:
  1053  		return rewriteValueAMD64_OpRsh32x32_0(v)
  1054  	case OpRsh32x64:
  1055  		return rewriteValueAMD64_OpRsh32x64_0(v)
  1056  	case OpRsh32x8:
  1057  		return rewriteValueAMD64_OpRsh32x8_0(v)
  1058  	case OpRsh64Ux16:
  1059  		return rewriteValueAMD64_OpRsh64Ux16_0(v)
  1060  	case OpRsh64Ux32:
  1061  		return rewriteValueAMD64_OpRsh64Ux32_0(v)
  1062  	case OpRsh64Ux64:
  1063  		return rewriteValueAMD64_OpRsh64Ux64_0(v)
  1064  	case OpRsh64Ux8:
  1065  		return rewriteValueAMD64_OpRsh64Ux8_0(v)
  1066  	case OpRsh64x16:
  1067  		return rewriteValueAMD64_OpRsh64x16_0(v)
  1068  	case OpRsh64x32:
  1069  		return rewriteValueAMD64_OpRsh64x32_0(v)
  1070  	case OpRsh64x64:
  1071  		return rewriteValueAMD64_OpRsh64x64_0(v)
  1072  	case OpRsh64x8:
  1073  		return rewriteValueAMD64_OpRsh64x8_0(v)
  1074  	case OpRsh8Ux16:
  1075  		return rewriteValueAMD64_OpRsh8Ux16_0(v)
  1076  	case OpRsh8Ux32:
  1077  		return rewriteValueAMD64_OpRsh8Ux32_0(v)
  1078  	case OpRsh8Ux64:
  1079  		return rewriteValueAMD64_OpRsh8Ux64_0(v)
  1080  	case OpRsh8Ux8:
  1081  		return rewriteValueAMD64_OpRsh8Ux8_0(v)
  1082  	case OpRsh8x16:
  1083  		return rewriteValueAMD64_OpRsh8x16_0(v)
  1084  	case OpRsh8x32:
  1085  		return rewriteValueAMD64_OpRsh8x32_0(v)
  1086  	case OpRsh8x64:
  1087  		return rewriteValueAMD64_OpRsh8x64_0(v)
  1088  	case OpRsh8x8:
  1089  		return rewriteValueAMD64_OpRsh8x8_0(v)
  1090  	case OpSelect0:
  1091  		return rewriteValueAMD64_OpSelect0_0(v)
  1092  	case OpSelect1:
  1093  		return rewriteValueAMD64_OpSelect1_0(v)
  1094  	case OpSignExt16to32:
  1095  		return rewriteValueAMD64_OpSignExt16to32_0(v)
  1096  	case OpSignExt16to64:
  1097  		return rewriteValueAMD64_OpSignExt16to64_0(v)
  1098  	case OpSignExt32to64:
  1099  		return rewriteValueAMD64_OpSignExt32to64_0(v)
  1100  	case OpSignExt8to16:
  1101  		return rewriteValueAMD64_OpSignExt8to16_0(v)
  1102  	case OpSignExt8to32:
  1103  		return rewriteValueAMD64_OpSignExt8to32_0(v)
  1104  	case OpSignExt8to64:
  1105  		return rewriteValueAMD64_OpSignExt8to64_0(v)
  1106  	case OpSlicemask:
  1107  		return rewriteValueAMD64_OpSlicemask_0(v)
  1108  	case OpSqrt:
  1109  		return rewriteValueAMD64_OpSqrt_0(v)
  1110  	case OpStaticCall:
  1111  		return rewriteValueAMD64_OpStaticCall_0(v)
  1112  	case OpStore:
  1113  		return rewriteValueAMD64_OpStore_0(v)
  1114  	case OpSub16:
  1115  		return rewriteValueAMD64_OpSub16_0(v)
  1116  	case OpSub32:
  1117  		return rewriteValueAMD64_OpSub32_0(v)
  1118  	case OpSub32F:
  1119  		return rewriteValueAMD64_OpSub32F_0(v)
  1120  	case OpSub64:
  1121  		return rewriteValueAMD64_OpSub64_0(v)
  1122  	case OpSub64F:
  1123  		return rewriteValueAMD64_OpSub64F_0(v)
  1124  	case OpSub8:
  1125  		return rewriteValueAMD64_OpSub8_0(v)
  1126  	case OpSubPtr:
  1127  		return rewriteValueAMD64_OpSubPtr_0(v)
  1128  	case OpTrunc:
  1129  		return rewriteValueAMD64_OpTrunc_0(v)
  1130  	case OpTrunc16to8:
  1131  		return rewriteValueAMD64_OpTrunc16to8_0(v)
  1132  	case OpTrunc32to16:
  1133  		return rewriteValueAMD64_OpTrunc32to16_0(v)
  1134  	case OpTrunc32to8:
  1135  		return rewriteValueAMD64_OpTrunc32to8_0(v)
  1136  	case OpTrunc64to16:
  1137  		return rewriteValueAMD64_OpTrunc64to16_0(v)
  1138  	case OpTrunc64to32:
  1139  		return rewriteValueAMD64_OpTrunc64to32_0(v)
  1140  	case OpTrunc64to8:
  1141  		return rewriteValueAMD64_OpTrunc64to8_0(v)
  1142  	case OpWB:
  1143  		return rewriteValueAMD64_OpWB_0(v)
  1144  	case OpXor16:
  1145  		return rewriteValueAMD64_OpXor16_0(v)
  1146  	case OpXor32:
  1147  		return rewriteValueAMD64_OpXor32_0(v)
  1148  	case OpXor64:
  1149  		return rewriteValueAMD64_OpXor64_0(v)
  1150  	case OpXor8:
  1151  		return rewriteValueAMD64_OpXor8_0(v)
  1152  	case OpZero:
  1153  		return rewriteValueAMD64_OpZero_0(v) || rewriteValueAMD64_OpZero_10(v) || rewriteValueAMD64_OpZero_20(v)
  1154  	case OpZeroExt16to32:
  1155  		return rewriteValueAMD64_OpZeroExt16to32_0(v)
  1156  	case OpZeroExt16to64:
  1157  		return rewriteValueAMD64_OpZeroExt16to64_0(v)
  1158  	case OpZeroExt32to64:
  1159  		return rewriteValueAMD64_OpZeroExt32to64_0(v)
  1160  	case OpZeroExt8to16:
  1161  		return rewriteValueAMD64_OpZeroExt8to16_0(v)
  1162  	case OpZeroExt8to32:
  1163  		return rewriteValueAMD64_OpZeroExt8to32_0(v)
  1164  	case OpZeroExt8to64:
  1165  		return rewriteValueAMD64_OpZeroExt8to64_0(v)
  1166  	}
  1167  	return false
  1168  }
  1169  func rewriteValueAMD64_OpAMD64ADCQ_0(v *Value) bool {
  1170  	// match: (ADCQ x (MOVQconst [c]) carry)
  1171  	// cond: is32Bit(c)
  1172  	// result: (ADCQconst x [c] carry)
  1173  	for {
  1174  		carry := v.Args[2]
  1175  		x := v.Args[0]
  1176  		v_1 := v.Args[1]
  1177  		if v_1.Op != OpAMD64MOVQconst {
  1178  			break
  1179  		}
  1180  		c := v_1.AuxInt
  1181  		if !(is32Bit(c)) {
  1182  			break
  1183  		}
  1184  		v.reset(OpAMD64ADCQconst)
  1185  		v.AuxInt = c
  1186  		v.AddArg(x)
  1187  		v.AddArg(carry)
  1188  		return true
  1189  	}
  1190  	// match: (ADCQ (MOVQconst [c]) x carry)
  1191  	// cond: is32Bit(c)
  1192  	// result: (ADCQconst x [c] carry)
  1193  	for {
  1194  		carry := v.Args[2]
  1195  		v_0 := v.Args[0]
  1196  		if v_0.Op != OpAMD64MOVQconst {
  1197  			break
  1198  		}
  1199  		c := v_0.AuxInt
  1200  		x := v.Args[1]
  1201  		if !(is32Bit(c)) {
  1202  			break
  1203  		}
  1204  		v.reset(OpAMD64ADCQconst)
  1205  		v.AuxInt = c
  1206  		v.AddArg(x)
  1207  		v.AddArg(carry)
  1208  		return true
  1209  	}
  1210  	// match: (ADCQ x y (FlagEQ))
  1211  	// cond:
  1212  	// result: (ADDQcarry x y)
  1213  	for {
  1214  		_ = v.Args[2]
  1215  		x := v.Args[0]
  1216  		y := v.Args[1]
  1217  		v_2 := v.Args[2]
  1218  		if v_2.Op != OpAMD64FlagEQ {
  1219  			break
  1220  		}
  1221  		v.reset(OpAMD64ADDQcarry)
  1222  		v.AddArg(x)
  1223  		v.AddArg(y)
  1224  		return true
  1225  	}
  1226  	return false
  1227  }
  1228  func rewriteValueAMD64_OpAMD64ADCQconst_0(v *Value) bool {
  1229  	// match: (ADCQconst x [c] (FlagEQ))
  1230  	// cond:
  1231  	// result: (ADDQconstcarry x [c])
  1232  	for {
  1233  		c := v.AuxInt
  1234  		_ = v.Args[1]
  1235  		x := v.Args[0]
  1236  		v_1 := v.Args[1]
  1237  		if v_1.Op != OpAMD64FlagEQ {
  1238  			break
  1239  		}
  1240  		v.reset(OpAMD64ADDQconstcarry)
  1241  		v.AuxInt = c
  1242  		v.AddArg(x)
  1243  		return true
  1244  	}
  1245  	return false
  1246  }
  1247  func rewriteValueAMD64_OpAMD64ADDL_0(v *Value) bool {
  1248  	// match: (ADDL x (MOVLconst [c]))
  1249  	// cond:
  1250  	// result: (ADDLconst [c] x)
  1251  	for {
  1252  		_ = v.Args[1]
  1253  		x := v.Args[0]
  1254  		v_1 := v.Args[1]
  1255  		if v_1.Op != OpAMD64MOVLconst {
  1256  			break
  1257  		}
  1258  		c := v_1.AuxInt
  1259  		v.reset(OpAMD64ADDLconst)
  1260  		v.AuxInt = c
  1261  		v.AddArg(x)
  1262  		return true
  1263  	}
  1264  	// match: (ADDL (MOVLconst [c]) x)
  1265  	// cond:
  1266  	// result: (ADDLconst [c] x)
  1267  	for {
  1268  		x := v.Args[1]
  1269  		v_0 := v.Args[0]
  1270  		if v_0.Op != OpAMD64MOVLconst {
  1271  			break
  1272  		}
  1273  		c := v_0.AuxInt
  1274  		v.reset(OpAMD64ADDLconst)
  1275  		v.AuxInt = c
  1276  		v.AddArg(x)
  1277  		return true
  1278  	}
  1279  	// match: (ADDL (SHLLconst x [c]) (SHRLconst x [d]))
  1280  	// cond: d==32-c
  1281  	// result: (ROLLconst x [c])
  1282  	for {
  1283  		_ = v.Args[1]
  1284  		v_0 := v.Args[0]
  1285  		if v_0.Op != OpAMD64SHLLconst {
  1286  			break
  1287  		}
  1288  		c := v_0.AuxInt
  1289  		x := v_0.Args[0]
  1290  		v_1 := v.Args[1]
  1291  		if v_1.Op != OpAMD64SHRLconst {
  1292  			break
  1293  		}
  1294  		d := v_1.AuxInt
  1295  		if x != v_1.Args[0] {
  1296  			break
  1297  		}
  1298  		if !(d == 32-c) {
  1299  			break
  1300  		}
  1301  		v.reset(OpAMD64ROLLconst)
  1302  		v.AuxInt = c
  1303  		v.AddArg(x)
  1304  		return true
  1305  	}
  1306  	// match: (ADDL (SHRLconst x [d]) (SHLLconst x [c]))
  1307  	// cond: d==32-c
  1308  	// result: (ROLLconst x [c])
  1309  	for {
  1310  		_ = v.Args[1]
  1311  		v_0 := v.Args[0]
  1312  		if v_0.Op != OpAMD64SHRLconst {
  1313  			break
  1314  		}
  1315  		d := v_0.AuxInt
  1316  		x := v_0.Args[0]
  1317  		v_1 := v.Args[1]
  1318  		if v_1.Op != OpAMD64SHLLconst {
  1319  			break
  1320  		}
  1321  		c := v_1.AuxInt
  1322  		if x != v_1.Args[0] {
  1323  			break
  1324  		}
  1325  		if !(d == 32-c) {
  1326  			break
  1327  		}
  1328  		v.reset(OpAMD64ROLLconst)
  1329  		v.AuxInt = c
  1330  		v.AddArg(x)
  1331  		return true
  1332  	}
  1333  	// match: (ADDL <t> (SHLLconst x [c]) (SHRWconst x [d]))
  1334  	// cond: d==16-c && c < 16 && t.Size() == 2
  1335  	// result: (ROLWconst x [c])
  1336  	for {
  1337  		t := v.Type
  1338  		_ = v.Args[1]
  1339  		v_0 := v.Args[0]
  1340  		if v_0.Op != OpAMD64SHLLconst {
  1341  			break
  1342  		}
  1343  		c := v_0.AuxInt
  1344  		x := v_0.Args[0]
  1345  		v_1 := v.Args[1]
  1346  		if v_1.Op != OpAMD64SHRWconst {
  1347  			break
  1348  		}
  1349  		d := v_1.AuxInt
  1350  		if x != v_1.Args[0] {
  1351  			break
  1352  		}
  1353  		if !(d == 16-c && c < 16 && t.Size() == 2) {
  1354  			break
  1355  		}
  1356  		v.reset(OpAMD64ROLWconst)
  1357  		v.AuxInt = c
  1358  		v.AddArg(x)
  1359  		return true
  1360  	}
  1361  	// match: (ADDL <t> (SHRWconst x [d]) (SHLLconst x [c]))
  1362  	// cond: d==16-c && c < 16 && t.Size() == 2
  1363  	// result: (ROLWconst x [c])
  1364  	for {
  1365  		t := v.Type
  1366  		_ = v.Args[1]
  1367  		v_0 := v.Args[0]
  1368  		if v_0.Op != OpAMD64SHRWconst {
  1369  			break
  1370  		}
  1371  		d := v_0.AuxInt
  1372  		x := v_0.Args[0]
  1373  		v_1 := v.Args[1]
  1374  		if v_1.Op != OpAMD64SHLLconst {
  1375  			break
  1376  		}
  1377  		c := v_1.AuxInt
  1378  		if x != v_1.Args[0] {
  1379  			break
  1380  		}
  1381  		if !(d == 16-c && c < 16 && t.Size() == 2) {
  1382  			break
  1383  		}
  1384  		v.reset(OpAMD64ROLWconst)
  1385  		v.AuxInt = c
  1386  		v.AddArg(x)
  1387  		return true
  1388  	}
  1389  	// match: (ADDL <t> (SHLLconst x [c]) (SHRBconst x [d]))
  1390  	// cond: d==8-c && c < 8 && t.Size() == 1
  1391  	// result: (ROLBconst x [c])
  1392  	for {
  1393  		t := v.Type
  1394  		_ = v.Args[1]
  1395  		v_0 := v.Args[0]
  1396  		if v_0.Op != OpAMD64SHLLconst {
  1397  			break
  1398  		}
  1399  		c := v_0.AuxInt
  1400  		x := v_0.Args[0]
  1401  		v_1 := v.Args[1]
  1402  		if v_1.Op != OpAMD64SHRBconst {
  1403  			break
  1404  		}
  1405  		d := v_1.AuxInt
  1406  		if x != v_1.Args[0] {
  1407  			break
  1408  		}
  1409  		if !(d == 8-c && c < 8 && t.Size() == 1) {
  1410  			break
  1411  		}
  1412  		v.reset(OpAMD64ROLBconst)
  1413  		v.AuxInt = c
  1414  		v.AddArg(x)
  1415  		return true
  1416  	}
  1417  	// match: (ADDL <t> (SHRBconst x [d]) (SHLLconst x [c]))
  1418  	// cond: d==8-c && c < 8 && t.Size() == 1
  1419  	// result: (ROLBconst x [c])
  1420  	for {
  1421  		t := v.Type
  1422  		_ = v.Args[1]
  1423  		v_0 := v.Args[0]
  1424  		if v_0.Op != OpAMD64SHRBconst {
  1425  			break
  1426  		}
  1427  		d := v_0.AuxInt
  1428  		x := v_0.Args[0]
  1429  		v_1 := v.Args[1]
  1430  		if v_1.Op != OpAMD64SHLLconst {
  1431  			break
  1432  		}
  1433  		c := v_1.AuxInt
  1434  		if x != v_1.Args[0] {
  1435  			break
  1436  		}
  1437  		if !(d == 8-c && c < 8 && t.Size() == 1) {
  1438  			break
  1439  		}
  1440  		v.reset(OpAMD64ROLBconst)
  1441  		v.AuxInt = c
  1442  		v.AddArg(x)
  1443  		return true
  1444  	}
  1445  	// match: (ADDL x (SHLLconst [3] y))
  1446  	// cond:
  1447  	// result: (LEAL8 x y)
  1448  	for {
  1449  		_ = v.Args[1]
  1450  		x := v.Args[0]
  1451  		v_1 := v.Args[1]
  1452  		if v_1.Op != OpAMD64SHLLconst {
  1453  			break
  1454  		}
  1455  		if v_1.AuxInt != 3 {
  1456  			break
  1457  		}
  1458  		y := v_1.Args[0]
  1459  		v.reset(OpAMD64LEAL8)
  1460  		v.AddArg(x)
  1461  		v.AddArg(y)
  1462  		return true
  1463  	}
  1464  	// match: (ADDL (SHLLconst [3] y) x)
  1465  	// cond:
  1466  	// result: (LEAL8 x y)
  1467  	for {
  1468  		x := v.Args[1]
  1469  		v_0 := v.Args[0]
  1470  		if v_0.Op != OpAMD64SHLLconst {
  1471  			break
  1472  		}
  1473  		if v_0.AuxInt != 3 {
  1474  			break
  1475  		}
  1476  		y := v_0.Args[0]
  1477  		v.reset(OpAMD64LEAL8)
  1478  		v.AddArg(x)
  1479  		v.AddArg(y)
  1480  		return true
  1481  	}
  1482  	return false
  1483  }
  1484  func rewriteValueAMD64_OpAMD64ADDL_10(v *Value) bool {
  1485  	// match: (ADDL x (SHLLconst [2] y))
  1486  	// cond:
  1487  	// result: (LEAL4 x y)
  1488  	for {
  1489  		_ = v.Args[1]
  1490  		x := v.Args[0]
  1491  		v_1 := v.Args[1]
  1492  		if v_1.Op != OpAMD64SHLLconst {
  1493  			break
  1494  		}
  1495  		if v_1.AuxInt != 2 {
  1496  			break
  1497  		}
  1498  		y := v_1.Args[0]
  1499  		v.reset(OpAMD64LEAL4)
  1500  		v.AddArg(x)
  1501  		v.AddArg(y)
  1502  		return true
  1503  	}
  1504  	// match: (ADDL (SHLLconst [2] y) x)
  1505  	// cond:
  1506  	// result: (LEAL4 x y)
  1507  	for {
  1508  		x := v.Args[1]
  1509  		v_0 := v.Args[0]
  1510  		if v_0.Op != OpAMD64SHLLconst {
  1511  			break
  1512  		}
  1513  		if v_0.AuxInt != 2 {
  1514  			break
  1515  		}
  1516  		y := v_0.Args[0]
  1517  		v.reset(OpAMD64LEAL4)
  1518  		v.AddArg(x)
  1519  		v.AddArg(y)
  1520  		return true
  1521  	}
  1522  	// match: (ADDL x (SHLLconst [1] y))
  1523  	// cond:
  1524  	// result: (LEAL2 x y)
  1525  	for {
  1526  		_ = v.Args[1]
  1527  		x := v.Args[0]
  1528  		v_1 := v.Args[1]
  1529  		if v_1.Op != OpAMD64SHLLconst {
  1530  			break
  1531  		}
  1532  		if v_1.AuxInt != 1 {
  1533  			break
  1534  		}
  1535  		y := v_1.Args[0]
  1536  		v.reset(OpAMD64LEAL2)
  1537  		v.AddArg(x)
  1538  		v.AddArg(y)
  1539  		return true
  1540  	}
  1541  	// match: (ADDL (SHLLconst [1] y) x)
  1542  	// cond:
  1543  	// result: (LEAL2 x y)
  1544  	for {
  1545  		x := v.Args[1]
  1546  		v_0 := v.Args[0]
  1547  		if v_0.Op != OpAMD64SHLLconst {
  1548  			break
  1549  		}
  1550  		if v_0.AuxInt != 1 {
  1551  			break
  1552  		}
  1553  		y := v_0.Args[0]
  1554  		v.reset(OpAMD64LEAL2)
  1555  		v.AddArg(x)
  1556  		v.AddArg(y)
  1557  		return true
  1558  	}
  1559  	// match: (ADDL x (ADDL y y))
  1560  	// cond:
  1561  	// result: (LEAL2 x y)
  1562  	for {
  1563  		_ = v.Args[1]
  1564  		x := v.Args[0]
  1565  		v_1 := v.Args[1]
  1566  		if v_1.Op != OpAMD64ADDL {
  1567  			break
  1568  		}
  1569  		y := v_1.Args[1]
  1570  		if y != v_1.Args[0] {
  1571  			break
  1572  		}
  1573  		v.reset(OpAMD64LEAL2)
  1574  		v.AddArg(x)
  1575  		v.AddArg(y)
  1576  		return true
  1577  	}
  1578  	// match: (ADDL (ADDL y y) x)
  1579  	// cond:
  1580  	// result: (LEAL2 x y)
  1581  	for {
  1582  		x := v.Args[1]
  1583  		v_0 := v.Args[0]
  1584  		if v_0.Op != OpAMD64ADDL {
  1585  			break
  1586  		}
  1587  		y := v_0.Args[1]
  1588  		if y != v_0.Args[0] {
  1589  			break
  1590  		}
  1591  		v.reset(OpAMD64LEAL2)
  1592  		v.AddArg(x)
  1593  		v.AddArg(y)
  1594  		return true
  1595  	}
  1596  	// match: (ADDL x (ADDL x y))
  1597  	// cond:
  1598  	// result: (LEAL2 y x)
  1599  	for {
  1600  		_ = v.Args[1]
  1601  		x := v.Args[0]
  1602  		v_1 := v.Args[1]
  1603  		if v_1.Op != OpAMD64ADDL {
  1604  			break
  1605  		}
  1606  		y := v_1.Args[1]
  1607  		if x != v_1.Args[0] {
  1608  			break
  1609  		}
  1610  		v.reset(OpAMD64LEAL2)
  1611  		v.AddArg(y)
  1612  		v.AddArg(x)
  1613  		return true
  1614  	}
  1615  	// match: (ADDL x (ADDL y x))
  1616  	// cond:
  1617  	// result: (LEAL2 y x)
  1618  	for {
  1619  		_ = v.Args[1]
  1620  		x := v.Args[0]
  1621  		v_1 := v.Args[1]
  1622  		if v_1.Op != OpAMD64ADDL {
  1623  			break
  1624  		}
  1625  		_ = v_1.Args[1]
  1626  		y := v_1.Args[0]
  1627  		if x != v_1.Args[1] {
  1628  			break
  1629  		}
  1630  		v.reset(OpAMD64LEAL2)
  1631  		v.AddArg(y)
  1632  		v.AddArg(x)
  1633  		return true
  1634  	}
  1635  	// match: (ADDL (ADDL x y) x)
  1636  	// cond:
  1637  	// result: (LEAL2 y x)
  1638  	for {
  1639  		x := v.Args[1]
  1640  		v_0 := v.Args[0]
  1641  		if v_0.Op != OpAMD64ADDL {
  1642  			break
  1643  		}
  1644  		y := v_0.Args[1]
  1645  		if x != v_0.Args[0] {
  1646  			break
  1647  		}
  1648  		v.reset(OpAMD64LEAL2)
  1649  		v.AddArg(y)
  1650  		v.AddArg(x)
  1651  		return true
  1652  	}
  1653  	// match: (ADDL (ADDL y x) x)
  1654  	// cond:
  1655  	// result: (LEAL2 y x)
  1656  	for {
  1657  		x := v.Args[1]
  1658  		v_0 := v.Args[0]
  1659  		if v_0.Op != OpAMD64ADDL {
  1660  			break
  1661  		}
  1662  		_ = v_0.Args[1]
  1663  		y := v_0.Args[0]
  1664  		if x != v_0.Args[1] {
  1665  			break
  1666  		}
  1667  		v.reset(OpAMD64LEAL2)
  1668  		v.AddArg(y)
  1669  		v.AddArg(x)
  1670  		return true
  1671  	}
  1672  	return false
  1673  }
  1674  func rewriteValueAMD64_OpAMD64ADDL_20(v *Value) bool {
  1675  	// match: (ADDL (ADDLconst [c] x) y)
  1676  	// cond:
  1677  	// result: (LEAL1 [c] x y)
  1678  	for {
  1679  		y := v.Args[1]
  1680  		v_0 := v.Args[0]
  1681  		if v_0.Op != OpAMD64ADDLconst {
  1682  			break
  1683  		}
  1684  		c := v_0.AuxInt
  1685  		x := v_0.Args[0]
  1686  		v.reset(OpAMD64LEAL1)
  1687  		v.AuxInt = c
  1688  		v.AddArg(x)
  1689  		v.AddArg(y)
  1690  		return true
  1691  	}
  1692  	// match: (ADDL y (ADDLconst [c] x))
  1693  	// cond:
  1694  	// result: (LEAL1 [c] x y)
  1695  	for {
  1696  		_ = v.Args[1]
  1697  		y := v.Args[0]
  1698  		v_1 := v.Args[1]
  1699  		if v_1.Op != OpAMD64ADDLconst {
  1700  			break
  1701  		}
  1702  		c := v_1.AuxInt
  1703  		x := v_1.Args[0]
  1704  		v.reset(OpAMD64LEAL1)
  1705  		v.AuxInt = c
  1706  		v.AddArg(x)
  1707  		v.AddArg(y)
  1708  		return true
  1709  	}
  1710  	// match: (ADDL x (LEAL [c] {s} y))
  1711  	// cond: x.Op != OpSB && y.Op != OpSB
  1712  	// result: (LEAL1 [c] {s} x y)
  1713  	for {
  1714  		_ = v.Args[1]
  1715  		x := v.Args[0]
  1716  		v_1 := v.Args[1]
  1717  		if v_1.Op != OpAMD64LEAL {
  1718  			break
  1719  		}
  1720  		c := v_1.AuxInt
  1721  		s := v_1.Aux
  1722  		y := v_1.Args[0]
  1723  		if !(x.Op != OpSB && y.Op != OpSB) {
  1724  			break
  1725  		}
  1726  		v.reset(OpAMD64LEAL1)
  1727  		v.AuxInt = c
  1728  		v.Aux = s
  1729  		v.AddArg(x)
  1730  		v.AddArg(y)
  1731  		return true
  1732  	}
  1733  	// match: (ADDL (LEAL [c] {s} y) x)
  1734  	// cond: x.Op != OpSB && y.Op != OpSB
  1735  	// result: (LEAL1 [c] {s} x y)
  1736  	for {
  1737  		x := v.Args[1]
  1738  		v_0 := v.Args[0]
  1739  		if v_0.Op != OpAMD64LEAL {
  1740  			break
  1741  		}
  1742  		c := v_0.AuxInt
  1743  		s := v_0.Aux
  1744  		y := v_0.Args[0]
  1745  		if !(x.Op != OpSB && y.Op != OpSB) {
  1746  			break
  1747  		}
  1748  		v.reset(OpAMD64LEAL1)
  1749  		v.AuxInt = c
  1750  		v.Aux = s
  1751  		v.AddArg(x)
  1752  		v.AddArg(y)
  1753  		return true
  1754  	}
  1755  	// match: (ADDL x (NEGL y))
  1756  	// cond:
  1757  	// result: (SUBL x y)
  1758  	for {
  1759  		_ = v.Args[1]
  1760  		x := v.Args[0]
  1761  		v_1 := v.Args[1]
  1762  		if v_1.Op != OpAMD64NEGL {
  1763  			break
  1764  		}
  1765  		y := v_1.Args[0]
  1766  		v.reset(OpAMD64SUBL)
  1767  		v.AddArg(x)
  1768  		v.AddArg(y)
  1769  		return true
  1770  	}
  1771  	// match: (ADDL (NEGL y) x)
  1772  	// cond:
  1773  	// result: (SUBL x y)
  1774  	for {
  1775  		x := v.Args[1]
  1776  		v_0 := v.Args[0]
  1777  		if v_0.Op != OpAMD64NEGL {
  1778  			break
  1779  		}
  1780  		y := v_0.Args[0]
  1781  		v.reset(OpAMD64SUBL)
  1782  		v.AddArg(x)
  1783  		v.AddArg(y)
  1784  		return true
  1785  	}
  1786  	// match: (ADDL x l:(MOVLload [off] {sym} ptr mem))
  1787  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  1788  	// result: (ADDLload x [off] {sym} ptr mem)
  1789  	for {
  1790  		_ = v.Args[1]
  1791  		x := v.Args[0]
  1792  		l := v.Args[1]
  1793  		if l.Op != OpAMD64MOVLload {
  1794  			break
  1795  		}
  1796  		off := l.AuxInt
  1797  		sym := l.Aux
  1798  		mem := l.Args[1]
  1799  		ptr := l.Args[0]
  1800  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  1801  			break
  1802  		}
  1803  		v.reset(OpAMD64ADDLload)
  1804  		v.AuxInt = off
  1805  		v.Aux = sym
  1806  		v.AddArg(x)
  1807  		v.AddArg(ptr)
  1808  		v.AddArg(mem)
  1809  		return true
  1810  	}
  1811  	// match: (ADDL l:(MOVLload [off] {sym} ptr mem) x)
  1812  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  1813  	// result: (ADDLload x [off] {sym} ptr mem)
  1814  	for {
  1815  		x := v.Args[1]
  1816  		l := v.Args[0]
  1817  		if l.Op != OpAMD64MOVLload {
  1818  			break
  1819  		}
  1820  		off := l.AuxInt
  1821  		sym := l.Aux
  1822  		mem := l.Args[1]
  1823  		ptr := l.Args[0]
  1824  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  1825  			break
  1826  		}
  1827  		v.reset(OpAMD64ADDLload)
  1828  		v.AuxInt = off
  1829  		v.Aux = sym
  1830  		v.AddArg(x)
  1831  		v.AddArg(ptr)
  1832  		v.AddArg(mem)
  1833  		return true
  1834  	}
  1835  	return false
  1836  }
  1837  func rewriteValueAMD64_OpAMD64ADDLconst_0(v *Value) bool {
  1838  	// match: (ADDLconst [c] (ADDL x y))
  1839  	// cond:
  1840  	// result: (LEAL1 [c] x y)
  1841  	for {
  1842  		c := v.AuxInt
  1843  		v_0 := v.Args[0]
  1844  		if v_0.Op != OpAMD64ADDL {
  1845  			break
  1846  		}
  1847  		y := v_0.Args[1]
  1848  		x := v_0.Args[0]
  1849  		v.reset(OpAMD64LEAL1)
  1850  		v.AuxInt = c
  1851  		v.AddArg(x)
  1852  		v.AddArg(y)
  1853  		return true
  1854  	}
  1855  	// match: (ADDLconst [c] (SHLLconst [1] x))
  1856  	// cond:
  1857  	// result: (LEAL1 [c] x x)
  1858  	for {
  1859  		c := v.AuxInt
  1860  		v_0 := v.Args[0]
  1861  		if v_0.Op != OpAMD64SHLLconst {
  1862  			break
  1863  		}
  1864  		if v_0.AuxInt != 1 {
  1865  			break
  1866  		}
  1867  		x := v_0.Args[0]
  1868  		v.reset(OpAMD64LEAL1)
  1869  		v.AuxInt = c
  1870  		v.AddArg(x)
  1871  		v.AddArg(x)
  1872  		return true
  1873  	}
  1874  	// match: (ADDLconst [c] (LEAL [d] {s} x))
  1875  	// cond: is32Bit(c+d)
  1876  	// result: (LEAL [c+d] {s} x)
  1877  	for {
  1878  		c := v.AuxInt
  1879  		v_0 := v.Args[0]
  1880  		if v_0.Op != OpAMD64LEAL {
  1881  			break
  1882  		}
  1883  		d := v_0.AuxInt
  1884  		s := v_0.Aux
  1885  		x := v_0.Args[0]
  1886  		if !(is32Bit(c + d)) {
  1887  			break
  1888  		}
  1889  		v.reset(OpAMD64LEAL)
  1890  		v.AuxInt = c + d
  1891  		v.Aux = s
  1892  		v.AddArg(x)
  1893  		return true
  1894  	}
  1895  	// match: (ADDLconst [c] (LEAL1 [d] {s} x y))
  1896  	// cond: is32Bit(c+d)
  1897  	// result: (LEAL1 [c+d] {s} x y)
  1898  	for {
  1899  		c := v.AuxInt
  1900  		v_0 := v.Args[0]
  1901  		if v_0.Op != OpAMD64LEAL1 {
  1902  			break
  1903  		}
  1904  		d := v_0.AuxInt
  1905  		s := v_0.Aux
  1906  		y := v_0.Args[1]
  1907  		x := v_0.Args[0]
  1908  		if !(is32Bit(c + d)) {
  1909  			break
  1910  		}
  1911  		v.reset(OpAMD64LEAL1)
  1912  		v.AuxInt = c + d
  1913  		v.Aux = s
  1914  		v.AddArg(x)
  1915  		v.AddArg(y)
  1916  		return true
  1917  	}
  1918  	// match: (ADDLconst [c] (LEAL2 [d] {s} x y))
  1919  	// cond: is32Bit(c+d)
  1920  	// result: (LEAL2 [c+d] {s} x y)
  1921  	for {
  1922  		c := v.AuxInt
  1923  		v_0 := v.Args[0]
  1924  		if v_0.Op != OpAMD64LEAL2 {
  1925  			break
  1926  		}
  1927  		d := v_0.AuxInt
  1928  		s := v_0.Aux
  1929  		y := v_0.Args[1]
  1930  		x := v_0.Args[0]
  1931  		if !(is32Bit(c + d)) {
  1932  			break
  1933  		}
  1934  		v.reset(OpAMD64LEAL2)
  1935  		v.AuxInt = c + d
  1936  		v.Aux = s
  1937  		v.AddArg(x)
  1938  		v.AddArg(y)
  1939  		return true
  1940  	}
  1941  	// match: (ADDLconst [c] (LEAL4 [d] {s} x y))
  1942  	// cond: is32Bit(c+d)
  1943  	// result: (LEAL4 [c+d] {s} x y)
  1944  	for {
  1945  		c := v.AuxInt
  1946  		v_0 := v.Args[0]
  1947  		if v_0.Op != OpAMD64LEAL4 {
  1948  			break
  1949  		}
  1950  		d := v_0.AuxInt
  1951  		s := v_0.Aux
  1952  		y := v_0.Args[1]
  1953  		x := v_0.Args[0]
  1954  		if !(is32Bit(c + d)) {
  1955  			break
  1956  		}
  1957  		v.reset(OpAMD64LEAL4)
  1958  		v.AuxInt = c + d
  1959  		v.Aux = s
  1960  		v.AddArg(x)
  1961  		v.AddArg(y)
  1962  		return true
  1963  	}
  1964  	// match: (ADDLconst [c] (LEAL8 [d] {s} x y))
  1965  	// cond: is32Bit(c+d)
  1966  	// result: (LEAL8 [c+d] {s} x y)
  1967  	for {
  1968  		c := v.AuxInt
  1969  		v_0 := v.Args[0]
  1970  		if v_0.Op != OpAMD64LEAL8 {
  1971  			break
  1972  		}
  1973  		d := v_0.AuxInt
  1974  		s := v_0.Aux
  1975  		y := v_0.Args[1]
  1976  		x := v_0.Args[0]
  1977  		if !(is32Bit(c + d)) {
  1978  			break
  1979  		}
  1980  		v.reset(OpAMD64LEAL8)
  1981  		v.AuxInt = c + d
  1982  		v.Aux = s
  1983  		v.AddArg(x)
  1984  		v.AddArg(y)
  1985  		return true
  1986  	}
  1987  	// match: (ADDLconst [c] x)
  1988  	// cond: int32(c)==0
  1989  	// result: x
  1990  	for {
  1991  		c := v.AuxInt
  1992  		x := v.Args[0]
  1993  		if !(int32(c) == 0) {
  1994  			break
  1995  		}
  1996  		v.reset(OpCopy)
  1997  		v.Type = x.Type
  1998  		v.AddArg(x)
  1999  		return true
  2000  	}
  2001  	// match: (ADDLconst [c] (MOVLconst [d]))
  2002  	// cond:
  2003  	// result: (MOVLconst [int64(int32(c+d))])
  2004  	for {
  2005  		c := v.AuxInt
  2006  		v_0 := v.Args[0]
  2007  		if v_0.Op != OpAMD64MOVLconst {
  2008  			break
  2009  		}
  2010  		d := v_0.AuxInt
  2011  		v.reset(OpAMD64MOVLconst)
  2012  		v.AuxInt = int64(int32(c + d))
  2013  		return true
  2014  	}
  2015  	// match: (ADDLconst [c] (ADDLconst [d] x))
  2016  	// cond:
  2017  	// result: (ADDLconst [int64(int32(c+d))] x)
  2018  	for {
  2019  		c := v.AuxInt
  2020  		v_0 := v.Args[0]
  2021  		if v_0.Op != OpAMD64ADDLconst {
  2022  			break
  2023  		}
  2024  		d := v_0.AuxInt
  2025  		x := v_0.Args[0]
  2026  		v.reset(OpAMD64ADDLconst)
  2027  		v.AuxInt = int64(int32(c + d))
  2028  		v.AddArg(x)
  2029  		return true
  2030  	}
  2031  	return false
  2032  }
  2033  func rewriteValueAMD64_OpAMD64ADDLconst_10(v *Value) bool {
  2034  	// match: (ADDLconst [off] x:(SP))
  2035  	// cond:
  2036  	// result: (LEAL [off] x)
  2037  	for {
  2038  		off := v.AuxInt
  2039  		x := v.Args[0]
  2040  		if x.Op != OpSP {
  2041  			break
  2042  		}
  2043  		v.reset(OpAMD64LEAL)
  2044  		v.AuxInt = off
  2045  		v.AddArg(x)
  2046  		return true
  2047  	}
  2048  	return false
  2049  }
  2050  func rewriteValueAMD64_OpAMD64ADDLconstmodify_0(v *Value) bool {
  2051  	// match: (ADDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  2052  	// cond: ValAndOff(valoff1).canAdd(off2)
  2053  	// result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  2054  	for {
  2055  		valoff1 := v.AuxInt
  2056  		sym := v.Aux
  2057  		mem := v.Args[1]
  2058  		v_0 := v.Args[0]
  2059  		if v_0.Op != OpAMD64ADDQconst {
  2060  			break
  2061  		}
  2062  		off2 := v_0.AuxInt
  2063  		base := v_0.Args[0]
  2064  		if !(ValAndOff(valoff1).canAdd(off2)) {
  2065  			break
  2066  		}
  2067  		v.reset(OpAMD64ADDLconstmodify)
  2068  		v.AuxInt = ValAndOff(valoff1).add(off2)
  2069  		v.Aux = sym
  2070  		v.AddArg(base)
  2071  		v.AddArg(mem)
  2072  		return true
  2073  	}
  2074  	// match: (ADDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  2075  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  2076  	// result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  2077  	for {
  2078  		valoff1 := v.AuxInt
  2079  		sym1 := v.Aux
  2080  		mem := v.Args[1]
  2081  		v_0 := v.Args[0]
  2082  		if v_0.Op != OpAMD64LEAQ {
  2083  			break
  2084  		}
  2085  		off2 := v_0.AuxInt
  2086  		sym2 := v_0.Aux
  2087  		base := v_0.Args[0]
  2088  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  2089  			break
  2090  		}
  2091  		v.reset(OpAMD64ADDLconstmodify)
  2092  		v.AuxInt = ValAndOff(valoff1).add(off2)
  2093  		v.Aux = mergeSym(sym1, sym2)
  2094  		v.AddArg(base)
  2095  		v.AddArg(mem)
  2096  		return true
  2097  	}
  2098  	return false
  2099  }
  2100  func rewriteValueAMD64_OpAMD64ADDLload_0(v *Value) bool {
  2101  	b := v.Block
  2102  	typ := &b.Func.Config.Types
  2103  	// match: (ADDLload [off1] {sym} val (ADDQconst [off2] base) mem)
  2104  	// cond: is32Bit(off1+off2)
  2105  	// result: (ADDLload [off1+off2] {sym} val base mem)
  2106  	for {
  2107  		off1 := v.AuxInt
  2108  		sym := v.Aux
  2109  		mem := v.Args[2]
  2110  		val := v.Args[0]
  2111  		v_1 := v.Args[1]
  2112  		if v_1.Op != OpAMD64ADDQconst {
  2113  			break
  2114  		}
  2115  		off2 := v_1.AuxInt
  2116  		base := v_1.Args[0]
  2117  		if !(is32Bit(off1 + off2)) {
  2118  			break
  2119  		}
  2120  		v.reset(OpAMD64ADDLload)
  2121  		v.AuxInt = off1 + off2
  2122  		v.Aux = sym
  2123  		v.AddArg(val)
  2124  		v.AddArg(base)
  2125  		v.AddArg(mem)
  2126  		return true
  2127  	}
  2128  	// match: (ADDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
  2129  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  2130  	// result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  2131  	for {
  2132  		off1 := v.AuxInt
  2133  		sym1 := v.Aux
  2134  		mem := v.Args[2]
  2135  		val := v.Args[0]
  2136  		v_1 := v.Args[1]
  2137  		if v_1.Op != OpAMD64LEAQ {
  2138  			break
  2139  		}
  2140  		off2 := v_1.AuxInt
  2141  		sym2 := v_1.Aux
  2142  		base := v_1.Args[0]
  2143  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  2144  			break
  2145  		}
  2146  		v.reset(OpAMD64ADDLload)
  2147  		v.AuxInt = off1 + off2
  2148  		v.Aux = mergeSym(sym1, sym2)
  2149  		v.AddArg(val)
  2150  		v.AddArg(base)
  2151  		v.AddArg(mem)
  2152  		return true
  2153  	}
  2154  	// match: (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _))
  2155  	// cond:
  2156  	// result: (ADDL x (MOVLf2i y))
  2157  	for {
  2158  		off := v.AuxInt
  2159  		sym := v.Aux
  2160  		_ = v.Args[2]
  2161  		x := v.Args[0]
  2162  		ptr := v.Args[1]
  2163  		v_2 := v.Args[2]
  2164  		if v_2.Op != OpAMD64MOVSSstore {
  2165  			break
  2166  		}
  2167  		if v_2.AuxInt != off {
  2168  			break
  2169  		}
  2170  		if v_2.Aux != sym {
  2171  			break
  2172  		}
  2173  		_ = v_2.Args[2]
  2174  		if ptr != v_2.Args[0] {
  2175  			break
  2176  		}
  2177  		y := v_2.Args[1]
  2178  		v.reset(OpAMD64ADDL)
  2179  		v.AddArg(x)
  2180  		v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32)
  2181  		v0.AddArg(y)
  2182  		v.AddArg(v0)
  2183  		return true
  2184  	}
  2185  	return false
  2186  }
  2187  func rewriteValueAMD64_OpAMD64ADDLmodify_0(v *Value) bool {
  2188  	// match: (ADDLmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  2189  	// cond: is32Bit(off1+off2)
  2190  	// result: (ADDLmodify [off1+off2] {sym} base val mem)
  2191  	for {
  2192  		off1 := v.AuxInt
  2193  		sym := v.Aux
  2194  		mem := v.Args[2]
  2195  		v_0 := v.Args[0]
  2196  		if v_0.Op != OpAMD64ADDQconst {
  2197  			break
  2198  		}
  2199  		off2 := v_0.AuxInt
  2200  		base := v_0.Args[0]
  2201  		val := v.Args[1]
  2202  		if !(is32Bit(off1 + off2)) {
  2203  			break
  2204  		}
  2205  		v.reset(OpAMD64ADDLmodify)
  2206  		v.AuxInt = off1 + off2
  2207  		v.Aux = sym
  2208  		v.AddArg(base)
  2209  		v.AddArg(val)
  2210  		v.AddArg(mem)
  2211  		return true
  2212  	}
  2213  	// match: (ADDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  2214  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  2215  	// result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  2216  	for {
  2217  		off1 := v.AuxInt
  2218  		sym1 := v.Aux
  2219  		mem := v.Args[2]
  2220  		v_0 := v.Args[0]
  2221  		if v_0.Op != OpAMD64LEAQ {
  2222  			break
  2223  		}
  2224  		off2 := v_0.AuxInt
  2225  		sym2 := v_0.Aux
  2226  		base := v_0.Args[0]
  2227  		val := v.Args[1]
  2228  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  2229  			break
  2230  		}
  2231  		v.reset(OpAMD64ADDLmodify)
  2232  		v.AuxInt = off1 + off2
  2233  		v.Aux = mergeSym(sym1, sym2)
  2234  		v.AddArg(base)
  2235  		v.AddArg(val)
  2236  		v.AddArg(mem)
  2237  		return true
  2238  	}
  2239  	return false
  2240  }
  2241  func rewriteValueAMD64_OpAMD64ADDQ_0(v *Value) bool {
  2242  	// match: (ADDQ x (MOVQconst [c]))
  2243  	// cond: is32Bit(c)
  2244  	// result: (ADDQconst [c] x)
  2245  	for {
  2246  		_ = v.Args[1]
  2247  		x := v.Args[0]
  2248  		v_1 := v.Args[1]
  2249  		if v_1.Op != OpAMD64MOVQconst {
  2250  			break
  2251  		}
  2252  		c := v_1.AuxInt
  2253  		if !(is32Bit(c)) {
  2254  			break
  2255  		}
  2256  		v.reset(OpAMD64ADDQconst)
  2257  		v.AuxInt = c
  2258  		v.AddArg(x)
  2259  		return true
  2260  	}
  2261  	// match: (ADDQ (MOVQconst [c]) x)
  2262  	// cond: is32Bit(c)
  2263  	// result: (ADDQconst [c] x)
  2264  	for {
  2265  		x := v.Args[1]
  2266  		v_0 := v.Args[0]
  2267  		if v_0.Op != OpAMD64MOVQconst {
  2268  			break
  2269  		}
  2270  		c := v_0.AuxInt
  2271  		if !(is32Bit(c)) {
  2272  			break
  2273  		}
  2274  		v.reset(OpAMD64ADDQconst)
  2275  		v.AuxInt = c
  2276  		v.AddArg(x)
  2277  		return true
  2278  	}
  2279  	// match: (ADDQ (SHLQconst x [c]) (SHRQconst x [d]))
  2280  	// cond: d==64-c
  2281  	// result: (ROLQconst x [c])
  2282  	for {
  2283  		_ = v.Args[1]
  2284  		v_0 := v.Args[0]
  2285  		if v_0.Op != OpAMD64SHLQconst {
  2286  			break
  2287  		}
  2288  		c := v_0.AuxInt
  2289  		x := v_0.Args[0]
  2290  		v_1 := v.Args[1]
  2291  		if v_1.Op != OpAMD64SHRQconst {
  2292  			break
  2293  		}
  2294  		d := v_1.AuxInt
  2295  		if x != v_1.Args[0] {
  2296  			break
  2297  		}
  2298  		if !(d == 64-c) {
  2299  			break
  2300  		}
  2301  		v.reset(OpAMD64ROLQconst)
  2302  		v.AuxInt = c
  2303  		v.AddArg(x)
  2304  		return true
  2305  	}
  2306  	// match: (ADDQ (SHRQconst x [d]) (SHLQconst x [c]))
  2307  	// cond: d==64-c
  2308  	// result: (ROLQconst x [c])
  2309  	for {
  2310  		_ = v.Args[1]
  2311  		v_0 := v.Args[0]
  2312  		if v_0.Op != OpAMD64SHRQconst {
  2313  			break
  2314  		}
  2315  		d := v_0.AuxInt
  2316  		x := v_0.Args[0]
  2317  		v_1 := v.Args[1]
  2318  		if v_1.Op != OpAMD64SHLQconst {
  2319  			break
  2320  		}
  2321  		c := v_1.AuxInt
  2322  		if x != v_1.Args[0] {
  2323  			break
  2324  		}
  2325  		if !(d == 64-c) {
  2326  			break
  2327  		}
  2328  		v.reset(OpAMD64ROLQconst)
  2329  		v.AuxInt = c
  2330  		v.AddArg(x)
  2331  		return true
  2332  	}
  2333  	// match: (ADDQ x (SHLQconst [3] y))
  2334  	// cond:
  2335  	// result: (LEAQ8 x y)
  2336  	for {
  2337  		_ = v.Args[1]
  2338  		x := v.Args[0]
  2339  		v_1 := v.Args[1]
  2340  		if v_1.Op != OpAMD64SHLQconst {
  2341  			break
  2342  		}
  2343  		if v_1.AuxInt != 3 {
  2344  			break
  2345  		}
  2346  		y := v_1.Args[0]
  2347  		v.reset(OpAMD64LEAQ8)
  2348  		v.AddArg(x)
  2349  		v.AddArg(y)
  2350  		return true
  2351  	}
  2352  	// match: (ADDQ (SHLQconst [3] y) x)
  2353  	// cond:
  2354  	// result: (LEAQ8 x y)
  2355  	for {
  2356  		x := v.Args[1]
  2357  		v_0 := v.Args[0]
  2358  		if v_0.Op != OpAMD64SHLQconst {
  2359  			break
  2360  		}
  2361  		if v_0.AuxInt != 3 {
  2362  			break
  2363  		}
  2364  		y := v_0.Args[0]
  2365  		v.reset(OpAMD64LEAQ8)
  2366  		v.AddArg(x)
  2367  		v.AddArg(y)
  2368  		return true
  2369  	}
  2370  	// match: (ADDQ x (SHLQconst [2] y))
  2371  	// cond:
  2372  	// result: (LEAQ4 x y)
  2373  	for {
  2374  		_ = v.Args[1]
  2375  		x := v.Args[0]
  2376  		v_1 := v.Args[1]
  2377  		if v_1.Op != OpAMD64SHLQconst {
  2378  			break
  2379  		}
  2380  		if v_1.AuxInt != 2 {
  2381  			break
  2382  		}
  2383  		y := v_1.Args[0]
  2384  		v.reset(OpAMD64LEAQ4)
  2385  		v.AddArg(x)
  2386  		v.AddArg(y)
  2387  		return true
  2388  	}
  2389  	// match: (ADDQ (SHLQconst [2] y) x)
  2390  	// cond:
  2391  	// result: (LEAQ4 x y)
  2392  	for {
  2393  		x := v.Args[1]
  2394  		v_0 := v.Args[0]
  2395  		if v_0.Op != OpAMD64SHLQconst {
  2396  			break
  2397  		}
  2398  		if v_0.AuxInt != 2 {
  2399  			break
  2400  		}
  2401  		y := v_0.Args[0]
  2402  		v.reset(OpAMD64LEAQ4)
  2403  		v.AddArg(x)
  2404  		v.AddArg(y)
  2405  		return true
  2406  	}
  2407  	// match: (ADDQ x (SHLQconst [1] y))
  2408  	// cond:
  2409  	// result: (LEAQ2 x y)
  2410  	for {
  2411  		_ = v.Args[1]
  2412  		x := v.Args[0]
  2413  		v_1 := v.Args[1]
  2414  		if v_1.Op != OpAMD64SHLQconst {
  2415  			break
  2416  		}
  2417  		if v_1.AuxInt != 1 {
  2418  			break
  2419  		}
  2420  		y := v_1.Args[0]
  2421  		v.reset(OpAMD64LEAQ2)
  2422  		v.AddArg(x)
  2423  		v.AddArg(y)
  2424  		return true
  2425  	}
  2426  	// match: (ADDQ (SHLQconst [1] y) x)
  2427  	// cond:
  2428  	// result: (LEAQ2 x y)
  2429  	for {
  2430  		x := v.Args[1]
  2431  		v_0 := v.Args[0]
  2432  		if v_0.Op != OpAMD64SHLQconst {
  2433  			break
  2434  		}
  2435  		if v_0.AuxInt != 1 {
  2436  			break
  2437  		}
  2438  		y := v_0.Args[0]
  2439  		v.reset(OpAMD64LEAQ2)
  2440  		v.AddArg(x)
  2441  		v.AddArg(y)
  2442  		return true
  2443  	}
  2444  	return false
  2445  }
  2446  func rewriteValueAMD64_OpAMD64ADDQ_10(v *Value) bool {
  2447  	// match: (ADDQ x (ADDQ y y))
  2448  	// cond:
  2449  	// result: (LEAQ2 x y)
  2450  	for {
  2451  		_ = v.Args[1]
  2452  		x := v.Args[0]
  2453  		v_1 := v.Args[1]
  2454  		if v_1.Op != OpAMD64ADDQ {
  2455  			break
  2456  		}
  2457  		y := v_1.Args[1]
  2458  		if y != v_1.Args[0] {
  2459  			break
  2460  		}
  2461  		v.reset(OpAMD64LEAQ2)
  2462  		v.AddArg(x)
  2463  		v.AddArg(y)
  2464  		return true
  2465  	}
  2466  	// match: (ADDQ (ADDQ y y) x)
  2467  	// cond:
  2468  	// result: (LEAQ2 x y)
  2469  	for {
  2470  		x := v.Args[1]
  2471  		v_0 := v.Args[0]
  2472  		if v_0.Op != OpAMD64ADDQ {
  2473  			break
  2474  		}
  2475  		y := v_0.Args[1]
  2476  		if y != v_0.Args[0] {
  2477  			break
  2478  		}
  2479  		v.reset(OpAMD64LEAQ2)
  2480  		v.AddArg(x)
  2481  		v.AddArg(y)
  2482  		return true
  2483  	}
  2484  	// match: (ADDQ x (ADDQ x y))
  2485  	// cond:
  2486  	// result: (LEAQ2 y x)
  2487  	for {
  2488  		_ = v.Args[1]
  2489  		x := v.Args[0]
  2490  		v_1 := v.Args[1]
  2491  		if v_1.Op != OpAMD64ADDQ {
  2492  			break
  2493  		}
  2494  		y := v_1.Args[1]
  2495  		if x != v_1.Args[0] {
  2496  			break
  2497  		}
  2498  		v.reset(OpAMD64LEAQ2)
  2499  		v.AddArg(y)
  2500  		v.AddArg(x)
  2501  		return true
  2502  	}
  2503  	// match: (ADDQ x (ADDQ y x))
  2504  	// cond:
  2505  	// result: (LEAQ2 y x)
  2506  	for {
  2507  		_ = v.Args[1]
  2508  		x := v.Args[0]
  2509  		v_1 := v.Args[1]
  2510  		if v_1.Op != OpAMD64ADDQ {
  2511  			break
  2512  		}
  2513  		_ = v_1.Args[1]
  2514  		y := v_1.Args[0]
  2515  		if x != v_1.Args[1] {
  2516  			break
  2517  		}
  2518  		v.reset(OpAMD64LEAQ2)
  2519  		v.AddArg(y)
  2520  		v.AddArg(x)
  2521  		return true
  2522  	}
  2523  	// match: (ADDQ (ADDQ x y) x)
  2524  	// cond:
  2525  	// result: (LEAQ2 y x)
  2526  	for {
  2527  		x := v.Args[1]
  2528  		v_0 := v.Args[0]
  2529  		if v_0.Op != OpAMD64ADDQ {
  2530  			break
  2531  		}
  2532  		y := v_0.Args[1]
  2533  		if x != v_0.Args[0] {
  2534  			break
  2535  		}
  2536  		v.reset(OpAMD64LEAQ2)
  2537  		v.AddArg(y)
  2538  		v.AddArg(x)
  2539  		return true
  2540  	}
  2541  	// match: (ADDQ (ADDQ y x) x)
  2542  	// cond:
  2543  	// result: (LEAQ2 y x)
  2544  	for {
  2545  		x := v.Args[1]
  2546  		v_0 := v.Args[0]
  2547  		if v_0.Op != OpAMD64ADDQ {
  2548  			break
  2549  		}
  2550  		_ = v_0.Args[1]
  2551  		y := v_0.Args[0]
  2552  		if x != v_0.Args[1] {
  2553  			break
  2554  		}
  2555  		v.reset(OpAMD64LEAQ2)
  2556  		v.AddArg(y)
  2557  		v.AddArg(x)
  2558  		return true
  2559  	}
  2560  	// match: (ADDQ (ADDQconst [c] x) y)
  2561  	// cond:
  2562  	// result: (LEAQ1 [c] x y)
  2563  	for {
  2564  		y := v.Args[1]
  2565  		v_0 := v.Args[0]
  2566  		if v_0.Op != OpAMD64ADDQconst {
  2567  			break
  2568  		}
  2569  		c := v_0.AuxInt
  2570  		x := v_0.Args[0]
  2571  		v.reset(OpAMD64LEAQ1)
  2572  		v.AuxInt = c
  2573  		v.AddArg(x)
  2574  		v.AddArg(y)
  2575  		return true
  2576  	}
  2577  	// match: (ADDQ y (ADDQconst [c] x))
  2578  	// cond:
  2579  	// result: (LEAQ1 [c] x y)
  2580  	for {
  2581  		_ = v.Args[1]
  2582  		y := v.Args[0]
  2583  		v_1 := v.Args[1]
  2584  		if v_1.Op != OpAMD64ADDQconst {
  2585  			break
  2586  		}
  2587  		c := v_1.AuxInt
  2588  		x := v_1.Args[0]
  2589  		v.reset(OpAMD64LEAQ1)
  2590  		v.AuxInt = c
  2591  		v.AddArg(x)
  2592  		v.AddArg(y)
  2593  		return true
  2594  	}
  2595  	// match: (ADDQ x (LEAQ [c] {s} y))
  2596  	// cond: x.Op != OpSB && y.Op != OpSB
  2597  	// result: (LEAQ1 [c] {s} x y)
  2598  	for {
  2599  		_ = v.Args[1]
  2600  		x := v.Args[0]
  2601  		v_1 := v.Args[1]
  2602  		if v_1.Op != OpAMD64LEAQ {
  2603  			break
  2604  		}
  2605  		c := v_1.AuxInt
  2606  		s := v_1.Aux
  2607  		y := v_1.Args[0]
  2608  		if !(x.Op != OpSB && y.Op != OpSB) {
  2609  			break
  2610  		}
  2611  		v.reset(OpAMD64LEAQ1)
  2612  		v.AuxInt = c
  2613  		v.Aux = s
  2614  		v.AddArg(x)
  2615  		v.AddArg(y)
  2616  		return true
  2617  	}
  2618  	// match: (ADDQ (LEAQ [c] {s} y) x)
  2619  	// cond: x.Op != OpSB && y.Op != OpSB
  2620  	// result: (LEAQ1 [c] {s} x y)
  2621  	for {
  2622  		x := v.Args[1]
  2623  		v_0 := v.Args[0]
  2624  		if v_0.Op != OpAMD64LEAQ {
  2625  			break
  2626  		}
  2627  		c := v_0.AuxInt
  2628  		s := v_0.Aux
  2629  		y := v_0.Args[0]
  2630  		if !(x.Op != OpSB && y.Op != OpSB) {
  2631  			break
  2632  		}
  2633  		v.reset(OpAMD64LEAQ1)
  2634  		v.AuxInt = c
  2635  		v.Aux = s
  2636  		v.AddArg(x)
  2637  		v.AddArg(y)
  2638  		return true
  2639  	}
  2640  	return false
  2641  }
  2642  func rewriteValueAMD64_OpAMD64ADDQ_20(v *Value) bool {
  2643  	// match: (ADDQ x (NEGQ y))
  2644  	// cond:
  2645  	// result: (SUBQ x y)
  2646  	for {
  2647  		_ = v.Args[1]
  2648  		x := v.Args[0]
  2649  		v_1 := v.Args[1]
  2650  		if v_1.Op != OpAMD64NEGQ {
  2651  			break
  2652  		}
  2653  		y := v_1.Args[0]
  2654  		v.reset(OpAMD64SUBQ)
  2655  		v.AddArg(x)
  2656  		v.AddArg(y)
  2657  		return true
  2658  	}
  2659  	// match: (ADDQ (NEGQ y) x)
  2660  	// cond:
  2661  	// result: (SUBQ x y)
  2662  	for {
  2663  		x := v.Args[1]
  2664  		v_0 := v.Args[0]
  2665  		if v_0.Op != OpAMD64NEGQ {
  2666  			break
  2667  		}
  2668  		y := v_0.Args[0]
  2669  		v.reset(OpAMD64SUBQ)
  2670  		v.AddArg(x)
  2671  		v.AddArg(y)
  2672  		return true
  2673  	}
  2674  	// match: (ADDQ x l:(MOVQload [off] {sym} ptr mem))
  2675  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  2676  	// result: (ADDQload x [off] {sym} ptr mem)
  2677  	for {
  2678  		_ = v.Args[1]
  2679  		x := v.Args[0]
  2680  		l := v.Args[1]
  2681  		if l.Op != OpAMD64MOVQload {
  2682  			break
  2683  		}
  2684  		off := l.AuxInt
  2685  		sym := l.Aux
  2686  		mem := l.Args[1]
  2687  		ptr := l.Args[0]
  2688  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  2689  			break
  2690  		}
  2691  		v.reset(OpAMD64ADDQload)
  2692  		v.AuxInt = off
  2693  		v.Aux = sym
  2694  		v.AddArg(x)
  2695  		v.AddArg(ptr)
  2696  		v.AddArg(mem)
  2697  		return true
  2698  	}
  2699  	// match: (ADDQ l:(MOVQload [off] {sym} ptr mem) x)
  2700  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  2701  	// result: (ADDQload x [off] {sym} ptr mem)
  2702  	for {
  2703  		x := v.Args[1]
  2704  		l := v.Args[0]
  2705  		if l.Op != OpAMD64MOVQload {
  2706  			break
  2707  		}
  2708  		off := l.AuxInt
  2709  		sym := l.Aux
  2710  		mem := l.Args[1]
  2711  		ptr := l.Args[0]
  2712  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  2713  			break
  2714  		}
  2715  		v.reset(OpAMD64ADDQload)
  2716  		v.AuxInt = off
  2717  		v.Aux = sym
  2718  		v.AddArg(x)
  2719  		v.AddArg(ptr)
  2720  		v.AddArg(mem)
  2721  		return true
  2722  	}
  2723  	return false
  2724  }
  2725  func rewriteValueAMD64_OpAMD64ADDQcarry_0(v *Value) bool {
  2726  	// match: (ADDQcarry x (MOVQconst [c]))
  2727  	// cond: is32Bit(c)
  2728  	// result: (ADDQconstcarry x [c])
  2729  	for {
  2730  		_ = v.Args[1]
  2731  		x := v.Args[0]
  2732  		v_1 := v.Args[1]
  2733  		if v_1.Op != OpAMD64MOVQconst {
  2734  			break
  2735  		}
  2736  		c := v_1.AuxInt
  2737  		if !(is32Bit(c)) {
  2738  			break
  2739  		}
  2740  		v.reset(OpAMD64ADDQconstcarry)
  2741  		v.AuxInt = c
  2742  		v.AddArg(x)
  2743  		return true
  2744  	}
  2745  	// match: (ADDQcarry (MOVQconst [c]) x)
  2746  	// cond: is32Bit(c)
  2747  	// result: (ADDQconstcarry x [c])
  2748  	for {
  2749  		x := v.Args[1]
  2750  		v_0 := v.Args[0]
  2751  		if v_0.Op != OpAMD64MOVQconst {
  2752  			break
  2753  		}
  2754  		c := v_0.AuxInt
  2755  		if !(is32Bit(c)) {
  2756  			break
  2757  		}
  2758  		v.reset(OpAMD64ADDQconstcarry)
  2759  		v.AuxInt = c
  2760  		v.AddArg(x)
  2761  		return true
  2762  	}
  2763  	return false
  2764  }
  2765  func rewriteValueAMD64_OpAMD64ADDQconst_0(v *Value) bool {
  2766  	// match: (ADDQconst [c] (ADDQ x y))
  2767  	// cond:
  2768  	// result: (LEAQ1 [c] x y)
  2769  	for {
  2770  		c := v.AuxInt
  2771  		v_0 := v.Args[0]
  2772  		if v_0.Op != OpAMD64ADDQ {
  2773  			break
  2774  		}
  2775  		y := v_0.Args[1]
  2776  		x := v_0.Args[0]
  2777  		v.reset(OpAMD64LEAQ1)
  2778  		v.AuxInt = c
  2779  		v.AddArg(x)
  2780  		v.AddArg(y)
  2781  		return true
  2782  	}
  2783  	// match: (ADDQconst [c] (SHLQconst [1] x))
  2784  	// cond:
  2785  	// result: (LEAQ1 [c] x x)
  2786  	for {
  2787  		c := v.AuxInt
  2788  		v_0 := v.Args[0]
  2789  		if v_0.Op != OpAMD64SHLQconst {
  2790  			break
  2791  		}
  2792  		if v_0.AuxInt != 1 {
  2793  			break
  2794  		}
  2795  		x := v_0.Args[0]
  2796  		v.reset(OpAMD64LEAQ1)
  2797  		v.AuxInt = c
  2798  		v.AddArg(x)
  2799  		v.AddArg(x)
  2800  		return true
  2801  	}
  2802  	// match: (ADDQconst [c] (LEAQ [d] {s} x))
  2803  	// cond: is32Bit(c+d)
  2804  	// result: (LEAQ [c+d] {s} x)
  2805  	for {
  2806  		c := v.AuxInt
  2807  		v_0 := v.Args[0]
  2808  		if v_0.Op != OpAMD64LEAQ {
  2809  			break
  2810  		}
  2811  		d := v_0.AuxInt
  2812  		s := v_0.Aux
  2813  		x := v_0.Args[0]
  2814  		if !(is32Bit(c + d)) {
  2815  			break
  2816  		}
  2817  		v.reset(OpAMD64LEAQ)
  2818  		v.AuxInt = c + d
  2819  		v.Aux = s
  2820  		v.AddArg(x)
  2821  		return true
  2822  	}
  2823  	// match: (ADDQconst [c] (LEAQ1 [d] {s} x y))
  2824  	// cond: is32Bit(c+d)
  2825  	// result: (LEAQ1 [c+d] {s} x y)
  2826  	for {
  2827  		c := v.AuxInt
  2828  		v_0 := v.Args[0]
  2829  		if v_0.Op != OpAMD64LEAQ1 {
  2830  			break
  2831  		}
  2832  		d := v_0.AuxInt
  2833  		s := v_0.Aux
  2834  		y := v_0.Args[1]
  2835  		x := v_0.Args[0]
  2836  		if !(is32Bit(c + d)) {
  2837  			break
  2838  		}
  2839  		v.reset(OpAMD64LEAQ1)
  2840  		v.AuxInt = c + d
  2841  		v.Aux = s
  2842  		v.AddArg(x)
  2843  		v.AddArg(y)
  2844  		return true
  2845  	}
  2846  	// match: (ADDQconst [c] (LEAQ2 [d] {s} x y))
  2847  	// cond: is32Bit(c+d)
  2848  	// result: (LEAQ2 [c+d] {s} x y)
  2849  	for {
  2850  		c := v.AuxInt
  2851  		v_0 := v.Args[0]
  2852  		if v_0.Op != OpAMD64LEAQ2 {
  2853  			break
  2854  		}
  2855  		d := v_0.AuxInt
  2856  		s := v_0.Aux
  2857  		y := v_0.Args[1]
  2858  		x := v_0.Args[0]
  2859  		if !(is32Bit(c + d)) {
  2860  			break
  2861  		}
  2862  		v.reset(OpAMD64LEAQ2)
  2863  		v.AuxInt = c + d
  2864  		v.Aux = s
  2865  		v.AddArg(x)
  2866  		v.AddArg(y)
  2867  		return true
  2868  	}
  2869  	// match: (ADDQconst [c] (LEAQ4 [d] {s} x y))
  2870  	// cond: is32Bit(c+d)
  2871  	// result: (LEAQ4 [c+d] {s} x y)
  2872  	for {
  2873  		c := v.AuxInt
  2874  		v_0 := v.Args[0]
  2875  		if v_0.Op != OpAMD64LEAQ4 {
  2876  			break
  2877  		}
  2878  		d := v_0.AuxInt
  2879  		s := v_0.Aux
  2880  		y := v_0.Args[1]
  2881  		x := v_0.Args[0]
  2882  		if !(is32Bit(c + d)) {
  2883  			break
  2884  		}
  2885  		v.reset(OpAMD64LEAQ4)
  2886  		v.AuxInt = c + d
  2887  		v.Aux = s
  2888  		v.AddArg(x)
  2889  		v.AddArg(y)
  2890  		return true
  2891  	}
  2892  	// match: (ADDQconst [c] (LEAQ8 [d] {s} x y))
  2893  	// cond: is32Bit(c+d)
  2894  	// result: (LEAQ8 [c+d] {s} x y)
  2895  	for {
  2896  		c := v.AuxInt
  2897  		v_0 := v.Args[0]
  2898  		if v_0.Op != OpAMD64LEAQ8 {
  2899  			break
  2900  		}
  2901  		d := v_0.AuxInt
  2902  		s := v_0.Aux
  2903  		y := v_0.Args[1]
  2904  		x := v_0.Args[0]
  2905  		if !(is32Bit(c + d)) {
  2906  			break
  2907  		}
  2908  		v.reset(OpAMD64LEAQ8)
  2909  		v.AuxInt = c + d
  2910  		v.Aux = s
  2911  		v.AddArg(x)
  2912  		v.AddArg(y)
  2913  		return true
  2914  	}
  2915  	// match: (ADDQconst [0] x)
  2916  	// cond:
  2917  	// result: x
  2918  	for {
  2919  		if v.AuxInt != 0 {
  2920  			break
  2921  		}
  2922  		x := v.Args[0]
  2923  		v.reset(OpCopy)
  2924  		v.Type = x.Type
  2925  		v.AddArg(x)
  2926  		return true
  2927  	}
  2928  	// match: (ADDQconst [c] (MOVQconst [d]))
  2929  	// cond:
  2930  	// result: (MOVQconst [c+d])
  2931  	for {
  2932  		c := v.AuxInt
  2933  		v_0 := v.Args[0]
  2934  		if v_0.Op != OpAMD64MOVQconst {
  2935  			break
  2936  		}
  2937  		d := v_0.AuxInt
  2938  		v.reset(OpAMD64MOVQconst)
  2939  		v.AuxInt = c + d
  2940  		return true
  2941  	}
  2942  	// match: (ADDQconst [c] (ADDQconst [d] x))
  2943  	// cond: is32Bit(c+d)
  2944  	// result: (ADDQconst [c+d] x)
  2945  	for {
  2946  		c := v.AuxInt
  2947  		v_0 := v.Args[0]
  2948  		if v_0.Op != OpAMD64ADDQconst {
  2949  			break
  2950  		}
  2951  		d := v_0.AuxInt
  2952  		x := v_0.Args[0]
  2953  		if !(is32Bit(c + d)) {
  2954  			break
  2955  		}
  2956  		v.reset(OpAMD64ADDQconst)
  2957  		v.AuxInt = c + d
  2958  		v.AddArg(x)
  2959  		return true
  2960  	}
  2961  	return false
  2962  }
  2963  func rewriteValueAMD64_OpAMD64ADDQconst_10(v *Value) bool {
  2964  	// match: (ADDQconst [off] x:(SP))
  2965  	// cond:
  2966  	// result: (LEAQ [off] x)
  2967  	for {
  2968  		off := v.AuxInt
  2969  		x := v.Args[0]
  2970  		if x.Op != OpSP {
  2971  			break
  2972  		}
  2973  		v.reset(OpAMD64LEAQ)
  2974  		v.AuxInt = off
  2975  		v.AddArg(x)
  2976  		return true
  2977  	}
  2978  	return false
  2979  }
  2980  func rewriteValueAMD64_OpAMD64ADDQconstmodify_0(v *Value) bool {
  2981  	// match: (ADDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  2982  	// cond: ValAndOff(valoff1).canAdd(off2)
  2983  	// result: (ADDQconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  2984  	for {
  2985  		valoff1 := v.AuxInt
  2986  		sym := v.Aux
  2987  		mem := v.Args[1]
  2988  		v_0 := v.Args[0]
  2989  		if v_0.Op != OpAMD64ADDQconst {
  2990  			break
  2991  		}
  2992  		off2 := v_0.AuxInt
  2993  		base := v_0.Args[0]
  2994  		if !(ValAndOff(valoff1).canAdd(off2)) {
  2995  			break
  2996  		}
  2997  		v.reset(OpAMD64ADDQconstmodify)
  2998  		v.AuxInt = ValAndOff(valoff1).add(off2)
  2999  		v.Aux = sym
  3000  		v.AddArg(base)
  3001  		v.AddArg(mem)
  3002  		return true
  3003  	}
  3004  	// match: (ADDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  3005  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  3006  	// result: (ADDQconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  3007  	for {
  3008  		valoff1 := v.AuxInt
  3009  		sym1 := v.Aux
  3010  		mem := v.Args[1]
  3011  		v_0 := v.Args[0]
  3012  		if v_0.Op != OpAMD64LEAQ {
  3013  			break
  3014  		}
  3015  		off2 := v_0.AuxInt
  3016  		sym2 := v_0.Aux
  3017  		base := v_0.Args[0]
  3018  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  3019  			break
  3020  		}
  3021  		v.reset(OpAMD64ADDQconstmodify)
  3022  		v.AuxInt = ValAndOff(valoff1).add(off2)
  3023  		v.Aux = mergeSym(sym1, sym2)
  3024  		v.AddArg(base)
  3025  		v.AddArg(mem)
  3026  		return true
  3027  	}
  3028  	return false
  3029  }
  3030  func rewriteValueAMD64_OpAMD64ADDQload_0(v *Value) bool {
  3031  	b := v.Block
  3032  	typ := &b.Func.Config.Types
  3033  	// match: (ADDQload [off1] {sym} val (ADDQconst [off2] base) mem)
  3034  	// cond: is32Bit(off1+off2)
  3035  	// result: (ADDQload [off1+off2] {sym} val base mem)
  3036  	for {
  3037  		off1 := v.AuxInt
  3038  		sym := v.Aux
  3039  		mem := v.Args[2]
  3040  		val := v.Args[0]
  3041  		v_1 := v.Args[1]
  3042  		if v_1.Op != OpAMD64ADDQconst {
  3043  			break
  3044  		}
  3045  		off2 := v_1.AuxInt
  3046  		base := v_1.Args[0]
  3047  		if !(is32Bit(off1 + off2)) {
  3048  			break
  3049  		}
  3050  		v.reset(OpAMD64ADDQload)
  3051  		v.AuxInt = off1 + off2
  3052  		v.Aux = sym
  3053  		v.AddArg(val)
  3054  		v.AddArg(base)
  3055  		v.AddArg(mem)
  3056  		return true
  3057  	}
  3058  	// match: (ADDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
  3059  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  3060  	// result: (ADDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  3061  	for {
  3062  		off1 := v.AuxInt
  3063  		sym1 := v.Aux
  3064  		mem := v.Args[2]
  3065  		val := v.Args[0]
  3066  		v_1 := v.Args[1]
  3067  		if v_1.Op != OpAMD64LEAQ {
  3068  			break
  3069  		}
  3070  		off2 := v_1.AuxInt
  3071  		sym2 := v_1.Aux
  3072  		base := v_1.Args[0]
  3073  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  3074  			break
  3075  		}
  3076  		v.reset(OpAMD64ADDQload)
  3077  		v.AuxInt = off1 + off2
  3078  		v.Aux = mergeSym(sym1, sym2)
  3079  		v.AddArg(val)
  3080  		v.AddArg(base)
  3081  		v.AddArg(mem)
  3082  		return true
  3083  	}
  3084  	// match: (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _))
  3085  	// cond:
  3086  	// result: (ADDQ x (MOVQf2i y))
  3087  	for {
  3088  		off := v.AuxInt
  3089  		sym := v.Aux
  3090  		_ = v.Args[2]
  3091  		x := v.Args[0]
  3092  		ptr := v.Args[1]
  3093  		v_2 := v.Args[2]
  3094  		if v_2.Op != OpAMD64MOVSDstore {
  3095  			break
  3096  		}
  3097  		if v_2.AuxInt != off {
  3098  			break
  3099  		}
  3100  		if v_2.Aux != sym {
  3101  			break
  3102  		}
  3103  		_ = v_2.Args[2]
  3104  		if ptr != v_2.Args[0] {
  3105  			break
  3106  		}
  3107  		y := v_2.Args[1]
  3108  		v.reset(OpAMD64ADDQ)
  3109  		v.AddArg(x)
  3110  		v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64)
  3111  		v0.AddArg(y)
  3112  		v.AddArg(v0)
  3113  		return true
  3114  	}
  3115  	return false
  3116  }
  3117  func rewriteValueAMD64_OpAMD64ADDQmodify_0(v *Value) bool {
  3118  	// match: (ADDQmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  3119  	// cond: is32Bit(off1+off2)
  3120  	// result: (ADDQmodify [off1+off2] {sym} base val mem)
  3121  	for {
  3122  		off1 := v.AuxInt
  3123  		sym := v.Aux
  3124  		mem := v.Args[2]
  3125  		v_0 := v.Args[0]
  3126  		if v_0.Op != OpAMD64ADDQconst {
  3127  			break
  3128  		}
  3129  		off2 := v_0.AuxInt
  3130  		base := v_0.Args[0]
  3131  		val := v.Args[1]
  3132  		if !(is32Bit(off1 + off2)) {
  3133  			break
  3134  		}
  3135  		v.reset(OpAMD64ADDQmodify)
  3136  		v.AuxInt = off1 + off2
  3137  		v.Aux = sym
  3138  		v.AddArg(base)
  3139  		v.AddArg(val)
  3140  		v.AddArg(mem)
  3141  		return true
  3142  	}
  3143  	// match: (ADDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  3144  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  3145  	// result: (ADDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  3146  	for {
  3147  		off1 := v.AuxInt
  3148  		sym1 := v.Aux
  3149  		mem := v.Args[2]
  3150  		v_0 := v.Args[0]
  3151  		if v_0.Op != OpAMD64LEAQ {
  3152  			break
  3153  		}
  3154  		off2 := v_0.AuxInt
  3155  		sym2 := v_0.Aux
  3156  		base := v_0.Args[0]
  3157  		val := v.Args[1]
  3158  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  3159  			break
  3160  		}
  3161  		v.reset(OpAMD64ADDQmodify)
  3162  		v.AuxInt = off1 + off2
  3163  		v.Aux = mergeSym(sym1, sym2)
  3164  		v.AddArg(base)
  3165  		v.AddArg(val)
  3166  		v.AddArg(mem)
  3167  		return true
  3168  	}
  3169  	return false
  3170  }
  3171  func rewriteValueAMD64_OpAMD64ADDSD_0(v *Value) bool {
  3172  	// match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem))
  3173  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  3174  	// result: (ADDSDload x [off] {sym} ptr mem)
  3175  	for {
  3176  		_ = v.Args[1]
  3177  		x := v.Args[0]
  3178  		l := v.Args[1]
  3179  		if l.Op != OpAMD64MOVSDload {
  3180  			break
  3181  		}
  3182  		off := l.AuxInt
  3183  		sym := l.Aux
  3184  		mem := l.Args[1]
  3185  		ptr := l.Args[0]
  3186  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  3187  			break
  3188  		}
  3189  		v.reset(OpAMD64ADDSDload)
  3190  		v.AuxInt = off
  3191  		v.Aux = sym
  3192  		v.AddArg(x)
  3193  		v.AddArg(ptr)
  3194  		v.AddArg(mem)
  3195  		return true
  3196  	}
  3197  	// match: (ADDSD l:(MOVSDload [off] {sym} ptr mem) x)
  3198  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  3199  	// result: (ADDSDload x [off] {sym} ptr mem)
  3200  	for {
  3201  		x := v.Args[1]
  3202  		l := v.Args[0]
  3203  		if l.Op != OpAMD64MOVSDload {
  3204  			break
  3205  		}
  3206  		off := l.AuxInt
  3207  		sym := l.Aux
  3208  		mem := l.Args[1]
  3209  		ptr := l.Args[0]
  3210  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  3211  			break
  3212  		}
  3213  		v.reset(OpAMD64ADDSDload)
  3214  		v.AuxInt = off
  3215  		v.Aux = sym
  3216  		v.AddArg(x)
  3217  		v.AddArg(ptr)
  3218  		v.AddArg(mem)
  3219  		return true
  3220  	}
  3221  	return false
  3222  }
  3223  func rewriteValueAMD64_OpAMD64ADDSDload_0(v *Value) bool {
  3224  	b := v.Block
  3225  	typ := &b.Func.Config.Types
  3226  	// match: (ADDSDload [off1] {sym} val (ADDQconst [off2] base) mem)
  3227  	// cond: is32Bit(off1+off2)
  3228  	// result: (ADDSDload [off1+off2] {sym} val base mem)
  3229  	for {
  3230  		off1 := v.AuxInt
  3231  		sym := v.Aux
  3232  		mem := v.Args[2]
  3233  		val := v.Args[0]
  3234  		v_1 := v.Args[1]
  3235  		if v_1.Op != OpAMD64ADDQconst {
  3236  			break
  3237  		}
  3238  		off2 := v_1.AuxInt
  3239  		base := v_1.Args[0]
  3240  		if !(is32Bit(off1 + off2)) {
  3241  			break
  3242  		}
  3243  		v.reset(OpAMD64ADDSDload)
  3244  		v.AuxInt = off1 + off2
  3245  		v.Aux = sym
  3246  		v.AddArg(val)
  3247  		v.AddArg(base)
  3248  		v.AddArg(mem)
  3249  		return true
  3250  	}
  3251  	// match: (ADDSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
  3252  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  3253  	// result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  3254  	for {
  3255  		off1 := v.AuxInt
  3256  		sym1 := v.Aux
  3257  		mem := v.Args[2]
  3258  		val := v.Args[0]
  3259  		v_1 := v.Args[1]
  3260  		if v_1.Op != OpAMD64LEAQ {
  3261  			break
  3262  		}
  3263  		off2 := v_1.AuxInt
  3264  		sym2 := v_1.Aux
  3265  		base := v_1.Args[0]
  3266  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  3267  			break
  3268  		}
  3269  		v.reset(OpAMD64ADDSDload)
  3270  		v.AuxInt = off1 + off2
  3271  		v.Aux = mergeSym(sym1, sym2)
  3272  		v.AddArg(val)
  3273  		v.AddArg(base)
  3274  		v.AddArg(mem)
  3275  		return true
  3276  	}
  3277  	// match: (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _))
  3278  	// cond:
  3279  	// result: (ADDSD x (MOVQi2f y))
  3280  	for {
  3281  		off := v.AuxInt
  3282  		sym := v.Aux
  3283  		_ = v.Args[2]
  3284  		x := v.Args[0]
  3285  		ptr := v.Args[1]
  3286  		v_2 := v.Args[2]
  3287  		if v_2.Op != OpAMD64MOVQstore {
  3288  			break
  3289  		}
  3290  		if v_2.AuxInt != off {
  3291  			break
  3292  		}
  3293  		if v_2.Aux != sym {
  3294  			break
  3295  		}
  3296  		_ = v_2.Args[2]
  3297  		if ptr != v_2.Args[0] {
  3298  			break
  3299  		}
  3300  		y := v_2.Args[1]
  3301  		v.reset(OpAMD64ADDSD)
  3302  		v.AddArg(x)
  3303  		v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64)
  3304  		v0.AddArg(y)
  3305  		v.AddArg(v0)
  3306  		return true
  3307  	}
  3308  	return false
  3309  }
  3310  func rewriteValueAMD64_OpAMD64ADDSS_0(v *Value) bool {
  3311  	// match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem))
  3312  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  3313  	// result: (ADDSSload x [off] {sym} ptr mem)
  3314  	for {
  3315  		_ = v.Args[1]
  3316  		x := v.Args[0]
  3317  		l := v.Args[1]
  3318  		if l.Op != OpAMD64MOVSSload {
  3319  			break
  3320  		}
  3321  		off := l.AuxInt
  3322  		sym := l.Aux
  3323  		mem := l.Args[1]
  3324  		ptr := l.Args[0]
  3325  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  3326  			break
  3327  		}
  3328  		v.reset(OpAMD64ADDSSload)
  3329  		v.AuxInt = off
  3330  		v.Aux = sym
  3331  		v.AddArg(x)
  3332  		v.AddArg(ptr)
  3333  		v.AddArg(mem)
  3334  		return true
  3335  	}
  3336  	// match: (ADDSS l:(MOVSSload [off] {sym} ptr mem) x)
  3337  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  3338  	// result: (ADDSSload x [off] {sym} ptr mem)
  3339  	for {
  3340  		x := v.Args[1]
  3341  		l := v.Args[0]
  3342  		if l.Op != OpAMD64MOVSSload {
  3343  			break
  3344  		}
  3345  		off := l.AuxInt
  3346  		sym := l.Aux
  3347  		mem := l.Args[1]
  3348  		ptr := l.Args[0]
  3349  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  3350  			break
  3351  		}
  3352  		v.reset(OpAMD64ADDSSload)
  3353  		v.AuxInt = off
  3354  		v.Aux = sym
  3355  		v.AddArg(x)
  3356  		v.AddArg(ptr)
  3357  		v.AddArg(mem)
  3358  		return true
  3359  	}
  3360  	return false
  3361  }
  3362  func rewriteValueAMD64_OpAMD64ADDSSload_0(v *Value) bool {
  3363  	b := v.Block
  3364  	typ := &b.Func.Config.Types
  3365  	// match: (ADDSSload [off1] {sym} val (ADDQconst [off2] base) mem)
  3366  	// cond: is32Bit(off1+off2)
  3367  	// result: (ADDSSload [off1+off2] {sym} val base mem)
  3368  	for {
  3369  		off1 := v.AuxInt
  3370  		sym := v.Aux
  3371  		mem := v.Args[2]
  3372  		val := v.Args[0]
  3373  		v_1 := v.Args[1]
  3374  		if v_1.Op != OpAMD64ADDQconst {
  3375  			break
  3376  		}
  3377  		off2 := v_1.AuxInt
  3378  		base := v_1.Args[0]
  3379  		if !(is32Bit(off1 + off2)) {
  3380  			break
  3381  		}
  3382  		v.reset(OpAMD64ADDSSload)
  3383  		v.AuxInt = off1 + off2
  3384  		v.Aux = sym
  3385  		v.AddArg(val)
  3386  		v.AddArg(base)
  3387  		v.AddArg(mem)
  3388  		return true
  3389  	}
  3390  	// match: (ADDSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
  3391  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  3392  	// result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  3393  	for {
  3394  		off1 := v.AuxInt
  3395  		sym1 := v.Aux
  3396  		mem := v.Args[2]
  3397  		val := v.Args[0]
  3398  		v_1 := v.Args[1]
  3399  		if v_1.Op != OpAMD64LEAQ {
  3400  			break
  3401  		}
  3402  		off2 := v_1.AuxInt
  3403  		sym2 := v_1.Aux
  3404  		base := v_1.Args[0]
  3405  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  3406  			break
  3407  		}
  3408  		v.reset(OpAMD64ADDSSload)
  3409  		v.AuxInt = off1 + off2
  3410  		v.Aux = mergeSym(sym1, sym2)
  3411  		v.AddArg(val)
  3412  		v.AddArg(base)
  3413  		v.AddArg(mem)
  3414  		return true
  3415  	}
  3416  	// match: (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _))
  3417  	// cond:
  3418  	// result: (ADDSS x (MOVLi2f y))
  3419  	for {
  3420  		off := v.AuxInt
  3421  		sym := v.Aux
  3422  		_ = v.Args[2]
  3423  		x := v.Args[0]
  3424  		ptr := v.Args[1]
  3425  		v_2 := v.Args[2]
  3426  		if v_2.Op != OpAMD64MOVLstore {
  3427  			break
  3428  		}
  3429  		if v_2.AuxInt != off {
  3430  			break
  3431  		}
  3432  		if v_2.Aux != sym {
  3433  			break
  3434  		}
  3435  		_ = v_2.Args[2]
  3436  		if ptr != v_2.Args[0] {
  3437  			break
  3438  		}
  3439  		y := v_2.Args[1]
  3440  		v.reset(OpAMD64ADDSS)
  3441  		v.AddArg(x)
  3442  		v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32)
  3443  		v0.AddArg(y)
  3444  		v.AddArg(v0)
  3445  		return true
  3446  	}
  3447  	return false
  3448  }
  3449  func rewriteValueAMD64_OpAMD64ANDL_0(v *Value) bool {
  3450  	b := v.Block
  3451  	config := b.Func.Config
  3452  	// match: (ANDL (NOTL (SHLL (MOVLconst [1]) y)) x)
  3453  	// cond: !config.nacl
  3454  	// result: (BTRL x y)
  3455  	for {
  3456  		x := v.Args[1]
  3457  		v_0 := v.Args[0]
  3458  		if v_0.Op != OpAMD64NOTL {
  3459  			break
  3460  		}
  3461  		v_0_0 := v_0.Args[0]
  3462  		if v_0_0.Op != OpAMD64SHLL {
  3463  			break
  3464  		}
  3465  		y := v_0_0.Args[1]
  3466  		v_0_0_0 := v_0_0.Args[0]
  3467  		if v_0_0_0.Op != OpAMD64MOVLconst {
  3468  			break
  3469  		}
  3470  		if v_0_0_0.AuxInt != 1 {
  3471  			break
  3472  		}
  3473  		if !(!config.nacl) {
  3474  			break
  3475  		}
  3476  		v.reset(OpAMD64BTRL)
  3477  		v.AddArg(x)
  3478  		v.AddArg(y)
  3479  		return true
  3480  	}
  3481  	// match: (ANDL x (NOTL (SHLL (MOVLconst [1]) y)))
  3482  	// cond: !config.nacl
  3483  	// result: (BTRL x y)
  3484  	for {
  3485  		_ = v.Args[1]
  3486  		x := v.Args[0]
  3487  		v_1 := v.Args[1]
  3488  		if v_1.Op != OpAMD64NOTL {
  3489  			break
  3490  		}
  3491  		v_1_0 := v_1.Args[0]
  3492  		if v_1_0.Op != OpAMD64SHLL {
  3493  			break
  3494  		}
  3495  		y := v_1_0.Args[1]
  3496  		v_1_0_0 := v_1_0.Args[0]
  3497  		if v_1_0_0.Op != OpAMD64MOVLconst {
  3498  			break
  3499  		}
  3500  		if v_1_0_0.AuxInt != 1 {
  3501  			break
  3502  		}
  3503  		if !(!config.nacl) {
  3504  			break
  3505  		}
  3506  		v.reset(OpAMD64BTRL)
  3507  		v.AddArg(x)
  3508  		v.AddArg(y)
  3509  		return true
  3510  	}
  3511  	// match: (ANDL (MOVLconst [c]) x)
  3512  	// cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128 && !config.nacl
  3513  	// result: (BTRLconst [log2uint32(^c)] x)
  3514  	for {
  3515  		x := v.Args[1]
  3516  		v_0 := v.Args[0]
  3517  		if v_0.Op != OpAMD64MOVLconst {
  3518  			break
  3519  		}
  3520  		c := v_0.AuxInt
  3521  		if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128 && !config.nacl) {
  3522  			break
  3523  		}
  3524  		v.reset(OpAMD64BTRLconst)
  3525  		v.AuxInt = log2uint32(^c)
  3526  		v.AddArg(x)
  3527  		return true
  3528  	}
  3529  	// match: (ANDL x (MOVLconst [c]))
  3530  	// cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128 && !config.nacl
  3531  	// result: (BTRLconst [log2uint32(^c)] x)
  3532  	for {
  3533  		_ = v.Args[1]
  3534  		x := v.Args[0]
  3535  		v_1 := v.Args[1]
  3536  		if v_1.Op != OpAMD64MOVLconst {
  3537  			break
  3538  		}
  3539  		c := v_1.AuxInt
  3540  		if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128 && !config.nacl) {
  3541  			break
  3542  		}
  3543  		v.reset(OpAMD64BTRLconst)
  3544  		v.AuxInt = log2uint32(^c)
  3545  		v.AddArg(x)
  3546  		return true
  3547  	}
  3548  	// match: (ANDL x (MOVLconst [c]))
  3549  	// cond:
  3550  	// result: (ANDLconst [c] x)
  3551  	for {
  3552  		_ = v.Args[1]
  3553  		x := v.Args[0]
  3554  		v_1 := v.Args[1]
  3555  		if v_1.Op != OpAMD64MOVLconst {
  3556  			break
  3557  		}
  3558  		c := v_1.AuxInt
  3559  		v.reset(OpAMD64ANDLconst)
  3560  		v.AuxInt = c
  3561  		v.AddArg(x)
  3562  		return true
  3563  	}
  3564  	// match: (ANDL (MOVLconst [c]) x)
  3565  	// cond:
  3566  	// result: (ANDLconst [c] x)
  3567  	for {
  3568  		x := v.Args[1]
  3569  		v_0 := v.Args[0]
  3570  		if v_0.Op != OpAMD64MOVLconst {
  3571  			break
  3572  		}
  3573  		c := v_0.AuxInt
  3574  		v.reset(OpAMD64ANDLconst)
  3575  		v.AuxInt = c
  3576  		v.AddArg(x)
  3577  		return true
  3578  	}
  3579  	// match: (ANDL x x)
  3580  	// cond:
  3581  	// result: x
  3582  	for {
  3583  		x := v.Args[1]
  3584  		if x != v.Args[0] {
  3585  			break
  3586  		}
  3587  		v.reset(OpCopy)
  3588  		v.Type = x.Type
  3589  		v.AddArg(x)
  3590  		return true
  3591  	}
  3592  	// match: (ANDL x l:(MOVLload [off] {sym} ptr mem))
  3593  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  3594  	// result: (ANDLload x [off] {sym} ptr mem)
  3595  	for {
  3596  		_ = v.Args[1]
  3597  		x := v.Args[0]
  3598  		l := v.Args[1]
  3599  		if l.Op != OpAMD64MOVLload {
  3600  			break
  3601  		}
  3602  		off := l.AuxInt
  3603  		sym := l.Aux
  3604  		mem := l.Args[1]
  3605  		ptr := l.Args[0]
  3606  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  3607  			break
  3608  		}
  3609  		v.reset(OpAMD64ANDLload)
  3610  		v.AuxInt = off
  3611  		v.Aux = sym
  3612  		v.AddArg(x)
  3613  		v.AddArg(ptr)
  3614  		v.AddArg(mem)
  3615  		return true
  3616  	}
  3617  	// match: (ANDL l:(MOVLload [off] {sym} ptr mem) x)
  3618  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  3619  	// result: (ANDLload x [off] {sym} ptr mem)
  3620  	for {
  3621  		x := v.Args[1]
  3622  		l := v.Args[0]
  3623  		if l.Op != OpAMD64MOVLload {
  3624  			break
  3625  		}
  3626  		off := l.AuxInt
  3627  		sym := l.Aux
  3628  		mem := l.Args[1]
  3629  		ptr := l.Args[0]
  3630  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  3631  			break
  3632  		}
  3633  		v.reset(OpAMD64ANDLload)
  3634  		v.AuxInt = off
  3635  		v.Aux = sym
  3636  		v.AddArg(x)
  3637  		v.AddArg(ptr)
  3638  		v.AddArg(mem)
  3639  		return true
  3640  	}
  3641  	return false
  3642  }
  3643  func rewriteValueAMD64_OpAMD64ANDLconst_0(v *Value) bool {
  3644  	b := v.Block
  3645  	config := b.Func.Config
  3646  	// match: (ANDLconst [c] x)
  3647  	// cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128 && !config.nacl
  3648  	// result: (BTRLconst [log2uint32(^c)] x)
  3649  	for {
  3650  		c := v.AuxInt
  3651  		x := v.Args[0]
  3652  		if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128 && !config.nacl) {
  3653  			break
  3654  		}
  3655  		v.reset(OpAMD64BTRLconst)
  3656  		v.AuxInt = log2uint32(^c)
  3657  		v.AddArg(x)
  3658  		return true
  3659  	}
  3660  	// match: (ANDLconst [c] (ANDLconst [d] x))
  3661  	// cond:
  3662  	// result: (ANDLconst [c & d] x)
  3663  	for {
  3664  		c := v.AuxInt
  3665  		v_0 := v.Args[0]
  3666  		if v_0.Op != OpAMD64ANDLconst {
  3667  			break
  3668  		}
  3669  		d := v_0.AuxInt
  3670  		x := v_0.Args[0]
  3671  		v.reset(OpAMD64ANDLconst)
  3672  		v.AuxInt = c & d
  3673  		v.AddArg(x)
  3674  		return true
  3675  	}
  3676  	// match: (ANDLconst [c] (BTRLconst [d] x))
  3677  	// cond:
  3678  	// result: (ANDLconst [c &^ (1<<uint32(d))] x)
  3679  	for {
  3680  		c := v.AuxInt
  3681  		v_0 := v.Args[0]
  3682  		if v_0.Op != OpAMD64BTRLconst {
  3683  			break
  3684  		}
  3685  		d := v_0.AuxInt
  3686  		x := v_0.Args[0]
  3687  		v.reset(OpAMD64ANDLconst)
  3688  		v.AuxInt = c &^ (1 << uint32(d))
  3689  		v.AddArg(x)
  3690  		return true
  3691  	}
  3692  	// match: (ANDLconst [ 0xFF] x)
  3693  	// cond:
  3694  	// result: (MOVBQZX x)
  3695  	for {
  3696  		if v.AuxInt != 0xFF {
  3697  			break
  3698  		}
  3699  		x := v.Args[0]
  3700  		v.reset(OpAMD64MOVBQZX)
  3701  		v.AddArg(x)
  3702  		return true
  3703  	}
  3704  	// match: (ANDLconst [0xFFFF] x)
  3705  	// cond:
  3706  	// result: (MOVWQZX x)
  3707  	for {
  3708  		if v.AuxInt != 0xFFFF {
  3709  			break
  3710  		}
  3711  		x := v.Args[0]
  3712  		v.reset(OpAMD64MOVWQZX)
  3713  		v.AddArg(x)
  3714  		return true
  3715  	}
  3716  	// match: (ANDLconst [c] _)
  3717  	// cond: int32(c)==0
  3718  	// result: (MOVLconst [0])
  3719  	for {
  3720  		c := v.AuxInt
  3721  		if !(int32(c) == 0) {
  3722  			break
  3723  		}
  3724  		v.reset(OpAMD64MOVLconst)
  3725  		v.AuxInt = 0
  3726  		return true
  3727  	}
  3728  	// match: (ANDLconst [c] x)
  3729  	// cond: int32(c)==-1
  3730  	// result: x
  3731  	for {
  3732  		c := v.AuxInt
  3733  		x := v.Args[0]
  3734  		if !(int32(c) == -1) {
  3735  			break
  3736  		}
  3737  		v.reset(OpCopy)
  3738  		v.Type = x.Type
  3739  		v.AddArg(x)
  3740  		return true
  3741  	}
  3742  	// match: (ANDLconst [c] (MOVLconst [d]))
  3743  	// cond:
  3744  	// result: (MOVLconst [c&d])
  3745  	for {
  3746  		c := v.AuxInt
  3747  		v_0 := v.Args[0]
  3748  		if v_0.Op != OpAMD64MOVLconst {
  3749  			break
  3750  		}
  3751  		d := v_0.AuxInt
  3752  		v.reset(OpAMD64MOVLconst)
  3753  		v.AuxInt = c & d
  3754  		return true
  3755  	}
  3756  	return false
  3757  }
  3758  func rewriteValueAMD64_OpAMD64ANDLconstmodify_0(v *Value) bool {
  3759  	// match: (ANDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  3760  	// cond: ValAndOff(valoff1).canAdd(off2)
  3761  	// result: (ANDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  3762  	for {
  3763  		valoff1 := v.AuxInt
  3764  		sym := v.Aux
  3765  		mem := v.Args[1]
  3766  		v_0 := v.Args[0]
  3767  		if v_0.Op != OpAMD64ADDQconst {
  3768  			break
  3769  		}
  3770  		off2 := v_0.AuxInt
  3771  		base := v_0.Args[0]
  3772  		if !(ValAndOff(valoff1).canAdd(off2)) {
  3773  			break
  3774  		}
  3775  		v.reset(OpAMD64ANDLconstmodify)
  3776  		v.AuxInt = ValAndOff(valoff1).add(off2)
  3777  		v.Aux = sym
  3778  		v.AddArg(base)
  3779  		v.AddArg(mem)
  3780  		return true
  3781  	}
  3782  	// match: (ANDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  3783  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  3784  	// result: (ANDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  3785  	for {
  3786  		valoff1 := v.AuxInt
  3787  		sym1 := v.Aux
  3788  		mem := v.Args[1]
  3789  		v_0 := v.Args[0]
  3790  		if v_0.Op != OpAMD64LEAQ {
  3791  			break
  3792  		}
  3793  		off2 := v_0.AuxInt
  3794  		sym2 := v_0.Aux
  3795  		base := v_0.Args[0]
  3796  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  3797  			break
  3798  		}
  3799  		v.reset(OpAMD64ANDLconstmodify)
  3800  		v.AuxInt = ValAndOff(valoff1).add(off2)
  3801  		v.Aux = mergeSym(sym1, sym2)
  3802  		v.AddArg(base)
  3803  		v.AddArg(mem)
  3804  		return true
  3805  	}
  3806  	return false
  3807  }
  3808  func rewriteValueAMD64_OpAMD64ANDLload_0(v *Value) bool {
  3809  	b := v.Block
  3810  	typ := &b.Func.Config.Types
  3811  	// match: (ANDLload [off1] {sym} val (ADDQconst [off2] base) mem)
  3812  	// cond: is32Bit(off1+off2)
  3813  	// result: (ANDLload [off1+off2] {sym} val base mem)
  3814  	for {
  3815  		off1 := v.AuxInt
  3816  		sym := v.Aux
  3817  		mem := v.Args[2]
  3818  		val := v.Args[0]
  3819  		v_1 := v.Args[1]
  3820  		if v_1.Op != OpAMD64ADDQconst {
  3821  			break
  3822  		}
  3823  		off2 := v_1.AuxInt
  3824  		base := v_1.Args[0]
  3825  		if !(is32Bit(off1 + off2)) {
  3826  			break
  3827  		}
  3828  		v.reset(OpAMD64ANDLload)
  3829  		v.AuxInt = off1 + off2
  3830  		v.Aux = sym
  3831  		v.AddArg(val)
  3832  		v.AddArg(base)
  3833  		v.AddArg(mem)
  3834  		return true
  3835  	}
  3836  	// match: (ANDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
  3837  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  3838  	// result: (ANDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  3839  	for {
  3840  		off1 := v.AuxInt
  3841  		sym1 := v.Aux
  3842  		mem := v.Args[2]
  3843  		val := v.Args[0]
  3844  		v_1 := v.Args[1]
  3845  		if v_1.Op != OpAMD64LEAQ {
  3846  			break
  3847  		}
  3848  		off2 := v_1.AuxInt
  3849  		sym2 := v_1.Aux
  3850  		base := v_1.Args[0]
  3851  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  3852  			break
  3853  		}
  3854  		v.reset(OpAMD64ANDLload)
  3855  		v.AuxInt = off1 + off2
  3856  		v.Aux = mergeSym(sym1, sym2)
  3857  		v.AddArg(val)
  3858  		v.AddArg(base)
  3859  		v.AddArg(mem)
  3860  		return true
  3861  	}
  3862  	// match: (ANDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _))
  3863  	// cond:
  3864  	// result: (ANDL x (MOVLf2i y))
  3865  	for {
  3866  		off := v.AuxInt
  3867  		sym := v.Aux
  3868  		_ = v.Args[2]
  3869  		x := v.Args[0]
  3870  		ptr := v.Args[1]
  3871  		v_2 := v.Args[2]
  3872  		if v_2.Op != OpAMD64MOVSSstore {
  3873  			break
  3874  		}
  3875  		if v_2.AuxInt != off {
  3876  			break
  3877  		}
  3878  		if v_2.Aux != sym {
  3879  			break
  3880  		}
  3881  		_ = v_2.Args[2]
  3882  		if ptr != v_2.Args[0] {
  3883  			break
  3884  		}
  3885  		y := v_2.Args[1]
  3886  		v.reset(OpAMD64ANDL)
  3887  		v.AddArg(x)
  3888  		v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32)
  3889  		v0.AddArg(y)
  3890  		v.AddArg(v0)
  3891  		return true
  3892  	}
  3893  	return false
  3894  }
  3895  func rewriteValueAMD64_OpAMD64ANDLmodify_0(v *Value) bool {
  3896  	// match: (ANDLmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  3897  	// cond: is32Bit(off1+off2)
  3898  	// result: (ANDLmodify [off1+off2] {sym} base val mem)
  3899  	for {
  3900  		off1 := v.AuxInt
  3901  		sym := v.Aux
  3902  		mem := v.Args[2]
  3903  		v_0 := v.Args[0]
  3904  		if v_0.Op != OpAMD64ADDQconst {
  3905  			break
  3906  		}
  3907  		off2 := v_0.AuxInt
  3908  		base := v_0.Args[0]
  3909  		val := v.Args[1]
  3910  		if !(is32Bit(off1 + off2)) {
  3911  			break
  3912  		}
  3913  		v.reset(OpAMD64ANDLmodify)
  3914  		v.AuxInt = off1 + off2
  3915  		v.Aux = sym
  3916  		v.AddArg(base)
  3917  		v.AddArg(val)
  3918  		v.AddArg(mem)
  3919  		return true
  3920  	}
  3921  	// match: (ANDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  3922  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  3923  	// result: (ANDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  3924  	for {
  3925  		off1 := v.AuxInt
  3926  		sym1 := v.Aux
  3927  		mem := v.Args[2]
  3928  		v_0 := v.Args[0]
  3929  		if v_0.Op != OpAMD64LEAQ {
  3930  			break
  3931  		}
  3932  		off2 := v_0.AuxInt
  3933  		sym2 := v_0.Aux
  3934  		base := v_0.Args[0]
  3935  		val := v.Args[1]
  3936  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  3937  			break
  3938  		}
  3939  		v.reset(OpAMD64ANDLmodify)
  3940  		v.AuxInt = off1 + off2
  3941  		v.Aux = mergeSym(sym1, sym2)
  3942  		v.AddArg(base)
  3943  		v.AddArg(val)
  3944  		v.AddArg(mem)
  3945  		return true
  3946  	}
  3947  	return false
  3948  }
  3949  func rewriteValueAMD64_OpAMD64ANDQ_0(v *Value) bool {
  3950  	b := v.Block
  3951  	config := b.Func.Config
  3952  	// match: (ANDQ (NOTQ (SHLQ (MOVQconst [1]) y)) x)
  3953  	// cond: !config.nacl
  3954  	// result: (BTRQ x y)
  3955  	for {
  3956  		x := v.Args[1]
  3957  		v_0 := v.Args[0]
  3958  		if v_0.Op != OpAMD64NOTQ {
  3959  			break
  3960  		}
  3961  		v_0_0 := v_0.Args[0]
  3962  		if v_0_0.Op != OpAMD64SHLQ {
  3963  			break
  3964  		}
  3965  		y := v_0_0.Args[1]
  3966  		v_0_0_0 := v_0_0.Args[0]
  3967  		if v_0_0_0.Op != OpAMD64MOVQconst {
  3968  			break
  3969  		}
  3970  		if v_0_0_0.AuxInt != 1 {
  3971  			break
  3972  		}
  3973  		if !(!config.nacl) {
  3974  			break
  3975  		}
  3976  		v.reset(OpAMD64BTRQ)
  3977  		v.AddArg(x)
  3978  		v.AddArg(y)
  3979  		return true
  3980  	}
  3981  	// match: (ANDQ x (NOTQ (SHLQ (MOVQconst [1]) y)))
  3982  	// cond: !config.nacl
  3983  	// result: (BTRQ x y)
  3984  	for {
  3985  		_ = v.Args[1]
  3986  		x := v.Args[0]
  3987  		v_1 := v.Args[1]
  3988  		if v_1.Op != OpAMD64NOTQ {
  3989  			break
  3990  		}
  3991  		v_1_0 := v_1.Args[0]
  3992  		if v_1_0.Op != OpAMD64SHLQ {
  3993  			break
  3994  		}
  3995  		y := v_1_0.Args[1]
  3996  		v_1_0_0 := v_1_0.Args[0]
  3997  		if v_1_0_0.Op != OpAMD64MOVQconst {
  3998  			break
  3999  		}
  4000  		if v_1_0_0.AuxInt != 1 {
  4001  			break
  4002  		}
  4003  		if !(!config.nacl) {
  4004  			break
  4005  		}
  4006  		v.reset(OpAMD64BTRQ)
  4007  		v.AddArg(x)
  4008  		v.AddArg(y)
  4009  		return true
  4010  	}
  4011  	// match: (ANDQ (MOVQconst [c]) x)
  4012  	// cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128 && !config.nacl
  4013  	// result: (BTRQconst [log2(^c)] x)
  4014  	for {
  4015  		x := v.Args[1]
  4016  		v_0 := v.Args[0]
  4017  		if v_0.Op != OpAMD64MOVQconst {
  4018  			break
  4019  		}
  4020  		c := v_0.AuxInt
  4021  		if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128 && !config.nacl) {
  4022  			break
  4023  		}
  4024  		v.reset(OpAMD64BTRQconst)
  4025  		v.AuxInt = log2(^c)
  4026  		v.AddArg(x)
  4027  		return true
  4028  	}
  4029  	// match: (ANDQ x (MOVQconst [c]))
  4030  	// cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128 && !config.nacl
  4031  	// result: (BTRQconst [log2(^c)] x)
  4032  	for {
  4033  		_ = v.Args[1]
  4034  		x := v.Args[0]
  4035  		v_1 := v.Args[1]
  4036  		if v_1.Op != OpAMD64MOVQconst {
  4037  			break
  4038  		}
  4039  		c := v_1.AuxInt
  4040  		if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128 && !config.nacl) {
  4041  			break
  4042  		}
  4043  		v.reset(OpAMD64BTRQconst)
  4044  		v.AuxInt = log2(^c)
  4045  		v.AddArg(x)
  4046  		return true
  4047  	}
  4048  	// match: (ANDQ x (MOVQconst [c]))
  4049  	// cond: is32Bit(c)
  4050  	// result: (ANDQconst [c] x)
  4051  	for {
  4052  		_ = v.Args[1]
  4053  		x := v.Args[0]
  4054  		v_1 := v.Args[1]
  4055  		if v_1.Op != OpAMD64MOVQconst {
  4056  			break
  4057  		}
  4058  		c := v_1.AuxInt
  4059  		if !(is32Bit(c)) {
  4060  			break
  4061  		}
  4062  		v.reset(OpAMD64ANDQconst)
  4063  		v.AuxInt = c
  4064  		v.AddArg(x)
  4065  		return true
  4066  	}
  4067  	// match: (ANDQ (MOVQconst [c]) x)
  4068  	// cond: is32Bit(c)
  4069  	// result: (ANDQconst [c] x)
  4070  	for {
  4071  		x := v.Args[1]
  4072  		v_0 := v.Args[0]
  4073  		if v_0.Op != OpAMD64MOVQconst {
  4074  			break
  4075  		}
  4076  		c := v_0.AuxInt
  4077  		if !(is32Bit(c)) {
  4078  			break
  4079  		}
  4080  		v.reset(OpAMD64ANDQconst)
  4081  		v.AuxInt = c
  4082  		v.AddArg(x)
  4083  		return true
  4084  	}
  4085  	// match: (ANDQ x x)
  4086  	// cond:
  4087  	// result: x
  4088  	for {
  4089  		x := v.Args[1]
  4090  		if x != v.Args[0] {
  4091  			break
  4092  		}
  4093  		v.reset(OpCopy)
  4094  		v.Type = x.Type
  4095  		v.AddArg(x)
  4096  		return true
  4097  	}
  4098  	// match: (ANDQ x l:(MOVQload [off] {sym} ptr mem))
  4099  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  4100  	// result: (ANDQload x [off] {sym} ptr mem)
  4101  	for {
  4102  		_ = v.Args[1]
  4103  		x := v.Args[0]
  4104  		l := v.Args[1]
  4105  		if l.Op != OpAMD64MOVQload {
  4106  			break
  4107  		}
  4108  		off := l.AuxInt
  4109  		sym := l.Aux
  4110  		mem := l.Args[1]
  4111  		ptr := l.Args[0]
  4112  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  4113  			break
  4114  		}
  4115  		v.reset(OpAMD64ANDQload)
  4116  		v.AuxInt = off
  4117  		v.Aux = sym
  4118  		v.AddArg(x)
  4119  		v.AddArg(ptr)
  4120  		v.AddArg(mem)
  4121  		return true
  4122  	}
  4123  	// match: (ANDQ l:(MOVQload [off] {sym} ptr mem) x)
  4124  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  4125  	// result: (ANDQload x [off] {sym} ptr mem)
  4126  	for {
  4127  		x := v.Args[1]
  4128  		l := v.Args[0]
  4129  		if l.Op != OpAMD64MOVQload {
  4130  			break
  4131  		}
  4132  		off := l.AuxInt
  4133  		sym := l.Aux
  4134  		mem := l.Args[1]
  4135  		ptr := l.Args[0]
  4136  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  4137  			break
  4138  		}
  4139  		v.reset(OpAMD64ANDQload)
  4140  		v.AuxInt = off
  4141  		v.Aux = sym
  4142  		v.AddArg(x)
  4143  		v.AddArg(ptr)
  4144  		v.AddArg(mem)
  4145  		return true
  4146  	}
  4147  	return false
  4148  }
  4149  func rewriteValueAMD64_OpAMD64ANDQconst_0(v *Value) bool {
  4150  	b := v.Block
  4151  	config := b.Func.Config
  4152  	// match: (ANDQconst [c] x)
  4153  	// cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128 && !config.nacl
  4154  	// result: (BTRQconst [log2(^c)] x)
  4155  	for {
  4156  		c := v.AuxInt
  4157  		x := v.Args[0]
  4158  		if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128 && !config.nacl) {
  4159  			break
  4160  		}
  4161  		v.reset(OpAMD64BTRQconst)
  4162  		v.AuxInt = log2(^c)
  4163  		v.AddArg(x)
  4164  		return true
  4165  	}
  4166  	// match: (ANDQconst [c] (ANDQconst [d] x))
  4167  	// cond:
  4168  	// result: (ANDQconst [c & d] x)
  4169  	for {
  4170  		c := v.AuxInt
  4171  		v_0 := v.Args[0]
  4172  		if v_0.Op != OpAMD64ANDQconst {
  4173  			break
  4174  		}
  4175  		d := v_0.AuxInt
  4176  		x := v_0.Args[0]
  4177  		v.reset(OpAMD64ANDQconst)
  4178  		v.AuxInt = c & d
  4179  		v.AddArg(x)
  4180  		return true
  4181  	}
  4182  	// match: (ANDQconst [c] (BTRQconst [d] x))
  4183  	// cond:
  4184  	// result: (ANDQconst [c &^ (1<<uint32(d))] x)
  4185  	for {
  4186  		c := v.AuxInt
  4187  		v_0 := v.Args[0]
  4188  		if v_0.Op != OpAMD64BTRQconst {
  4189  			break
  4190  		}
  4191  		d := v_0.AuxInt
  4192  		x := v_0.Args[0]
  4193  		v.reset(OpAMD64ANDQconst)
  4194  		v.AuxInt = c &^ (1 << uint32(d))
  4195  		v.AddArg(x)
  4196  		return true
  4197  	}
  4198  	// match: (ANDQconst [ 0xFF] x)
  4199  	// cond:
  4200  	// result: (MOVBQZX x)
  4201  	for {
  4202  		if v.AuxInt != 0xFF {
  4203  			break
  4204  		}
  4205  		x := v.Args[0]
  4206  		v.reset(OpAMD64MOVBQZX)
  4207  		v.AddArg(x)
  4208  		return true
  4209  	}
  4210  	// match: (ANDQconst [0xFFFF] x)
  4211  	// cond:
  4212  	// result: (MOVWQZX x)
  4213  	for {
  4214  		if v.AuxInt != 0xFFFF {
  4215  			break
  4216  		}
  4217  		x := v.Args[0]
  4218  		v.reset(OpAMD64MOVWQZX)
  4219  		v.AddArg(x)
  4220  		return true
  4221  	}
  4222  	// match: (ANDQconst [0xFFFFFFFF] x)
  4223  	// cond:
  4224  	// result: (MOVLQZX x)
  4225  	for {
  4226  		if v.AuxInt != 0xFFFFFFFF {
  4227  			break
  4228  		}
  4229  		x := v.Args[0]
  4230  		v.reset(OpAMD64MOVLQZX)
  4231  		v.AddArg(x)
  4232  		return true
  4233  	}
  4234  	// match: (ANDQconst [0] _)
  4235  	// cond:
  4236  	// result: (MOVQconst [0])
  4237  	for {
  4238  		if v.AuxInt != 0 {
  4239  			break
  4240  		}
  4241  		v.reset(OpAMD64MOVQconst)
  4242  		v.AuxInt = 0
  4243  		return true
  4244  	}
  4245  	// match: (ANDQconst [-1] x)
  4246  	// cond:
  4247  	// result: x
  4248  	for {
  4249  		if v.AuxInt != -1 {
  4250  			break
  4251  		}
  4252  		x := v.Args[0]
  4253  		v.reset(OpCopy)
  4254  		v.Type = x.Type
  4255  		v.AddArg(x)
  4256  		return true
  4257  	}
  4258  	// match: (ANDQconst [c] (MOVQconst [d]))
  4259  	// cond:
  4260  	// result: (MOVQconst [c&d])
  4261  	for {
  4262  		c := v.AuxInt
  4263  		v_0 := v.Args[0]
  4264  		if v_0.Op != OpAMD64MOVQconst {
  4265  			break
  4266  		}
  4267  		d := v_0.AuxInt
  4268  		v.reset(OpAMD64MOVQconst)
  4269  		v.AuxInt = c & d
  4270  		return true
  4271  	}
  4272  	return false
  4273  }
  4274  func rewriteValueAMD64_OpAMD64ANDQconstmodify_0(v *Value) bool {
  4275  	// match: (ANDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  4276  	// cond: ValAndOff(valoff1).canAdd(off2)
  4277  	// result: (ANDQconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  4278  	for {
  4279  		valoff1 := v.AuxInt
  4280  		sym := v.Aux
  4281  		mem := v.Args[1]
  4282  		v_0 := v.Args[0]
  4283  		if v_0.Op != OpAMD64ADDQconst {
  4284  			break
  4285  		}
  4286  		off2 := v_0.AuxInt
  4287  		base := v_0.Args[0]
  4288  		if !(ValAndOff(valoff1).canAdd(off2)) {
  4289  			break
  4290  		}
  4291  		v.reset(OpAMD64ANDQconstmodify)
  4292  		v.AuxInt = ValAndOff(valoff1).add(off2)
  4293  		v.Aux = sym
  4294  		v.AddArg(base)
  4295  		v.AddArg(mem)
  4296  		return true
  4297  	}
  4298  	// match: (ANDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  4299  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  4300  	// result: (ANDQconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  4301  	for {
  4302  		valoff1 := v.AuxInt
  4303  		sym1 := v.Aux
  4304  		mem := v.Args[1]
  4305  		v_0 := v.Args[0]
  4306  		if v_0.Op != OpAMD64LEAQ {
  4307  			break
  4308  		}
  4309  		off2 := v_0.AuxInt
  4310  		sym2 := v_0.Aux
  4311  		base := v_0.Args[0]
  4312  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  4313  			break
  4314  		}
  4315  		v.reset(OpAMD64ANDQconstmodify)
  4316  		v.AuxInt = ValAndOff(valoff1).add(off2)
  4317  		v.Aux = mergeSym(sym1, sym2)
  4318  		v.AddArg(base)
  4319  		v.AddArg(mem)
  4320  		return true
  4321  	}
  4322  	return false
  4323  }
  4324  func rewriteValueAMD64_OpAMD64ANDQload_0(v *Value) bool {
  4325  	b := v.Block
  4326  	typ := &b.Func.Config.Types
  4327  	// match: (ANDQload [off1] {sym} val (ADDQconst [off2] base) mem)
  4328  	// cond: is32Bit(off1+off2)
  4329  	// result: (ANDQload [off1+off2] {sym} val base mem)
  4330  	for {
  4331  		off1 := v.AuxInt
  4332  		sym := v.Aux
  4333  		mem := v.Args[2]
  4334  		val := v.Args[0]
  4335  		v_1 := v.Args[1]
  4336  		if v_1.Op != OpAMD64ADDQconst {
  4337  			break
  4338  		}
  4339  		off2 := v_1.AuxInt
  4340  		base := v_1.Args[0]
  4341  		if !(is32Bit(off1 + off2)) {
  4342  			break
  4343  		}
  4344  		v.reset(OpAMD64ANDQload)
  4345  		v.AuxInt = off1 + off2
  4346  		v.Aux = sym
  4347  		v.AddArg(val)
  4348  		v.AddArg(base)
  4349  		v.AddArg(mem)
  4350  		return true
  4351  	}
  4352  	// match: (ANDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
  4353  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4354  	// result: (ANDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  4355  	for {
  4356  		off1 := v.AuxInt
  4357  		sym1 := v.Aux
  4358  		mem := v.Args[2]
  4359  		val := v.Args[0]
  4360  		v_1 := v.Args[1]
  4361  		if v_1.Op != OpAMD64LEAQ {
  4362  			break
  4363  		}
  4364  		off2 := v_1.AuxInt
  4365  		sym2 := v_1.Aux
  4366  		base := v_1.Args[0]
  4367  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4368  			break
  4369  		}
  4370  		v.reset(OpAMD64ANDQload)
  4371  		v.AuxInt = off1 + off2
  4372  		v.Aux = mergeSym(sym1, sym2)
  4373  		v.AddArg(val)
  4374  		v.AddArg(base)
  4375  		v.AddArg(mem)
  4376  		return true
  4377  	}
  4378  	// match: (ANDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _))
  4379  	// cond:
  4380  	// result: (ANDQ x (MOVQf2i y))
  4381  	for {
  4382  		off := v.AuxInt
  4383  		sym := v.Aux
  4384  		_ = v.Args[2]
  4385  		x := v.Args[0]
  4386  		ptr := v.Args[1]
  4387  		v_2 := v.Args[2]
  4388  		if v_2.Op != OpAMD64MOVSDstore {
  4389  			break
  4390  		}
  4391  		if v_2.AuxInt != off {
  4392  			break
  4393  		}
  4394  		if v_2.Aux != sym {
  4395  			break
  4396  		}
  4397  		_ = v_2.Args[2]
  4398  		if ptr != v_2.Args[0] {
  4399  			break
  4400  		}
  4401  		y := v_2.Args[1]
  4402  		v.reset(OpAMD64ANDQ)
  4403  		v.AddArg(x)
  4404  		v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64)
  4405  		v0.AddArg(y)
  4406  		v.AddArg(v0)
  4407  		return true
  4408  	}
  4409  	return false
  4410  }
  4411  func rewriteValueAMD64_OpAMD64ANDQmodify_0(v *Value) bool {
  4412  	// match: (ANDQmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  4413  	// cond: is32Bit(off1+off2)
  4414  	// result: (ANDQmodify [off1+off2] {sym} base val mem)
  4415  	for {
  4416  		off1 := v.AuxInt
  4417  		sym := v.Aux
  4418  		mem := v.Args[2]
  4419  		v_0 := v.Args[0]
  4420  		if v_0.Op != OpAMD64ADDQconst {
  4421  			break
  4422  		}
  4423  		off2 := v_0.AuxInt
  4424  		base := v_0.Args[0]
  4425  		val := v.Args[1]
  4426  		if !(is32Bit(off1 + off2)) {
  4427  			break
  4428  		}
  4429  		v.reset(OpAMD64ANDQmodify)
  4430  		v.AuxInt = off1 + off2
  4431  		v.Aux = sym
  4432  		v.AddArg(base)
  4433  		v.AddArg(val)
  4434  		v.AddArg(mem)
  4435  		return true
  4436  	}
  4437  	// match: (ANDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  4438  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4439  	// result: (ANDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  4440  	for {
  4441  		off1 := v.AuxInt
  4442  		sym1 := v.Aux
  4443  		mem := v.Args[2]
  4444  		v_0 := v.Args[0]
  4445  		if v_0.Op != OpAMD64LEAQ {
  4446  			break
  4447  		}
  4448  		off2 := v_0.AuxInt
  4449  		sym2 := v_0.Aux
  4450  		base := v_0.Args[0]
  4451  		val := v.Args[1]
  4452  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4453  			break
  4454  		}
  4455  		v.reset(OpAMD64ANDQmodify)
  4456  		v.AuxInt = off1 + off2
  4457  		v.Aux = mergeSym(sym1, sym2)
  4458  		v.AddArg(base)
  4459  		v.AddArg(val)
  4460  		v.AddArg(mem)
  4461  		return true
  4462  	}
  4463  	return false
  4464  }
  4465  func rewriteValueAMD64_OpAMD64BSFQ_0(v *Value) bool {
  4466  	b := v.Block
  4467  	// match: (BSFQ (ORQconst <t> [1<<8] (MOVBQZX x)))
  4468  	// cond:
  4469  	// result: (BSFQ (ORQconst <t> [1<<8] x))
  4470  	for {
  4471  		v_0 := v.Args[0]
  4472  		if v_0.Op != OpAMD64ORQconst {
  4473  			break
  4474  		}
  4475  		t := v_0.Type
  4476  		if v_0.AuxInt != 1<<8 {
  4477  			break
  4478  		}
  4479  		v_0_0 := v_0.Args[0]
  4480  		if v_0_0.Op != OpAMD64MOVBQZX {
  4481  			break
  4482  		}
  4483  		x := v_0_0.Args[0]
  4484  		v.reset(OpAMD64BSFQ)
  4485  		v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t)
  4486  		v0.AuxInt = 1 << 8
  4487  		v0.AddArg(x)
  4488  		v.AddArg(v0)
  4489  		return true
  4490  	}
  4491  	// match: (BSFQ (ORQconst <t> [1<<16] (MOVWQZX x)))
  4492  	// cond:
  4493  	// result: (BSFQ (ORQconst <t> [1<<16] x))
  4494  	for {
  4495  		v_0 := v.Args[0]
  4496  		if v_0.Op != OpAMD64ORQconst {
  4497  			break
  4498  		}
  4499  		t := v_0.Type
  4500  		if v_0.AuxInt != 1<<16 {
  4501  			break
  4502  		}
  4503  		v_0_0 := v_0.Args[0]
  4504  		if v_0_0.Op != OpAMD64MOVWQZX {
  4505  			break
  4506  		}
  4507  		x := v_0_0.Args[0]
  4508  		v.reset(OpAMD64BSFQ)
  4509  		v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t)
  4510  		v0.AuxInt = 1 << 16
  4511  		v0.AddArg(x)
  4512  		v.AddArg(v0)
  4513  		return true
  4514  	}
  4515  	return false
  4516  }
  4517  func rewriteValueAMD64_OpAMD64BTCLconst_0(v *Value) bool {
  4518  	// match: (BTCLconst [c] (XORLconst [d] x))
  4519  	// cond:
  4520  	// result: (XORLconst [d ^ 1<<uint32(c)] x)
  4521  	for {
  4522  		c := v.AuxInt
  4523  		v_0 := v.Args[0]
  4524  		if v_0.Op != OpAMD64XORLconst {
  4525  			break
  4526  		}
  4527  		d := v_0.AuxInt
  4528  		x := v_0.Args[0]
  4529  		v.reset(OpAMD64XORLconst)
  4530  		v.AuxInt = d ^ 1<<uint32(c)
  4531  		v.AddArg(x)
  4532  		return true
  4533  	}
  4534  	// match: (BTCLconst [c] (BTCLconst [d] x))
  4535  	// cond:
  4536  	// result: (XORLconst [1<<uint32(c) ^ 1<<uint32(d)] x)
  4537  	for {
  4538  		c := v.AuxInt
  4539  		v_0 := v.Args[0]
  4540  		if v_0.Op != OpAMD64BTCLconst {
  4541  			break
  4542  		}
  4543  		d := v_0.AuxInt
  4544  		x := v_0.Args[0]
  4545  		v.reset(OpAMD64XORLconst)
  4546  		v.AuxInt = 1<<uint32(c) ^ 1<<uint32(d)
  4547  		v.AddArg(x)
  4548  		return true
  4549  	}
  4550  	// match: (BTCLconst [c] (MOVLconst [d]))
  4551  	// cond:
  4552  	// result: (MOVLconst [d^(1<<uint32(c))])
  4553  	for {
  4554  		c := v.AuxInt
  4555  		v_0 := v.Args[0]
  4556  		if v_0.Op != OpAMD64MOVLconst {
  4557  			break
  4558  		}
  4559  		d := v_0.AuxInt
  4560  		v.reset(OpAMD64MOVLconst)
  4561  		v.AuxInt = d ^ (1 << uint32(c))
  4562  		return true
  4563  	}
  4564  	return false
  4565  }
  4566  func rewriteValueAMD64_OpAMD64BTCLconstmodify_0(v *Value) bool {
  4567  	// match: (BTCLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  4568  	// cond: ValAndOff(valoff1).canAdd(off2)
  4569  	// result: (BTCLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  4570  	for {
  4571  		valoff1 := v.AuxInt
  4572  		sym := v.Aux
  4573  		mem := v.Args[1]
  4574  		v_0 := v.Args[0]
  4575  		if v_0.Op != OpAMD64ADDQconst {
  4576  			break
  4577  		}
  4578  		off2 := v_0.AuxInt
  4579  		base := v_0.Args[0]
  4580  		if !(ValAndOff(valoff1).canAdd(off2)) {
  4581  			break
  4582  		}
  4583  		v.reset(OpAMD64BTCLconstmodify)
  4584  		v.AuxInt = ValAndOff(valoff1).add(off2)
  4585  		v.Aux = sym
  4586  		v.AddArg(base)
  4587  		v.AddArg(mem)
  4588  		return true
  4589  	}
  4590  	// match: (BTCLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  4591  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  4592  	// result: (BTCLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  4593  	for {
  4594  		valoff1 := v.AuxInt
  4595  		sym1 := v.Aux
  4596  		mem := v.Args[1]
  4597  		v_0 := v.Args[0]
  4598  		if v_0.Op != OpAMD64LEAQ {
  4599  			break
  4600  		}
  4601  		off2 := v_0.AuxInt
  4602  		sym2 := v_0.Aux
  4603  		base := v_0.Args[0]
  4604  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  4605  			break
  4606  		}
  4607  		v.reset(OpAMD64BTCLconstmodify)
  4608  		v.AuxInt = ValAndOff(valoff1).add(off2)
  4609  		v.Aux = mergeSym(sym1, sym2)
  4610  		v.AddArg(base)
  4611  		v.AddArg(mem)
  4612  		return true
  4613  	}
  4614  	return false
  4615  }
  4616  func rewriteValueAMD64_OpAMD64BTCLmodify_0(v *Value) bool {
  4617  	// match: (BTCLmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  4618  	// cond: is32Bit(off1+off2)
  4619  	// result: (BTCLmodify [off1+off2] {sym} base val mem)
  4620  	for {
  4621  		off1 := v.AuxInt
  4622  		sym := v.Aux
  4623  		mem := v.Args[2]
  4624  		v_0 := v.Args[0]
  4625  		if v_0.Op != OpAMD64ADDQconst {
  4626  			break
  4627  		}
  4628  		off2 := v_0.AuxInt
  4629  		base := v_0.Args[0]
  4630  		val := v.Args[1]
  4631  		if !(is32Bit(off1 + off2)) {
  4632  			break
  4633  		}
  4634  		v.reset(OpAMD64BTCLmodify)
  4635  		v.AuxInt = off1 + off2
  4636  		v.Aux = sym
  4637  		v.AddArg(base)
  4638  		v.AddArg(val)
  4639  		v.AddArg(mem)
  4640  		return true
  4641  	}
  4642  	// match: (BTCLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  4643  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4644  	// result: (BTCLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  4645  	for {
  4646  		off1 := v.AuxInt
  4647  		sym1 := v.Aux
  4648  		mem := v.Args[2]
  4649  		v_0 := v.Args[0]
  4650  		if v_0.Op != OpAMD64LEAQ {
  4651  			break
  4652  		}
  4653  		off2 := v_0.AuxInt
  4654  		sym2 := v_0.Aux
  4655  		base := v_0.Args[0]
  4656  		val := v.Args[1]
  4657  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4658  			break
  4659  		}
  4660  		v.reset(OpAMD64BTCLmodify)
  4661  		v.AuxInt = off1 + off2
  4662  		v.Aux = mergeSym(sym1, sym2)
  4663  		v.AddArg(base)
  4664  		v.AddArg(val)
  4665  		v.AddArg(mem)
  4666  		return true
  4667  	}
  4668  	return false
  4669  }
  4670  func rewriteValueAMD64_OpAMD64BTCQconst_0(v *Value) bool {
  4671  	// match: (BTCQconst [c] (XORQconst [d] x))
  4672  	// cond:
  4673  	// result: (XORQconst [d ^ 1<<uint32(c)] x)
  4674  	for {
  4675  		c := v.AuxInt
  4676  		v_0 := v.Args[0]
  4677  		if v_0.Op != OpAMD64XORQconst {
  4678  			break
  4679  		}
  4680  		d := v_0.AuxInt
  4681  		x := v_0.Args[0]
  4682  		v.reset(OpAMD64XORQconst)
  4683  		v.AuxInt = d ^ 1<<uint32(c)
  4684  		v.AddArg(x)
  4685  		return true
  4686  	}
  4687  	// match: (BTCQconst [c] (BTCQconst [d] x))
  4688  	// cond:
  4689  	// result: (XORQconst [1<<uint32(c) ^ 1<<uint32(d)] x)
  4690  	for {
  4691  		c := v.AuxInt
  4692  		v_0 := v.Args[0]
  4693  		if v_0.Op != OpAMD64BTCQconst {
  4694  			break
  4695  		}
  4696  		d := v_0.AuxInt
  4697  		x := v_0.Args[0]
  4698  		v.reset(OpAMD64XORQconst)
  4699  		v.AuxInt = 1<<uint32(c) ^ 1<<uint32(d)
  4700  		v.AddArg(x)
  4701  		return true
  4702  	}
  4703  	// match: (BTCQconst [c] (MOVQconst [d]))
  4704  	// cond:
  4705  	// result: (MOVQconst [d^(1<<uint32(c))])
  4706  	for {
  4707  		c := v.AuxInt
  4708  		v_0 := v.Args[0]
  4709  		if v_0.Op != OpAMD64MOVQconst {
  4710  			break
  4711  		}
  4712  		d := v_0.AuxInt
  4713  		v.reset(OpAMD64MOVQconst)
  4714  		v.AuxInt = d ^ (1 << uint32(c))
  4715  		return true
  4716  	}
  4717  	return false
  4718  }
  4719  func rewriteValueAMD64_OpAMD64BTCQconstmodify_0(v *Value) bool {
  4720  	// match: (BTCQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  4721  	// cond: ValAndOff(valoff1).canAdd(off2)
  4722  	// result: (BTCQconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  4723  	for {
  4724  		valoff1 := v.AuxInt
  4725  		sym := v.Aux
  4726  		mem := v.Args[1]
  4727  		v_0 := v.Args[0]
  4728  		if v_0.Op != OpAMD64ADDQconst {
  4729  			break
  4730  		}
  4731  		off2 := v_0.AuxInt
  4732  		base := v_0.Args[0]
  4733  		if !(ValAndOff(valoff1).canAdd(off2)) {
  4734  			break
  4735  		}
  4736  		v.reset(OpAMD64BTCQconstmodify)
  4737  		v.AuxInt = ValAndOff(valoff1).add(off2)
  4738  		v.Aux = sym
  4739  		v.AddArg(base)
  4740  		v.AddArg(mem)
  4741  		return true
  4742  	}
  4743  	// match: (BTCQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  4744  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  4745  	// result: (BTCQconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  4746  	for {
  4747  		valoff1 := v.AuxInt
  4748  		sym1 := v.Aux
  4749  		mem := v.Args[1]
  4750  		v_0 := v.Args[0]
  4751  		if v_0.Op != OpAMD64LEAQ {
  4752  			break
  4753  		}
  4754  		off2 := v_0.AuxInt
  4755  		sym2 := v_0.Aux
  4756  		base := v_0.Args[0]
  4757  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  4758  			break
  4759  		}
  4760  		v.reset(OpAMD64BTCQconstmodify)
  4761  		v.AuxInt = ValAndOff(valoff1).add(off2)
  4762  		v.Aux = mergeSym(sym1, sym2)
  4763  		v.AddArg(base)
  4764  		v.AddArg(mem)
  4765  		return true
  4766  	}
  4767  	return false
  4768  }
  4769  func rewriteValueAMD64_OpAMD64BTCQmodify_0(v *Value) bool {
  4770  	// match: (BTCQmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  4771  	// cond: is32Bit(off1+off2)
  4772  	// result: (BTCQmodify [off1+off2] {sym} base val mem)
  4773  	for {
  4774  		off1 := v.AuxInt
  4775  		sym := v.Aux
  4776  		mem := v.Args[2]
  4777  		v_0 := v.Args[0]
  4778  		if v_0.Op != OpAMD64ADDQconst {
  4779  			break
  4780  		}
  4781  		off2 := v_0.AuxInt
  4782  		base := v_0.Args[0]
  4783  		val := v.Args[1]
  4784  		if !(is32Bit(off1 + off2)) {
  4785  			break
  4786  		}
  4787  		v.reset(OpAMD64BTCQmodify)
  4788  		v.AuxInt = off1 + off2
  4789  		v.Aux = sym
  4790  		v.AddArg(base)
  4791  		v.AddArg(val)
  4792  		v.AddArg(mem)
  4793  		return true
  4794  	}
  4795  	// match: (BTCQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  4796  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4797  	// result: (BTCQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  4798  	for {
  4799  		off1 := v.AuxInt
  4800  		sym1 := v.Aux
  4801  		mem := v.Args[2]
  4802  		v_0 := v.Args[0]
  4803  		if v_0.Op != OpAMD64LEAQ {
  4804  			break
  4805  		}
  4806  		off2 := v_0.AuxInt
  4807  		sym2 := v_0.Aux
  4808  		base := v_0.Args[0]
  4809  		val := v.Args[1]
  4810  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4811  			break
  4812  		}
  4813  		v.reset(OpAMD64BTCQmodify)
  4814  		v.AuxInt = off1 + off2
  4815  		v.Aux = mergeSym(sym1, sym2)
  4816  		v.AddArg(base)
  4817  		v.AddArg(val)
  4818  		v.AddArg(mem)
  4819  		return true
  4820  	}
  4821  	return false
  4822  }
  4823  func rewriteValueAMD64_OpAMD64BTLconst_0(v *Value) bool {
  4824  	// match: (BTLconst [c] (SHRQconst [d] x))
  4825  	// cond: (c+d)<64
  4826  	// result: (BTQconst [c+d] x)
  4827  	for {
  4828  		c := v.AuxInt
  4829  		v_0 := v.Args[0]
  4830  		if v_0.Op != OpAMD64SHRQconst {
  4831  			break
  4832  		}
  4833  		d := v_0.AuxInt
  4834  		x := v_0.Args[0]
  4835  		if !((c + d) < 64) {
  4836  			break
  4837  		}
  4838  		v.reset(OpAMD64BTQconst)
  4839  		v.AuxInt = c + d
  4840  		v.AddArg(x)
  4841  		return true
  4842  	}
  4843  	// match: (BTLconst [c] (SHLQconst [d] x))
  4844  	// cond: c>d
  4845  	// result: (BTLconst [c-d] x)
  4846  	for {
  4847  		c := v.AuxInt
  4848  		v_0 := v.Args[0]
  4849  		if v_0.Op != OpAMD64SHLQconst {
  4850  			break
  4851  		}
  4852  		d := v_0.AuxInt
  4853  		x := v_0.Args[0]
  4854  		if !(c > d) {
  4855  			break
  4856  		}
  4857  		v.reset(OpAMD64BTLconst)
  4858  		v.AuxInt = c - d
  4859  		v.AddArg(x)
  4860  		return true
  4861  	}
  4862  	// match: (BTLconst [0] s:(SHRQ x y))
  4863  	// cond:
  4864  	// result: (BTQ y x)
  4865  	for {
  4866  		if v.AuxInt != 0 {
  4867  			break
  4868  		}
  4869  		s := v.Args[0]
  4870  		if s.Op != OpAMD64SHRQ {
  4871  			break
  4872  		}
  4873  		y := s.Args[1]
  4874  		x := s.Args[0]
  4875  		v.reset(OpAMD64BTQ)
  4876  		v.AddArg(y)
  4877  		v.AddArg(x)
  4878  		return true
  4879  	}
  4880  	// match: (BTLconst [c] (SHRLconst [d] x))
  4881  	// cond: (c+d)<32
  4882  	// result: (BTLconst [c+d] x)
  4883  	for {
  4884  		c := v.AuxInt
  4885  		v_0 := v.Args[0]
  4886  		if v_0.Op != OpAMD64SHRLconst {
  4887  			break
  4888  		}
  4889  		d := v_0.AuxInt
  4890  		x := v_0.Args[0]
  4891  		if !((c + d) < 32) {
  4892  			break
  4893  		}
  4894  		v.reset(OpAMD64BTLconst)
  4895  		v.AuxInt = c + d
  4896  		v.AddArg(x)
  4897  		return true
  4898  	}
  4899  	// match: (BTLconst [c] (SHLLconst [d] x))
  4900  	// cond: c>d
  4901  	// result: (BTLconst [c-d] x)
  4902  	for {
  4903  		c := v.AuxInt
  4904  		v_0 := v.Args[0]
  4905  		if v_0.Op != OpAMD64SHLLconst {
  4906  			break
  4907  		}
  4908  		d := v_0.AuxInt
  4909  		x := v_0.Args[0]
  4910  		if !(c > d) {
  4911  			break
  4912  		}
  4913  		v.reset(OpAMD64BTLconst)
  4914  		v.AuxInt = c - d
  4915  		v.AddArg(x)
  4916  		return true
  4917  	}
  4918  	// match: (BTLconst [0] s:(SHRL x y))
  4919  	// cond:
  4920  	// result: (BTL y x)
  4921  	for {
  4922  		if v.AuxInt != 0 {
  4923  			break
  4924  		}
  4925  		s := v.Args[0]
  4926  		if s.Op != OpAMD64SHRL {
  4927  			break
  4928  		}
  4929  		y := s.Args[1]
  4930  		x := s.Args[0]
  4931  		v.reset(OpAMD64BTL)
  4932  		v.AddArg(y)
  4933  		v.AddArg(x)
  4934  		return true
  4935  	}
  4936  	return false
  4937  }
  4938  func rewriteValueAMD64_OpAMD64BTQconst_0(v *Value) bool {
  4939  	// match: (BTQconst [c] (SHRQconst [d] x))
  4940  	// cond: (c+d)<64
  4941  	// result: (BTQconst [c+d] x)
  4942  	for {
  4943  		c := v.AuxInt
  4944  		v_0 := v.Args[0]
  4945  		if v_0.Op != OpAMD64SHRQconst {
  4946  			break
  4947  		}
  4948  		d := v_0.AuxInt
  4949  		x := v_0.Args[0]
  4950  		if !((c + d) < 64) {
  4951  			break
  4952  		}
  4953  		v.reset(OpAMD64BTQconst)
  4954  		v.AuxInt = c + d
  4955  		v.AddArg(x)
  4956  		return true
  4957  	}
  4958  	// match: (BTQconst [c] (SHLQconst [d] x))
  4959  	// cond: c>d
  4960  	// result: (BTQconst [c-d] x)
  4961  	for {
  4962  		c := v.AuxInt
  4963  		v_0 := v.Args[0]
  4964  		if v_0.Op != OpAMD64SHLQconst {
  4965  			break
  4966  		}
  4967  		d := v_0.AuxInt
  4968  		x := v_0.Args[0]
  4969  		if !(c > d) {
  4970  			break
  4971  		}
  4972  		v.reset(OpAMD64BTQconst)
  4973  		v.AuxInt = c - d
  4974  		v.AddArg(x)
  4975  		return true
  4976  	}
  4977  	// match: (BTQconst [0] s:(SHRQ x y))
  4978  	// cond:
  4979  	// result: (BTQ y x)
  4980  	for {
  4981  		if v.AuxInt != 0 {
  4982  			break
  4983  		}
  4984  		s := v.Args[0]
  4985  		if s.Op != OpAMD64SHRQ {
  4986  			break
  4987  		}
  4988  		y := s.Args[1]
  4989  		x := s.Args[0]
  4990  		v.reset(OpAMD64BTQ)
  4991  		v.AddArg(y)
  4992  		v.AddArg(x)
  4993  		return true
  4994  	}
  4995  	return false
  4996  }
  4997  func rewriteValueAMD64_OpAMD64BTRLconst_0(v *Value) bool {
  4998  	// match: (BTRLconst [c] (BTSLconst [c] x))
  4999  	// cond:
  5000  	// result: (BTRLconst [c] x)
  5001  	for {
  5002  		c := v.AuxInt
  5003  		v_0 := v.Args[0]
  5004  		if v_0.Op != OpAMD64BTSLconst {
  5005  			break
  5006  		}
  5007  		if v_0.AuxInt != c {
  5008  			break
  5009  		}
  5010  		x := v_0.Args[0]
  5011  		v.reset(OpAMD64BTRLconst)
  5012  		v.AuxInt = c
  5013  		v.AddArg(x)
  5014  		return true
  5015  	}
  5016  	// match: (BTRLconst [c] (BTCLconst [c] x))
  5017  	// cond:
  5018  	// result: (BTRLconst [c] x)
  5019  	for {
  5020  		c := v.AuxInt
  5021  		v_0 := v.Args[0]
  5022  		if v_0.Op != OpAMD64BTCLconst {
  5023  			break
  5024  		}
  5025  		if v_0.AuxInt != c {
  5026  			break
  5027  		}
  5028  		x := v_0.Args[0]
  5029  		v.reset(OpAMD64BTRLconst)
  5030  		v.AuxInt = c
  5031  		v.AddArg(x)
  5032  		return true
  5033  	}
  5034  	// match: (BTRLconst [c] (ANDLconst [d] x))
  5035  	// cond:
  5036  	// result: (ANDLconst [d &^ (1<<uint32(c))] x)
  5037  	for {
  5038  		c := v.AuxInt
  5039  		v_0 := v.Args[0]
  5040  		if v_0.Op != OpAMD64ANDLconst {
  5041  			break
  5042  		}
  5043  		d := v_0.AuxInt
  5044  		x := v_0.Args[0]
  5045  		v.reset(OpAMD64ANDLconst)
  5046  		v.AuxInt = d &^ (1 << uint32(c))
  5047  		v.AddArg(x)
  5048  		return true
  5049  	}
  5050  	// match: (BTRLconst [c] (BTRLconst [d] x))
  5051  	// cond:
  5052  	// result: (ANDLconst [^(1<<uint32(c) | 1<<uint32(d))] x)
  5053  	for {
  5054  		c := v.AuxInt
  5055  		v_0 := v.Args[0]
  5056  		if v_0.Op != OpAMD64BTRLconst {
  5057  			break
  5058  		}
  5059  		d := v_0.AuxInt
  5060  		x := v_0.Args[0]
  5061  		v.reset(OpAMD64ANDLconst)
  5062  		v.AuxInt = ^(1<<uint32(c) | 1<<uint32(d))
  5063  		v.AddArg(x)
  5064  		return true
  5065  	}
  5066  	// match: (BTRLconst [c] (MOVLconst [d]))
  5067  	// cond:
  5068  	// result: (MOVLconst [d&^(1<<uint32(c))])
  5069  	for {
  5070  		c := v.AuxInt
  5071  		v_0 := v.Args[0]
  5072  		if v_0.Op != OpAMD64MOVLconst {
  5073  			break
  5074  		}
  5075  		d := v_0.AuxInt
  5076  		v.reset(OpAMD64MOVLconst)
  5077  		v.AuxInt = d &^ (1 << uint32(c))
  5078  		return true
  5079  	}
  5080  	return false
  5081  }
  5082  func rewriteValueAMD64_OpAMD64BTRLconstmodify_0(v *Value) bool {
  5083  	// match: (BTRLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  5084  	// cond: ValAndOff(valoff1).canAdd(off2)
  5085  	// result: (BTRLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  5086  	for {
  5087  		valoff1 := v.AuxInt
  5088  		sym := v.Aux
  5089  		mem := v.Args[1]
  5090  		v_0 := v.Args[0]
  5091  		if v_0.Op != OpAMD64ADDQconst {
  5092  			break
  5093  		}
  5094  		off2 := v_0.AuxInt
  5095  		base := v_0.Args[0]
  5096  		if !(ValAndOff(valoff1).canAdd(off2)) {
  5097  			break
  5098  		}
  5099  		v.reset(OpAMD64BTRLconstmodify)
  5100  		v.AuxInt = ValAndOff(valoff1).add(off2)
  5101  		v.Aux = sym
  5102  		v.AddArg(base)
  5103  		v.AddArg(mem)
  5104  		return true
  5105  	}
  5106  	// match: (BTRLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  5107  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  5108  	// result: (BTRLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  5109  	for {
  5110  		valoff1 := v.AuxInt
  5111  		sym1 := v.Aux
  5112  		mem := v.Args[1]
  5113  		v_0 := v.Args[0]
  5114  		if v_0.Op != OpAMD64LEAQ {
  5115  			break
  5116  		}
  5117  		off2 := v_0.AuxInt
  5118  		sym2 := v_0.Aux
  5119  		base := v_0.Args[0]
  5120  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  5121  			break
  5122  		}
  5123  		v.reset(OpAMD64BTRLconstmodify)
  5124  		v.AuxInt = ValAndOff(valoff1).add(off2)
  5125  		v.Aux = mergeSym(sym1, sym2)
  5126  		v.AddArg(base)
  5127  		v.AddArg(mem)
  5128  		return true
  5129  	}
  5130  	return false
  5131  }
  5132  func rewriteValueAMD64_OpAMD64BTRLmodify_0(v *Value) bool {
  5133  	// match: (BTRLmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  5134  	// cond: is32Bit(off1+off2)
  5135  	// result: (BTRLmodify [off1+off2] {sym} base val mem)
  5136  	for {
  5137  		off1 := v.AuxInt
  5138  		sym := v.Aux
  5139  		mem := v.Args[2]
  5140  		v_0 := v.Args[0]
  5141  		if v_0.Op != OpAMD64ADDQconst {
  5142  			break
  5143  		}
  5144  		off2 := v_0.AuxInt
  5145  		base := v_0.Args[0]
  5146  		val := v.Args[1]
  5147  		if !(is32Bit(off1 + off2)) {
  5148  			break
  5149  		}
  5150  		v.reset(OpAMD64BTRLmodify)
  5151  		v.AuxInt = off1 + off2
  5152  		v.Aux = sym
  5153  		v.AddArg(base)
  5154  		v.AddArg(val)
  5155  		v.AddArg(mem)
  5156  		return true
  5157  	}
  5158  	// match: (BTRLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  5159  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  5160  	// result: (BTRLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  5161  	for {
  5162  		off1 := v.AuxInt
  5163  		sym1 := v.Aux
  5164  		mem := v.Args[2]
  5165  		v_0 := v.Args[0]
  5166  		if v_0.Op != OpAMD64LEAQ {
  5167  			break
  5168  		}
  5169  		off2 := v_0.AuxInt
  5170  		sym2 := v_0.Aux
  5171  		base := v_0.Args[0]
  5172  		val := v.Args[1]
  5173  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  5174  			break
  5175  		}
  5176  		v.reset(OpAMD64BTRLmodify)
  5177  		v.AuxInt = off1 + off2
  5178  		v.Aux = mergeSym(sym1, sym2)
  5179  		v.AddArg(base)
  5180  		v.AddArg(val)
  5181  		v.AddArg(mem)
  5182  		return true
  5183  	}
  5184  	return false
  5185  }
  5186  func rewriteValueAMD64_OpAMD64BTRQconst_0(v *Value) bool {
  5187  	// match: (BTRQconst [c] (BTSQconst [c] x))
  5188  	// cond:
  5189  	// result: (BTRQconst [c] x)
  5190  	for {
  5191  		c := v.AuxInt
  5192  		v_0 := v.Args[0]
  5193  		if v_0.Op != OpAMD64BTSQconst {
  5194  			break
  5195  		}
  5196  		if v_0.AuxInt != c {
  5197  			break
  5198  		}
  5199  		x := v_0.Args[0]
  5200  		v.reset(OpAMD64BTRQconst)
  5201  		v.AuxInt = c
  5202  		v.AddArg(x)
  5203  		return true
  5204  	}
  5205  	// match: (BTRQconst [c] (BTCQconst [c] x))
  5206  	// cond:
  5207  	// result: (BTRQconst [c] x)
  5208  	for {
  5209  		c := v.AuxInt
  5210  		v_0 := v.Args[0]
  5211  		if v_0.Op != OpAMD64BTCQconst {
  5212  			break
  5213  		}
  5214  		if v_0.AuxInt != c {
  5215  			break
  5216  		}
  5217  		x := v_0.Args[0]
  5218  		v.reset(OpAMD64BTRQconst)
  5219  		v.AuxInt = c
  5220  		v.AddArg(x)
  5221  		return true
  5222  	}
  5223  	// match: (BTRQconst [c] (ANDQconst [d] x))
  5224  	// cond:
  5225  	// result: (ANDQconst [d &^ (1<<uint32(c))] x)
  5226  	for {
  5227  		c := v.AuxInt
  5228  		v_0 := v.Args[0]
  5229  		if v_0.Op != OpAMD64ANDQconst {
  5230  			break
  5231  		}
  5232  		d := v_0.AuxInt
  5233  		x := v_0.Args[0]
  5234  		v.reset(OpAMD64ANDQconst)
  5235  		v.AuxInt = d &^ (1 << uint32(c))
  5236  		v.AddArg(x)
  5237  		return true
  5238  	}
  5239  	// match: (BTRQconst [c] (BTRQconst [d] x))
  5240  	// cond:
  5241  	// result: (ANDQconst [^(1<<uint32(c) | 1<<uint32(d))] x)
  5242  	for {
  5243  		c := v.AuxInt
  5244  		v_0 := v.Args[0]
  5245  		if v_0.Op != OpAMD64BTRQconst {
  5246  			break
  5247  		}
  5248  		d := v_0.AuxInt
  5249  		x := v_0.Args[0]
  5250  		v.reset(OpAMD64ANDQconst)
  5251  		v.AuxInt = ^(1<<uint32(c) | 1<<uint32(d))
  5252  		v.AddArg(x)
  5253  		return true
  5254  	}
  5255  	// match: (BTRQconst [c] (MOVQconst [d]))
  5256  	// cond:
  5257  	// result: (MOVQconst [d&^(1<<uint32(c))])
  5258  	for {
  5259  		c := v.AuxInt
  5260  		v_0 := v.Args[0]
  5261  		if v_0.Op != OpAMD64MOVQconst {
  5262  			break
  5263  		}
  5264  		d := v_0.AuxInt
  5265  		v.reset(OpAMD64MOVQconst)
  5266  		v.AuxInt = d &^ (1 << uint32(c))
  5267  		return true
  5268  	}
  5269  	return false
  5270  }
  5271  func rewriteValueAMD64_OpAMD64BTRQconstmodify_0(v *Value) bool {
  5272  	// match: (BTRQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  5273  	// cond: ValAndOff(valoff1).canAdd(off2)
  5274  	// result: (BTRQconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  5275  	for {
  5276  		valoff1 := v.AuxInt
  5277  		sym := v.Aux
  5278  		mem := v.Args[1]
  5279  		v_0 := v.Args[0]
  5280  		if v_0.Op != OpAMD64ADDQconst {
  5281  			break
  5282  		}
  5283  		off2 := v_0.AuxInt
  5284  		base := v_0.Args[0]
  5285  		if !(ValAndOff(valoff1).canAdd(off2)) {
  5286  			break
  5287  		}
  5288  		v.reset(OpAMD64BTRQconstmodify)
  5289  		v.AuxInt = ValAndOff(valoff1).add(off2)
  5290  		v.Aux = sym
  5291  		v.AddArg(base)
  5292  		v.AddArg(mem)
  5293  		return true
  5294  	}
  5295  	// match: (BTRQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  5296  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  5297  	// result: (BTRQconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  5298  	for {
  5299  		valoff1 := v.AuxInt
  5300  		sym1 := v.Aux
  5301  		mem := v.Args[1]
  5302  		v_0 := v.Args[0]
  5303  		if v_0.Op != OpAMD64LEAQ {
  5304  			break
  5305  		}
  5306  		off2 := v_0.AuxInt
  5307  		sym2 := v_0.Aux
  5308  		base := v_0.Args[0]
  5309  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  5310  			break
  5311  		}
  5312  		v.reset(OpAMD64BTRQconstmodify)
  5313  		v.AuxInt = ValAndOff(valoff1).add(off2)
  5314  		v.Aux = mergeSym(sym1, sym2)
  5315  		v.AddArg(base)
  5316  		v.AddArg(mem)
  5317  		return true
  5318  	}
  5319  	return false
  5320  }
  5321  func rewriteValueAMD64_OpAMD64BTRQmodify_0(v *Value) bool {
  5322  	// match: (BTRQmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  5323  	// cond: is32Bit(off1+off2)
  5324  	// result: (BTRQmodify [off1+off2] {sym} base val mem)
  5325  	for {
  5326  		off1 := v.AuxInt
  5327  		sym := v.Aux
  5328  		mem := v.Args[2]
  5329  		v_0 := v.Args[0]
  5330  		if v_0.Op != OpAMD64ADDQconst {
  5331  			break
  5332  		}
  5333  		off2 := v_0.AuxInt
  5334  		base := v_0.Args[0]
  5335  		val := v.Args[1]
  5336  		if !(is32Bit(off1 + off2)) {
  5337  			break
  5338  		}
  5339  		v.reset(OpAMD64BTRQmodify)
  5340  		v.AuxInt = off1 + off2
  5341  		v.Aux = sym
  5342  		v.AddArg(base)
  5343  		v.AddArg(val)
  5344  		v.AddArg(mem)
  5345  		return true
  5346  	}
  5347  	// match: (BTRQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  5348  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  5349  	// result: (BTRQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  5350  	for {
  5351  		off1 := v.AuxInt
  5352  		sym1 := v.Aux
  5353  		mem := v.Args[2]
  5354  		v_0 := v.Args[0]
  5355  		if v_0.Op != OpAMD64LEAQ {
  5356  			break
  5357  		}
  5358  		off2 := v_0.AuxInt
  5359  		sym2 := v_0.Aux
  5360  		base := v_0.Args[0]
  5361  		val := v.Args[1]
  5362  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  5363  			break
  5364  		}
  5365  		v.reset(OpAMD64BTRQmodify)
  5366  		v.AuxInt = off1 + off2
  5367  		v.Aux = mergeSym(sym1, sym2)
  5368  		v.AddArg(base)
  5369  		v.AddArg(val)
  5370  		v.AddArg(mem)
  5371  		return true
  5372  	}
  5373  	return false
  5374  }
  5375  func rewriteValueAMD64_OpAMD64BTSLconst_0(v *Value) bool {
  5376  	// match: (BTSLconst [c] (BTRLconst [c] x))
  5377  	// cond:
  5378  	// result: (BTSLconst [c] x)
  5379  	for {
  5380  		c := v.AuxInt
  5381  		v_0 := v.Args[0]
  5382  		if v_0.Op != OpAMD64BTRLconst {
  5383  			break
  5384  		}
  5385  		if v_0.AuxInt != c {
  5386  			break
  5387  		}
  5388  		x := v_0.Args[0]
  5389  		v.reset(OpAMD64BTSLconst)
  5390  		v.AuxInt = c
  5391  		v.AddArg(x)
  5392  		return true
  5393  	}
  5394  	// match: (BTSLconst [c] (BTCLconst [c] x))
  5395  	// cond:
  5396  	// result: (BTSLconst [c] x)
  5397  	for {
  5398  		c := v.AuxInt
  5399  		v_0 := v.Args[0]
  5400  		if v_0.Op != OpAMD64BTCLconst {
  5401  			break
  5402  		}
  5403  		if v_0.AuxInt != c {
  5404  			break
  5405  		}
  5406  		x := v_0.Args[0]
  5407  		v.reset(OpAMD64BTSLconst)
  5408  		v.AuxInt = c
  5409  		v.AddArg(x)
  5410  		return true
  5411  	}
  5412  	// match: (BTSLconst [c] (ORLconst [d] x))
  5413  	// cond:
  5414  	// result: (ORLconst [d | 1<<uint32(c)] x)
  5415  	for {
  5416  		c := v.AuxInt
  5417  		v_0 := v.Args[0]
  5418  		if v_0.Op != OpAMD64ORLconst {
  5419  			break
  5420  		}
  5421  		d := v_0.AuxInt
  5422  		x := v_0.Args[0]
  5423  		v.reset(OpAMD64ORLconst)
  5424  		v.AuxInt = d | 1<<uint32(c)
  5425  		v.AddArg(x)
  5426  		return true
  5427  	}
  5428  	// match: (BTSLconst [c] (BTSLconst [d] x))
  5429  	// cond:
  5430  	// result: (ORLconst [1<<uint32(d) | 1<<uint32(c)] x)
  5431  	for {
  5432  		c := v.AuxInt
  5433  		v_0 := v.Args[0]
  5434  		if v_0.Op != OpAMD64BTSLconst {
  5435  			break
  5436  		}
  5437  		d := v_0.AuxInt
  5438  		x := v_0.Args[0]
  5439  		v.reset(OpAMD64ORLconst)
  5440  		v.AuxInt = 1<<uint32(d) | 1<<uint32(c)
  5441  		v.AddArg(x)
  5442  		return true
  5443  	}
  5444  	// match: (BTSLconst [c] (MOVLconst [d]))
  5445  	// cond:
  5446  	// result: (MOVLconst [d|(1<<uint32(c))])
  5447  	for {
  5448  		c := v.AuxInt
  5449  		v_0 := v.Args[0]
  5450  		if v_0.Op != OpAMD64MOVLconst {
  5451  			break
  5452  		}
  5453  		d := v_0.AuxInt
  5454  		v.reset(OpAMD64MOVLconst)
  5455  		v.AuxInt = d | (1 << uint32(c))
  5456  		return true
  5457  	}
  5458  	return false
  5459  }
  5460  func rewriteValueAMD64_OpAMD64BTSLconstmodify_0(v *Value) bool {
  5461  	// match: (BTSLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  5462  	// cond: ValAndOff(valoff1).canAdd(off2)
  5463  	// result: (BTSLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  5464  	for {
  5465  		valoff1 := v.AuxInt
  5466  		sym := v.Aux
  5467  		mem := v.Args[1]
  5468  		v_0 := v.Args[0]
  5469  		if v_0.Op != OpAMD64ADDQconst {
  5470  			break
  5471  		}
  5472  		off2 := v_0.AuxInt
  5473  		base := v_0.Args[0]
  5474  		if !(ValAndOff(valoff1).canAdd(off2)) {
  5475  			break
  5476  		}
  5477  		v.reset(OpAMD64BTSLconstmodify)
  5478  		v.AuxInt = ValAndOff(valoff1).add(off2)
  5479  		v.Aux = sym
  5480  		v.AddArg(base)
  5481  		v.AddArg(mem)
  5482  		return true
  5483  	}
  5484  	// match: (BTSLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  5485  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  5486  	// result: (BTSLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  5487  	for {
  5488  		valoff1 := v.AuxInt
  5489  		sym1 := v.Aux
  5490  		mem := v.Args[1]
  5491  		v_0 := v.Args[0]
  5492  		if v_0.Op != OpAMD64LEAQ {
  5493  			break
  5494  		}
  5495  		off2 := v_0.AuxInt
  5496  		sym2 := v_0.Aux
  5497  		base := v_0.Args[0]
  5498  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  5499  			break
  5500  		}
  5501  		v.reset(OpAMD64BTSLconstmodify)
  5502  		v.AuxInt = ValAndOff(valoff1).add(off2)
  5503  		v.Aux = mergeSym(sym1, sym2)
  5504  		v.AddArg(base)
  5505  		v.AddArg(mem)
  5506  		return true
  5507  	}
  5508  	return false
  5509  }
  5510  func rewriteValueAMD64_OpAMD64BTSLmodify_0(v *Value) bool {
  5511  	// match: (BTSLmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  5512  	// cond: is32Bit(off1+off2)
  5513  	// result: (BTSLmodify [off1+off2] {sym} base val mem)
  5514  	for {
  5515  		off1 := v.AuxInt
  5516  		sym := v.Aux
  5517  		mem := v.Args[2]
  5518  		v_0 := v.Args[0]
  5519  		if v_0.Op != OpAMD64ADDQconst {
  5520  			break
  5521  		}
  5522  		off2 := v_0.AuxInt
  5523  		base := v_0.Args[0]
  5524  		val := v.Args[1]
  5525  		if !(is32Bit(off1 + off2)) {
  5526  			break
  5527  		}
  5528  		v.reset(OpAMD64BTSLmodify)
  5529  		v.AuxInt = off1 + off2
  5530  		v.Aux = sym
  5531  		v.AddArg(base)
  5532  		v.AddArg(val)
  5533  		v.AddArg(mem)
  5534  		return true
  5535  	}
  5536  	// match: (BTSLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  5537  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  5538  	// result: (BTSLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  5539  	for {
  5540  		off1 := v.AuxInt
  5541  		sym1 := v.Aux
  5542  		mem := v.Args[2]
  5543  		v_0 := v.Args[0]
  5544  		if v_0.Op != OpAMD64LEAQ {
  5545  			break
  5546  		}
  5547  		off2 := v_0.AuxInt
  5548  		sym2 := v_0.Aux
  5549  		base := v_0.Args[0]
  5550  		val := v.Args[1]
  5551  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  5552  			break
  5553  		}
  5554  		v.reset(OpAMD64BTSLmodify)
  5555  		v.AuxInt = off1 + off2
  5556  		v.Aux = mergeSym(sym1, sym2)
  5557  		v.AddArg(base)
  5558  		v.AddArg(val)
  5559  		v.AddArg(mem)
  5560  		return true
  5561  	}
  5562  	return false
  5563  }
  5564  func rewriteValueAMD64_OpAMD64BTSQconst_0(v *Value) bool {
  5565  	// match: (BTSQconst [c] (BTRQconst [c] x))
  5566  	// cond:
  5567  	// result: (BTSQconst [c] x)
  5568  	for {
  5569  		c := v.AuxInt
  5570  		v_0 := v.Args[0]
  5571  		if v_0.Op != OpAMD64BTRQconst {
  5572  			break
  5573  		}
  5574  		if v_0.AuxInt != c {
  5575  			break
  5576  		}
  5577  		x := v_0.Args[0]
  5578  		v.reset(OpAMD64BTSQconst)
  5579  		v.AuxInt = c
  5580  		v.AddArg(x)
  5581  		return true
  5582  	}
  5583  	// match: (BTSQconst [c] (BTCQconst [c] x))
  5584  	// cond:
  5585  	// result: (BTSQconst [c] x)
  5586  	for {
  5587  		c := v.AuxInt
  5588  		v_0 := v.Args[0]
  5589  		if v_0.Op != OpAMD64BTCQconst {
  5590  			break
  5591  		}
  5592  		if v_0.AuxInt != c {
  5593  			break
  5594  		}
  5595  		x := v_0.Args[0]
  5596  		v.reset(OpAMD64BTSQconst)
  5597  		v.AuxInt = c
  5598  		v.AddArg(x)
  5599  		return true
  5600  	}
  5601  	// match: (BTSQconst [c] (ORQconst [d] x))
  5602  	// cond:
  5603  	// result: (ORQconst [d | 1<<uint32(c)] x)
  5604  	for {
  5605  		c := v.AuxInt
  5606  		v_0 := v.Args[0]
  5607  		if v_0.Op != OpAMD64ORQconst {
  5608  			break
  5609  		}
  5610  		d := v_0.AuxInt
  5611  		x := v_0.Args[0]
  5612  		v.reset(OpAMD64ORQconst)
  5613  		v.AuxInt = d | 1<<uint32(c)
  5614  		v.AddArg(x)
  5615  		return true
  5616  	}
  5617  	// match: (BTSQconst [c] (BTSQconst [d] x))
  5618  	// cond:
  5619  	// result: (ORQconst [1<<uint32(d) | 1<<uint32(c)] x)
  5620  	for {
  5621  		c := v.AuxInt
  5622  		v_0 := v.Args[0]
  5623  		if v_0.Op != OpAMD64BTSQconst {
  5624  			break
  5625  		}
  5626  		d := v_0.AuxInt
  5627  		x := v_0.Args[0]
  5628  		v.reset(OpAMD64ORQconst)
  5629  		v.AuxInt = 1<<uint32(d) | 1<<uint32(c)
  5630  		v.AddArg(x)
  5631  		return true
  5632  	}
  5633  	// match: (BTSQconst [c] (MOVQconst [d]))
  5634  	// cond:
  5635  	// result: (MOVQconst [d|(1<<uint32(c))])
  5636  	for {
  5637  		c := v.AuxInt
  5638  		v_0 := v.Args[0]
  5639  		if v_0.Op != OpAMD64MOVQconst {
  5640  			break
  5641  		}
  5642  		d := v_0.AuxInt
  5643  		v.reset(OpAMD64MOVQconst)
  5644  		v.AuxInt = d | (1 << uint32(c))
  5645  		return true
  5646  	}
  5647  	return false
  5648  }
  5649  func rewriteValueAMD64_OpAMD64BTSQconstmodify_0(v *Value) bool {
  5650  	// match: (BTSQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
  5651  	// cond: ValAndOff(valoff1).canAdd(off2)
  5652  	// result: (BTSQconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  5653  	for {
  5654  		valoff1 := v.AuxInt
  5655  		sym := v.Aux
  5656  		mem := v.Args[1]
  5657  		v_0 := v.Args[0]
  5658  		if v_0.Op != OpAMD64ADDQconst {
  5659  			break
  5660  		}
  5661  		off2 := v_0.AuxInt
  5662  		base := v_0.Args[0]
  5663  		if !(ValAndOff(valoff1).canAdd(off2)) {
  5664  			break
  5665  		}
  5666  		v.reset(OpAMD64BTSQconstmodify)
  5667  		v.AuxInt = ValAndOff(valoff1).add(off2)
  5668  		v.Aux = sym
  5669  		v.AddArg(base)
  5670  		v.AddArg(mem)
  5671  		return true
  5672  	}
  5673  	// match: (BTSQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  5674  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  5675  	// result: (BTSQconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  5676  	for {
  5677  		valoff1 := v.AuxInt
  5678  		sym1 := v.Aux
  5679  		mem := v.Args[1]
  5680  		v_0 := v.Args[0]
  5681  		if v_0.Op != OpAMD64LEAQ {
  5682  			break
  5683  		}
  5684  		off2 := v_0.AuxInt
  5685  		sym2 := v_0.Aux
  5686  		base := v_0.Args[0]
  5687  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  5688  			break
  5689  		}
  5690  		v.reset(OpAMD64BTSQconstmodify)
  5691  		v.AuxInt = ValAndOff(valoff1).add(off2)
  5692  		v.Aux = mergeSym(sym1, sym2)
  5693  		v.AddArg(base)
  5694  		v.AddArg(mem)
  5695  		return true
  5696  	}
  5697  	return false
  5698  }
  5699  func rewriteValueAMD64_OpAMD64BTSQmodify_0(v *Value) bool {
  5700  	// match: (BTSQmodify [off1] {sym} (ADDQconst [off2] base) val mem)
  5701  	// cond: is32Bit(off1+off2)
  5702  	// result: (BTSQmodify [off1+off2] {sym} base val mem)
  5703  	for {
  5704  		off1 := v.AuxInt
  5705  		sym := v.Aux
  5706  		mem := v.Args[2]
  5707  		v_0 := v.Args[0]
  5708  		if v_0.Op != OpAMD64ADDQconst {
  5709  			break
  5710  		}
  5711  		off2 := v_0.AuxInt
  5712  		base := v_0.Args[0]
  5713  		val := v.Args[1]
  5714  		if !(is32Bit(off1 + off2)) {
  5715  			break
  5716  		}
  5717  		v.reset(OpAMD64BTSQmodify)
  5718  		v.AuxInt = off1 + off2
  5719  		v.Aux = sym
  5720  		v.AddArg(base)
  5721  		v.AddArg(val)
  5722  		v.AddArg(mem)
  5723  		return true
  5724  	}
  5725  	// match: (BTSQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  5726  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  5727  	// result: (BTSQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  5728  	for {
  5729  		off1 := v.AuxInt
  5730  		sym1 := v.Aux
  5731  		mem := v.Args[2]
  5732  		v_0 := v.Args[0]
  5733  		if v_0.Op != OpAMD64LEAQ {
  5734  			break
  5735  		}
  5736  		off2 := v_0.AuxInt
  5737  		sym2 := v_0.Aux
  5738  		base := v_0.Args[0]
  5739  		val := v.Args[1]
  5740  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  5741  			break
  5742  		}
  5743  		v.reset(OpAMD64BTSQmodify)
  5744  		v.AuxInt = off1 + off2
  5745  		v.Aux = mergeSym(sym1, sym2)
  5746  		v.AddArg(base)
  5747  		v.AddArg(val)
  5748  		v.AddArg(mem)
  5749  		return true
  5750  	}
  5751  	return false
  5752  }
  5753  func rewriteValueAMD64_OpAMD64CMOVLCC_0(v *Value) bool {
  5754  	// match: (CMOVLCC x y (InvertFlags cond))
  5755  	// cond:
  5756  	// result: (CMOVLLS x y cond)
  5757  	for {
  5758  		_ = v.Args[2]
  5759  		x := v.Args[0]
  5760  		y := v.Args[1]
  5761  		v_2 := v.Args[2]
  5762  		if v_2.Op != OpAMD64InvertFlags {
  5763  			break
  5764  		}
  5765  		cond := v_2.Args[0]
  5766  		v.reset(OpAMD64CMOVLLS)
  5767  		v.AddArg(x)
  5768  		v.AddArg(y)
  5769  		v.AddArg(cond)
  5770  		return true
  5771  	}
  5772  	// match: (CMOVLCC _ x (FlagEQ))
  5773  	// cond:
  5774  	// result: x
  5775  	for {
  5776  		_ = v.Args[2]
  5777  		x := v.Args[1]
  5778  		v_2 := v.Args[2]
  5779  		if v_2.Op != OpAMD64FlagEQ {
  5780  			break
  5781  		}
  5782  		v.reset(OpCopy)
  5783  		v.Type = x.Type
  5784  		v.AddArg(x)
  5785  		return true
  5786  	}
  5787  	// match: (CMOVLCC _ x (FlagGT_UGT))
  5788  	// cond:
  5789  	// result: x
  5790  	for {
  5791  		_ = v.Args[2]
  5792  		x := v.Args[1]
  5793  		v_2 := v.Args[2]
  5794  		if v_2.Op != OpAMD64FlagGT_UGT {
  5795  			break
  5796  		}
  5797  		v.reset(OpCopy)
  5798  		v.Type = x.Type
  5799  		v.AddArg(x)
  5800  		return true
  5801  	}
  5802  	// match: (CMOVLCC y _ (FlagGT_ULT))
  5803  	// cond:
  5804  	// result: y
  5805  	for {
  5806  		_ = v.Args[2]
  5807  		y := v.Args[0]
  5808  		v_2 := v.Args[2]
  5809  		if v_2.Op != OpAMD64FlagGT_ULT {
  5810  			break
  5811  		}
  5812  		v.reset(OpCopy)
  5813  		v.Type = y.Type
  5814  		v.AddArg(y)
  5815  		return true
  5816  	}
  5817  	// match: (CMOVLCC y _ (FlagLT_ULT))
  5818  	// cond:
  5819  	// result: y
  5820  	for {
  5821  		_ = v.Args[2]
  5822  		y := v.Args[0]
  5823  		v_2 := v.Args[2]
  5824  		if v_2.Op != OpAMD64FlagLT_ULT {
  5825  			break
  5826  		}
  5827  		v.reset(OpCopy)
  5828  		v.Type = y.Type
  5829  		v.AddArg(y)
  5830  		return true
  5831  	}
  5832  	// match: (CMOVLCC _ x (FlagLT_UGT))
  5833  	// cond:
  5834  	// result: x
  5835  	for {
  5836  		_ = v.Args[2]
  5837  		x := v.Args[1]
  5838  		v_2 := v.Args[2]
  5839  		if v_2.Op != OpAMD64FlagLT_UGT {
  5840  			break
  5841  		}
  5842  		v.reset(OpCopy)
  5843  		v.Type = x.Type
  5844  		v.AddArg(x)
  5845  		return true
  5846  	}
  5847  	return false
  5848  }
  5849  func rewriteValueAMD64_OpAMD64CMOVLCS_0(v *Value) bool {
  5850  	// match: (CMOVLCS x y (InvertFlags cond))
  5851  	// cond:
  5852  	// result: (CMOVLHI x y cond)
  5853  	for {
  5854  		_ = v.Args[2]
  5855  		x := v.Args[0]
  5856  		y := v.Args[1]
  5857  		v_2 := v.Args[2]
  5858  		if v_2.Op != OpAMD64InvertFlags {
  5859  			break
  5860  		}
  5861  		cond := v_2.Args[0]
  5862  		v.reset(OpAMD64CMOVLHI)
  5863  		v.AddArg(x)
  5864  		v.AddArg(y)
  5865  		v.AddArg(cond)
  5866  		return true
  5867  	}
  5868  	// match: (CMOVLCS y _ (FlagEQ))
  5869  	// cond:
  5870  	// result: y
  5871  	for {
  5872  		_ = v.Args[2]
  5873  		y := v.Args[0]
  5874  		v_2 := v.Args[2]
  5875  		if v_2.Op != OpAMD64FlagEQ {
  5876  			break
  5877  		}
  5878  		v.reset(OpCopy)
  5879  		v.Type = y.Type
  5880  		v.AddArg(y)
  5881  		return true
  5882  	}
  5883  	// match: (CMOVLCS y _ (FlagGT_UGT))
  5884  	// cond:
  5885  	// result: y
  5886  	for {
  5887  		_ = v.Args[2]
  5888  		y := v.Args[0]
  5889  		v_2 := v.Args[2]
  5890  		if v_2.Op != OpAMD64FlagGT_UGT {
  5891  			break
  5892  		}
  5893  		v.reset(OpCopy)
  5894  		v.Type = y.Type
  5895  		v.AddArg(y)
  5896  		return true
  5897  	}
  5898  	// match: (CMOVLCS _ x (FlagGT_ULT))
  5899  	// cond:
  5900  	// result: x
  5901  	for {
  5902  		_ = v.Args[2]
  5903  		x := v.Args[1]
  5904  		v_2 := v.Args[2]
  5905  		if v_2.Op != OpAMD64FlagGT_ULT {
  5906  			break
  5907  		}
  5908  		v.reset(OpCopy)
  5909  		v.Type = x.Type
  5910  		v.AddArg(x)
  5911  		return true
  5912  	}
  5913  	// match: (CMOVLCS _ x (FlagLT_ULT))
  5914  	// cond:
  5915  	// result: x
  5916  	for {
  5917  		_ = v.Args[2]
  5918  		x := v.Args[1]
  5919  		v_2 := v.Args[2]
  5920  		if v_2.Op != OpAMD64FlagLT_ULT {
  5921  			break
  5922  		}
  5923  		v.reset(OpCopy)
  5924  		v.Type = x.Type
  5925  		v.AddArg(x)
  5926  		return true
  5927  	}
  5928  	// match: (CMOVLCS y _ (FlagLT_UGT))
  5929  	// cond:
  5930  	// result: y
  5931  	for {
  5932  		_ = v.Args[2]
  5933  		y := v.Args[0]
  5934  		v_2 := v.Args[2]
  5935  		if v_2.Op != OpAMD64FlagLT_UGT {
  5936  			break
  5937  		}
  5938  		v.reset(OpCopy)
  5939  		v.Type = y.Type
  5940  		v.AddArg(y)
  5941  		return true
  5942  	}
  5943  	return false
  5944  }
  5945  func rewriteValueAMD64_OpAMD64CMOVLEQ_0(v *Value) bool {
  5946  	// match: (CMOVLEQ x y (InvertFlags cond))
  5947  	// cond:
  5948  	// result: (CMOVLEQ x y cond)
  5949  	for {
  5950  		_ = v.Args[2]
  5951  		x := v.Args[0]
  5952  		y := v.Args[1]
  5953  		v_2 := v.Args[2]
  5954  		if v_2.Op != OpAMD64InvertFlags {
  5955  			break
  5956  		}
  5957  		cond := v_2.Args[0]
  5958  		v.reset(OpAMD64CMOVLEQ)
  5959  		v.AddArg(x)
  5960  		v.AddArg(y)
  5961  		v.AddArg(cond)
  5962  		return true
  5963  	}
  5964  	// match: (CMOVLEQ _ x (FlagEQ))
  5965  	// cond:
  5966  	// result: x
  5967  	for {
  5968  		_ = v.Args[2]
  5969  		x := v.Args[1]
  5970  		v_2 := v.Args[2]
  5971  		if v_2.Op != OpAMD64FlagEQ {
  5972  			break
  5973  		}
  5974  		v.reset(OpCopy)
  5975  		v.Type = x.Type
  5976  		v.AddArg(x)
  5977  		return true
  5978  	}
  5979  	// match: (CMOVLEQ y _ (FlagGT_UGT))
  5980  	// cond:
  5981  	// result: y
  5982  	for {
  5983  		_ = v.Args[2]
  5984  		y := v.Args[0]
  5985  		v_2 := v.Args[2]
  5986  		if v_2.Op != OpAMD64FlagGT_UGT {
  5987  			break
  5988  		}
  5989  		v.reset(OpCopy)
  5990  		v.Type = y.Type
  5991  		v.AddArg(y)
  5992  		return true
  5993  	}
  5994  	// match: (CMOVLEQ y _ (FlagGT_ULT))
  5995  	// cond:
  5996  	// result: y
  5997  	for {
  5998  		_ = v.Args[2]
  5999  		y := v.Args[0]
  6000  		v_2 := v.Args[2]
  6001  		if v_2.Op != OpAMD64FlagGT_ULT {
  6002  			break
  6003  		}
  6004  		v.reset(OpCopy)
  6005  		v.Type = y.Type
  6006  		v.AddArg(y)
  6007  		return true
  6008  	}
  6009  	// match: (CMOVLEQ y _ (FlagLT_ULT))
  6010  	// cond:
  6011  	// result: y
  6012  	for {
  6013  		_ = v.Args[2]
  6014  		y := v.Args[0]
  6015  		v_2 := v.Args[2]
  6016  		if v_2.Op != OpAMD64FlagLT_ULT {
  6017  			break
  6018  		}
  6019  		v.reset(OpCopy)
  6020  		v.Type = y.Type
  6021  		v.AddArg(y)
  6022  		return true
  6023  	}
  6024  	// match: (CMOVLEQ y _ (FlagLT_UGT))
  6025  	// cond:
  6026  	// result: y
  6027  	for {
  6028  		_ = v.Args[2]
  6029  		y := v.Args[0]
  6030  		v_2 := v.Args[2]
  6031  		if v_2.Op != OpAMD64FlagLT_UGT {
  6032  			break
  6033  		}
  6034  		v.reset(OpCopy)
  6035  		v.Type = y.Type
  6036  		v.AddArg(y)
  6037  		return true
  6038  	}
  6039  	return false
  6040  }
  6041  func rewriteValueAMD64_OpAMD64CMOVLGE_0(v *Value) bool {
  6042  	// match: (CMOVLGE x y (InvertFlags cond))
  6043  	// cond:
  6044  	// result: (CMOVLLE x y cond)
  6045  	for {
  6046  		_ = v.Args[2]
  6047  		x := v.Args[0]
  6048  		y := v.Args[1]
  6049  		v_2 := v.Args[2]
  6050  		if v_2.Op != OpAMD64InvertFlags {
  6051  			break
  6052  		}
  6053  		cond := v_2.Args[0]
  6054  		v.reset(OpAMD64CMOVLLE)
  6055  		v.AddArg(x)
  6056  		v.AddArg(y)
  6057  		v.AddArg(cond)
  6058  		return true
  6059  	}
  6060  	// match: (CMOVLGE _ x (FlagEQ))
  6061  	// cond:
  6062  	// result: x
  6063  	for {
  6064  		_ = v.Args[2]
  6065  		x := v.Args[1]
  6066  		v_2 := v.Args[2]
  6067  		if v_2.Op != OpAMD64FlagEQ {
  6068  			break
  6069  		}
  6070  		v.reset(OpCopy)
  6071  		v.Type = x.Type
  6072  		v.AddArg(x)
  6073  		return true
  6074  	}
  6075  	// match: (CMOVLGE _ x (FlagGT_UGT))
  6076  	// cond:
  6077  	// result: x
  6078  	for {
  6079  		_ = v.Args[2]
  6080  		x := v.Args[1]
  6081  		v_2 := v.Args[2]
  6082  		if v_2.Op != OpAMD64FlagGT_UGT {
  6083  			break
  6084  		}
  6085  		v.reset(OpCopy)
  6086  		v.Type = x.Type
  6087  		v.AddArg(x)
  6088  		return true
  6089  	}
  6090  	// match: (CMOVLGE _ x (FlagGT_ULT))
  6091  	// cond:
  6092  	// result: x
  6093  	for {
  6094  		_ = v.Args[2]
  6095  		x := v.Args[1]
  6096  		v_2 := v.Args[2]
  6097  		if v_2.Op != OpAMD64FlagGT_ULT {
  6098  			break
  6099  		}
  6100  		v.reset(OpCopy)
  6101  		v.Type = x.Type
  6102  		v.AddArg(x)
  6103  		return true
  6104  	}
  6105  	// match: (CMOVLGE y _ (FlagLT_ULT))
  6106  	// cond:
  6107  	// result: y
  6108  	for {
  6109  		_ = v.Args[2]
  6110  		y := v.Args[0]
  6111  		v_2 := v.Args[2]
  6112  		if v_2.Op != OpAMD64FlagLT_ULT {
  6113  			break
  6114  		}
  6115  		v.reset(OpCopy)
  6116  		v.Type = y.Type
  6117  		v.AddArg(y)
  6118  		return true
  6119  	}
  6120  	// match: (CMOVLGE y _ (FlagLT_UGT))
  6121  	// cond:
  6122  	// result: y
  6123  	for {
  6124  		_ = v.Args[2]
  6125  		y := v.Args[0]
  6126  		v_2 := v.Args[2]
  6127  		if v_2.Op != OpAMD64FlagLT_UGT {
  6128  			break
  6129  		}
  6130  		v.reset(OpCopy)
  6131  		v.Type = y.Type
  6132  		v.AddArg(y)
  6133  		return true
  6134  	}
  6135  	return false
  6136  }
  6137  func rewriteValueAMD64_OpAMD64CMOVLGT_0(v *Value) bool {
  6138  	// match: (CMOVLGT x y (InvertFlags cond))
  6139  	// cond:
  6140  	// result: (CMOVLLT x y cond)
  6141  	for {
  6142  		_ = v.Args[2]
  6143  		x := v.Args[0]
  6144  		y := v.Args[1]
  6145  		v_2 := v.Args[2]
  6146  		if v_2.Op != OpAMD64InvertFlags {
  6147  			break
  6148  		}
  6149  		cond := v_2.Args[0]
  6150  		v.reset(OpAMD64CMOVLLT)
  6151  		v.AddArg(x)
  6152  		v.AddArg(y)
  6153  		v.AddArg(cond)
  6154  		return true
  6155  	}
  6156  	// match: (CMOVLGT y _ (FlagEQ))
  6157  	// cond:
  6158  	// result: y
  6159  	for {
  6160  		_ = v.Args[2]
  6161  		y := v.Args[0]
  6162  		v_2 := v.Args[2]
  6163  		if v_2.Op != OpAMD64FlagEQ {
  6164  			break
  6165  		}
  6166  		v.reset(OpCopy)
  6167  		v.Type = y.Type
  6168  		v.AddArg(y)
  6169  		return true
  6170  	}
  6171  	// match: (CMOVLGT _ x (FlagGT_UGT))
  6172  	// cond:
  6173  	// result: x
  6174  	for {
  6175  		_ = v.Args[2]
  6176  		x := v.Args[1]
  6177  		v_2 := v.Args[2]
  6178  		if v_2.Op != OpAMD64FlagGT_UGT {
  6179  			break
  6180  		}
  6181  		v.reset(OpCopy)
  6182  		v.Type = x.Type
  6183  		v.AddArg(x)
  6184  		return true
  6185  	}
  6186  	// match: (CMOVLGT _ x (FlagGT_ULT))
  6187  	// cond:
  6188  	// result: x
  6189  	for {
  6190  		_ = v.Args[2]
  6191  		x := v.Args[1]
  6192  		v_2 := v.Args[2]
  6193  		if v_2.Op != OpAMD64FlagGT_ULT {
  6194  			break
  6195  		}
  6196  		v.reset(OpCopy)
  6197  		v.Type = x.Type
  6198  		v.AddArg(x)
  6199  		return true
  6200  	}
  6201  	// match: (CMOVLGT y _ (FlagLT_ULT))
  6202  	// cond:
  6203  	// result: y
  6204  	for {
  6205  		_ = v.Args[2]
  6206  		y := v.Args[0]
  6207  		v_2 := v.Args[2]
  6208  		if v_2.Op != OpAMD64FlagLT_ULT {
  6209  			break
  6210  		}
  6211  		v.reset(OpCopy)
  6212  		v.Type = y.Type
  6213  		v.AddArg(y)
  6214  		return true
  6215  	}
  6216  	// match: (CMOVLGT y _ (FlagLT_UGT))
  6217  	// cond:
  6218  	// result: y
  6219  	for {
  6220  		_ = v.Args[2]
  6221  		y := v.Args[0]
  6222  		v_2 := v.Args[2]
  6223  		if v_2.Op != OpAMD64FlagLT_UGT {
  6224  			break
  6225  		}
  6226  		v.reset(OpCopy)
  6227  		v.Type = y.Type
  6228  		v.AddArg(y)
  6229  		return true
  6230  	}
  6231  	return false
  6232  }
  6233  func rewriteValueAMD64_OpAMD64CMOVLHI_0(v *Value) bool {
  6234  	// match: (CMOVLHI x y (InvertFlags cond))
  6235  	// cond:
  6236  	// result: (CMOVLCS x y cond)
  6237  	for {
  6238  		_ = v.Args[2]
  6239  		x := v.Args[0]
  6240  		y := v.Args[1]
  6241  		v_2 := v.Args[2]
  6242  		if v_2.Op != OpAMD64InvertFlags {
  6243  			break
  6244  		}
  6245  		cond := v_2.Args[0]
  6246  		v.reset(OpAMD64CMOVLCS)
  6247  		v.AddArg(x)
  6248  		v.AddArg(y)
  6249  		v.AddArg(cond)
  6250  		return true
  6251  	}
  6252  	// match: (CMOVLHI y _ (FlagEQ))
  6253  	// cond:
  6254  	// result: y
  6255  	for {
  6256  		_ = v.Args[2]
  6257  		y := v.Args[0]
  6258  		v_2 := v.Args[2]
  6259  		if v_2.Op != OpAMD64FlagEQ {
  6260  			break
  6261  		}
  6262  		v.reset(OpCopy)
  6263  		v.Type = y.Type
  6264  		v.AddArg(y)
  6265  		return true
  6266  	}
  6267  	// match: (CMOVLHI _ x (FlagGT_UGT))
  6268  	// cond:
  6269  	// result: x
  6270  	for {
  6271  		_ = v.Args[2]
  6272  		x := v.Args[1]
  6273  		v_2 := v.Args[2]
  6274  		if v_2.Op != OpAMD64FlagGT_UGT {
  6275  			break
  6276  		}
  6277  		v.reset(OpCopy)
  6278  		v.Type = x.Type
  6279  		v.AddArg(x)
  6280  		return true
  6281  	}
  6282  	// match: (CMOVLHI y _ (FlagGT_ULT))
  6283  	// cond:
  6284  	// result: y
  6285  	for {
  6286  		_ = v.Args[2]
  6287  		y := v.Args[0]
  6288  		v_2 := v.Args[2]
  6289  		if v_2.Op != OpAMD64FlagGT_ULT {
  6290  			break
  6291  		}
  6292  		v.reset(OpCopy)
  6293  		v.Type = y.Type
  6294  		v.AddArg(y)
  6295  		return true
  6296  	}
  6297  	// match: (CMOVLHI y _ (FlagLT_ULT))
  6298  	// cond:
  6299  	// result: y
  6300  	for {
  6301  		_ = v.Args[2]
  6302  		y := v.Args[0]
  6303  		v_2 := v.Args[2]
  6304  		if v_2.Op != OpAMD64FlagLT_ULT {
  6305  			break
  6306  		}
  6307  		v.reset(OpCopy)
  6308  		v.Type = y.Type
  6309  		v.AddArg(y)
  6310  		return true
  6311  	}
  6312  	// match: (CMOVLHI _ x (FlagLT_UGT))
  6313  	// cond:
  6314  	// result: x
  6315  	for {
  6316  		_ = v.Args[2]
  6317  		x := v.Args[1]
  6318  		v_2 := v.Args[2]
  6319  		if v_2.Op != OpAMD64FlagLT_UGT {
  6320  			break
  6321  		}
  6322  		v.reset(OpCopy)
  6323  		v.Type = x.Type
  6324  		v.AddArg(x)
  6325  		return true
  6326  	}
  6327  	return false
  6328  }
  6329  func rewriteValueAMD64_OpAMD64CMOVLLE_0(v *Value) bool {
  6330  	// match: (CMOVLLE x y (InvertFlags cond))
  6331  	// cond:
  6332  	// result: (CMOVLGE x y cond)
  6333  	for {
  6334  		_ = v.Args[2]
  6335  		x := v.Args[0]
  6336  		y := v.Args[1]
  6337  		v_2 := v.Args[2]
  6338  		if v_2.Op != OpAMD64InvertFlags {
  6339  			break
  6340  		}
  6341  		cond := v_2.Args[0]
  6342  		v.reset(OpAMD64CMOVLGE)
  6343  		v.AddArg(x)
  6344  		v.AddArg(y)
  6345  		v.AddArg(cond)
  6346  		return true
  6347  	}
  6348  	// match: (CMOVLLE _ x (FlagEQ))
  6349  	// cond:
  6350  	// result: x
  6351  	for {
  6352  		_ = v.Args[2]
  6353  		x := v.Args[1]
  6354  		v_2 := v.Args[2]
  6355  		if v_2.Op != OpAMD64FlagEQ {
  6356  			break
  6357  		}
  6358  		v.reset(OpCopy)
  6359  		v.Type = x.Type
  6360  		v.AddArg(x)
  6361  		return true
  6362  	}
  6363  	// match: (CMOVLLE y _ (FlagGT_UGT))
  6364  	// cond:
  6365  	// result: y
  6366  	for {
  6367  		_ = v.Args[2]
  6368  		y := v.Args[0]
  6369  		v_2 := v.Args[2]
  6370  		if v_2.Op != OpAMD64FlagGT_UGT {
  6371  			break
  6372  		}
  6373  		v.reset(OpCopy)
  6374  		v.Type = y.Type
  6375  		v.AddArg(y)
  6376  		return true
  6377  	}
  6378  	// match: (CMOVLLE y _ (FlagGT_ULT))
  6379  	// cond:
  6380  	// result: y
  6381  	for {
  6382  		_ = v.Args[2]
  6383  		y := v.Args[0]
  6384  		v_2 := v.Args[2]
  6385  		if v_2.Op != OpAMD64FlagGT_ULT {
  6386  			break
  6387  		}
  6388  		v.reset(OpCopy)
  6389  		v.Type = y.Type
  6390  		v.AddArg(y)
  6391  		return true
  6392  	}
  6393  	// match: (CMOVLLE _ x (FlagLT_ULT))
  6394  	// cond:
  6395  	// result: x
  6396  	for {
  6397  		_ = v.Args[2]
  6398  		x := v.Args[1]
  6399  		v_2 := v.Args[2]
  6400  		if v_2.Op != OpAMD64FlagLT_ULT {
  6401  			break
  6402  		}
  6403  		v.reset(OpCopy)
  6404  		v.Type = x.Type
  6405  		v.AddArg(x)
  6406  		return true
  6407  	}
  6408  	// match: (CMOVLLE _ x (FlagLT_UGT))
  6409  	// cond:
  6410  	// result: x
  6411  	for {
  6412  		_ = v.Args[2]
  6413  		x := v.Args[1]
  6414  		v_2 := v.Args[2]
  6415  		if v_2.Op != OpAMD64FlagLT_UGT {
  6416  			break
  6417  		}
  6418  		v.reset(OpCopy)
  6419  		v.Type = x.Type
  6420  		v.AddArg(x)
  6421  		return true
  6422  	}
  6423  	return false
  6424  }
  6425  func rewriteValueAMD64_OpAMD64CMOVLLS_0(v *Value) bool {
  6426  	// match: (CMOVLLS x y (InvertFlags cond))
  6427  	// cond:
  6428  	// result: (CMOVLCC x y cond)
  6429  	for {
  6430  		_ = v.Args[2]
  6431  		x := v.Args[0]
  6432  		y := v.Args[1]
  6433  		v_2 := v.Args[2]
  6434  		if v_2.Op != OpAMD64InvertFlags {
  6435  			break
  6436  		}
  6437  		cond := v_2.Args[0]
  6438  		v.reset(OpAMD64CMOVLCC)
  6439  		v.AddArg(x)
  6440  		v.AddArg(y)
  6441  		v.AddArg(cond)
  6442  		return true
  6443  	}
  6444  	// match: (CMOVLLS _ x (FlagEQ))
  6445  	// cond:
  6446  	// result: x
  6447  	for {
  6448  		_ = v.Args[2]
  6449  		x := v.Args[1]
  6450  		v_2 := v.Args[2]
  6451  		if v_2.Op != OpAMD64FlagEQ {
  6452  			break
  6453  		}
  6454  		v.reset(OpCopy)
  6455  		v.Type = x.Type
  6456  		v.AddArg(x)
  6457  		return true
  6458  	}
  6459  	// match: (CMOVLLS y _ (FlagGT_UGT))
  6460  	// cond:
  6461  	// result: y
  6462  	for {
  6463  		_ = v.Args[2]
  6464  		y := v.Args[0]
  6465  		v_2 := v.Args[2]
  6466  		if v_2.Op != OpAMD64FlagGT_UGT {
  6467  			break
  6468  		}
  6469  		v.reset(OpCopy)
  6470  		v.Type = y.Type
  6471  		v.AddArg(y)
  6472  		return true
  6473  	}
  6474  	// match: (CMOVLLS _ x (FlagGT_ULT))
  6475  	// cond:
  6476  	// result: x
  6477  	for {
  6478  		_ = v.Args[2]
  6479  		x := v.Args[1]
  6480  		v_2 := v.Args[2]
  6481  		if v_2.Op != OpAMD64FlagGT_ULT {
  6482  			break
  6483  		}
  6484  		v.reset(OpCopy)
  6485  		v.Type = x.Type
  6486  		v.AddArg(x)
  6487  		return true
  6488  	}
  6489  	// match: (CMOVLLS _ x (FlagLT_ULT))
  6490  	// cond:
  6491  	// result: x
  6492  	for {
  6493  		_ = v.Args[2]
  6494  		x := v.Args[1]
  6495  		v_2 := v.Args[2]
  6496  		if v_2.Op != OpAMD64FlagLT_ULT {
  6497  			break
  6498  		}
  6499  		v.reset(OpCopy)
  6500  		v.Type = x.Type
  6501  		v.AddArg(x)
  6502  		return true
  6503  	}
  6504  	// match: (CMOVLLS y _ (FlagLT_UGT))
  6505  	// cond:
  6506  	// result: y
  6507  	for {
  6508  		_ = v.Args[2]
  6509  		y := v.Args[0]
  6510  		v_2 := v.Args[2]
  6511  		if v_2.Op != OpAMD64FlagLT_UGT {
  6512  			break
  6513  		}
  6514  		v.reset(OpCopy)
  6515  		v.Type = y.Type
  6516  		v.AddArg(y)
  6517  		return true
  6518  	}
  6519  	return false
  6520  }
  6521  func rewriteValueAMD64_OpAMD64CMOVLLT_0(v *Value) bool {
  6522  	// match: (CMOVLLT x y (InvertFlags cond))
  6523  	// cond:
  6524  	// result: (CMOVLGT x y cond)
  6525  	for {
  6526  		_ = v.Args[2]
  6527  		x := v.Args[0]
  6528  		y := v.Args[1]
  6529  		v_2 := v.Args[2]
  6530  		if v_2.Op != OpAMD64InvertFlags {
  6531  			break
  6532  		}
  6533  		cond := v_2.Args[0]
  6534  		v.reset(OpAMD64CMOVLGT)
  6535  		v.AddArg(x)
  6536  		v.AddArg(y)
  6537  		v.AddArg(cond)
  6538  		return true
  6539  	}
  6540  	// match: (CMOVLLT y _ (FlagEQ))
  6541  	// cond:
  6542  	// result: y
  6543  	for {
  6544  		_ = v.Args[2]
  6545  		y := v.Args[0]
  6546  		v_2 := v.Args[2]
  6547  		if v_2.Op != OpAMD64FlagEQ {
  6548  			break
  6549  		}
  6550  		v.reset(OpCopy)
  6551  		v.Type = y.Type
  6552  		v.AddArg(y)
  6553  		return true
  6554  	}
  6555  	// match: (CMOVLLT y _ (FlagGT_UGT))
  6556  	// cond:
  6557  	// result: y
  6558  	for {
  6559  		_ = v.Args[2]
  6560  		y := v.Args[0]
  6561  		v_2 := v.Args[2]
  6562  		if v_2.Op != OpAMD64FlagGT_UGT {
  6563  			break
  6564  		}
  6565  		v.reset(OpCopy)
  6566  		v.Type = y.Type
  6567  		v.AddArg(y)
  6568  		return true
  6569  	}
  6570  	// match: (CMOVLLT y _ (FlagGT_ULT))
  6571  	// cond:
  6572  	// result: y
  6573  	for {
  6574  		_ = v.Args[2]
  6575  		y := v.Args[0]
  6576  		v_2 := v.Args[2]
  6577  		if v_2.Op != OpAMD64FlagGT_ULT {
  6578  			break
  6579  		}
  6580  		v.reset(OpCopy)
  6581  		v.Type = y.Type
  6582  		v.AddArg(y)
  6583  		return true
  6584  	}
  6585  	// match: (CMOVLLT _ x (FlagLT_ULT))
  6586  	// cond:
  6587  	// result: x
  6588  	for {
  6589  		_ = v.Args[2]
  6590  		x := v.Args[1]
  6591  		v_2 := v.Args[2]
  6592  		if v_2.Op != OpAMD64FlagLT_ULT {
  6593  			break
  6594  		}
  6595  		v.reset(OpCopy)
  6596  		v.Type = x.Type
  6597  		v.AddArg(x)
  6598  		return true
  6599  	}
  6600  	// match: (CMOVLLT _ x (FlagLT_UGT))
  6601  	// cond:
  6602  	// result: x
  6603  	for {
  6604  		_ = v.Args[2]
  6605  		x := v.Args[1]
  6606  		v_2 := v.Args[2]
  6607  		if v_2.Op != OpAMD64FlagLT_UGT {
  6608  			break
  6609  		}
  6610  		v.reset(OpCopy)
  6611  		v.Type = x.Type
  6612  		v.AddArg(x)
  6613  		return true
  6614  	}
  6615  	return false
  6616  }
  6617  func rewriteValueAMD64_OpAMD64CMOVLNE_0(v *Value) bool {
  6618  	// match: (CMOVLNE x y (InvertFlags cond))
  6619  	// cond:
  6620  	// result: (CMOVLNE x y cond)
  6621  	for {
  6622  		_ = v.Args[2]
  6623  		x := v.Args[0]
  6624  		y := v.Args[1]
  6625  		v_2 := v.Args[2]
  6626  		if v_2.Op != OpAMD64InvertFlags {
  6627  			break
  6628  		}
  6629  		cond := v_2.Args[0]
  6630  		v.reset(OpAMD64CMOVLNE)
  6631  		v.AddArg(x)
  6632  		v.AddArg(y)
  6633  		v.AddArg(cond)
  6634  		return true
  6635  	}
  6636  	// match: (CMOVLNE y _ (FlagEQ))
  6637  	// cond:
  6638  	// result: y
  6639  	for {
  6640  		_ = v.Args[2]
  6641  		y := v.Args[0]
  6642  		v_2 := v.Args[2]
  6643  		if v_2.Op != OpAMD64FlagEQ {
  6644  			break
  6645  		}
  6646  		v.reset(OpCopy)
  6647  		v.Type = y.Type
  6648  		v.AddArg(y)
  6649  		return true
  6650  	}
  6651  	// match: (CMOVLNE _ x (FlagGT_UGT))
  6652  	// cond:
  6653  	// result: x
  6654  	for {
  6655  		_ = v.Args[2]
  6656  		x := v.Args[1]
  6657  		v_2 := v.Args[2]
  6658  		if v_2.Op != OpAMD64FlagGT_UGT {
  6659  			break
  6660  		}
  6661  		v.reset(OpCopy)
  6662  		v.Type = x.Type
  6663  		v.AddArg(x)
  6664  		return true
  6665  	}
  6666  	// match: (CMOVLNE _ x (FlagGT_ULT))
  6667  	// cond:
  6668  	// result: x
  6669  	for {
  6670  		_ = v.Args[2]
  6671  		x := v.Args[1]
  6672  		v_2 := v.Args[2]
  6673  		if v_2.Op != OpAMD64FlagGT_ULT {
  6674  			break
  6675  		}
  6676  		v.reset(OpCopy)
  6677  		v.Type = x.Type
  6678  		v.AddArg(x)
  6679  		return true
  6680  	}
  6681  	// match: (CMOVLNE _ x (FlagLT_ULT))
  6682  	// cond:
  6683  	// result: x
  6684  	for {
  6685  		_ = v.Args[2]
  6686  		x := v.Args[1]
  6687  		v_2 := v.Args[2]
  6688  		if v_2.Op != OpAMD64FlagLT_ULT {
  6689  			break
  6690  		}
  6691  		v.reset(OpCopy)
  6692  		v.Type = x.Type
  6693  		v.AddArg(x)
  6694  		return true
  6695  	}
  6696  	// match: (CMOVLNE _ x (FlagLT_UGT))
  6697  	// cond:
  6698  	// result: x
  6699  	for {
  6700  		_ = v.Args[2]
  6701  		x := v.Args[1]
  6702  		v_2 := v.Args[2]
  6703  		if v_2.Op != OpAMD64FlagLT_UGT {
  6704  			break
  6705  		}
  6706  		v.reset(OpCopy)
  6707  		v.Type = x.Type
  6708  		v.AddArg(x)
  6709  		return true
  6710  	}
  6711  	return false
  6712  }
  6713  func rewriteValueAMD64_OpAMD64CMOVQCC_0(v *Value) bool {
  6714  	// match: (CMOVQCC x y (InvertFlags cond))
  6715  	// cond:
  6716  	// result: (CMOVQLS x y cond)
  6717  	for {
  6718  		_ = v.Args[2]
  6719  		x := v.Args[0]
  6720  		y := v.Args[1]
  6721  		v_2 := v.Args[2]
  6722  		if v_2.Op != OpAMD64InvertFlags {
  6723  			break
  6724  		}
  6725  		cond := v_2.Args[0]
  6726  		v.reset(OpAMD64CMOVQLS)
  6727  		v.AddArg(x)
  6728  		v.AddArg(y)
  6729  		v.AddArg(cond)
  6730  		return true
  6731  	}
  6732  	// match: (CMOVQCC _ x (FlagEQ))
  6733  	// cond:
  6734  	// result: x
  6735  	for {
  6736  		_ = v.Args[2]
  6737  		x := v.Args[1]
  6738  		v_2 := v.Args[2]
  6739  		if v_2.Op != OpAMD64FlagEQ {
  6740  			break
  6741  		}
  6742  		v.reset(OpCopy)
  6743  		v.Type = x.Type
  6744  		v.AddArg(x)
  6745  		return true
  6746  	}
  6747  	// match: (CMOVQCC _ x (FlagGT_UGT))
  6748  	// cond:
  6749  	// result: x
  6750  	for {
  6751  		_ = v.Args[2]
  6752  		x := v.Args[1]
  6753  		v_2 := v.Args[2]
  6754  		if v_2.Op != OpAMD64FlagGT_UGT {
  6755  			break
  6756  		}
  6757  		v.reset(OpCopy)
  6758  		v.Type = x.Type
  6759  		v.AddArg(x)
  6760  		return true
  6761  	}
  6762  	// match: (CMOVQCC y _ (FlagGT_ULT))
  6763  	// cond:
  6764  	// result: y
  6765  	for {
  6766  		_ = v.Args[2]
  6767  		y := v.Args[0]
  6768  		v_2 := v.Args[2]
  6769  		if v_2.Op != OpAMD64FlagGT_ULT {
  6770  			break
  6771  		}
  6772  		v.reset(OpCopy)
  6773  		v.Type = y.Type
  6774  		v.AddArg(y)
  6775  		return true
  6776  	}
  6777  	// match: (CMOVQCC y _ (FlagLT_ULT))
  6778  	// cond:
  6779  	// result: y
  6780  	for {
  6781  		_ = v.Args[2]
  6782  		y := v.Args[0]
  6783  		v_2 := v.Args[2]
  6784  		if v_2.Op != OpAMD64FlagLT_ULT {
  6785  			break
  6786  		}
  6787  		v.reset(OpCopy)
  6788  		v.Type = y.Type
  6789  		v.AddArg(y)
  6790  		return true
  6791  	}
  6792  	// match: (CMOVQCC _ x (FlagLT_UGT))
  6793  	// cond:
  6794  	// result: x
  6795  	for {
  6796  		_ = v.Args[2]
  6797  		x := v.Args[1]
  6798  		v_2 := v.Args[2]
  6799  		if v_2.Op != OpAMD64FlagLT_UGT {
  6800  			break
  6801  		}
  6802  		v.reset(OpCopy)
  6803  		v.Type = x.Type
  6804  		v.AddArg(x)
  6805  		return true
  6806  	}
  6807  	return false
  6808  }
  6809  func rewriteValueAMD64_OpAMD64CMOVQCS_0(v *Value) bool {
  6810  	// match: (CMOVQCS x y (InvertFlags cond))
  6811  	// cond:
  6812  	// result: (CMOVQHI x y cond)
  6813  	for {
  6814  		_ = v.Args[2]
  6815  		x := v.Args[0]
  6816  		y := v.Args[1]
  6817  		v_2 := v.Args[2]
  6818  		if v_2.Op != OpAMD64InvertFlags {
  6819  			break
  6820  		}
  6821  		cond := v_2.Args[0]
  6822  		v.reset(OpAMD64CMOVQHI)
  6823  		v.AddArg(x)
  6824  		v.AddArg(y)
  6825  		v.AddArg(cond)
  6826  		return true
  6827  	}
  6828  	// match: (CMOVQCS y _ (FlagEQ))
  6829  	// cond:
  6830  	// result: y
  6831  	for {
  6832  		_ = v.Args[2]
  6833  		y := v.Args[0]
  6834  		v_2 := v.Args[2]
  6835  		if v_2.Op != OpAMD64FlagEQ {
  6836  			break
  6837  		}
  6838  		v.reset(OpCopy)
  6839  		v.Type = y.Type
  6840  		v.AddArg(y)
  6841  		return true
  6842  	}
  6843  	// match: (CMOVQCS y _ (FlagGT_UGT))
  6844  	// cond:
  6845  	// result: y
  6846  	for {
  6847  		_ = v.Args[2]
  6848  		y := v.Args[0]
  6849  		v_2 := v.Args[2]
  6850  		if v_2.Op != OpAMD64FlagGT_UGT {
  6851  			break
  6852  		}
  6853  		v.reset(OpCopy)
  6854  		v.Type = y.Type
  6855  		v.AddArg(y)
  6856  		return true
  6857  	}
  6858  	// match: (CMOVQCS _ x (FlagGT_ULT))
  6859  	// cond:
  6860  	// result: x
  6861  	for {
  6862  		_ = v.Args[2]
  6863  		x := v.Args[1]
  6864  		v_2 := v.Args[2]
  6865  		if v_2.Op != OpAMD64FlagGT_ULT {
  6866  			break
  6867  		}
  6868  		v.reset(OpCopy)
  6869  		v.Type = x.Type
  6870  		v.AddArg(x)
  6871  		return true
  6872  	}
  6873  	// match: (CMOVQCS _ x (FlagLT_ULT))
  6874  	// cond:
  6875  	// result: x
  6876  	for {
  6877  		_ = v.Args[2]
  6878  		x := v.Args[1]
  6879  		v_2 := v.Args[2]
  6880  		if v_2.Op != OpAMD64FlagLT_ULT {
  6881  			break
  6882  		}
  6883  		v.reset(OpCopy)
  6884  		v.Type = x.Type
  6885  		v.AddArg(x)
  6886  		return true
  6887  	}
  6888  	// match: (CMOVQCS y _ (FlagLT_UGT))
  6889  	// cond:
  6890  	// result: y
  6891  	for {
  6892  		_ = v.Args[2]
  6893  		y := v.Args[0]
  6894  		v_2 := v.Args[2]
  6895  		if v_2.Op != OpAMD64FlagLT_UGT {
  6896  			break
  6897  		}
  6898  		v.reset(OpCopy)
  6899  		v.Type = y.Type
  6900  		v.AddArg(y)
  6901  		return true
  6902  	}
  6903  	return false
  6904  }
  6905  func rewriteValueAMD64_OpAMD64CMOVQEQ_0(v *Value) bool {
  6906  	// match: (CMOVQEQ x y (InvertFlags cond))
  6907  	// cond:
  6908  	// result: (CMOVQEQ x y cond)
  6909  	for {
  6910  		_ = v.Args[2]
  6911  		x := v.Args[0]
  6912  		y := v.Args[1]
  6913  		v_2 := v.Args[2]
  6914  		if v_2.Op != OpAMD64InvertFlags {
  6915  			break
  6916  		}
  6917  		cond := v_2.Args[0]
  6918  		v.reset(OpAMD64CMOVQEQ)
  6919  		v.AddArg(x)
  6920  		v.AddArg(y)
  6921  		v.AddArg(cond)
  6922  		return true
  6923  	}
  6924  	// match: (CMOVQEQ _ x (FlagEQ))
  6925  	// cond:
  6926  	// result: x
  6927  	for {
  6928  		_ = v.Args[2]
  6929  		x := v.Args[1]
  6930  		v_2 := v.Args[2]
  6931  		if v_2.Op != OpAMD64FlagEQ {
  6932  			break
  6933  		}
  6934  		v.reset(OpCopy)
  6935  		v.Type = x.Type
  6936  		v.AddArg(x)
  6937  		return true
  6938  	}
  6939  	// match: (CMOVQEQ y _ (FlagGT_UGT))
  6940  	// cond:
  6941  	// result: y
  6942  	for {
  6943  		_ = v.Args[2]
  6944  		y := v.Args[0]
  6945  		v_2 := v.Args[2]
  6946  		if v_2.Op != OpAMD64FlagGT_UGT {
  6947  			break
  6948  		}
  6949  		v.reset(OpCopy)
  6950  		v.Type = y.Type
  6951  		v.AddArg(y)
  6952  		return true
  6953  	}
  6954  	// match: (CMOVQEQ y _ (FlagGT_ULT))
  6955  	// cond:
  6956  	// result: y
  6957  	for {
  6958  		_ = v.Args[2]
  6959  		y := v.Args[0]
  6960  		v_2 := v.Args[2]
  6961  		if v_2.Op != OpAMD64FlagGT_ULT {
  6962  			break
  6963  		}
  6964  		v.reset(OpCopy)
  6965  		v.Type = y.Type
  6966  		v.AddArg(y)
  6967  		return true
  6968  	}
  6969  	// match: (CMOVQEQ y _ (FlagLT_ULT))
  6970  	// cond:
  6971  	// result: y
  6972  	for {
  6973  		_ = v.Args[2]
  6974  		y := v.Args[0]
  6975  		v_2 := v.Args[2]
  6976  		if v_2.Op != OpAMD64FlagLT_ULT {
  6977  			break
  6978  		}
  6979  		v.reset(OpCopy)
  6980  		v.Type = y.Type
  6981  		v.AddArg(y)
  6982  		return true
  6983  	}
  6984  	// match: (CMOVQEQ y _ (FlagLT_UGT))
  6985  	// cond:
  6986  	// result: y
  6987  	for {
  6988  		_ = v.Args[2]
  6989  		y := v.Args[0]
  6990  		v_2 := v.Args[2]
  6991  		if v_2.Op != OpAMD64FlagLT_UGT {
  6992  			break
  6993  		}
  6994  		v.reset(OpCopy)
  6995  		v.Type = y.Type
  6996  		v.AddArg(y)
  6997  		return true
  6998  	}
  6999  	// match: (CMOVQEQ x _ (Select1 (BSFQ (ORQconst [c] _))))
  7000  	// cond: c != 0
  7001  	// result: x
  7002  	for {
  7003  		_ = v.Args[2]
  7004  		x := v.Args[0]
  7005  		v_2 := v.Args[2]
  7006  		if v_2.Op != OpSelect1 {
  7007  			break
  7008  		}
  7009  		v_2_0 := v_2.Args[0]
  7010  		if v_2_0.Op != OpAMD64BSFQ {
  7011  			break
  7012  		}
  7013  		v_2_0_0 := v_2_0.Args[0]
  7014  		if v_2_0_0.Op != OpAMD64ORQconst {
  7015  			break
  7016  		}
  7017  		c := v_2_0_0.AuxInt
  7018  		if !(c != 0) {
  7019  			break
  7020  		}
  7021  		v.reset(OpCopy)
  7022  		v.Type = x.Type
  7023  		v.AddArg(x)
  7024  		return true
  7025  	}
  7026  	return false
  7027  }
  7028  func rewriteValueAMD64_OpAMD64CMOVQGE_0(v *Value) bool {
  7029  	// match: (CMOVQGE x y (InvertFlags cond))
  7030  	// cond:
  7031  	// result: (CMOVQLE x y cond)
  7032  	for {
  7033  		_ = v.Args[2]
  7034  		x := v.Args[0]
  7035  		y := v.Args[1]
  7036  		v_2 := v.Args[2]
  7037  		if v_2.Op != OpAMD64InvertFlags {
  7038  			break
  7039  		}
  7040  		cond := v_2.Args[0]
  7041  		v.reset(OpAMD64CMOVQLE)
  7042  		v.AddArg(x)
  7043  		v.AddArg(y)
  7044  		v.AddArg(cond)
  7045  		return true
  7046  	}
  7047  	// match: (CMOVQGE _ x (FlagEQ))
  7048  	// cond:
  7049  	// result: x
  7050  	for {
  7051  		_ = v.Args[2]
  7052  		x := v.Args[1]
  7053  		v_2 := v.Args[2]
  7054  		if v_2.Op != OpAMD64FlagEQ {
  7055  			break
  7056  		}
  7057  		v.reset(OpCopy)
  7058  		v.Type = x.Type
  7059  		v.AddArg(x)
  7060  		return true
  7061  	}
  7062  	// match: (CMOVQGE _ x (FlagGT_UGT))
  7063  	// cond:
  7064  	// result: x
  7065  	for {
  7066  		_ = v.Args[2]
  7067  		x := v.Args[1]
  7068  		v_2 := v.Args[2]
  7069  		if v_2.Op != OpAMD64FlagGT_UGT {
  7070  			break
  7071  		}
  7072  		v.reset(OpCopy)
  7073  		v.Type = x.Type
  7074  		v.AddArg(x)
  7075  		return true
  7076  	}
  7077  	// match: (CMOVQGE _ x (FlagGT_ULT))
  7078  	// cond:
  7079  	// result: x
  7080  	for {
  7081  		_ = v.Args[2]
  7082  		x := v.Args[1]
  7083  		v_2 := v.Args[2]
  7084  		if v_2.Op != OpAMD64FlagGT_ULT {
  7085  			break
  7086  		}
  7087  		v.reset(OpCopy)
  7088  		v.Type = x.Type
  7089  		v.AddArg(x)
  7090  		return true
  7091  	}
  7092  	// match: (CMOVQGE y _ (FlagLT_ULT))
  7093  	// cond:
  7094  	// result: y
  7095  	for {
  7096  		_ = v.Args[2]
  7097  		y := v.Args[0]
  7098  		v_2 := v.Args[2]
  7099  		if v_2.Op != OpAMD64FlagLT_ULT {
  7100  			break
  7101  		}
  7102  		v.reset(OpCopy)
  7103  		v.Type = y.Type
  7104  		v.AddArg(y)
  7105  		return true
  7106  	}
  7107  	// match: (CMOVQGE y _ (FlagLT_UGT))
  7108  	// cond:
  7109  	// result: y
  7110  	for {
  7111  		_ = v.Args[2]
  7112  		y := v.Args[0]
  7113  		v_2 := v.Args[2]
  7114  		if v_2.Op != OpAMD64FlagLT_UGT {
  7115  			break
  7116  		}
  7117  		v.reset(OpCopy)
  7118  		v.Type = y.Type
  7119  		v.AddArg(y)
  7120  		return true
  7121  	}
  7122  	return false
  7123  }
  7124  func rewriteValueAMD64_OpAMD64CMOVQGT_0(v *Value) bool {
  7125  	// match: (CMOVQGT x y (InvertFlags cond))
  7126  	// cond:
  7127  	// result: (CMOVQLT x y cond)
  7128  	for {
  7129  		_ = v.Args[2]
  7130  		x := v.Args[0]
  7131  		y := v.Args[1]
  7132  		v_2 := v.Args[2]
  7133  		if v_2.Op != OpAMD64InvertFlags {
  7134  			break
  7135  		}
  7136  		cond := v_2.Args[0]
  7137  		v.reset(OpAMD64CMOVQLT)
  7138  		v.AddArg(x)
  7139  		v.AddArg(y)
  7140  		v.AddArg(cond)
  7141  		return true
  7142  	}
  7143  	// match: (CMOVQGT y _ (FlagEQ))
  7144  	// cond:
  7145  	// result: y
  7146  	for {
  7147  		_ = v.Args[2]
  7148  		y := v.Args[0]
  7149  		v_2 := v.Args[2]
  7150  		if v_2.Op != OpAMD64FlagEQ {
  7151  			break
  7152  		}
  7153  		v.reset(OpCopy)
  7154  		v.Type = y.Type
  7155  		v.AddArg(y)
  7156  		return true
  7157  	}
  7158  	// match: (CMOVQGT _ x (FlagGT_UGT))
  7159  	// cond:
  7160  	// result: x
  7161  	for {
  7162  		_ = v.Args[2]
  7163  		x := v.Args[1]
  7164  		v_2 := v.Args[2]
  7165  		if v_2.Op != OpAMD64FlagGT_UGT {
  7166  			break
  7167  		}
  7168  		v.reset(OpCopy)
  7169  		v.Type = x.Type
  7170  		v.AddArg(x)
  7171  		return true
  7172  	}
  7173  	// match: (CMOVQGT _ x (FlagGT_ULT))
  7174  	// cond:
  7175  	// result: x
  7176  	for {
  7177  		_ = v.Args[2]
  7178  		x := v.Args[1]
  7179  		v_2 := v.Args[2]
  7180  		if v_2.Op != OpAMD64FlagGT_ULT {
  7181  			break
  7182  		}
  7183  		v.reset(OpCopy)
  7184  		v.Type = x.Type
  7185  		v.AddArg(x)
  7186  		return true
  7187  	}
  7188  	// match: (CMOVQGT y _ (FlagLT_ULT))
  7189  	// cond:
  7190  	// result: y
  7191  	for {
  7192  		_ = v.Args[2]
  7193  		y := v.Args[0]
  7194  		v_2 := v.Args[2]
  7195  		if v_2.Op != OpAMD64FlagLT_ULT {
  7196  			break
  7197  		}
  7198  		v.reset(OpCopy)
  7199  		v.Type = y.Type
  7200  		v.AddArg(y)
  7201  		return true
  7202  	}
  7203  	// match: (CMOVQGT y _ (FlagLT_UGT))
  7204  	// cond:
  7205  	// result: y
  7206  	for {
  7207  		_ = v.Args[2]
  7208  		y := v.Args[0]
  7209  		v_2 := v.Args[2]
  7210  		if v_2.Op != OpAMD64FlagLT_UGT {
  7211  			break
  7212  		}
  7213  		v.reset(OpCopy)
  7214  		v.Type = y.Type
  7215  		v.AddArg(y)
  7216  		return true
  7217  	}
  7218  	return false
  7219  }
  7220  func rewriteValueAMD64_OpAMD64CMOVQHI_0(v *Value) bool {
  7221  	// match: (CMOVQHI x y (InvertFlags cond))
  7222  	// cond:
  7223  	// result: (CMOVQCS x y cond)
  7224  	for {
  7225  		_ = v.Args[2]
  7226  		x := v.Args[0]
  7227  		y := v.Args[1]
  7228  		v_2 := v.Args[2]
  7229  		if v_2.Op != OpAMD64InvertFlags {
  7230  			break
  7231  		}
  7232  		cond := v_2.Args[0]
  7233  		v.reset(OpAMD64CMOVQCS)
  7234  		v.AddArg(x)
  7235  		v.AddArg(y)
  7236  		v.AddArg(cond)
  7237  		return true
  7238  	}
  7239  	// match: (CMOVQHI y _ (FlagEQ))
  7240  	// cond:
  7241  	// result: y
  7242  	for {
  7243  		_ = v.Args[2]
  7244  		y := v.Args[0]
  7245  		v_2 := v.Args[2]
  7246  		if v_2.Op != OpAMD64FlagEQ {
  7247  			break
  7248  		}
  7249  		v.reset(OpCopy)
  7250  		v.Type = y.Type
  7251  		v.AddArg(y)
  7252  		return true
  7253  	}
  7254  	// match: (CMOVQHI _ x (FlagGT_UGT))
  7255  	// cond:
  7256  	// result: x
  7257  	for {
  7258  		_ = v.Args[2]
  7259  		x := v.Args[1]
  7260  		v_2 := v.Args[2]
  7261  		if v_2.Op != OpAMD64FlagGT_UGT {
  7262  			break
  7263  		}
  7264  		v.reset(OpCopy)
  7265  		v.Type = x.Type
  7266  		v.AddArg(x)
  7267  		return true
  7268  	}
  7269  	// match: (CMOVQHI y _ (FlagGT_ULT))
  7270  	// cond:
  7271  	// result: y
  7272  	for {
  7273  		_ = v.Args[2]
  7274  		y := v.Args[0]
  7275  		v_2 := v.Args[2]
  7276  		if v_2.Op != OpAMD64FlagGT_ULT {
  7277  			break
  7278  		}
  7279  		v.reset(OpCopy)
  7280  		v.Type = y.Type
  7281  		v.AddArg(y)
  7282  		return true
  7283  	}
  7284  	// match: (CMOVQHI y _ (FlagLT_ULT))
  7285  	// cond:
  7286  	// result: y
  7287  	for {
  7288  		_ = v.Args[2]
  7289  		y := v.Args[0]
  7290  		v_2 := v.Args[2]
  7291  		if v_2.Op != OpAMD64FlagLT_ULT {
  7292  			break
  7293  		}
  7294  		v.reset(OpCopy)
  7295  		v.Type = y.Type
  7296  		v.AddArg(y)
  7297  		return true
  7298  	}
  7299  	// match: (CMOVQHI _ x (FlagLT_UGT))
  7300  	// cond:
  7301  	// result: x
  7302  	for {
  7303  		_ = v.Args[2]
  7304  		x := v.Args[1]
  7305  		v_2 := v.Args[2]
  7306  		if v_2.Op != OpAMD64FlagLT_UGT {
  7307  			break
  7308  		}
  7309  		v.reset(OpCopy)
  7310  		v.Type = x.Type
  7311  		v.AddArg(x)
  7312  		return true
  7313  	}
  7314  	return false
  7315  }
  7316  func rewriteValueAMD64_OpAMD64CMOVQLE_0(v *Value) bool {
  7317  	// match: (CMOVQLE x y (InvertFlags cond))
  7318  	// cond:
  7319  	// result: (CMOVQGE x y cond)
  7320  	for {
  7321  		_ = v.Args[2]
  7322  		x := v.Args[0]
  7323  		y := v.Args[1]
  7324  		v_2 := v.Args[2]
  7325  		if v_2.Op != OpAMD64InvertFlags {
  7326  			break
  7327  		}
  7328  		cond := v_2.Args[0]
  7329  		v.reset(OpAMD64CMOVQGE)
  7330  		v.AddArg(x)
  7331  		v.AddArg(y)
  7332  		v.AddArg(cond)
  7333  		return true
  7334  	}
  7335  	// match: (CMOVQLE _ x (FlagEQ))
  7336  	// cond:
  7337  	// result: x
  7338  	for {
  7339  		_ = v.Args[2]
  7340  		x := v.Args[1]
  7341  		v_2 := v.Args[2]
  7342  		if v_2.Op != OpAMD64FlagEQ {
  7343  			break
  7344  		}
  7345  		v.reset(OpCopy)
  7346  		v.Type = x.Type
  7347  		v.AddArg(x)
  7348  		return true
  7349  	}
  7350  	// match: (CMOVQLE y _ (FlagGT_UGT))
  7351  	// cond:
  7352  	// result: y
  7353  	for {
  7354  		_ = v.Args[2]
  7355  		y := v.Args[0]
  7356  		v_2 := v.Args[2]
  7357  		if v_2.Op != OpAMD64FlagGT_UGT {
  7358  			break
  7359  		}
  7360  		v.reset(OpCopy)
  7361  		v.Type = y.Type
  7362  		v.AddArg(y)
  7363  		return true
  7364  	}
  7365  	// match: (CMOVQLE y _ (FlagGT_ULT))
  7366  	// cond:
  7367  	// result: y
  7368  	for {
  7369  		_ = v.Args[2]
  7370  		y := v.Args[0]
  7371  		v_2 := v.Args[2]
  7372  		if v_2.Op != OpAMD64FlagGT_ULT {
  7373  			break
  7374  		}
  7375  		v.reset(OpCopy)
  7376  		v.Type = y.Type
  7377  		v.AddArg(y)
  7378  		return true
  7379  	}
  7380  	// match: (CMOVQLE _ x (FlagLT_ULT))
  7381  	// cond:
  7382  	// result: x
  7383  	for {
  7384  		_ = v.Args[2]
  7385  		x := v.Args[1]
  7386  		v_2 := v.Args[2]
  7387  		if v_2.Op != OpAMD64FlagLT_ULT {
  7388  			break
  7389  		}
  7390  		v.reset(OpCopy)
  7391  		v.Type = x.Type
  7392  		v.AddArg(x)
  7393  		return true
  7394  	}
  7395  	// match: (CMOVQLE _ x (FlagLT_UGT))
  7396  	// cond:
  7397  	// result: x
  7398  	for {
  7399  		_ = v.Args[2]
  7400  		x := v.Args[1]
  7401  		v_2 := v.Args[2]
  7402  		if v_2.Op != OpAMD64FlagLT_UGT {
  7403  			break
  7404  		}
  7405  		v.reset(OpCopy)
  7406  		v.Type = x.Type
  7407  		v.AddArg(x)
  7408  		return true
  7409  	}
  7410  	return false
  7411  }
  7412  func rewriteValueAMD64_OpAMD64CMOVQLS_0(v *Value) bool {
  7413  	// match: (CMOVQLS x y (InvertFlags cond))
  7414  	// cond:
  7415  	// result: (CMOVQCC x y cond)
  7416  	for {
  7417  		_ = v.Args[2]
  7418  		x := v.Args[0]
  7419  		y := v.Args[1]
  7420  		v_2 := v.Args[2]
  7421  		if v_2.Op != OpAMD64InvertFlags {
  7422  			break
  7423  		}
  7424  		cond := v_2.Args[0]
  7425  		v.reset(OpAMD64CMOVQCC)
  7426  		v.AddArg(x)
  7427  		v.AddArg(y)
  7428  		v.AddArg(cond)
  7429  		return true
  7430  	}
  7431  	// match: (CMOVQLS _ x (FlagEQ))
  7432  	// cond:
  7433  	// result: x
  7434  	for {
  7435  		_ = v.Args[2]
  7436  		x := v.Args[1]
  7437  		v_2 := v.Args[2]
  7438  		if v_2.Op != OpAMD64FlagEQ {
  7439  			break
  7440  		}
  7441  		v.reset(OpCopy)
  7442  		v.Type = x.Type
  7443  		v.AddArg(x)
  7444  		return true
  7445  	}
  7446  	// match: (CMOVQLS y _ (FlagGT_UGT))
  7447  	// cond:
  7448  	// result: y
  7449  	for {
  7450  		_ = v.Args[2]
  7451  		y := v.Args[0]
  7452  		v_2 := v.Args[2]
  7453  		if v_2.Op != OpAMD64FlagGT_UGT {
  7454  			break
  7455  		}
  7456  		v.reset(OpCopy)
  7457  		v.Type = y.Type
  7458  		v.AddArg(y)
  7459  		return true
  7460  	}
  7461  	// match: (CMOVQLS _ x (FlagGT_ULT))
  7462  	// cond:
  7463  	// result: x
  7464  	for {
  7465  		_ = v.Args[2]
  7466  		x := v.Args[1]
  7467  		v_2 := v.Args[2]
  7468  		if v_2.Op != OpAMD64FlagGT_ULT {
  7469  			break
  7470  		}
  7471  		v.reset(OpCopy)
  7472  		v.Type = x.Type
  7473  		v.AddArg(x)
  7474  		return true
  7475  	}
  7476  	// match: (CMOVQLS _ x (FlagLT_ULT))
  7477  	// cond:
  7478  	// result: x
  7479  	for {
  7480  		_ = v.Args[2]
  7481  		x := v.Args[1]
  7482  		v_2 := v.Args[2]
  7483  		if v_2.Op != OpAMD64FlagLT_ULT {
  7484  			break
  7485  		}
  7486  		v.reset(OpCopy)
  7487  		v.Type = x.Type
  7488  		v.AddArg(x)
  7489  		return true
  7490  	}
  7491  	// match: (CMOVQLS y _ (FlagLT_UGT))
  7492  	// cond:
  7493  	// result: y
  7494  	for {
  7495  		_ = v.Args[2]
  7496  		y := v.Args[0]
  7497  		v_2 := v.Args[2]
  7498  		if v_2.Op != OpAMD64FlagLT_UGT {
  7499  			break
  7500  		}
  7501  		v.reset(OpCopy)
  7502  		v.Type = y.Type
  7503  		v.AddArg(y)
  7504  		return true
  7505  	}
  7506  	return false
  7507  }
  7508  func rewriteValueAMD64_OpAMD64CMOVQLT_0(v *Value) bool {
  7509  	// match: (CMOVQLT x y (InvertFlags cond))
  7510  	// cond:
  7511  	// result: (CMOVQGT x y cond)
  7512  	for {
  7513  		_ = v.Args[2]
  7514  		x := v.Args[0]
  7515  		y := v.Args[1]
  7516  		v_2 := v.Args[2]
  7517  		if v_2.Op != OpAMD64InvertFlags {
  7518  			break
  7519  		}
  7520  		cond := v_2.Args[0]
  7521  		v.reset(OpAMD64CMOVQGT)
  7522  		v.AddArg(x)
  7523  		v.AddArg(y)
  7524  		v.AddArg(cond)
  7525  		return true
  7526  	}
  7527  	// match: (CMOVQLT y _ (FlagEQ))
  7528  	// cond:
  7529  	// result: y
  7530  	for {
  7531  		_ = v.Args[2]
  7532  		y := v.Args[0]
  7533  		v_2 := v.Args[2]
  7534  		if v_2.Op != OpAMD64FlagEQ {
  7535  			break
  7536  		}
  7537  		v.reset(OpCopy)
  7538  		v.Type = y.Type
  7539  		v.AddArg(y)
  7540  		return true
  7541  	}
  7542  	// match: (CMOVQLT y _ (FlagGT_UGT))
  7543  	// cond:
  7544  	// result: y
  7545  	for {
  7546  		_ = v.Args[2]
  7547  		y := v.Args[0]
  7548  		v_2 := v.Args[2]
  7549  		if v_2.Op != OpAMD64FlagGT_UGT {
  7550  			break
  7551  		}
  7552  		v.reset(OpCopy)
  7553  		v.Type = y.Type
  7554  		v.AddArg(y)
  7555  		return true
  7556  	}
  7557  	// match: (CMOVQLT y _ (FlagGT_ULT))
  7558  	// cond:
  7559  	// result: y
  7560  	for {
  7561  		_ = v.Args[2]
  7562  		y := v.Args[0]
  7563  		v_2 := v.Args[2]
  7564  		if v_2.Op != OpAMD64FlagGT_ULT {
  7565  			break
  7566  		}
  7567  		v.reset(OpCopy)
  7568  		v.Type = y.Type
  7569  		v.AddArg(y)
  7570  		return true
  7571  	}
  7572  	// match: (CMOVQLT _ x (FlagLT_ULT))
  7573  	// cond:
  7574  	// result: x
  7575  	for {
  7576  		_ = v.Args[2]
  7577  		x := v.Args[1]
  7578  		v_2 := v.Args[2]
  7579  		if v_2.Op != OpAMD64FlagLT_ULT {
  7580  			break
  7581  		}
  7582  		v.reset(OpCopy)
  7583  		v.Type = x.Type
  7584  		v.AddArg(x)
  7585  		return true
  7586  	}
  7587  	// match: (CMOVQLT _ x (FlagLT_UGT))
  7588  	// cond:
  7589  	// result: x
  7590  	for {
  7591  		_ = v.Args[2]
  7592  		x := v.Args[1]
  7593  		v_2 := v.Args[2]
  7594  		if v_2.Op != OpAMD64FlagLT_UGT {
  7595  			break
  7596  		}
  7597  		v.reset(OpCopy)
  7598  		v.Type = x.Type
  7599  		v.AddArg(x)
  7600  		return true
  7601  	}
  7602  	return false
  7603  }
  7604  func rewriteValueAMD64_OpAMD64CMOVQNE_0(v *Value) bool {
  7605  	// match: (CMOVQNE x y (InvertFlags cond))
  7606  	// cond:
  7607  	// result: (CMOVQNE x y cond)
  7608  	for {
  7609  		_ = v.Args[2]
  7610  		x := v.Args[0]
  7611  		y := v.Args[1]
  7612  		v_2 := v.Args[2]
  7613  		if v_2.Op != OpAMD64InvertFlags {
  7614  			break
  7615  		}
  7616  		cond := v_2.Args[0]
  7617  		v.reset(OpAMD64CMOVQNE)
  7618  		v.AddArg(x)
  7619  		v.AddArg(y)
  7620  		v.AddArg(cond)
  7621  		return true
  7622  	}
  7623  	// match: (CMOVQNE y _ (FlagEQ))
  7624  	// cond:
  7625  	// result: y
  7626  	for {
  7627  		_ = v.Args[2]
  7628  		y := v.Args[0]
  7629  		v_2 := v.Args[2]
  7630  		if v_2.Op != OpAMD64FlagEQ {
  7631  			break
  7632  		}
  7633  		v.reset(OpCopy)
  7634  		v.Type = y.Type
  7635  		v.AddArg(y)
  7636  		return true
  7637  	}
  7638  	// match: (CMOVQNE _ x (FlagGT_UGT))
  7639  	// cond:
  7640  	// result: x
  7641  	for {
  7642  		_ = v.Args[2]
  7643  		x := v.Args[1]
  7644  		v_2 := v.Args[2]
  7645  		if v_2.Op != OpAMD64FlagGT_UGT {
  7646  			break
  7647  		}
  7648  		v.reset(OpCopy)
  7649  		v.Type = x.Type
  7650  		v.AddArg(x)
  7651  		return true
  7652  	}
  7653  	// match: (CMOVQNE _ x (FlagGT_ULT))
  7654  	// cond:
  7655  	// result: x
  7656  	for {
  7657  		_ = v.Args[2]
  7658  		x := v.Args[1]
  7659  		v_2 := v.Args[2]
  7660  		if v_2.Op != OpAMD64FlagGT_ULT {
  7661  			break
  7662  		}
  7663  		v.reset(OpCopy)
  7664  		v.Type = x.Type
  7665  		v.AddArg(x)
  7666  		return true
  7667  	}
  7668  	// match: (CMOVQNE _ x (FlagLT_ULT))
  7669  	// cond:
  7670  	// result: x
  7671  	for {
  7672  		_ = v.Args[2]
  7673  		x := v.Args[1]
  7674  		v_2 := v.Args[2]
  7675  		if v_2.Op != OpAMD64FlagLT_ULT {
  7676  			break
  7677  		}
  7678  		v.reset(OpCopy)
  7679  		v.Type = x.Type
  7680  		v.AddArg(x)
  7681  		return true
  7682  	}
  7683  	// match: (CMOVQNE _ x (FlagLT_UGT))
  7684  	// cond:
  7685  	// result: x
  7686  	for {
  7687  		_ = v.Args[2]
  7688  		x := v.Args[1]
  7689  		v_2 := v.Args[2]
  7690  		if v_2.Op != OpAMD64FlagLT_UGT {
  7691  			break
  7692  		}
  7693  		v.reset(OpCopy)
  7694  		v.Type = x.Type
  7695  		v.AddArg(x)
  7696  		return true
  7697  	}
  7698  	return false
  7699  }
  7700  func rewriteValueAMD64_OpAMD64CMOVWCC_0(v *Value) bool {
  7701  	// match: (CMOVWCC x y (InvertFlags cond))
  7702  	// cond:
  7703  	// result: (CMOVWLS x y cond)
  7704  	for {
  7705  		_ = v.Args[2]
  7706  		x := v.Args[0]
  7707  		y := v.Args[1]
  7708  		v_2 := v.Args[2]
  7709  		if v_2.Op != OpAMD64InvertFlags {
  7710  			break
  7711  		}
  7712  		cond := v_2.Args[0]
  7713  		v.reset(OpAMD64CMOVWLS)
  7714  		v.AddArg(x)
  7715  		v.AddArg(y)
  7716  		v.AddArg(cond)
  7717  		return true
  7718  	}
  7719  	// match: (CMOVWCC _ x (FlagEQ))
  7720  	// cond:
  7721  	// result: x
  7722  	for {
  7723  		_ = v.Args[2]
  7724  		x := v.Args[1]
  7725  		v_2 := v.Args[2]
  7726  		if v_2.Op != OpAMD64FlagEQ {
  7727  			break
  7728  		}
  7729  		v.reset(OpCopy)
  7730  		v.Type = x.Type
  7731  		v.AddArg(x)
  7732  		return true
  7733  	}
  7734  	// match: (CMOVWCC _ x (FlagGT_UGT))
  7735  	// cond:
  7736  	// result: x
  7737  	for {
  7738  		_ = v.Args[2]
  7739  		x := v.Args[1]
  7740  		v_2 := v.Args[2]
  7741  		if v_2.Op != OpAMD64FlagGT_UGT {
  7742  			break
  7743  		}
  7744  		v.reset(OpCopy)
  7745  		v.Type = x.Type
  7746  		v.AddArg(x)
  7747  		return true
  7748  	}
  7749  	// match: (CMOVWCC y _ (FlagGT_ULT))
  7750  	// cond:
  7751  	// result: y
  7752  	for {
  7753  		_ = v.Args[2]
  7754  		y := v.Args[0]
  7755  		v_2 := v.Args[2]
  7756  		if v_2.Op != OpAMD64FlagGT_ULT {
  7757  			break
  7758  		}
  7759  		v.reset(OpCopy)
  7760  		v.Type = y.Type
  7761  		v.AddArg(y)
  7762  		return true
  7763  	}
  7764  	// match: (CMOVWCC y _ (FlagLT_ULT))
  7765  	// cond:
  7766  	// result: y
  7767  	for {
  7768  		_ = v.Args[2]
  7769  		y := v.Args[0]
  7770  		v_2 := v.Args[2]
  7771  		if v_2.Op != OpAMD64FlagLT_ULT {
  7772  			break
  7773  		}
  7774  		v.reset(OpCopy)
  7775  		v.Type = y.Type
  7776  		v.AddArg(y)
  7777  		return true
  7778  	}
  7779  	// match: (CMOVWCC _ x (FlagLT_UGT))
  7780  	// cond:
  7781  	// result: x
  7782  	for {
  7783  		_ = v.Args[2]
  7784  		x := v.Args[1]
  7785  		v_2 := v.Args[2]
  7786  		if v_2.Op != OpAMD64FlagLT_UGT {
  7787  			break
  7788  		}
  7789  		v.reset(OpCopy)
  7790  		v.Type = x.Type
  7791  		v.AddArg(x)
  7792  		return true
  7793  	}
  7794  	return false
  7795  }
  7796  func rewriteValueAMD64_OpAMD64CMOVWCS_0(v *Value) bool {
  7797  	// match: (CMOVWCS x y (InvertFlags cond))
  7798  	// cond:
  7799  	// result: (CMOVWHI x y cond)
  7800  	for {
  7801  		_ = v.Args[2]
  7802  		x := v.Args[0]
  7803  		y := v.Args[1]
  7804  		v_2 := v.Args[2]
  7805  		if v_2.Op != OpAMD64InvertFlags {
  7806  			break
  7807  		}
  7808  		cond := v_2.Args[0]
  7809  		v.reset(OpAMD64CMOVWHI)
  7810  		v.AddArg(x)
  7811  		v.AddArg(y)
  7812  		v.AddArg(cond)
  7813  		return true
  7814  	}
  7815  	// match: (CMOVWCS y _ (FlagEQ))
  7816  	// cond:
  7817  	// result: y
  7818  	for {
  7819  		_ = v.Args[2]
  7820  		y := v.Args[0]
  7821  		v_2 := v.Args[2]
  7822  		if v_2.Op != OpAMD64FlagEQ {
  7823  			break
  7824  		}
  7825  		v.reset(OpCopy)
  7826  		v.Type = y.Type
  7827  		v.AddArg(y)
  7828  		return true
  7829  	}
  7830  	// match: (CMOVWCS y _ (FlagGT_UGT))
  7831  	// cond:
  7832  	// result: y
  7833  	for {
  7834  		_ = v.Args[2]
  7835  		y := v.Args[0]
  7836  		v_2 := v.Args[2]
  7837  		if v_2.Op != OpAMD64FlagGT_UGT {
  7838  			break
  7839  		}
  7840  		v.reset(OpCopy)
  7841  		v.Type = y.Type
  7842  		v.AddArg(y)
  7843  		return true
  7844  	}
  7845  	// match: (CMOVWCS _ x (FlagGT_ULT))
  7846  	// cond:
  7847  	// result: x
  7848  	for {
  7849  		_ = v.Args[2]
  7850  		x := v.Args[1]
  7851  		v_2 := v.Args[2]
  7852  		if v_2.Op != OpAMD64FlagGT_ULT {
  7853  			break
  7854  		}
  7855  		v.reset(OpCopy)
  7856  		v.Type = x.Type
  7857  		v.AddArg(x)
  7858  		return true
  7859  	}
  7860  	// match: (CMOVWCS _ x (FlagLT_ULT))
  7861  	// cond:
  7862  	// result: x
  7863  	for {
  7864  		_ = v.Args[2]
  7865  		x := v.Args[1]
  7866  		v_2 := v.Args[2]
  7867  		if v_2.Op != OpAMD64FlagLT_ULT {
  7868  			break
  7869  		}
  7870  		v.reset(OpCopy)
  7871  		v.Type = x.Type
  7872  		v.AddArg(x)
  7873  		return true
  7874  	}
  7875  	// match: (CMOVWCS y _ (FlagLT_UGT))
  7876  	// cond:
  7877  	// result: y
  7878  	for {
  7879  		_ = v.Args[2]
  7880  		y := v.Args[0]
  7881  		v_2 := v.Args[2]
  7882  		if v_2.Op != OpAMD64FlagLT_UGT {
  7883  			break
  7884  		}
  7885  		v.reset(OpCopy)
  7886  		v.Type = y.Type
  7887  		v.AddArg(y)
  7888  		return true
  7889  	}
  7890  	return false
  7891  }
  7892  func rewriteValueAMD64_OpAMD64CMOVWEQ_0(v *Value) bool {
  7893  	// match: (CMOVWEQ x y (InvertFlags cond))
  7894  	// cond:
  7895  	// result: (CMOVWEQ x y cond)
  7896  	for {
  7897  		_ = v.Args[2]
  7898  		x := v.Args[0]
  7899  		y := v.Args[1]
  7900  		v_2 := v.Args[2]
  7901  		if v_2.Op != OpAMD64InvertFlags {
  7902  			break
  7903  		}
  7904  		cond := v_2.Args[0]
  7905  		v.reset(OpAMD64CMOVWEQ)
  7906  		v.AddArg(x)
  7907  		v.AddArg(y)
  7908  		v.AddArg(cond)
  7909  		return true
  7910  	}
  7911  	// match: (CMOVWEQ _ x (FlagEQ))
  7912  	// cond:
  7913  	// result: x
  7914  	for {
  7915  		_ = v.Args[2]
  7916  		x := v.Args[1]
  7917  		v_2 := v.Args[2]
  7918  		if v_2.Op != OpAMD64FlagEQ {
  7919  			break
  7920  		}
  7921  		v.reset(OpCopy)
  7922  		v.Type = x.Type
  7923  		v.AddArg(x)
  7924  		return true
  7925  	}
  7926  	// match: (CMOVWEQ y _ (FlagGT_UGT))
  7927  	// cond:
  7928  	// result: y
  7929  	for {
  7930  		_ = v.Args[2]
  7931  		y := v.Args[0]
  7932  		v_2 := v.Args[2]
  7933  		if v_2.Op != OpAMD64FlagGT_UGT {
  7934  			break
  7935  		}
  7936  		v.reset(OpCopy)
  7937  		v.Type = y.Type
  7938  		v.AddArg(y)
  7939  		return true
  7940  	}
  7941  	// match: (CMOVWEQ y _ (FlagGT_ULT))
  7942  	// cond:
  7943  	// result: y
  7944  	for {
  7945  		_ = v.Args[2]
  7946  		y := v.Args[0]
  7947  		v_2 := v.Args[2]
  7948  		if v_2.Op != OpAMD64FlagGT_ULT {
  7949  			break
  7950  		}
  7951  		v.reset(OpCopy)
  7952  		v.Type = y.Type
  7953  		v.AddArg(y)
  7954  		return true
  7955  	}
  7956  	// match: (CMOVWEQ y _ (FlagLT_ULT))
  7957  	// cond:
  7958  	// result: y
  7959  	for {
  7960  		_ = v.Args[2]
  7961  		y := v.Args[0]
  7962  		v_2 := v.Args[2]
  7963  		if v_2.Op != OpAMD64FlagLT_ULT {
  7964  			break
  7965  		}
  7966  		v.reset(OpCopy)
  7967  		v.Type = y.Type
  7968  		v.AddArg(y)
  7969  		return true
  7970  	}
  7971  	// match: (CMOVWEQ y _ (FlagLT_UGT))
  7972  	// cond:
  7973  	// result: y
  7974  	for {
  7975  		_ = v.Args[2]
  7976  		y := v.Args[0]
  7977  		v_2 := v.Args[2]
  7978  		if v_2.Op != OpAMD64FlagLT_UGT {
  7979  			break
  7980  		}
  7981  		v.reset(OpCopy)
  7982  		v.Type = y.Type
  7983  		v.AddArg(y)
  7984  		return true
  7985  	}
  7986  	return false
  7987  }
  7988  func rewriteValueAMD64_OpAMD64CMOVWGE_0(v *Value) bool {
  7989  	// match: (CMOVWGE x y (InvertFlags cond))
  7990  	// cond:
  7991  	// result: (CMOVWLE x y cond)
  7992  	for {
  7993  		_ = v.Args[2]
  7994  		x := v.Args[0]
  7995  		y := v.Args[1]
  7996  		v_2 := v.Args[2]
  7997  		if v_2.Op != OpAMD64InvertFlags {
  7998  			break
  7999  		}
  8000  		cond := v_2.Args[0]
  8001  		v.reset(OpAMD64CMOVWLE)
  8002  		v.AddArg(x)
  8003  		v.AddArg(y)
  8004  		v.AddArg(cond)
  8005  		return true
  8006  	}
  8007  	// match: (CMOVWGE _ x (FlagEQ))
  8008  	// cond:
  8009  	// result: x
  8010  	for {
  8011  		_ = v.Args[2]
  8012  		x := v.Args[1]
  8013  		v_2 := v.Args[2]
  8014  		if v_2.Op != OpAMD64FlagEQ {
  8015  			break
  8016  		}
  8017  		v.reset(OpCopy)
  8018  		v.Type = x.Type
  8019  		v.AddArg(x)
  8020  		return true
  8021  	}
  8022  	// match: (CMOVWGE _ x (FlagGT_UGT))
  8023  	// cond:
  8024  	// result: x
  8025  	for {
  8026  		_ = v.Args[2]
  8027  		x := v.Args[1]
  8028  		v_2 := v.Args[2]
  8029  		if v_2.Op != OpAMD64FlagGT_UGT {
  8030  			break
  8031  		}
  8032  		v.reset(OpCopy)
  8033  		v.Type = x.Type
  8034  		v.AddArg(x)
  8035  		return true
  8036  	}
  8037  	// match: (CMOVWGE _ x (FlagGT_ULT))
  8038  	// cond:
  8039  	// result: x
  8040  	for {
  8041  		_ = v.Args[2]
  8042  		x := v.Args[1]
  8043  		v_2 := v.Args[2]
  8044  		if v_2.Op != OpAMD64FlagGT_ULT {
  8045  			break
  8046  		}
  8047  		v.reset(OpCopy)
  8048  		v.Type = x.Type
  8049  		v.AddArg(x)
  8050  		return true
  8051  	}
  8052  	// match: (CMOVWGE y _ (FlagLT_ULT))
  8053  	// cond:
  8054  	// result: y
  8055  	for {
  8056  		_ = v.Args[2]
  8057  		y := v.Args[0]
  8058  		v_2 := v.Args[2]
  8059  		if v_2.Op != OpAMD64FlagLT_ULT {
  8060  			break
  8061  		}
  8062  		v.reset(OpCopy)
  8063  		v.Type = y.Type
  8064  		v.AddArg(y)
  8065  		return true
  8066  	}
  8067  	// match: (CMOVWGE y _ (FlagLT_UGT))
  8068  	// cond:
  8069  	// result: y
  8070  	for {
  8071  		_ = v.Args[2]
  8072  		y := v.Args[0]
  8073  		v_2 := v.Args[2]
  8074  		if v_2.Op != OpAMD64FlagLT_UGT {
  8075  			break
  8076  		}
  8077  		v.reset(OpCopy)
  8078  		v.Type = y.Type
  8079  		v.AddArg(y)
  8080  		return true
  8081  	}
  8082  	return false
  8083  }
  8084  func rewriteValueAMD64_OpAMD64CMOVWGT_0(v *Value) bool {
  8085  	// match: (CMOVWGT x y (InvertFlags cond))
  8086  	// cond:
  8087  	// result: (CMOVWLT x y cond)
  8088  	for {
  8089  		_ = v.Args[2]
  8090  		x := v.Args[0]
  8091  		y := v.Args[1]
  8092  		v_2 := v.Args[2]
  8093  		if v_2.Op != OpAMD64InvertFlags {
  8094  			break
  8095  		}
  8096  		cond := v_2.Args[0]
  8097  		v.reset(OpAMD64CMOVWLT)
  8098  		v.AddArg(x)
  8099  		v.AddArg(y)
  8100  		v.AddArg(cond)
  8101  		return true
  8102  	}
  8103  	// match: (CMOVWGT y _ (FlagEQ))
  8104  	// cond:
  8105  	// result: y
  8106  	for {
  8107  		_ = v.Args[2]
  8108  		y := v.Args[0]
  8109  		v_2 := v.Args[2]
  8110  		if v_2.Op != OpAMD64FlagEQ {
  8111  			break
  8112  		}
  8113  		v.reset(OpCopy)
  8114  		v.Type = y.Type
  8115  		v.AddArg(y)
  8116  		return true
  8117  	}
  8118  	// match: (CMOVWGT _ x (FlagGT_UGT))
  8119  	// cond:
  8120  	// result: x
  8121  	for {
  8122  		_ = v.Args[2]
  8123  		x := v.Args[1]
  8124  		v_2 := v.Args[2]
  8125  		if v_2.Op != OpAMD64FlagGT_UGT {
  8126  			break
  8127  		}
  8128  		v.reset(OpCopy)
  8129  		v.Type = x.Type
  8130  		v.AddArg(x)
  8131  		return true
  8132  	}
  8133  	// match: (CMOVWGT _ x (FlagGT_ULT))
  8134  	// cond:
  8135  	// result: x
  8136  	for {
  8137  		_ = v.Args[2]
  8138  		x := v.Args[1]
  8139  		v_2 := v.Args[2]
  8140  		if v_2.Op != OpAMD64FlagGT_ULT {
  8141  			break
  8142  		}
  8143  		v.reset(OpCopy)
  8144  		v.Type = x.Type
  8145  		v.AddArg(x)
  8146  		return true
  8147  	}
  8148  	// match: (CMOVWGT y _ (FlagLT_ULT))
  8149  	// cond:
  8150  	// result: y
  8151  	for {
  8152  		_ = v.Args[2]
  8153  		y := v.Args[0]
  8154  		v_2 := v.Args[2]
  8155  		if v_2.Op != OpAMD64FlagLT_ULT {
  8156  			break
  8157  		}
  8158  		v.reset(OpCopy)
  8159  		v.Type = y.Type
  8160  		v.AddArg(y)
  8161  		return true
  8162  	}
  8163  	// match: (CMOVWGT y _ (FlagLT_UGT))
  8164  	// cond:
  8165  	// result: y
  8166  	for {
  8167  		_ = v.Args[2]
  8168  		y := v.Args[0]
  8169  		v_2 := v.Args[2]
  8170  		if v_2.Op != OpAMD64FlagLT_UGT {
  8171  			break
  8172  		}
  8173  		v.reset(OpCopy)
  8174  		v.Type = y.Type
  8175  		v.AddArg(y)
  8176  		return true
  8177  	}
  8178  	return false
  8179  }
  8180  func rewriteValueAMD64_OpAMD64CMOVWHI_0(v *Value) bool {
  8181  	// match: (CMOVWHI x y (InvertFlags cond))
  8182  	// cond:
  8183  	// result: (CMOVWCS x y cond)
  8184  	for {
  8185  		_ = v.Args[2]
  8186  		x := v.Args[0]
  8187  		y := v.Args[1]
  8188  		v_2 := v.Args[2]
  8189  		if v_2.Op != OpAMD64InvertFlags {
  8190  			break
  8191  		}
  8192  		cond := v_2.Args[0]
  8193  		v.reset(OpAMD64CMOVWCS)
  8194  		v.AddArg(x)
  8195  		v.AddArg(y)
  8196  		v.AddArg(cond)
  8197  		return true
  8198  	}
  8199  	// match: (CMOVWHI y _ (FlagEQ))
  8200  	// cond:
  8201  	// result: y
  8202  	for {
  8203  		_ = v.Args[2]
  8204  		y := v.Args[0]
  8205  		v_2 := v.Args[2]
  8206  		if v_2.Op != OpAMD64FlagEQ {
  8207  			break
  8208  		}
  8209  		v.reset(OpCopy)
  8210  		v.Type = y.Type
  8211  		v.AddArg(y)
  8212  		return true
  8213  	}
  8214  	// match: (CMOVWHI _ x (FlagGT_UGT))
  8215  	// cond:
  8216  	// result: x
  8217  	for {
  8218  		_ = v.Args[2]
  8219  		x := v.Args[1]
  8220  		v_2 := v.Args[2]
  8221  		if v_2.Op != OpAMD64FlagGT_UGT {
  8222  			break
  8223  		}
  8224  		v.reset(OpCopy)
  8225  		v.Type = x.Type
  8226  		v.AddArg(x)
  8227  		return true
  8228  	}
  8229  	// match: (CMOVWHI y _ (FlagGT_ULT))
  8230  	// cond:
  8231  	// result: y
  8232  	for {
  8233  		_ = v.Args[2]
  8234  		y := v.Args[0]
  8235  		v_2 := v.Args[2]
  8236  		if v_2.Op != OpAMD64FlagGT_ULT {
  8237  			break
  8238  		}
  8239  		v.reset(OpCopy)
  8240  		v.Type = y.Type
  8241  		v.AddArg(y)
  8242  		return true
  8243  	}
  8244  	// match: (CMOVWHI y _ (FlagLT_ULT))
  8245  	// cond:
  8246  	// result: y
  8247  	for {
  8248  		_ = v.Args[2]
  8249  		y := v.Args[0]
  8250  		v_2 := v.Args[2]
  8251  		if v_2.Op != OpAMD64FlagLT_ULT {
  8252  			break
  8253  		}
  8254  		v.reset(OpCopy)
  8255  		v.Type = y.Type
  8256  		v.AddArg(y)
  8257  		return true
  8258  	}
  8259  	// match: (CMOVWHI _ x (FlagLT_UGT))
  8260  	// cond:
  8261  	// result: x
  8262  	for {
  8263  		_ = v.Args[2]
  8264  		x := v.Args[1]
  8265  		v_2 := v.Args[2]
  8266  		if v_2.Op != OpAMD64FlagLT_UGT {
  8267  			break
  8268  		}
  8269  		v.reset(OpCopy)
  8270  		v.Type = x.Type
  8271  		v.AddArg(x)
  8272  		return true
  8273  	}
  8274  	return false
  8275  }
  8276  func rewriteValueAMD64_OpAMD64CMOVWLE_0(v *Value) bool {
  8277  	// match: (CMOVWLE x y (InvertFlags cond))
  8278  	// cond:
  8279  	// result: (CMOVWGE x y cond)
  8280  	for {
  8281  		_ = v.Args[2]
  8282  		x := v.Args[0]
  8283  		y := v.Args[1]
  8284  		v_2 := v.Args[2]
  8285  		if v_2.Op != OpAMD64InvertFlags {
  8286  			break
  8287  		}
  8288  		cond := v_2.Args[0]
  8289  		v.reset(OpAMD64CMOVWGE)
  8290  		v.AddArg(x)
  8291  		v.AddArg(y)
  8292  		v.AddArg(cond)
  8293  		return true
  8294  	}
  8295  	// match: (CMOVWLE _ x (FlagEQ))
  8296  	// cond:
  8297  	// result: x
  8298  	for {
  8299  		_ = v.Args[2]
  8300  		x := v.Args[1]
  8301  		v_2 := v.Args[2]
  8302  		if v_2.Op != OpAMD64FlagEQ {
  8303  			break
  8304  		}
  8305  		v.reset(OpCopy)
  8306  		v.Type = x.Type
  8307  		v.AddArg(x)
  8308  		return true
  8309  	}
  8310  	// match: (CMOVWLE y _ (FlagGT_UGT))
  8311  	// cond:
  8312  	// result: y
  8313  	for {
  8314  		_ = v.Args[2]
  8315  		y := v.Args[0]
  8316  		v_2 := v.Args[2]
  8317  		if v_2.Op != OpAMD64FlagGT_UGT {
  8318  			break
  8319  		}
  8320  		v.reset(OpCopy)
  8321  		v.Type = y.Type
  8322  		v.AddArg(y)
  8323  		return true
  8324  	}
  8325  	// match: (CMOVWLE y _ (FlagGT_ULT))
  8326  	// cond:
  8327  	// result: y
  8328  	for {
  8329  		_ = v.Args[2]
  8330  		y := v.Args[0]
  8331  		v_2 := v.Args[2]
  8332  		if v_2.Op != OpAMD64FlagGT_ULT {
  8333  			break
  8334  		}
  8335  		v.reset(OpCopy)
  8336  		v.Type = y.Type
  8337  		v.AddArg(y)
  8338  		return true
  8339  	}
  8340  	// match: (CMOVWLE _ x (FlagLT_ULT))
  8341  	// cond:
  8342  	// result: x
  8343  	for {
  8344  		_ = v.Args[2]
  8345  		x := v.Args[1]
  8346  		v_2 := v.Args[2]
  8347  		if v_2.Op != OpAMD64FlagLT_ULT {
  8348  			break
  8349  		}
  8350  		v.reset(OpCopy)
  8351  		v.Type = x.Type
  8352  		v.AddArg(x)
  8353  		return true
  8354  	}
  8355  	// match: (CMOVWLE _ x (FlagLT_UGT))
  8356  	// cond:
  8357  	// result: x
  8358  	for {
  8359  		_ = v.Args[2]
  8360  		x := v.Args[1]
  8361  		v_2 := v.Args[2]
  8362  		if v_2.Op != OpAMD64FlagLT_UGT {
  8363  			break
  8364  		}
  8365  		v.reset(OpCopy)
  8366  		v.Type = x.Type
  8367  		v.AddArg(x)
  8368  		return true
  8369  	}
  8370  	return false
  8371  }
  8372  func rewriteValueAMD64_OpAMD64CMOVWLS_0(v *Value) bool {
  8373  	// match: (CMOVWLS x y (InvertFlags cond))
  8374  	// cond:
  8375  	// result: (CMOVWCC x y cond)
  8376  	for {
  8377  		_ = v.Args[2]
  8378  		x := v.Args[0]
  8379  		y := v.Args[1]
  8380  		v_2 := v.Args[2]
  8381  		if v_2.Op != OpAMD64InvertFlags {
  8382  			break
  8383  		}
  8384  		cond := v_2.Args[0]
  8385  		v.reset(OpAMD64CMOVWCC)
  8386  		v.AddArg(x)
  8387  		v.AddArg(y)
  8388  		v.AddArg(cond)
  8389  		return true
  8390  	}
  8391  	// match: (CMOVWLS _ x (FlagEQ))
  8392  	// cond:
  8393  	// result: x
  8394  	for {
  8395  		_ = v.Args[2]
  8396  		x := v.Args[1]
  8397  		v_2 := v.Args[2]
  8398  		if v_2.Op != OpAMD64FlagEQ {
  8399  			break
  8400  		}
  8401  		v.reset(OpCopy)
  8402  		v.Type = x.Type
  8403  		v.AddArg(x)
  8404  		return true
  8405  	}
  8406  	// match: (CMOVWLS y _ (FlagGT_UGT))
  8407  	// cond:
  8408  	// result: y
  8409  	for {
  8410  		_ = v.Args[2]
  8411  		y := v.Args[0]
  8412  		v_2 := v.Args[2]
  8413  		if v_2.Op != OpAMD64FlagGT_UGT {
  8414  			break
  8415  		}
  8416  		v.reset(OpCopy)
  8417  		v.Type = y.Type
  8418  		v.AddArg(y)
  8419  		return true
  8420  	}
  8421  	// match: (CMOVWLS _ x (FlagGT_ULT))
  8422  	// cond:
  8423  	// result: x
  8424  	for {
  8425  		_ = v.Args[2]
  8426  		x := v.Args[1]
  8427  		v_2 := v.Args[2]
  8428  		if v_2.Op != OpAMD64FlagGT_ULT {
  8429  			break
  8430  		}
  8431  		v.reset(OpCopy)
  8432  		v.Type = x.Type
  8433  		v.AddArg(x)
  8434  		return true
  8435  	}
  8436  	// match: (CMOVWLS _ x (FlagLT_ULT))
  8437  	// cond:
  8438  	// result: x
  8439  	for {
  8440  		_ = v.Args[2]
  8441  		x := v.Args[1]
  8442  		v_2 := v.Args[2]
  8443  		if v_2.Op != OpAMD64FlagLT_ULT {
  8444  			break
  8445  		}
  8446  		v.reset(OpCopy)
  8447  		v.Type = x.Type
  8448  		v.AddArg(x)
  8449  		return true
  8450  	}
  8451  	// match: (CMOVWLS y _ (FlagLT_UGT))
  8452  	// cond:
  8453  	// result: y
  8454  	for {
  8455  		_ = v.Args[2]
  8456  		y := v.Args[0]
  8457  		v_2 := v.Args[2]
  8458  		if v_2.Op != OpAMD64FlagLT_UGT {
  8459  			break
  8460  		}
  8461  		v.reset(OpCopy)
  8462  		v.Type = y.Type
  8463  		v.AddArg(y)
  8464  		return true
  8465  	}
  8466  	return false
  8467  }
  8468  func rewriteValueAMD64_OpAMD64CMOVWLT_0(v *Value) bool {
  8469  	// match: (CMOVWLT x y (InvertFlags cond))
  8470  	// cond:
  8471  	// result: (CMOVWGT x y cond)
  8472  	for {
  8473  		_ = v.Args[2]
  8474  		x := v.Args[0]
  8475  		y := v.Args[1]
  8476  		v_2 := v.Args[2]
  8477  		if v_2.Op != OpAMD64InvertFlags {
  8478  			break
  8479  		}
  8480  		cond := v_2.Args[0]
  8481  		v.reset(OpAMD64CMOVWGT)
  8482  		v.AddArg(x)
  8483  		v.AddArg(y)
  8484  		v.AddArg(cond)
  8485  		return true
  8486  	}
  8487  	// match: (CMOVWLT y _ (FlagEQ))
  8488  	// cond:
  8489  	// result: y
  8490  	for {
  8491  		_ = v.Args[2]
  8492  		y := v.Args[0]
  8493  		v_2 := v.Args[2]
  8494  		if v_2.Op != OpAMD64FlagEQ {
  8495  			break
  8496  		}
  8497  		v.reset(OpCopy)
  8498  		v.Type = y.Type
  8499  		v.AddArg(y)
  8500  		return true
  8501  	}
  8502  	// match: (CMOVWLT y _ (FlagGT_UGT))
  8503  	// cond:
  8504  	// result: y
  8505  	for {
  8506  		_ = v.Args[2]
  8507  		y := v.Args[0]
  8508  		v_2 := v.Args[2]
  8509  		if v_2.Op != OpAMD64FlagGT_UGT {
  8510  			break
  8511  		}
  8512  		v.reset(OpCopy)
  8513  		v.Type = y.Type
  8514  		v.AddArg(y)
  8515  		return true
  8516  	}
  8517  	// match: (CMOVWLT y _ (FlagGT_ULT))
  8518  	// cond:
  8519  	// result: y
  8520  	for {
  8521  		_ = v.Args[2]
  8522  		y := v.Args[0]
  8523  		v_2 := v.Args[2]
  8524  		if v_2.Op != OpAMD64FlagGT_ULT {
  8525  			break
  8526  		}
  8527  		v.reset(OpCopy)
  8528  		v.Type = y.Type
  8529  		v.AddArg(y)
  8530  		return true
  8531  	}
  8532  	// match: (CMOVWLT _ x (FlagLT_ULT))
  8533  	// cond:
  8534  	// result: x
  8535  	for {
  8536  		_ = v.Args[2]
  8537  		x := v.Args[1]
  8538  		v_2 := v.Args[2]
  8539  		if v_2.Op != OpAMD64FlagLT_ULT {
  8540  			break
  8541  		}
  8542  		v.reset(OpCopy)
  8543  		v.Type = x.Type
  8544  		v.AddArg(x)
  8545  		return true
  8546  	}
  8547  	// match: (CMOVWLT _ x (FlagLT_UGT))
  8548  	// cond:
  8549  	// result: x
  8550  	for {
  8551  		_ = v.Args[2]
  8552  		x := v.Args[1]
  8553  		v_2 := v.Args[2]
  8554  		if v_2.Op != OpAMD64FlagLT_UGT {
  8555  			break
  8556  		}
  8557  		v.reset(OpCopy)
  8558  		v.Type = x.Type
  8559  		v.AddArg(x)
  8560  		return true
  8561  	}
  8562  	return false
  8563  }
  8564  func rewriteValueAMD64_OpAMD64CMOVWNE_0(v *Value) bool {
  8565  	// match: (CMOVWNE x y (InvertFlags cond))
  8566  	// cond:
  8567  	// result: (CMOVWNE x y cond)
  8568  	for {
  8569  		_ = v.Args[2]
  8570  		x := v.Args[0]
  8571  		y := v.Args[1]
  8572  		v_2 := v.Args[2]
  8573  		if v_2.Op != OpAMD64InvertFlags {
  8574  			break
  8575  		}
  8576  		cond := v_2.Args[0]
  8577  		v.reset(OpAMD64CMOVWNE)
  8578  		v.AddArg(x)
  8579  		v.AddArg(y)
  8580  		v.AddArg(cond)
  8581  		return true
  8582  	}
  8583  	// match: (CMOVWNE y _ (FlagEQ))
  8584  	// cond:
  8585  	// result: y
  8586  	for {
  8587  		_ = v.Args[2]
  8588  		y := v.Args[0]
  8589  		v_2 := v.Args[2]
  8590  		if v_2.Op != OpAMD64FlagEQ {
  8591  			break
  8592  		}
  8593  		v.reset(OpCopy)
  8594  		v.Type = y.Type
  8595  		v.AddArg(y)
  8596  		return true
  8597  	}
  8598  	// match: (CMOVWNE _ x (FlagGT_UGT))
  8599  	// cond:
  8600  	// result: x
  8601  	for {
  8602  		_ = v.Args[2]
  8603  		x := v.Args[1]
  8604  		v_2 := v.Args[2]
  8605  		if v_2.Op != OpAMD64FlagGT_UGT {
  8606  			break
  8607  		}
  8608  		v.reset(OpCopy)
  8609  		v.Type = x.Type
  8610  		v.AddArg(x)
  8611  		return true
  8612  	}
  8613  	// match: (CMOVWNE _ x (FlagGT_ULT))
  8614  	// cond:
  8615  	// result: x
  8616  	for {
  8617  		_ = v.Args[2]
  8618  		x := v.Args[1]
  8619  		v_2 := v.Args[2]
  8620  		if v_2.Op != OpAMD64FlagGT_ULT {
  8621  			break
  8622  		}
  8623  		v.reset(OpCopy)
  8624  		v.Type = x.Type
  8625  		v.AddArg(x)
  8626  		return true
  8627  	}
  8628  	// match: (CMOVWNE _ x (FlagLT_ULT))
  8629  	// cond:
  8630  	// result: x
  8631  	for {
  8632  		_ = v.Args[2]
  8633  		x := v.Args[1]
  8634  		v_2 := v.Args[2]
  8635  		if v_2.Op != OpAMD64FlagLT_ULT {
  8636  			break
  8637  		}
  8638  		v.reset(OpCopy)
  8639  		v.Type = x.Type
  8640  		v.AddArg(x)
  8641  		return true
  8642  	}
  8643  	// match: (CMOVWNE _ x (FlagLT_UGT))
  8644  	// cond:
  8645  	// result: x
  8646  	for {
  8647  		_ = v.Args[2]
  8648  		x := v.Args[1]
  8649  		v_2 := v.Args[2]
  8650  		if v_2.Op != OpAMD64FlagLT_UGT {
  8651  			break
  8652  		}
  8653  		v.reset(OpCopy)
  8654  		v.Type = x.Type
  8655  		v.AddArg(x)
  8656  		return true
  8657  	}
  8658  	return false
  8659  }
  8660  func rewriteValueAMD64_OpAMD64CMPB_0(v *Value) bool {
  8661  	b := v.Block
  8662  	// match: (CMPB x (MOVLconst [c]))
  8663  	// cond:
  8664  	// result: (CMPBconst x [int64(int8(c))])
  8665  	for {
  8666  		_ = v.Args[1]
  8667  		x := v.Args[0]
  8668  		v_1 := v.Args[1]
  8669  		if v_1.Op != OpAMD64MOVLconst {
  8670  			break
  8671  		}
  8672  		c := v_1.AuxInt
  8673  		v.reset(OpAMD64CMPBconst)
  8674  		v.AuxInt = int64(int8(c))
  8675  		v.AddArg(x)
  8676  		return true
  8677  	}
  8678  	// match: (CMPB (MOVLconst [c]) x)
  8679  	// cond:
  8680  	// result: (InvertFlags (CMPBconst x [int64(int8(c))]))
  8681  	for {
  8682  		x := v.Args[1]
  8683  		v_0 := v.Args[0]
  8684  		if v_0.Op != OpAMD64MOVLconst {
  8685  			break
  8686  		}
  8687  		c := v_0.AuxInt
  8688  		v.reset(OpAMD64InvertFlags)
  8689  		v0 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
  8690  		v0.AuxInt = int64(int8(c))
  8691  		v0.AddArg(x)
  8692  		v.AddArg(v0)
  8693  		return true
  8694  	}
  8695  	// match: (CMPB l:(MOVBload {sym} [off] ptr mem) x)
  8696  	// cond: canMergeLoad(v, l) && clobber(l)
  8697  	// result: (CMPBload {sym} [off] ptr x mem)
  8698  	for {
  8699  		x := v.Args[1]
  8700  		l := v.Args[0]
  8701  		if l.Op != OpAMD64MOVBload {
  8702  			break
  8703  		}
  8704  		off := l.AuxInt
  8705  		sym := l.Aux
  8706  		mem := l.Args[1]
  8707  		ptr := l.Args[0]
  8708  		if !(canMergeLoad(v, l) && clobber(l)) {
  8709  			break
  8710  		}
  8711  		v.reset(OpAMD64CMPBload)
  8712  		v.AuxInt = off
  8713  		v.Aux = sym
  8714  		v.AddArg(ptr)
  8715  		v.AddArg(x)
  8716  		v.AddArg(mem)
  8717  		return true
  8718  	}
  8719  	// match: (CMPB x l:(MOVBload {sym} [off] ptr mem))
  8720  	// cond: canMergeLoad(v, l) && clobber(l)
  8721  	// result: (InvertFlags (CMPBload {sym} [off] ptr x mem))
  8722  	for {
  8723  		_ = v.Args[1]
  8724  		x := v.Args[0]
  8725  		l := v.Args[1]
  8726  		if l.Op != OpAMD64MOVBload {
  8727  			break
  8728  		}
  8729  		off := l.AuxInt
  8730  		sym := l.Aux
  8731  		mem := l.Args[1]
  8732  		ptr := l.Args[0]
  8733  		if !(canMergeLoad(v, l) && clobber(l)) {
  8734  			break
  8735  		}
  8736  		v.reset(OpAMD64InvertFlags)
  8737  		v0 := b.NewValue0(l.Pos, OpAMD64CMPBload, types.TypeFlags)
  8738  		v0.AuxInt = off
  8739  		v0.Aux = sym
  8740  		v0.AddArg(ptr)
  8741  		v0.AddArg(x)
  8742  		v0.AddArg(mem)
  8743  		v.AddArg(v0)
  8744  		return true
  8745  	}
  8746  	return false
  8747  }
  8748  func rewriteValueAMD64_OpAMD64CMPBconst_0(v *Value) bool {
  8749  	b := v.Block
  8750  	// match: (CMPBconst (MOVLconst [x]) [y])
  8751  	// cond: int8(x)==int8(y)
  8752  	// result: (FlagEQ)
  8753  	for {
  8754  		y := v.AuxInt
  8755  		v_0 := v.Args[0]
  8756  		if v_0.Op != OpAMD64MOVLconst {
  8757  			break
  8758  		}
  8759  		x := v_0.AuxInt
  8760  		if !(int8(x) == int8(y)) {
  8761  			break
  8762  		}
  8763  		v.reset(OpAMD64FlagEQ)
  8764  		return true
  8765  	}
  8766  	// match: (CMPBconst (MOVLconst [x]) [y])
  8767  	// cond: int8(x)<int8(y) && uint8(x)<uint8(y)
  8768  	// result: (FlagLT_ULT)
  8769  	for {
  8770  		y := v.AuxInt
  8771  		v_0 := v.Args[0]
  8772  		if v_0.Op != OpAMD64MOVLconst {
  8773  			break
  8774  		}
  8775  		x := v_0.AuxInt
  8776  		if !(int8(x) < int8(y) && uint8(x) < uint8(y)) {
  8777  			break
  8778  		}
  8779  		v.reset(OpAMD64FlagLT_ULT)
  8780  		return true
  8781  	}
  8782  	// match: (CMPBconst (MOVLconst [x]) [y])
  8783  	// cond: int8(x)<int8(y) && uint8(x)>uint8(y)
  8784  	// result: (FlagLT_UGT)
  8785  	for {
  8786  		y := v.AuxInt
  8787  		v_0 := v.Args[0]
  8788  		if v_0.Op != OpAMD64MOVLconst {
  8789  			break
  8790  		}
  8791  		x := v_0.AuxInt
  8792  		if !(int8(x) < int8(y) && uint8(x) > uint8(y)) {
  8793  			break
  8794  		}
  8795  		v.reset(OpAMD64FlagLT_UGT)
  8796  		return true
  8797  	}
  8798  	// match: (CMPBconst (MOVLconst [x]) [y])
  8799  	// cond: int8(x)>int8(y) && uint8(x)<uint8(y)
  8800  	// result: (FlagGT_ULT)
  8801  	for {
  8802  		y := v.AuxInt
  8803  		v_0 := v.Args[0]
  8804  		if v_0.Op != OpAMD64MOVLconst {
  8805  			break
  8806  		}
  8807  		x := v_0.AuxInt
  8808  		if !(int8(x) > int8(y) && uint8(x) < uint8(y)) {
  8809  			break
  8810  		}
  8811  		v.reset(OpAMD64FlagGT_ULT)
  8812  		return true
  8813  	}
  8814  	// match: (CMPBconst (MOVLconst [x]) [y])
  8815  	// cond: int8(x)>int8(y) && uint8(x)>uint8(y)
  8816  	// result: (FlagGT_UGT)
  8817  	for {
  8818  		y := v.AuxInt
  8819  		v_0 := v.Args[0]
  8820  		if v_0.Op != OpAMD64MOVLconst {
  8821  			break
  8822  		}
  8823  		x := v_0.AuxInt
  8824  		if !(int8(x) > int8(y) && uint8(x) > uint8(y)) {
  8825  			break
  8826  		}
  8827  		v.reset(OpAMD64FlagGT_UGT)
  8828  		return true
  8829  	}
  8830  	// match: (CMPBconst (ANDLconst _ [m]) [n])
  8831  	// cond: 0 <= int8(m) && int8(m) < int8(n)
  8832  	// result: (FlagLT_ULT)
  8833  	for {
  8834  		n := v.AuxInt
  8835  		v_0 := v.Args[0]
  8836  		if v_0.Op != OpAMD64ANDLconst {
  8837  			break
  8838  		}
  8839  		m := v_0.AuxInt
  8840  		if !(0 <= int8(m) && int8(m) < int8(n)) {
  8841  			break
  8842  		}
  8843  		v.reset(OpAMD64FlagLT_ULT)
  8844  		return true
  8845  	}
  8846  	// match: (CMPBconst (ANDL x y) [0])
  8847  	// cond:
  8848  	// result: (TESTB x y)
  8849  	for {
  8850  		if v.AuxInt != 0 {
  8851  			break
  8852  		}
  8853  		v_0 := v.Args[0]
  8854  		if v_0.Op != OpAMD64ANDL {
  8855  			break
  8856  		}
  8857  		y := v_0.Args[1]
  8858  		x := v_0.Args[0]
  8859  		v.reset(OpAMD64TESTB)
  8860  		v.AddArg(x)
  8861  		v.AddArg(y)
  8862  		return true
  8863  	}
  8864  	// match: (CMPBconst (ANDLconst [c] x) [0])
  8865  	// cond:
  8866  	// result: (TESTBconst [int64(int8(c))] x)
  8867  	for {
  8868  		if v.AuxInt != 0 {
  8869  			break
  8870  		}
  8871  		v_0 := v.Args[0]
  8872  		if v_0.Op != OpAMD64ANDLconst {
  8873  			break
  8874  		}
  8875  		c := v_0.AuxInt
  8876  		x := v_0.Args[0]
  8877  		v.reset(OpAMD64TESTBconst)
  8878  		v.AuxInt = int64(int8(c))
  8879  		v.AddArg(x)
  8880  		return true
  8881  	}
  8882  	// match: (CMPBconst x [0])
  8883  	// cond:
  8884  	// result: (TESTB x x)
  8885  	for {
  8886  		if v.AuxInt != 0 {
  8887  			break
  8888  		}
  8889  		x := v.Args[0]
  8890  		v.reset(OpAMD64TESTB)
  8891  		v.AddArg(x)
  8892  		v.AddArg(x)
  8893  		return true
  8894  	}
  8895  	// match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c])
  8896  	// cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l)
  8897  	// result: @l.Block (CMPBconstload {sym} [makeValAndOff(c,off)] ptr mem)
  8898  	for {
  8899  		c := v.AuxInt
  8900  		l := v.Args[0]
  8901  		if l.Op != OpAMD64MOVBload {
  8902  			break
  8903  		}
  8904  		off := l.AuxInt
  8905  		sym := l.Aux
  8906  		mem := l.Args[1]
  8907  		ptr := l.Args[0]
  8908  		if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) {
  8909  			break
  8910  		}
  8911  		b = l.Block
  8912  		v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags)
  8913  		v.reset(OpCopy)
  8914  		v.AddArg(v0)
  8915  		v0.AuxInt = makeValAndOff(c, off)
  8916  		v0.Aux = sym
  8917  		v0.AddArg(ptr)
  8918  		v0.AddArg(mem)
  8919  		return true
  8920  	}
  8921  	return false
  8922  }
  8923  func rewriteValueAMD64_OpAMD64CMPBconstload_0(v *Value) bool {
  8924  	// match: (CMPBconstload [valoff1] {sym} (ADDQconst [off2] base) mem)
  8925  	// cond: ValAndOff(valoff1).canAdd(off2)
  8926  	// result: (CMPBconstload [ValAndOff(valoff1).add(off2)] {sym} base mem)
  8927  	for {
  8928  		valoff1 := v.AuxInt
  8929  		sym := v.Aux
  8930  		mem := v.Args[1]
  8931  		v_0 := v.Args[0]
  8932  		if v_0.Op != OpAMD64ADDQconst {
  8933  			break
  8934  		}
  8935  		off2 := v_0.AuxInt
  8936  		base := v_0.Args[0]
  8937  		if !(ValAndOff(valoff1).canAdd(off2)) {
  8938  			break
  8939  		}
  8940  		v.reset(OpAMD64CMPBconstload)
  8941  		v.AuxInt = ValAndOff(valoff1).add(off2)
  8942  		v.Aux = sym
  8943  		v.AddArg(base)
  8944  		v.AddArg(mem)
  8945  		return true
  8946  	}
  8947  	// match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  8948  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  8949  	// result: (CMPBconstload [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  8950  	for {
  8951  		valoff1 := v.AuxInt
  8952  		sym1 := v.Aux
  8953  		mem := v.Args[1]
  8954  		v_0 := v.Args[0]
  8955  		if v_0.Op != OpAMD64LEAQ {
  8956  			break
  8957  		}
  8958  		off2 := v_0.AuxInt
  8959  		sym2 := v_0.Aux
  8960  		base := v_0.Args[0]
  8961  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  8962  			break
  8963  		}
  8964  		v.reset(OpAMD64CMPBconstload)
  8965  		v.AuxInt = ValAndOff(valoff1).add(off2)
  8966  		v.Aux = mergeSym(sym1, sym2)
  8967  		v.AddArg(base)
  8968  		v.AddArg(mem)
  8969  		return true
  8970  	}
  8971  	return false
  8972  }
  8973  func rewriteValueAMD64_OpAMD64CMPBload_0(v *Value) bool {
  8974  	// match: (CMPBload [off1] {sym} (ADDQconst [off2] base) val mem)
  8975  	// cond: is32Bit(off1+off2)
  8976  	// result: (CMPBload [off1+off2] {sym} base val mem)
  8977  	for {
  8978  		off1 := v.AuxInt
  8979  		sym := v.Aux
  8980  		mem := v.Args[2]
  8981  		v_0 := v.Args[0]
  8982  		if v_0.Op != OpAMD64ADDQconst {
  8983  			break
  8984  		}
  8985  		off2 := v_0.AuxInt
  8986  		base := v_0.Args[0]
  8987  		val := v.Args[1]
  8988  		if !(is32Bit(off1 + off2)) {
  8989  			break
  8990  		}
  8991  		v.reset(OpAMD64CMPBload)
  8992  		v.AuxInt = off1 + off2
  8993  		v.Aux = sym
  8994  		v.AddArg(base)
  8995  		v.AddArg(val)
  8996  		v.AddArg(mem)
  8997  		return true
  8998  	}
  8999  	// match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  9000  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  9001  	// result: (CMPBload [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  9002  	for {
  9003  		off1 := v.AuxInt
  9004  		sym1 := v.Aux
  9005  		mem := v.Args[2]
  9006  		v_0 := v.Args[0]
  9007  		if v_0.Op != OpAMD64LEAQ {
  9008  			break
  9009  		}
  9010  		off2 := v_0.AuxInt
  9011  		sym2 := v_0.Aux
  9012  		base := v_0.Args[0]
  9013  		val := v.Args[1]
  9014  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  9015  			break
  9016  		}
  9017  		v.reset(OpAMD64CMPBload)
  9018  		v.AuxInt = off1 + off2
  9019  		v.Aux = mergeSym(sym1, sym2)
  9020  		v.AddArg(base)
  9021  		v.AddArg(val)
  9022  		v.AddArg(mem)
  9023  		return true
  9024  	}
  9025  	// match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem)
  9026  	// cond: validValAndOff(int64(int8(c)),off)
  9027  	// result: (CMPBconstload {sym} [makeValAndOff(int64(int8(c)),off)] ptr mem)
  9028  	for {
  9029  		off := v.AuxInt
  9030  		sym := v.Aux
  9031  		mem := v.Args[2]
  9032  		ptr := v.Args[0]
  9033  		v_1 := v.Args[1]
  9034  		if v_1.Op != OpAMD64MOVLconst {
  9035  			break
  9036  		}
  9037  		c := v_1.AuxInt
  9038  		if !(validValAndOff(int64(int8(c)), off)) {
  9039  			break
  9040  		}
  9041  		v.reset(OpAMD64CMPBconstload)
  9042  		v.AuxInt = makeValAndOff(int64(int8(c)), off)
  9043  		v.Aux = sym
  9044  		v.AddArg(ptr)
  9045  		v.AddArg(mem)
  9046  		return true
  9047  	}
  9048  	return false
  9049  }
  9050  func rewriteValueAMD64_OpAMD64CMPL_0(v *Value) bool {
  9051  	b := v.Block
  9052  	// match: (CMPL x (MOVLconst [c]))
  9053  	// cond:
  9054  	// result: (CMPLconst x [c])
  9055  	for {
  9056  		_ = v.Args[1]
  9057  		x := v.Args[0]
  9058  		v_1 := v.Args[1]
  9059  		if v_1.Op != OpAMD64MOVLconst {
  9060  			break
  9061  		}
  9062  		c := v_1.AuxInt
  9063  		v.reset(OpAMD64CMPLconst)
  9064  		v.AuxInt = c
  9065  		v.AddArg(x)
  9066  		return true
  9067  	}
  9068  	// match: (CMPL (MOVLconst [c]) x)
  9069  	// cond:
  9070  	// result: (InvertFlags (CMPLconst x [c]))
  9071  	for {
  9072  		x := v.Args[1]
  9073  		v_0 := v.Args[0]
  9074  		if v_0.Op != OpAMD64MOVLconst {
  9075  			break
  9076  		}
  9077  		c := v_0.AuxInt
  9078  		v.reset(OpAMD64InvertFlags)
  9079  		v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
  9080  		v0.AuxInt = c
  9081  		v0.AddArg(x)
  9082  		v.AddArg(v0)
  9083  		return true
  9084  	}
  9085  	// match: (CMPL l:(MOVLload {sym} [off] ptr mem) x)
  9086  	// cond: canMergeLoad(v, l) && clobber(l)
  9087  	// result: (CMPLload {sym} [off] ptr x mem)
  9088  	for {
  9089  		x := v.Args[1]
  9090  		l := v.Args[0]
  9091  		if l.Op != OpAMD64MOVLload {
  9092  			break
  9093  		}
  9094  		off := l.AuxInt
  9095  		sym := l.Aux
  9096  		mem := l.Args[1]
  9097  		ptr := l.Args[0]
  9098  		if !(canMergeLoad(v, l) && clobber(l)) {
  9099  			break
  9100  		}
  9101  		v.reset(OpAMD64CMPLload)
  9102  		v.AuxInt = off
  9103  		v.Aux = sym
  9104  		v.AddArg(ptr)
  9105  		v.AddArg(x)
  9106  		v.AddArg(mem)
  9107  		return true
  9108  	}
  9109  	// match: (CMPL x l:(MOVLload {sym} [off] ptr mem))
  9110  	// cond: canMergeLoad(v, l) && clobber(l)
  9111  	// result: (InvertFlags (CMPLload {sym} [off] ptr x mem))
  9112  	for {
  9113  		_ = v.Args[1]
  9114  		x := v.Args[0]
  9115  		l := v.Args[1]
  9116  		if l.Op != OpAMD64MOVLload {
  9117  			break
  9118  		}
  9119  		off := l.AuxInt
  9120  		sym := l.Aux
  9121  		mem := l.Args[1]
  9122  		ptr := l.Args[0]
  9123  		if !(canMergeLoad(v, l) && clobber(l)) {
  9124  			break
  9125  		}
  9126  		v.reset(OpAMD64InvertFlags)
  9127  		v0 := b.NewValue0(l.Pos, OpAMD64CMPLload, types.TypeFlags)
  9128  		v0.AuxInt = off
  9129  		v0.Aux = sym
  9130  		v0.AddArg(ptr)
  9131  		v0.AddArg(x)
  9132  		v0.AddArg(mem)
  9133  		v.AddArg(v0)
  9134  		return true
  9135  	}
  9136  	return false
  9137  }
  9138  func rewriteValueAMD64_OpAMD64CMPLconst_0(v *Value) bool {
  9139  	// match: (CMPLconst (MOVLconst [x]) [y])
  9140  	// cond: int32(x)==int32(y)
  9141  	// result: (FlagEQ)
  9142  	for {
  9143  		y := v.AuxInt
  9144  		v_0 := v.Args[0]
  9145  		if v_0.Op != OpAMD64MOVLconst {
  9146  			break
  9147  		}
  9148  		x := v_0.AuxInt
  9149  		if !(int32(x) == int32(y)) {
  9150  			break
  9151  		}
  9152  		v.reset(OpAMD64FlagEQ)
  9153  		return true
  9154  	}
  9155  	// match: (CMPLconst (MOVLconst [x]) [y])
  9156  	// cond: int32(x)<int32(y) && uint32(x)<uint32(y)
  9157  	// result: (FlagLT_ULT)
  9158  	for {
  9159  		y := v.AuxInt
  9160  		v_0 := v.Args[0]
  9161  		if v_0.Op != OpAMD64MOVLconst {
  9162  			break
  9163  		}
  9164  		x := v_0.AuxInt
  9165  		if !(int32(x) < int32(y) && uint32(x) < uint32(y)) {
  9166  			break
  9167  		}
  9168  		v.reset(OpAMD64FlagLT_ULT)
  9169  		return true
  9170  	}
  9171  	// match: (CMPLconst (MOVLconst [x]) [y])
  9172  	// cond: int32(x)<int32(y) && uint32(x)>uint32(y)
  9173  	// result: (FlagLT_UGT)
  9174  	for {
  9175  		y := v.AuxInt
  9176  		v_0 := v.Args[0]
  9177  		if v_0.Op != OpAMD64MOVLconst {
  9178  			break
  9179  		}
  9180  		x := v_0.AuxInt
  9181  		if !(int32(x) < int32(y) && uint32(x) > uint32(y)) {
  9182  			break
  9183  		}
  9184  		v.reset(OpAMD64FlagLT_UGT)
  9185  		return true
  9186  	}
  9187  	// match: (CMPLconst (MOVLconst [x]) [y])
  9188  	// cond: int32(x)>int32(y) && uint32(x)<uint32(y)
  9189  	// result: (FlagGT_ULT)
  9190  	for {
  9191  		y := v.AuxInt
  9192  		v_0 := v.Args[0]
  9193  		if v_0.Op != OpAMD64MOVLconst {
  9194  			break
  9195  		}
  9196  		x := v_0.AuxInt
  9197  		if !(int32(x) > int32(y) && uint32(x) < uint32(y)) {
  9198  			break
  9199  		}
  9200  		v.reset(OpAMD64FlagGT_ULT)
  9201  		return true
  9202  	}
  9203  	// match: (CMPLconst (MOVLconst [x]) [y])
  9204  	// cond: int32(x)>int32(y) && uint32(x)>uint32(y)
  9205  	// result: (FlagGT_UGT)
  9206  	for {
  9207  		y := v.AuxInt
  9208  		v_0 := v.Args[0]
  9209  		if v_0.Op != OpAMD64MOVLconst {
  9210  			break
  9211  		}
  9212  		x := v_0.AuxInt
  9213  		if !(int32(x) > int32(y) && uint32(x) > uint32(y)) {
  9214  			break
  9215  		}
  9216  		v.reset(OpAMD64FlagGT_UGT)
  9217  		return true
  9218  	}
  9219  	// match: (CMPLconst (SHRLconst _ [c]) [n])
  9220  	// cond: 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n)
  9221  	// result: (FlagLT_ULT)
  9222  	for {
  9223  		n := v.AuxInt
  9224  		v_0 := v.Args[0]
  9225  		if v_0.Op != OpAMD64SHRLconst {
  9226  			break
  9227  		}
  9228  		c := v_0.AuxInt
  9229  		if !(0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n)) {
  9230  			break
  9231  		}
  9232  		v.reset(OpAMD64FlagLT_ULT)
  9233  		return true
  9234  	}
  9235  	// match: (CMPLconst (ANDLconst _ [m]) [n])
  9236  	// cond: 0 <= int32(m) && int32(m) < int32(n)
  9237  	// result: (FlagLT_ULT)
  9238  	for {
  9239  		n := v.AuxInt
  9240  		v_0 := v.Args[0]
  9241  		if v_0.Op != OpAMD64ANDLconst {
  9242  			break
  9243  		}
  9244  		m := v_0.AuxInt
  9245  		if !(0 <= int32(m) && int32(m) < int32(n)) {
  9246  			break
  9247  		}
  9248  		v.reset(OpAMD64FlagLT_ULT)
  9249  		return true
  9250  	}
  9251  	// match: (CMPLconst (ANDL x y) [0])
  9252  	// cond:
  9253  	// result: (TESTL x y)
  9254  	for {
  9255  		if v.AuxInt != 0 {
  9256  			break
  9257  		}
  9258  		v_0 := v.Args[0]
  9259  		if v_0.Op != OpAMD64ANDL {
  9260  			break
  9261  		}
  9262  		y := v_0.Args[1]
  9263  		x := v_0.Args[0]
  9264  		v.reset(OpAMD64TESTL)
  9265  		v.AddArg(x)
  9266  		v.AddArg(y)
  9267  		return true
  9268  	}
  9269  	// match: (CMPLconst (ANDLconst [c] x) [0])
  9270  	// cond:
  9271  	// result: (TESTLconst [c] x)
  9272  	for {
  9273  		if v.AuxInt != 0 {
  9274  			break
  9275  		}
  9276  		v_0 := v.Args[0]
  9277  		if v_0.Op != OpAMD64ANDLconst {
  9278  			break
  9279  		}
  9280  		c := v_0.AuxInt
  9281  		x := v_0.Args[0]
  9282  		v.reset(OpAMD64TESTLconst)
  9283  		v.AuxInt = c
  9284  		v.AddArg(x)
  9285  		return true
  9286  	}
  9287  	// match: (CMPLconst x [0])
  9288  	// cond:
  9289  	// result: (TESTL x x)
  9290  	for {
  9291  		if v.AuxInt != 0 {
  9292  			break
  9293  		}
  9294  		x := v.Args[0]
  9295  		v.reset(OpAMD64TESTL)
  9296  		v.AddArg(x)
  9297  		v.AddArg(x)
  9298  		return true
  9299  	}
  9300  	return false
  9301  }
  9302  func rewriteValueAMD64_OpAMD64CMPLconst_10(v *Value) bool {
  9303  	b := v.Block
  9304  	// match: (CMPLconst l:(MOVLload {sym} [off] ptr mem) [c])
  9305  	// cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l)
  9306  	// result: @l.Block (CMPLconstload {sym} [makeValAndOff(c,off)] ptr mem)
  9307  	for {
  9308  		c := v.AuxInt
  9309  		l := v.Args[0]
  9310  		if l.Op != OpAMD64MOVLload {
  9311  			break
  9312  		}
  9313  		off := l.AuxInt
  9314  		sym := l.Aux
  9315  		mem := l.Args[1]
  9316  		ptr := l.Args[0]
  9317  		if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) {
  9318  			break
  9319  		}
  9320  		b = l.Block
  9321  		v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags)
  9322  		v.reset(OpCopy)
  9323  		v.AddArg(v0)
  9324  		v0.AuxInt = makeValAndOff(c, off)
  9325  		v0.Aux = sym
  9326  		v0.AddArg(ptr)
  9327  		v0.AddArg(mem)
  9328  		return true
  9329  	}
  9330  	return false
  9331  }
  9332  func rewriteValueAMD64_OpAMD64CMPLconstload_0(v *Value) bool {
  9333  	// match: (CMPLconstload [valoff1] {sym} (ADDQconst [off2] base) mem)
  9334  	// cond: ValAndOff(valoff1).canAdd(off2)
  9335  	// result: (CMPLconstload [ValAndOff(valoff1).add(off2)] {sym} base mem)
  9336  	for {
  9337  		valoff1 := v.AuxInt
  9338  		sym := v.Aux
  9339  		mem := v.Args[1]
  9340  		v_0 := v.Args[0]
  9341  		if v_0.Op != OpAMD64ADDQconst {
  9342  			break
  9343  		}
  9344  		off2 := v_0.AuxInt
  9345  		base := v_0.Args[0]
  9346  		if !(ValAndOff(valoff1).canAdd(off2)) {
  9347  			break
  9348  		}
  9349  		v.reset(OpAMD64CMPLconstload)
  9350  		v.AuxInt = ValAndOff(valoff1).add(off2)
  9351  		v.Aux = sym
  9352  		v.AddArg(base)
  9353  		v.AddArg(mem)
  9354  		return true
  9355  	}
  9356  	// match: (CMPLconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  9357  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  9358  	// result: (CMPLconstload [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  9359  	for {
  9360  		valoff1 := v.AuxInt
  9361  		sym1 := v.Aux
  9362  		mem := v.Args[1]
  9363  		v_0 := v.Args[0]
  9364  		if v_0.Op != OpAMD64LEAQ {
  9365  			break
  9366  		}
  9367  		off2 := v_0.AuxInt
  9368  		sym2 := v_0.Aux
  9369  		base := v_0.Args[0]
  9370  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  9371  			break
  9372  		}
  9373  		v.reset(OpAMD64CMPLconstload)
  9374  		v.AuxInt = ValAndOff(valoff1).add(off2)
  9375  		v.Aux = mergeSym(sym1, sym2)
  9376  		v.AddArg(base)
  9377  		v.AddArg(mem)
  9378  		return true
  9379  	}
  9380  	return false
  9381  }
  9382  func rewriteValueAMD64_OpAMD64CMPLload_0(v *Value) bool {
  9383  	// match: (CMPLload [off1] {sym} (ADDQconst [off2] base) val mem)
  9384  	// cond: is32Bit(off1+off2)
  9385  	// result: (CMPLload [off1+off2] {sym} base val mem)
  9386  	for {
  9387  		off1 := v.AuxInt
  9388  		sym := v.Aux
  9389  		mem := v.Args[2]
  9390  		v_0 := v.Args[0]
  9391  		if v_0.Op != OpAMD64ADDQconst {
  9392  			break
  9393  		}
  9394  		off2 := v_0.AuxInt
  9395  		base := v_0.Args[0]
  9396  		val := v.Args[1]
  9397  		if !(is32Bit(off1 + off2)) {
  9398  			break
  9399  		}
  9400  		v.reset(OpAMD64CMPLload)
  9401  		v.AuxInt = off1 + off2
  9402  		v.Aux = sym
  9403  		v.AddArg(base)
  9404  		v.AddArg(val)
  9405  		v.AddArg(mem)
  9406  		return true
  9407  	}
  9408  	// match: (CMPLload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  9409  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  9410  	// result: (CMPLload [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  9411  	for {
  9412  		off1 := v.AuxInt
  9413  		sym1 := v.Aux
  9414  		mem := v.Args[2]
  9415  		v_0 := v.Args[0]
  9416  		if v_0.Op != OpAMD64LEAQ {
  9417  			break
  9418  		}
  9419  		off2 := v_0.AuxInt
  9420  		sym2 := v_0.Aux
  9421  		base := v_0.Args[0]
  9422  		val := v.Args[1]
  9423  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  9424  			break
  9425  		}
  9426  		v.reset(OpAMD64CMPLload)
  9427  		v.AuxInt = off1 + off2
  9428  		v.Aux = mergeSym(sym1, sym2)
  9429  		v.AddArg(base)
  9430  		v.AddArg(val)
  9431  		v.AddArg(mem)
  9432  		return true
  9433  	}
  9434  	// match: (CMPLload {sym} [off] ptr (MOVLconst [c]) mem)
  9435  	// cond: validValAndOff(c,off)
  9436  	// result: (CMPLconstload {sym} [makeValAndOff(c,off)] ptr mem)
  9437  	for {
  9438  		off := v.AuxInt
  9439  		sym := v.Aux
  9440  		mem := v.Args[2]
  9441  		ptr := v.Args[0]
  9442  		v_1 := v.Args[1]
  9443  		if v_1.Op != OpAMD64MOVLconst {
  9444  			break
  9445  		}
  9446  		c := v_1.AuxInt
  9447  		if !(validValAndOff(c, off)) {
  9448  			break
  9449  		}
  9450  		v.reset(OpAMD64CMPLconstload)
  9451  		v.AuxInt = makeValAndOff(c, off)
  9452  		v.Aux = sym
  9453  		v.AddArg(ptr)
  9454  		v.AddArg(mem)
  9455  		return true
  9456  	}
  9457  	return false
  9458  }
  9459  func rewriteValueAMD64_OpAMD64CMPQ_0(v *Value) bool {
  9460  	b := v.Block
  9461  	// match: (CMPQ x (MOVQconst [c]))
  9462  	// cond: is32Bit(c)
  9463  	// result: (CMPQconst x [c])
  9464  	for {
  9465  		_ = v.Args[1]
  9466  		x := v.Args[0]
  9467  		v_1 := v.Args[1]
  9468  		if v_1.Op != OpAMD64MOVQconst {
  9469  			break
  9470  		}
  9471  		c := v_1.AuxInt
  9472  		if !(is32Bit(c)) {
  9473  			break
  9474  		}
  9475  		v.reset(OpAMD64CMPQconst)
  9476  		v.AuxInt = c
  9477  		v.AddArg(x)
  9478  		return true
  9479  	}
  9480  	// match: (CMPQ (MOVQconst [c]) x)
  9481  	// cond: is32Bit(c)
  9482  	// result: (InvertFlags (CMPQconst x [c]))
  9483  	for {
  9484  		x := v.Args[1]
  9485  		v_0 := v.Args[0]
  9486  		if v_0.Op != OpAMD64MOVQconst {
  9487  			break
  9488  		}
  9489  		c := v_0.AuxInt
  9490  		if !(is32Bit(c)) {
  9491  			break
  9492  		}
  9493  		v.reset(OpAMD64InvertFlags)
  9494  		v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
  9495  		v0.AuxInt = c
  9496  		v0.AddArg(x)
  9497  		v.AddArg(v0)
  9498  		return true
  9499  	}
  9500  	// match: (CMPQ l:(MOVQload {sym} [off] ptr mem) x)
  9501  	// cond: canMergeLoad(v, l) && clobber(l)
  9502  	// result: (CMPQload {sym} [off] ptr x mem)
  9503  	for {
  9504  		x := v.Args[1]
  9505  		l := v.Args[0]
  9506  		if l.Op != OpAMD64MOVQload {
  9507  			break
  9508  		}
  9509  		off := l.AuxInt
  9510  		sym := l.Aux
  9511  		mem := l.Args[1]
  9512  		ptr := l.Args[0]
  9513  		if !(canMergeLoad(v, l) && clobber(l)) {
  9514  			break
  9515  		}
  9516  		v.reset(OpAMD64CMPQload)
  9517  		v.AuxInt = off
  9518  		v.Aux = sym
  9519  		v.AddArg(ptr)
  9520  		v.AddArg(x)
  9521  		v.AddArg(mem)
  9522  		return true
  9523  	}
  9524  	// match: (CMPQ x l:(MOVQload {sym} [off] ptr mem))
  9525  	// cond: canMergeLoad(v, l) && clobber(l)
  9526  	// result: (InvertFlags (CMPQload {sym} [off] ptr x mem))
  9527  	for {
  9528  		_ = v.Args[1]
  9529  		x := v.Args[0]
  9530  		l := v.Args[1]
  9531  		if l.Op != OpAMD64MOVQload {
  9532  			break
  9533  		}
  9534  		off := l.AuxInt
  9535  		sym := l.Aux
  9536  		mem := l.Args[1]
  9537  		ptr := l.Args[0]
  9538  		if !(canMergeLoad(v, l) && clobber(l)) {
  9539  			break
  9540  		}
  9541  		v.reset(OpAMD64InvertFlags)
  9542  		v0 := b.NewValue0(l.Pos, OpAMD64CMPQload, types.TypeFlags)
  9543  		v0.AuxInt = off
  9544  		v0.Aux = sym
  9545  		v0.AddArg(ptr)
  9546  		v0.AddArg(x)
  9547  		v0.AddArg(mem)
  9548  		v.AddArg(v0)
  9549  		return true
  9550  	}
  9551  	return false
  9552  }
  9553  func rewriteValueAMD64_OpAMD64CMPQconst_0(v *Value) bool {
  9554  	// match: (CMPQconst (NEGQ (ADDQconst [-16] (ANDQconst [15] _))) [32])
  9555  	// cond:
  9556  	// result: (FlagLT_ULT)
  9557  	for {
  9558  		if v.AuxInt != 32 {
  9559  			break
  9560  		}
  9561  		v_0 := v.Args[0]
  9562  		if v_0.Op != OpAMD64NEGQ {
  9563  			break
  9564  		}
  9565  		v_0_0 := v_0.Args[0]
  9566  		if v_0_0.Op != OpAMD64ADDQconst {
  9567  			break
  9568  		}
  9569  		if v_0_0.AuxInt != -16 {
  9570  			break
  9571  		}
  9572  		v_0_0_0 := v_0_0.Args[0]
  9573  		if v_0_0_0.Op != OpAMD64ANDQconst {
  9574  			break
  9575  		}
  9576  		if v_0_0_0.AuxInt != 15 {
  9577  			break
  9578  		}
  9579  		v.reset(OpAMD64FlagLT_ULT)
  9580  		return true
  9581  	}
  9582  	// match: (CMPQconst (NEGQ (ADDQconst [ -8] (ANDQconst [7] _))) [32])
  9583  	// cond:
  9584  	// result: (FlagLT_ULT)
  9585  	for {
  9586  		if v.AuxInt != 32 {
  9587  			break
  9588  		}
  9589  		v_0 := v.Args[0]
  9590  		if v_0.Op != OpAMD64NEGQ {
  9591  			break
  9592  		}
  9593  		v_0_0 := v_0.Args[0]
  9594  		if v_0_0.Op != OpAMD64ADDQconst {
  9595  			break
  9596  		}
  9597  		if v_0_0.AuxInt != -8 {
  9598  			break
  9599  		}
  9600  		v_0_0_0 := v_0_0.Args[0]
  9601  		if v_0_0_0.Op != OpAMD64ANDQconst {
  9602  			break
  9603  		}
  9604  		if v_0_0_0.AuxInt != 7 {
  9605  			break
  9606  		}
  9607  		v.reset(OpAMD64FlagLT_ULT)
  9608  		return true
  9609  	}
  9610  	// match: (CMPQconst (MOVQconst [x]) [y])
  9611  	// cond: x==y
  9612  	// result: (FlagEQ)
  9613  	for {
  9614  		y := v.AuxInt
  9615  		v_0 := v.Args[0]
  9616  		if v_0.Op != OpAMD64MOVQconst {
  9617  			break
  9618  		}
  9619  		x := v_0.AuxInt
  9620  		if !(x == y) {
  9621  			break
  9622  		}
  9623  		v.reset(OpAMD64FlagEQ)
  9624  		return true
  9625  	}
  9626  	// match: (CMPQconst (MOVQconst [x]) [y])
  9627  	// cond: x<y && uint64(x)<uint64(y)
  9628  	// result: (FlagLT_ULT)
  9629  	for {
  9630  		y := v.AuxInt
  9631  		v_0 := v.Args[0]
  9632  		if v_0.Op != OpAMD64MOVQconst {
  9633  			break
  9634  		}
  9635  		x := v_0.AuxInt
  9636  		if !(x < y && uint64(x) < uint64(y)) {
  9637  			break
  9638  		}
  9639  		v.reset(OpAMD64FlagLT_ULT)
  9640  		return true
  9641  	}
  9642  	// match: (CMPQconst (MOVQconst [x]) [y])
  9643  	// cond: x<y && uint64(x)>uint64(y)
  9644  	// result: (FlagLT_UGT)
  9645  	for {
  9646  		y := v.AuxInt
  9647  		v_0 := v.Args[0]
  9648  		if v_0.Op != OpAMD64MOVQconst {
  9649  			break
  9650  		}
  9651  		x := v_0.AuxInt
  9652  		if !(x < y && uint64(x) > uint64(y)) {
  9653  			break
  9654  		}
  9655  		v.reset(OpAMD64FlagLT_UGT)
  9656  		return true
  9657  	}
  9658  	// match: (CMPQconst (MOVQconst [x]) [y])
  9659  	// cond: x>y && uint64(x)<uint64(y)
  9660  	// result: (FlagGT_ULT)
  9661  	for {
  9662  		y := v.AuxInt
  9663  		v_0 := v.Args[0]
  9664  		if v_0.Op != OpAMD64MOVQconst {
  9665  			break
  9666  		}
  9667  		x := v_0.AuxInt
  9668  		if !(x > y && uint64(x) < uint64(y)) {
  9669  			break
  9670  		}
  9671  		v.reset(OpAMD64FlagGT_ULT)
  9672  		return true
  9673  	}
  9674  	// match: (CMPQconst (MOVQconst [x]) [y])
  9675  	// cond: x>y && uint64(x)>uint64(y)
  9676  	// result: (FlagGT_UGT)
  9677  	for {
  9678  		y := v.AuxInt
  9679  		v_0 := v.Args[0]
  9680  		if v_0.Op != OpAMD64MOVQconst {
  9681  			break
  9682  		}
  9683  		x := v_0.AuxInt
  9684  		if !(x > y && uint64(x) > uint64(y)) {
  9685  			break
  9686  		}
  9687  		v.reset(OpAMD64FlagGT_UGT)
  9688  		return true
  9689  	}
  9690  	// match: (CMPQconst (MOVBQZX _) [c])
  9691  	// cond: 0xFF < c
  9692  	// result: (FlagLT_ULT)
  9693  	for {
  9694  		c := v.AuxInt
  9695  		v_0 := v.Args[0]
  9696  		if v_0.Op != OpAMD64MOVBQZX {
  9697  			break
  9698  		}
  9699  		if !(0xFF < c) {
  9700  			break
  9701  		}
  9702  		v.reset(OpAMD64FlagLT_ULT)
  9703  		return true
  9704  	}
  9705  	// match: (CMPQconst (MOVWQZX _) [c])
  9706  	// cond: 0xFFFF < c
  9707  	// result: (FlagLT_ULT)
  9708  	for {
  9709  		c := v.AuxInt
  9710  		v_0 := v.Args[0]
  9711  		if v_0.Op != OpAMD64MOVWQZX {
  9712  			break
  9713  		}
  9714  		if !(0xFFFF < c) {
  9715  			break
  9716  		}
  9717  		v.reset(OpAMD64FlagLT_ULT)
  9718  		return true
  9719  	}
  9720  	// match: (CMPQconst (MOVLQZX _) [c])
  9721  	// cond: 0xFFFFFFFF < c
  9722  	// result: (FlagLT_ULT)
  9723  	for {
  9724  		c := v.AuxInt
  9725  		v_0 := v.Args[0]
  9726  		if v_0.Op != OpAMD64MOVLQZX {
  9727  			break
  9728  		}
  9729  		if !(0xFFFFFFFF < c) {
  9730  			break
  9731  		}
  9732  		v.reset(OpAMD64FlagLT_ULT)
  9733  		return true
  9734  	}
  9735  	return false
  9736  }
  9737  func rewriteValueAMD64_OpAMD64CMPQconst_10(v *Value) bool {
  9738  	b := v.Block
  9739  	// match: (CMPQconst (SHRQconst _ [c]) [n])
  9740  	// cond: 0 <= n && 0 < c && c <= 64 && (1<<uint64(64-c)) <= uint64(n)
  9741  	// result: (FlagLT_ULT)
  9742  	for {
  9743  		n := v.AuxInt
  9744  		v_0 := v.Args[0]
  9745  		if v_0.Op != OpAMD64SHRQconst {
  9746  			break
  9747  		}
  9748  		c := v_0.AuxInt
  9749  		if !(0 <= n && 0 < c && c <= 64 && (1<<uint64(64-c)) <= uint64(n)) {
  9750  			break
  9751  		}
  9752  		v.reset(OpAMD64FlagLT_ULT)
  9753  		return true
  9754  	}
  9755  	// match: (CMPQconst (ANDQconst _ [m]) [n])
  9756  	// cond: 0 <= m && m < n
  9757  	// result: (FlagLT_ULT)
  9758  	for {
  9759  		n := v.AuxInt
  9760  		v_0 := v.Args[0]
  9761  		if v_0.Op != OpAMD64ANDQconst {
  9762  			break
  9763  		}
  9764  		m := v_0.AuxInt
  9765  		if !(0 <= m && m < n) {
  9766  			break
  9767  		}
  9768  		v.reset(OpAMD64FlagLT_ULT)
  9769  		return true
  9770  	}
  9771  	// match: (CMPQconst (ANDLconst _ [m]) [n])
  9772  	// cond: 0 <= m && m < n
  9773  	// result: (FlagLT_ULT)
  9774  	for {
  9775  		n := v.AuxInt
  9776  		v_0 := v.Args[0]
  9777  		if v_0.Op != OpAMD64ANDLconst {
  9778  			break
  9779  		}
  9780  		m := v_0.AuxInt
  9781  		if !(0 <= m && m < n) {
  9782  			break
  9783  		}
  9784  		v.reset(OpAMD64FlagLT_ULT)
  9785  		return true
  9786  	}
  9787  	// match: (CMPQconst (ANDQ x y) [0])
  9788  	// cond:
  9789  	// result: (TESTQ x y)
  9790  	for {
  9791  		if v.AuxInt != 0 {
  9792  			break
  9793  		}
  9794  		v_0 := v.Args[0]
  9795  		if v_0.Op != OpAMD64ANDQ {
  9796  			break
  9797  		}
  9798  		y := v_0.Args[1]
  9799  		x := v_0.Args[0]
  9800  		v.reset(OpAMD64TESTQ)
  9801  		v.AddArg(x)
  9802  		v.AddArg(y)
  9803  		return true
  9804  	}
  9805  	// match: (CMPQconst (ANDQconst [c] x) [0])
  9806  	// cond:
  9807  	// result: (TESTQconst [c] x)
  9808  	for {
  9809  		if v.AuxInt != 0 {
  9810  			break
  9811  		}
  9812  		v_0 := v.Args[0]
  9813  		if v_0.Op != OpAMD64ANDQconst {
  9814  			break
  9815  		}
  9816  		c := v_0.AuxInt
  9817  		x := v_0.Args[0]
  9818  		v.reset(OpAMD64TESTQconst)
  9819  		v.AuxInt = c
  9820  		v.AddArg(x)
  9821  		return true
  9822  	}
  9823  	// match: (CMPQconst x [0])
  9824  	// cond:
  9825  	// result: (TESTQ x x)
  9826  	for {
  9827  		if v.AuxInt != 0 {
  9828  			break
  9829  		}
  9830  		x := v.Args[0]
  9831  		v.reset(OpAMD64TESTQ)
  9832  		v.AddArg(x)
  9833  		v.AddArg(x)
  9834  		return true
  9835  	}
  9836  	// match: (CMPQconst l:(MOVQload {sym} [off] ptr mem) [c])
  9837  	// cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l)
  9838  	// result: @l.Block (CMPQconstload {sym} [makeValAndOff(c,off)] ptr mem)
  9839  	for {
  9840  		c := v.AuxInt
  9841  		l := v.Args[0]
  9842  		if l.Op != OpAMD64MOVQload {
  9843  			break
  9844  		}
  9845  		off := l.AuxInt
  9846  		sym := l.Aux
  9847  		mem := l.Args[1]
  9848  		ptr := l.Args[0]
  9849  		if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) {
  9850  			break
  9851  		}
  9852  		b = l.Block
  9853  		v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags)
  9854  		v.reset(OpCopy)
  9855  		v.AddArg(v0)
  9856  		v0.AuxInt = makeValAndOff(c, off)
  9857  		v0.Aux = sym
  9858  		v0.AddArg(ptr)
  9859  		v0.AddArg(mem)
  9860  		return true
  9861  	}
  9862  	return false
  9863  }
  9864  func rewriteValueAMD64_OpAMD64CMPQconstload_0(v *Value) bool {
  9865  	// match: (CMPQconstload [valoff1] {sym} (ADDQconst [off2] base) mem)
  9866  	// cond: ValAndOff(valoff1).canAdd(off2)
  9867  	// result: (CMPQconstload [ValAndOff(valoff1).add(off2)] {sym} base mem)
  9868  	for {
  9869  		valoff1 := v.AuxInt
  9870  		sym := v.Aux
  9871  		mem := v.Args[1]
  9872  		v_0 := v.Args[0]
  9873  		if v_0.Op != OpAMD64ADDQconst {
  9874  			break
  9875  		}
  9876  		off2 := v_0.AuxInt
  9877  		base := v_0.Args[0]
  9878  		if !(ValAndOff(valoff1).canAdd(off2)) {
  9879  			break
  9880  		}
  9881  		v.reset(OpAMD64CMPQconstload)
  9882  		v.AuxInt = ValAndOff(valoff1).add(off2)
  9883  		v.Aux = sym
  9884  		v.AddArg(base)
  9885  		v.AddArg(mem)
  9886  		return true
  9887  	}
  9888  	// match: (CMPQconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
  9889  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
  9890  	// result: (CMPQconstload [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  9891  	for {
  9892  		valoff1 := v.AuxInt
  9893  		sym1 := v.Aux
  9894  		mem := v.Args[1]
  9895  		v_0 := v.Args[0]
  9896  		if v_0.Op != OpAMD64LEAQ {
  9897  			break
  9898  		}
  9899  		off2 := v_0.AuxInt
  9900  		sym2 := v_0.Aux
  9901  		base := v_0.Args[0]
  9902  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
  9903  			break
  9904  		}
  9905  		v.reset(OpAMD64CMPQconstload)
  9906  		v.AuxInt = ValAndOff(valoff1).add(off2)
  9907  		v.Aux = mergeSym(sym1, sym2)
  9908  		v.AddArg(base)
  9909  		v.AddArg(mem)
  9910  		return true
  9911  	}
  9912  	return false
  9913  }
  9914  func rewriteValueAMD64_OpAMD64CMPQload_0(v *Value) bool {
  9915  	// match: (CMPQload [off1] {sym} (ADDQconst [off2] base) val mem)
  9916  	// cond: is32Bit(off1+off2)
  9917  	// result: (CMPQload [off1+off2] {sym} base val mem)
  9918  	for {
  9919  		off1 := v.AuxInt
  9920  		sym := v.Aux
  9921  		mem := v.Args[2]
  9922  		v_0 := v.Args[0]
  9923  		if v_0.Op != OpAMD64ADDQconst {
  9924  			break
  9925  		}
  9926  		off2 := v_0.AuxInt
  9927  		base := v_0.Args[0]
  9928  		val := v.Args[1]
  9929  		if !(is32Bit(off1 + off2)) {
  9930  			break
  9931  		}
  9932  		v.reset(OpAMD64CMPQload)
  9933  		v.AuxInt = off1 + off2
  9934  		v.Aux = sym
  9935  		v.AddArg(base)
  9936  		v.AddArg(val)
  9937  		v.AddArg(mem)
  9938  		return true
  9939  	}
  9940  	// match: (CMPQload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
  9941  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  9942  	// result: (CMPQload [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  9943  	for {
  9944  		off1 := v.AuxInt
  9945  		sym1 := v.Aux
  9946  		mem := v.Args[2]
  9947  		v_0 := v.Args[0]
  9948  		if v_0.Op != OpAMD64LEAQ {
  9949  			break
  9950  		}
  9951  		off2 := v_0.AuxInt
  9952  		sym2 := v_0.Aux
  9953  		base := v_0.Args[0]
  9954  		val := v.Args[1]
  9955  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  9956  			break
  9957  		}
  9958  		v.reset(OpAMD64CMPQload)
  9959  		v.AuxInt = off1 + off2
  9960  		v.Aux = mergeSym(sym1, sym2)
  9961  		v.AddArg(base)
  9962  		v.AddArg(val)
  9963  		v.AddArg(mem)
  9964  		return true
  9965  	}
  9966  	// match: (CMPQload {sym} [off] ptr (MOVQconst [c]) mem)
  9967  	// cond: validValAndOff(c,off)
  9968  	// result: (CMPQconstload {sym} [makeValAndOff(c,off)] ptr mem)
  9969  	for {
  9970  		off := v.AuxInt
  9971  		sym := v.Aux
  9972  		mem := v.Args[2]
  9973  		ptr := v.Args[0]
  9974  		v_1 := v.Args[1]
  9975  		if v_1.Op != OpAMD64MOVQconst {
  9976  			break
  9977  		}
  9978  		c := v_1.AuxInt
  9979  		if !(validValAndOff(c, off)) {
  9980  			break
  9981  		}
  9982  		v.reset(OpAMD64CMPQconstload)
  9983  		v.AuxInt = makeValAndOff(c, off)
  9984  		v.Aux = sym
  9985  		v.AddArg(ptr)
  9986  		v.AddArg(mem)
  9987  		return true
  9988  	}
  9989  	return false
  9990  }
  9991  func rewriteValueAMD64_OpAMD64CMPW_0(v *Value) bool {
  9992  	b := v.Block
  9993  	// match: (CMPW x (MOVLconst [c]))
  9994  	// cond:
  9995  	// result: (CMPWconst x [int64(int16(c))])
  9996  	for {
  9997  		_ = v.Args[1]
  9998  		x := v.Args[0]
  9999  		v_1 := v.Args[1]
 10000  		if v_1.Op != OpAMD64MOVLconst {
 10001  			break
 10002  		}
 10003  		c := v_1.AuxInt
 10004  		v.reset(OpAMD64CMPWconst)
 10005  		v.AuxInt = int64(int16(c))
 10006  		v.AddArg(x)
 10007  		return true
 10008  	}
 10009  	// match: (CMPW (MOVLconst [c]) x)
 10010  	// cond:
 10011  	// result: (InvertFlags (CMPWconst x [int64(int16(c))]))
 10012  	for {
 10013  		x := v.Args[1]
 10014  		v_0 := v.Args[0]
 10015  		if v_0.Op != OpAMD64MOVLconst {
 10016  			break
 10017  		}
 10018  		c := v_0.AuxInt
 10019  		v.reset(OpAMD64InvertFlags)
 10020  		v0 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
 10021  		v0.AuxInt = int64(int16(c))
 10022  		v0.AddArg(x)
 10023  		v.AddArg(v0)
 10024  		return true
 10025  	}
 10026  	// match: (CMPW l:(MOVWload {sym} [off] ptr mem) x)
 10027  	// cond: canMergeLoad(v, l) && clobber(l)
 10028  	// result: (CMPWload {sym} [off] ptr x mem)
 10029  	for {
 10030  		x := v.Args[1]
 10031  		l := v.Args[0]
 10032  		if l.Op != OpAMD64MOVWload {
 10033  			break
 10034  		}
 10035  		off := l.AuxInt
 10036  		sym := l.Aux
 10037  		mem := l.Args[1]
 10038  		ptr := l.Args[0]
 10039  		if !(canMergeLoad(v, l) && clobber(l)) {
 10040  			break
 10041  		}
 10042  		v.reset(OpAMD64CMPWload)
 10043  		v.AuxInt = off
 10044  		v.Aux = sym
 10045  		v.AddArg(ptr)
 10046  		v.AddArg(x)
 10047  		v.AddArg(mem)
 10048  		return true
 10049  	}
 10050  	// match: (CMPW x l:(MOVWload {sym} [off] ptr mem))
 10051  	// cond: canMergeLoad(v, l) && clobber(l)
 10052  	// result: (InvertFlags (CMPWload {sym} [off] ptr x mem))
 10053  	for {
 10054  		_ = v.Args[1]
 10055  		x := v.Args[0]
 10056  		l := v.Args[1]
 10057  		if l.Op != OpAMD64MOVWload {
 10058  			break
 10059  		}
 10060  		off := l.AuxInt
 10061  		sym := l.Aux
 10062  		mem := l.Args[1]
 10063  		ptr := l.Args[0]
 10064  		if !(canMergeLoad(v, l) && clobber(l)) {
 10065  			break
 10066  		}
 10067  		v.reset(OpAMD64InvertFlags)
 10068  		v0 := b.NewValue0(l.Pos, OpAMD64CMPWload, types.TypeFlags)
 10069  		v0.AuxInt = off
 10070  		v0.Aux = sym
 10071  		v0.AddArg(ptr)
 10072  		v0.AddArg(x)
 10073  		v0.AddArg(mem)
 10074  		v.AddArg(v0)
 10075  		return true
 10076  	}
 10077  	return false
 10078  }
 10079  func rewriteValueAMD64_OpAMD64CMPWconst_0(v *Value) bool {
 10080  	b := v.Block
 10081  	// match: (CMPWconst (MOVLconst [x]) [y])
 10082  	// cond: int16(x)==int16(y)
 10083  	// result: (FlagEQ)
 10084  	for {
 10085  		y := v.AuxInt
 10086  		v_0 := v.Args[0]
 10087  		if v_0.Op != OpAMD64MOVLconst {
 10088  			break
 10089  		}
 10090  		x := v_0.AuxInt
 10091  		if !(int16(x) == int16(y)) {
 10092  			break
 10093  		}
 10094  		v.reset(OpAMD64FlagEQ)
 10095  		return true
 10096  	}
 10097  	// match: (CMPWconst (MOVLconst [x]) [y])
 10098  	// cond: int16(x)<int16(y) && uint16(x)<uint16(y)
 10099  	// result: (FlagLT_ULT)
 10100  	for {
 10101  		y := v.AuxInt
 10102  		v_0 := v.Args[0]
 10103  		if v_0.Op != OpAMD64MOVLconst {
 10104  			break
 10105  		}
 10106  		x := v_0.AuxInt
 10107  		if !(int16(x) < int16(y) && uint16(x) < uint16(y)) {
 10108  			break
 10109  		}
 10110  		v.reset(OpAMD64FlagLT_ULT)
 10111  		return true
 10112  	}
 10113  	// match: (CMPWconst (MOVLconst [x]) [y])
 10114  	// cond: int16(x)<int16(y) && uint16(x)>uint16(y)
 10115  	// result: (FlagLT_UGT)
 10116  	for {
 10117  		y := v.AuxInt
 10118  		v_0 := v.Args[0]
 10119  		if v_0.Op != OpAMD64MOVLconst {
 10120  			break
 10121  		}
 10122  		x := v_0.AuxInt
 10123  		if !(int16(x) < int16(y) && uint16(x) > uint16(y)) {
 10124  			break
 10125  		}
 10126  		v.reset(OpAMD64FlagLT_UGT)
 10127  		return true
 10128  	}
 10129  	// match: (CMPWconst (MOVLconst [x]) [y])
 10130  	// cond: int16(x)>int16(y) && uint16(x)<uint16(y)
 10131  	// result: (FlagGT_ULT)
 10132  	for {
 10133  		y := v.AuxInt
 10134  		v_0 := v.Args[0]
 10135  		if v_0.Op != OpAMD64MOVLconst {
 10136  			break
 10137  		}
 10138  		x := v_0.AuxInt
 10139  		if !(int16(x) > int16(y) && uint16(x) < uint16(y)) {
 10140  			break
 10141  		}
 10142  		v.reset(OpAMD64FlagGT_ULT)
 10143  		return true
 10144  	}
 10145  	// match: (CMPWconst (MOVLconst [x]) [y])
 10146  	// cond: int16(x)>int16(y) && uint16(x)>uint16(y)
 10147  	// result: (FlagGT_UGT)
 10148  	for {
 10149  		y := v.AuxInt
 10150  		v_0 := v.Args[0]
 10151  		if v_0.Op != OpAMD64MOVLconst {
 10152  			break
 10153  		}
 10154  		x := v_0.AuxInt
 10155  		if !(int16(x) > int16(y) && uint16(x) > uint16(y)) {
 10156  			break
 10157  		}
 10158  		v.reset(OpAMD64FlagGT_UGT)
 10159  		return true
 10160  	}
 10161  	// match: (CMPWconst (ANDLconst _ [m]) [n])
 10162  	// cond: 0 <= int16(m) && int16(m) < int16(n)
 10163  	// result: (FlagLT_ULT)
 10164  	for {
 10165  		n := v.AuxInt
 10166  		v_0 := v.Args[0]
 10167  		if v_0.Op != OpAMD64ANDLconst {
 10168  			break
 10169  		}
 10170  		m := v_0.AuxInt
 10171  		if !(0 <= int16(m) && int16(m) < int16(n)) {
 10172  			break
 10173  		}
 10174  		v.reset(OpAMD64FlagLT_ULT)
 10175  		return true
 10176  	}
 10177  	// match: (CMPWconst (ANDL x y) [0])
 10178  	// cond:
 10179  	// result: (TESTW x y)
 10180  	for {
 10181  		if v.AuxInt != 0 {
 10182  			break
 10183  		}
 10184  		v_0 := v.Args[0]
 10185  		if v_0.Op != OpAMD64ANDL {
 10186  			break
 10187  		}
 10188  		y := v_0.Args[1]
 10189  		x := v_0.Args[0]
 10190  		v.reset(OpAMD64TESTW)
 10191  		v.AddArg(x)
 10192  		v.AddArg(y)
 10193  		return true
 10194  	}
 10195  	// match: (CMPWconst (ANDLconst [c] x) [0])
 10196  	// cond:
 10197  	// result: (TESTWconst [int64(int16(c))] x)
 10198  	for {
 10199  		if v.AuxInt != 0 {
 10200  			break
 10201  		}
 10202  		v_0 := v.Args[0]
 10203  		if v_0.Op != OpAMD64ANDLconst {
 10204  			break
 10205  		}
 10206  		c := v_0.AuxInt
 10207  		x := v_0.Args[0]
 10208  		v.reset(OpAMD64TESTWconst)
 10209  		v.AuxInt = int64(int16(c))
 10210  		v.AddArg(x)
 10211  		return true
 10212  	}
 10213  	// match: (CMPWconst x [0])
 10214  	// cond:
 10215  	// result: (TESTW x x)
 10216  	for {
 10217  		if v.AuxInt != 0 {
 10218  			break
 10219  		}
 10220  		x := v.Args[0]
 10221  		v.reset(OpAMD64TESTW)
 10222  		v.AddArg(x)
 10223  		v.AddArg(x)
 10224  		return true
 10225  	}
 10226  	// match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c])
 10227  	// cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l)
 10228  	// result: @l.Block (CMPWconstload {sym} [makeValAndOff(c,off)] ptr mem)
 10229  	for {
 10230  		c := v.AuxInt
 10231  		l := v.Args[0]
 10232  		if l.Op != OpAMD64MOVWload {
 10233  			break
 10234  		}
 10235  		off := l.AuxInt
 10236  		sym := l.Aux
 10237  		mem := l.Args[1]
 10238  		ptr := l.Args[0]
 10239  		if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) {
 10240  			break
 10241  		}
 10242  		b = l.Block
 10243  		v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags)
 10244  		v.reset(OpCopy)
 10245  		v.AddArg(v0)
 10246  		v0.AuxInt = makeValAndOff(c, off)
 10247  		v0.Aux = sym
 10248  		v0.AddArg(ptr)
 10249  		v0.AddArg(mem)
 10250  		return true
 10251  	}
 10252  	return false
 10253  }
 10254  func rewriteValueAMD64_OpAMD64CMPWconstload_0(v *Value) bool {
 10255  	// match: (CMPWconstload [valoff1] {sym} (ADDQconst [off2] base) mem)
 10256  	// cond: ValAndOff(valoff1).canAdd(off2)
 10257  	// result: (CMPWconstload [ValAndOff(valoff1).add(off2)] {sym} base mem)
 10258  	for {
 10259  		valoff1 := v.AuxInt
 10260  		sym := v.Aux
 10261  		mem := v.Args[1]
 10262  		v_0 := v.Args[0]
 10263  		if v_0.Op != OpAMD64ADDQconst {
 10264  			break
 10265  		}
 10266  		off2 := v_0.AuxInt
 10267  		base := v_0.Args[0]
 10268  		if !(ValAndOff(valoff1).canAdd(off2)) {
 10269  			break
 10270  		}
 10271  		v.reset(OpAMD64CMPWconstload)
 10272  		v.AuxInt = ValAndOff(valoff1).add(off2)
 10273  		v.Aux = sym
 10274  		v.AddArg(base)
 10275  		v.AddArg(mem)
 10276  		return true
 10277  	}
 10278  	// match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
 10279  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)
 10280  	// result: (CMPWconstload [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
 10281  	for {
 10282  		valoff1 := v.AuxInt
 10283  		sym1 := v.Aux
 10284  		mem := v.Args[1]
 10285  		v_0 := v.Args[0]
 10286  		if v_0.Op != OpAMD64LEAQ {
 10287  			break
 10288  		}
 10289  		off2 := v_0.AuxInt
 10290  		sym2 := v_0.Aux
 10291  		base := v_0.Args[0]
 10292  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) {
 10293  			break
 10294  		}
 10295  		v.reset(OpAMD64CMPWconstload)
 10296  		v.AuxInt = ValAndOff(valoff1).add(off2)
 10297  		v.Aux = mergeSym(sym1, sym2)
 10298  		v.AddArg(base)
 10299  		v.AddArg(mem)
 10300  		return true
 10301  	}
 10302  	return false
 10303  }
 10304  func rewriteValueAMD64_OpAMD64CMPWload_0(v *Value) bool {
 10305  	// match: (CMPWload [off1] {sym} (ADDQconst [off2] base) val mem)
 10306  	// cond: is32Bit(off1+off2)
 10307  	// result: (CMPWload [off1+off2] {sym} base val mem)
 10308  	for {
 10309  		off1 := v.AuxInt
 10310  		sym := v.Aux
 10311  		mem := v.Args[2]
 10312  		v_0 := v.Args[0]
 10313  		if v_0.Op != OpAMD64ADDQconst {
 10314  			break
 10315  		}
 10316  		off2 := v_0.AuxInt
 10317  		base := v_0.Args[0]
 10318  		val := v.Args[1]
 10319  		if !(is32Bit(off1 + off2)) {
 10320  			break
 10321  		}
 10322  		v.reset(OpAMD64CMPWload)
 10323  		v.AuxInt = off1 + off2
 10324  		v.Aux = sym
 10325  		v.AddArg(base)
 10326  		v.AddArg(val)
 10327  		v.AddArg(mem)
 10328  		return true
 10329  	}
 10330  	// match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
 10331  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10332  	// result: (CMPWload [off1+off2] {mergeSym(sym1,sym2)} base val mem)
 10333  	for {
 10334  		off1 := v.AuxInt
 10335  		sym1 := v.Aux
 10336  		mem := v.Args[2]
 10337  		v_0 := v.Args[0]
 10338  		if v_0.Op != OpAMD64LEAQ {
 10339  			break
 10340  		}
 10341  		off2 := v_0.AuxInt
 10342  		sym2 := v_0.Aux
 10343  		base := v_0.Args[0]
 10344  		val := v.Args[1]
 10345  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10346  			break
 10347  		}
 10348  		v.reset(OpAMD64CMPWload)
 10349  		v.AuxInt = off1 + off2
 10350  		v.Aux = mergeSym(sym1, sym2)
 10351  		v.AddArg(base)
 10352  		v.AddArg(val)
 10353  		v.AddArg(mem)
 10354  		return true
 10355  	}
 10356  	// match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem)
 10357  	// cond: validValAndOff(int64(int16(c)),off)
 10358  	// result: (CMPWconstload {sym} [makeValAndOff(int64(int16(c)),off)] ptr mem)
 10359  	for {
 10360  		off := v.AuxInt
 10361  		sym := v.Aux
 10362  		mem := v.Args[2]
 10363  		ptr := v.Args[0]
 10364  		v_1 := v.Args[1]
 10365  		if v_1.Op != OpAMD64MOVLconst {
 10366  			break
 10367  		}
 10368  		c := v_1.AuxInt
 10369  		if !(validValAndOff(int64(int16(c)), off)) {
 10370  			break
 10371  		}
 10372  		v.reset(OpAMD64CMPWconstload)
 10373  		v.AuxInt = makeValAndOff(int64(int16(c)), off)
 10374  		v.Aux = sym
 10375  		v.AddArg(ptr)
 10376  		v.AddArg(mem)
 10377  		return true
 10378  	}
 10379  	return false
 10380  }
 10381  func rewriteValueAMD64_OpAMD64CMPXCHGLlock_0(v *Value) bool {
 10382  	// match: (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem)
 10383  	// cond: is32Bit(off1+off2)
 10384  	// result: (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem)
 10385  	for {
 10386  		off1 := v.AuxInt
 10387  		sym := v.Aux
 10388  		mem := v.Args[3]
 10389  		v_0 := v.Args[0]
 10390  		if v_0.Op != OpAMD64ADDQconst {
 10391  			break
 10392  		}
 10393  		off2 := v_0.AuxInt
 10394  		ptr := v_0.Args[0]
 10395  		old := v.Args[1]
 10396  		new_ := v.Args[2]
 10397  		if !(is32Bit(off1 + off2)) {
 10398  			break
 10399  		}
 10400  		v.reset(OpAMD64CMPXCHGLlock)
 10401  		v.AuxInt = off1 + off2
 10402  		v.Aux = sym
 10403  		v.AddArg(ptr)
 10404  		v.AddArg(old)
 10405  		v.AddArg(new_)
 10406  		v.AddArg(mem)
 10407  		return true
 10408  	}
 10409  	return false
 10410  }
 10411  func rewriteValueAMD64_OpAMD64CMPXCHGQlock_0(v *Value) bool {
 10412  	// match: (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem)
 10413  	// cond: is32Bit(off1+off2)
 10414  	// result: (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem)
 10415  	for {
 10416  		off1 := v.AuxInt
 10417  		sym := v.Aux
 10418  		mem := v.Args[3]
 10419  		v_0 := v.Args[0]
 10420  		if v_0.Op != OpAMD64ADDQconst {
 10421  			break
 10422  		}
 10423  		off2 := v_0.AuxInt
 10424  		ptr := v_0.Args[0]
 10425  		old := v.Args[1]
 10426  		new_ := v.Args[2]
 10427  		if !(is32Bit(off1 + off2)) {
 10428  			break
 10429  		}
 10430  		v.reset(OpAMD64CMPXCHGQlock)
 10431  		v.AuxInt = off1 + off2
 10432  		v.Aux = sym
 10433  		v.AddArg(ptr)
 10434  		v.AddArg(old)
 10435  		v.AddArg(new_)
 10436  		v.AddArg(mem)
 10437  		return true
 10438  	}
 10439  	return false
 10440  }
 10441  func rewriteValueAMD64_OpAMD64DIVSD_0(v *Value) bool {
 10442  	// match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem))
 10443  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
 10444  	// result: (DIVSDload x [off] {sym} ptr mem)
 10445  	for {
 10446  		_ = v.Args[1]
 10447  		x := v.Args[0]
 10448  		l := v.Args[1]
 10449  		if l.Op != OpAMD64MOVSDload {
 10450  			break
 10451  		}
 10452  		off := l.AuxInt
 10453  		sym := l.Aux
 10454  		mem := l.Args[1]
 10455  		ptr := l.Args[0]
 10456  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
 10457  			break
 10458  		}
 10459  		v.reset(OpAMD64DIVSDload)
 10460  		v.AuxInt = off
 10461  		v.Aux = sym
 10462  		v.AddArg(x)
 10463  		v.AddArg(ptr)
 10464  		v.AddArg(mem)
 10465  		return true
 10466  	}
 10467  	return false
 10468  }
 10469  func rewriteValueAMD64_OpAMD64DIVSDload_0(v *Value) bool {
 10470  	// match: (DIVSDload [off1] {sym} val (ADDQconst [off2] base) mem)
 10471  	// cond: is32Bit(off1+off2)
 10472  	// result: (DIVSDload [off1+off2] {sym} val base mem)
 10473  	for {
 10474  		off1 := v.AuxInt
 10475  		sym := v.Aux
 10476  		mem := v.Args[2]
 10477  		val := v.Args[0]
 10478  		v_1 := v.Args[1]
 10479  		if v_1.Op != OpAMD64ADDQconst {
 10480  			break
 10481  		}
 10482  		off2 := v_1.AuxInt
 10483  		base := v_1.Args[0]
 10484  		if !(is32Bit(off1 + off2)) {
 10485  			break
 10486  		}
 10487  		v.reset(OpAMD64DIVSDload)
 10488  		v.AuxInt = off1 + off2
 10489  		v.Aux = sym
 10490  		v.AddArg(val)
 10491  		v.AddArg(base)
 10492  		v.AddArg(mem)
 10493  		return true
 10494  	}
 10495  	// match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
 10496  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10497  	// result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
 10498  	for {
 10499  		off1 := v.AuxInt
 10500  		sym1 := v.Aux
 10501  		mem := v.Args[2]
 10502  		val := v.Args[0]
 10503  		v_1 := v.Args[1]
 10504  		if v_1.Op != OpAMD64LEAQ {
 10505  			break
 10506  		}
 10507  		off2 := v_1.AuxInt
 10508  		sym2 := v_1.Aux
 10509  		base := v_1.Args[0]
 10510  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10511  			break
 10512  		}
 10513  		v.reset(OpAMD64DIVSDload)
 10514  		v.AuxInt = off1 + off2
 10515  		v.Aux = mergeSym(sym1, sym2)
 10516  		v.AddArg(val)
 10517  		v.AddArg(base)
 10518  		v.AddArg(mem)
 10519  		return true
 10520  	}
 10521  	return false
 10522  }
 10523  func rewriteValueAMD64_OpAMD64DIVSS_0(v *Value) bool {
 10524  	// match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem))
 10525  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
 10526  	// result: (DIVSSload x [off] {sym} ptr mem)
 10527  	for {
 10528  		_ = v.Args[1]
 10529  		x := v.Args[0]
 10530  		l := v.Args[1]
 10531  		if l.Op != OpAMD64MOVSSload {
 10532  			break
 10533  		}
 10534  		off := l.AuxInt
 10535  		sym := l.Aux
 10536  		mem := l.Args[1]
 10537  		ptr := l.Args[0]
 10538  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
 10539  			break
 10540  		}
 10541  		v.reset(OpAMD64DIVSSload)
 10542  		v.AuxInt = off
 10543  		v.Aux = sym
 10544  		v.AddArg(x)
 10545  		v.AddArg(ptr)
 10546  		v.AddArg(mem)
 10547  		return true
 10548  	}
 10549  	return false
 10550  }
 10551  func rewriteValueAMD64_OpAMD64DIVSSload_0(v *Value) bool {
 10552  	// match: (DIVSSload [off1] {sym} val (ADDQconst [off2] base) mem)
 10553  	// cond: is32Bit(off1+off2)
 10554  	// result: (DIVSSload [off1+off2] {sym} val base mem)
 10555  	for {
 10556  		off1 := v.AuxInt
 10557  		sym := v.Aux
 10558  		mem := v.Args[2]
 10559  		val := v.Args[0]
 10560  		v_1 := v.Args[1]
 10561  		if v_1.Op != OpAMD64ADDQconst {
 10562  			break
 10563  		}
 10564  		off2 := v_1.AuxInt
 10565  		base := v_1.Args[0]
 10566  		if !(is32Bit(off1 + off2)) {
 10567  			break
 10568  		}
 10569  		v.reset(OpAMD64DIVSSload)
 10570  		v.AuxInt = off1 + off2
 10571  		v.Aux = sym
 10572  		v.AddArg(val)
 10573  		v.AddArg(base)
 10574  		v.AddArg(mem)
 10575  		return true
 10576  	}
 10577  	// match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
 10578  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10579  	// result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
 10580  	for {
 10581  		off1 := v.AuxInt
 10582  		sym1 := v.Aux
 10583  		mem := v.Args[2]
 10584  		val := v.Args[0]
 10585  		v_1 := v.Args[1]
 10586  		if v_1.Op != OpAMD64LEAQ {
 10587  			break
 10588  		}
 10589  		off2 := v_1.AuxInt
 10590  		sym2 := v_1.Aux
 10591  		base := v_1.Args[0]
 10592  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10593  			break
 10594  		}
 10595  		v.reset(OpAMD64DIVSSload)
 10596  		v.AuxInt = off1 + off2
 10597  		v.Aux = mergeSym(sym1, sym2)
 10598  		v.AddArg(val)
 10599  		v.AddArg(base)
 10600  		v.AddArg(mem)
 10601  		return true
 10602  	}
 10603  	return false
 10604  }
 10605  func rewriteValueAMD64_OpAMD64HMULL_0(v *Value) bool {
 10606  	// match: (HMULL x y)
 10607  	// cond: !x.rematerializeable() && y.rematerializeable()
 10608  	// result: (HMULL y x)
 10609  	for {
 10610  		y := v.Args[1]
 10611  		x := v.Args[0]
 10612  		if !(!x.rematerializeable() && y.rematerializeable()) {
 10613  			break
 10614  		}
 10615  		v.reset(OpAMD64HMULL)
 10616  		v.AddArg(y)
 10617  		v.AddArg(x)
 10618  		return true
 10619  	}
 10620  	return false
 10621  }
 10622  func rewriteValueAMD64_OpAMD64HMULLU_0(v *Value) bool {
 10623  	// match: (HMULLU x y)
 10624  	// cond: !x.rematerializeable() && y.rematerializeable()
 10625  	// result: (HMULLU y x)
 10626  	for {
 10627  		y := v.Args[1]
 10628  		x := v.Args[0]
 10629  		if !(!x.rematerializeable() && y.rematerializeable()) {
 10630  			break
 10631  		}
 10632  		v.reset(OpAMD64HMULLU)
 10633  		v.AddArg(y)
 10634  		v.AddArg(x)
 10635  		return true
 10636  	}
 10637  	return false
 10638  }
 10639  func rewriteValueAMD64_OpAMD64HMULQ_0(v *Value) bool {
 10640  	// match: (HMULQ x y)
 10641  	// cond: !x.rematerializeable() && y.rematerializeable()
 10642  	// result: (HMULQ y x)
 10643  	for {
 10644  		y := v.Args[1]
 10645  		x := v.Args[0]
 10646  		if !(!x.rematerializeable() && y.rematerializeable()) {
 10647  			break
 10648  		}
 10649  		v.reset(OpAMD64HMULQ)
 10650  		v.AddArg(y)
 10651  		v.AddArg(x)
 10652  		return true
 10653  	}
 10654  	return false
 10655  }
 10656  func rewriteValueAMD64_OpAMD64HMULQU_0(v *Value) bool {
 10657  	// match: (HMULQU x y)
 10658  	// cond: !x.rematerializeable() && y.rematerializeable()
 10659  	// result: (HMULQU y x)
 10660  	for {
 10661  		y := v.Args[1]
 10662  		x := v.Args[0]
 10663  		if !(!x.rematerializeable() && y.rematerializeable()) {
 10664  			break
 10665  		}
 10666  		v.reset(OpAMD64HMULQU)
 10667  		v.AddArg(y)
 10668  		v.AddArg(x)
 10669  		return true
 10670  	}
 10671  	return false
 10672  }
 10673  func rewriteValueAMD64_OpAMD64LEAL_0(v *Value) bool {
 10674  	// match: (LEAL [c] {s} (ADDLconst [d] x))
 10675  	// cond: is32Bit(c+d)
 10676  	// result: (LEAL [c+d] {s} x)
 10677  	for {
 10678  		c := v.AuxInt
 10679  		s := v.Aux
 10680  		v_0 := v.Args[0]
 10681  		if v_0.Op != OpAMD64ADDLconst {
 10682  			break
 10683  		}
 10684  		d := v_0.AuxInt
 10685  		x := v_0.Args[0]
 10686  		if !(is32Bit(c + d)) {
 10687  			break
 10688  		}
 10689  		v.reset(OpAMD64LEAL)
 10690  		v.AuxInt = c + d
 10691  		v.Aux = s
 10692  		v.AddArg(x)
 10693  		return true
 10694  	}
 10695  	// match: (LEAL [c] {s} (ADDL x y))
 10696  	// cond: x.Op != OpSB && y.Op != OpSB
 10697  	// result: (LEAL1 [c] {s} x y)
 10698  	for {
 10699  		c := v.AuxInt
 10700  		s := v.Aux
 10701  		v_0 := v.Args[0]
 10702  		if v_0.Op != OpAMD64ADDL {
 10703  			break
 10704  		}
 10705  		y := v_0.Args[1]
 10706  		x := v_0.Args[0]
 10707  		if !(x.Op != OpSB && y.Op != OpSB) {
 10708  			break
 10709  		}
 10710  		v.reset(OpAMD64LEAL1)
 10711  		v.AuxInt = c
 10712  		v.Aux = s
 10713  		v.AddArg(x)
 10714  		v.AddArg(y)
 10715  		return true
 10716  	}
 10717  	return false
 10718  }
 10719  func rewriteValueAMD64_OpAMD64LEAL1_0(v *Value) bool {
 10720  	// match: (LEAL1 [c] {s} (ADDLconst [d] x) y)
 10721  	// cond: is32Bit(c+d) && x.Op != OpSB
 10722  	// result: (LEAL1 [c+d] {s} x y)
 10723  	for {
 10724  		c := v.AuxInt
 10725  		s := v.Aux
 10726  		y := v.Args[1]
 10727  		v_0 := v.Args[0]
 10728  		if v_0.Op != OpAMD64ADDLconst {
 10729  			break
 10730  		}
 10731  		d := v_0.AuxInt
 10732  		x := v_0.Args[0]
 10733  		if !(is32Bit(c+d) && x.Op != OpSB) {
 10734  			break
 10735  		}
 10736  		v.reset(OpAMD64LEAL1)
 10737  		v.AuxInt = c + d
 10738  		v.Aux = s
 10739  		v.AddArg(x)
 10740  		v.AddArg(y)
 10741  		return true
 10742  	}
 10743  	// match: (LEAL1 [c] {s} y (ADDLconst [d] x))
 10744  	// cond: is32Bit(c+d) && x.Op != OpSB
 10745  	// result: (LEAL1 [c+d] {s} x y)
 10746  	for {
 10747  		c := v.AuxInt
 10748  		s := v.Aux
 10749  		_ = v.Args[1]
 10750  		y := v.Args[0]
 10751  		v_1 := v.Args[1]
 10752  		if v_1.Op != OpAMD64ADDLconst {
 10753  			break
 10754  		}
 10755  		d := v_1.AuxInt
 10756  		x := v_1.Args[0]
 10757  		if !(is32Bit(c+d) && x.Op != OpSB) {
 10758  			break
 10759  		}
 10760  		v.reset(OpAMD64LEAL1)
 10761  		v.AuxInt = c + d
 10762  		v.Aux = s
 10763  		v.AddArg(x)
 10764  		v.AddArg(y)
 10765  		return true
 10766  	}
 10767  	// match: (LEAL1 [c] {s} x (SHLLconst [1] y))
 10768  	// cond:
 10769  	// result: (LEAL2 [c] {s} x y)
 10770  	for {
 10771  		c := v.AuxInt
 10772  		s := v.Aux
 10773  		_ = v.Args[1]
 10774  		x := v.Args[0]
 10775  		v_1 := v.Args[1]
 10776  		if v_1.Op != OpAMD64SHLLconst {
 10777  			break
 10778  		}
 10779  		if v_1.AuxInt != 1 {
 10780  			break
 10781  		}
 10782  		y := v_1.Args[0]
 10783  		v.reset(OpAMD64LEAL2)
 10784  		v.AuxInt = c
 10785  		v.Aux = s
 10786  		v.AddArg(x)
 10787  		v.AddArg(y)
 10788  		return true
 10789  	}
 10790  	// match: (LEAL1 [c] {s} (SHLLconst [1] y) x)
 10791  	// cond:
 10792  	// result: (LEAL2 [c] {s} x y)
 10793  	for {
 10794  		c := v.AuxInt
 10795  		s := v.Aux
 10796  		x := v.Args[1]
 10797  		v_0 := v.Args[0]
 10798  		if v_0.Op != OpAMD64SHLLconst {
 10799  			break
 10800  		}
 10801  		if v_0.AuxInt != 1 {
 10802  			break
 10803  		}
 10804  		y := v_0.Args[0]
 10805  		v.reset(OpAMD64LEAL2)
 10806  		v.AuxInt = c
 10807  		v.Aux = s
 10808  		v.AddArg(x)
 10809  		v.AddArg(y)
 10810  		return true
 10811  	}
 10812  	// match: (LEAL1 [c] {s} x (SHLLconst [2] y))
 10813  	// cond:
 10814  	// result: (LEAL4 [c] {s} x y)
 10815  	for {
 10816  		c := v.AuxInt
 10817  		s := v.Aux
 10818  		_ = v.Args[1]
 10819  		x := v.Args[0]
 10820  		v_1 := v.Args[1]
 10821  		if v_1.Op != OpAMD64SHLLconst {
 10822  			break
 10823  		}
 10824  		if v_1.AuxInt != 2 {
 10825  			break
 10826  		}
 10827  		y := v_1.Args[0]
 10828  		v.reset(OpAMD64LEAL4)
 10829  		v.AuxInt = c
 10830  		v.Aux = s
 10831  		v.AddArg(x)
 10832  		v.AddArg(y)
 10833  		return true
 10834  	}
 10835  	// match: (LEAL1 [c] {s} (SHLLconst [2] y) x)
 10836  	// cond:
 10837  	// result: (LEAL4 [c] {s} x y)
 10838  	for {
 10839  		c := v.AuxInt
 10840  		s := v.Aux
 10841  		x := v.Args[1]
 10842  		v_0 := v.Args[0]
 10843  		if v_0.Op != OpAMD64SHLLconst {
 10844  			break
 10845  		}
 10846  		if v_0.AuxInt != 2 {
 10847  			break
 10848  		}
 10849  		y := v_0.Args[0]
 10850  		v.reset(OpAMD64LEAL4)
 10851  		v.AuxInt = c
 10852  		v.Aux = s
 10853  		v.AddArg(x)
 10854  		v.AddArg(y)
 10855  		return true
 10856  	}
 10857  	// match: (LEAL1 [c] {s} x (SHLLconst [3] y))
 10858  	// cond:
 10859  	// result: (LEAL8 [c] {s} x y)
 10860  	for {
 10861  		c := v.AuxInt
 10862  		s := v.Aux
 10863  		_ = v.Args[1]
 10864  		x := v.Args[0]
 10865  		v_1 := v.Args[1]
 10866  		if v_1.Op != OpAMD64SHLLconst {
 10867  			break
 10868  		}
 10869  		if v_1.AuxInt != 3 {
 10870  			break
 10871  		}
 10872  		y := v_1.Args[0]
 10873  		v.reset(OpAMD64LEAL8)
 10874  		v.AuxInt = c
 10875  		v.Aux = s
 10876  		v.AddArg(x)
 10877  		v.AddArg(y)
 10878  		return true
 10879  	}
 10880  	// match: (LEAL1 [c] {s} (SHLLconst [3] y) x)
 10881  	// cond:
 10882  	// result: (LEAL8 [c] {s} x y)
 10883  	for {
 10884  		c := v.AuxInt
 10885  		s := v.Aux
 10886  		x := v.Args[1]
 10887  		v_0 := v.Args[0]
 10888  		if v_0.Op != OpAMD64SHLLconst {
 10889  			break
 10890  		}
 10891  		if v_0.AuxInt != 3 {
 10892  			break
 10893  		}
 10894  		y := v_0.Args[0]
 10895  		v.reset(OpAMD64LEAL8)
 10896  		v.AuxInt = c
 10897  		v.Aux = s
 10898  		v.AddArg(x)
 10899  		v.AddArg(y)
 10900  		return true
 10901  	}
 10902  	return false
 10903  }
 10904  func rewriteValueAMD64_OpAMD64LEAL2_0(v *Value) bool {
 10905  	// match: (LEAL2 [c] {s} (ADDLconst [d] x) y)
 10906  	// cond: is32Bit(c+d) && x.Op != OpSB
 10907  	// result: (LEAL2 [c+d] {s} x y)
 10908  	for {
 10909  		c := v.AuxInt
 10910  		s := v.Aux
 10911  		y := v.Args[1]
 10912  		v_0 := v.Args[0]
 10913  		if v_0.Op != OpAMD64ADDLconst {
 10914  			break
 10915  		}
 10916  		d := v_0.AuxInt
 10917  		x := v_0.Args[0]
 10918  		if !(is32Bit(c+d) && x.Op != OpSB) {
 10919  			break
 10920  		}
 10921  		v.reset(OpAMD64LEAL2)
 10922  		v.AuxInt = c + d
 10923  		v.Aux = s
 10924  		v.AddArg(x)
 10925  		v.AddArg(y)
 10926  		return true
 10927  	}
 10928  	// match: (LEAL2 [c] {s} x (ADDLconst [d] y))
 10929  	// cond: is32Bit(c+2*d) && y.Op != OpSB
 10930  	// result: (LEAL2 [c+2*d] {s} x y)
 10931  	for {
 10932  		c := v.AuxInt
 10933  		s := v.Aux
 10934  		_ = v.Args[1]
 10935  		x := v.Args[0]
 10936  		v_1 := v.Args[1]
 10937  		if v_1.Op != OpAMD64ADDLconst {
 10938  			break
 10939  		}
 10940  		d := v_1.AuxInt
 10941  		y := v_1.Args[0]
 10942  		if !(is32Bit(c+2*d) && y.Op != OpSB) {
 10943  			break
 10944  		}
 10945  		v.reset(OpAMD64LEAL2)
 10946  		v.AuxInt = c + 2*d
 10947  		v.Aux = s
 10948  		v.AddArg(x)
 10949  		v.AddArg(y)
 10950  		return true
 10951  	}
 10952  	// match: (LEAL2 [c] {s} x (SHLLconst [1] y))
 10953  	// cond:
 10954  	// result: (LEAL4 [c] {s} x y)
 10955  	for {
 10956  		c := v.AuxInt
 10957  		s := v.Aux
 10958  		_ = v.Args[1]
 10959  		x := v.Args[0]
 10960  		v_1 := v.Args[1]
 10961  		if v_1.Op != OpAMD64SHLLconst {
 10962  			break
 10963  		}
 10964  		if v_1.AuxInt != 1 {
 10965  			break
 10966  		}
 10967  		y := v_1.Args[0]
 10968  		v.reset(OpAMD64LEAL4)
 10969  		v.AuxInt = c
 10970  		v.Aux = s
 10971  		v.AddArg(x)
 10972  		v.AddArg(y)
 10973  		return true
 10974  	}
 10975  	// match: (LEAL2 [c] {s} x (SHLLconst [2] y))
 10976  	// cond:
 10977  	// result: (LEAL8 [c] {s} x y)
 10978  	for {
 10979  		c := v.AuxInt
 10980  		s := v.Aux
 10981  		_ = v.Args[1]
 10982  		x := v.Args[0]
 10983  		v_1 := v.Args[1]
 10984  		if v_1.Op != OpAMD64SHLLconst {
 10985  			break
 10986  		}
 10987  		if v_1.AuxInt != 2 {
 10988  			break
 10989  		}
 10990  		y := v_1.Args[0]
 10991  		v.reset(OpAMD64LEAL8)
 10992  		v.AuxInt = c
 10993  		v.Aux = s
 10994  		v.AddArg(x)
 10995  		v.AddArg(y)
 10996  		return true
 10997  	}
 10998  	return false
 10999  }
 11000  func rewriteValueAMD64_OpAMD64LEAL4_0(v *Value) bool {
 11001  	// match: (LEAL4 [c] {s} (ADDLconst [d] x) y)
 11002  	// cond: is32Bit(c+d) && x.Op != OpSB
 11003  	// result: (LEAL4 [c+d] {s} x y)
 11004  	for {
 11005  		c := v.AuxInt
 11006  		s := v.Aux
 11007  		y := v.Args[1]
 11008  		v_0 := v.Args[0]
 11009  		if v_0.Op != OpAMD64ADDLconst {
 11010  			break
 11011  		}
 11012  		d := v_0.AuxInt
 11013  		x := v_0.Args[0]
 11014  		if !(is32Bit(c+d) && x.Op != OpSB) {
 11015  			break
 11016  		}
 11017  		v.reset(OpAMD64LEAL4)
 11018  		v.AuxInt = c + d
 11019  		v.Aux = s
 11020  		v.AddArg(x)
 11021  		v.AddArg(y)
 11022  		return true
 11023  	}
 11024  	// match: (LEAL4 [c] {s} x (ADDLconst [d] y))
 11025  	// cond: is32Bit(c+4*d) && y.Op != OpSB
 11026  	// result: (LEAL4 [c+4*d] {s} x y)
 11027  	for {
 11028  		c := v.AuxInt
 11029  		s := v.Aux
 11030  		_ = v.Args[1]
 11031  		x := v.Args[0]
 11032  		v_1 := v.Args[1]
 11033  		if v_1.Op != OpAMD64ADDLconst {
 11034  			break
 11035  		}
 11036  		d := v_1.AuxInt
 11037  		y := v_1.Args[0]
 11038  		if !(is32Bit(c+4*d) && y.Op != OpSB) {
 11039  			break
 11040  		}
 11041  		v.reset(OpAMD64LEAL4)
 11042  		v.AuxInt = c + 4*d
 11043  		v.Aux = s
 11044  		v.AddArg(x)
 11045  		v.AddArg(y)
 11046  		return true
 11047  	}
 11048  	// match: (LEAL4 [c] {s} x (SHLLconst [1] y))
 11049  	// cond:
 11050  	// result: (LEAL8 [c] {s} x y)
 11051  	for {
 11052  		c := v.AuxInt
 11053  		s := v.Aux
 11054  		_ = v.Args[1]
 11055  		x := v.Args[0]
 11056  		v_1 := v.Args[1]
 11057  		if v_1.Op != OpAMD64SHLLconst {
 11058  			break
 11059  		}
 11060  		if v_1.AuxInt != 1 {
 11061  			break
 11062  		}
 11063  		y := v_1.Args[0]
 11064  		v.reset(OpAMD64LEAL8)
 11065  		v.AuxInt = c
 11066  		v.Aux = s
 11067  		v.AddArg(x)
 11068  		v.AddArg(y)
 11069  		return true
 11070  	}
 11071  	return false
 11072  }
 11073  func rewriteValueAMD64_OpAMD64LEAL8_0(v *Value) bool {
 11074  	// match: (LEAL8 [c] {s} (ADDLconst [d] x) y)
 11075  	// cond: is32Bit(c+d) && x.Op != OpSB
 11076  	// result: (LEAL8 [c+d] {s} x y)
 11077  	for {
 11078  		c := v.AuxInt
 11079  		s := v.Aux
 11080  		y := v.Args[1]
 11081  		v_0 := v.Args[0]
 11082  		if v_0.Op != OpAMD64ADDLconst {
 11083  			break
 11084  		}
 11085  		d := v_0.AuxInt
 11086  		x := v_0.Args[0]
 11087  		if !(is32Bit(c+d) && x.Op != OpSB) {
 11088  			break
 11089  		}
 11090  		v.reset(OpAMD64LEAL8)
 11091  		v.AuxInt = c + d
 11092  		v.Aux = s
 11093  		v.AddArg(x)
 11094  		v.AddArg(y)
 11095  		return true
 11096  	}
 11097  	// match: (LEAL8 [c] {s} x (ADDLconst [d] y))
 11098  	// cond: is32Bit(c+8*d) && y.Op != OpSB
 11099  	// result: (LEAL8 [c+8*d] {s} x y)
 11100  	for {
 11101  		c := v.AuxInt
 11102  		s := v.Aux
 11103  		_ = v.Args[1]
 11104  		x := v.Args[0]
 11105  		v_1 := v.Args[1]
 11106  		if v_1.Op != OpAMD64ADDLconst {
 11107  			break
 11108  		}
 11109  		d := v_1.AuxInt
 11110  		y := v_1.Args[0]
 11111  		if !(is32Bit(c+8*d) && y.Op != OpSB) {
 11112  			break
 11113  		}
 11114  		v.reset(OpAMD64LEAL8)
 11115  		v.AuxInt = c + 8*d
 11116  		v.Aux = s
 11117  		v.AddArg(x)
 11118  		v.AddArg(y)
 11119  		return true
 11120  	}
 11121  	return false
 11122  }
 11123  func rewriteValueAMD64_OpAMD64LEAQ_0(v *Value) bool {
 11124  	// match: (LEAQ [c] {s} (ADDQconst [d] x))
 11125  	// cond: is32Bit(c+d)
 11126  	// result: (LEAQ [c+d] {s} x)
 11127  	for {
 11128  		c := v.AuxInt
 11129  		s := v.Aux
 11130  		v_0 := v.Args[0]
 11131  		if v_0.Op != OpAMD64ADDQconst {
 11132  			break
 11133  		}
 11134  		d := v_0.AuxInt
 11135  		x := v_0.Args[0]
 11136  		if !(is32Bit(c + d)) {
 11137  			break
 11138  		}
 11139  		v.reset(OpAMD64LEAQ)
 11140  		v.AuxInt = c + d
 11141  		v.Aux = s
 11142  		v.AddArg(x)
 11143  		return true
 11144  	}
 11145  	// match: (LEAQ [c] {s} (ADDQ x y))
 11146  	// cond: x.Op != OpSB && y.Op != OpSB
 11147  	// result: (LEAQ1 [c] {s} x y)
 11148  	for {
 11149  		c := v.AuxInt
 11150  		s := v.Aux
 11151  		v_0 := v.Args[0]
 11152  		if v_0.Op != OpAMD64ADDQ {
 11153  			break
 11154  		}
 11155  		y := v_0.Args[1]
 11156  		x := v_0.Args[0]
 11157  		if !(x.Op != OpSB && y.Op != OpSB) {
 11158  			break
 11159  		}
 11160  		v.reset(OpAMD64LEAQ1)
 11161  		v.AuxInt = c
 11162  		v.Aux = s
 11163  		v.AddArg(x)
 11164  		v.AddArg(y)
 11165  		return true
 11166  	}
 11167  	// match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x))
 11168  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 11169  	// result: (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x)
 11170  	for {
 11171  		off1 := v.AuxInt
 11172  		sym1 := v.Aux
 11173  		v_0 := v.Args[0]
 11174  		if v_0.Op != OpAMD64LEAQ {
 11175  			break
 11176  		}
 11177  		off2 := v_0.AuxInt
 11178  		sym2 := v_0.Aux
 11179  		x := v_0.Args[0]
 11180  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 11181  			break
 11182  		}
 11183  		v.reset(OpAMD64LEAQ)
 11184  		v.AuxInt = off1 + off2
 11185  		v.Aux = mergeSym(sym1, sym2)
 11186  		v.AddArg(x)
 11187  		return true
 11188  	}
 11189  	// match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y))
 11190  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 11191  	// result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y)
 11192  	for {
 11193  		off1 := v.AuxInt
 11194  		sym1 := v.Aux
 11195  		v_0 := v.Args[0]
 11196  		if v_0.Op != OpAMD64LEAQ1 {
 11197  			break
 11198  		}
 11199  		off2 := v_0.AuxInt
 11200  		sym2 := v_0.Aux
 11201  		y := v_0.Args[1]
 11202  		x := v_0.Args[0]
 11203  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 11204  			break
 11205  		}
 11206  		v.reset(OpAMD64LEAQ1)
 11207  		v.AuxInt = off1 + off2
 11208  		v.Aux = mergeSym(sym1, sym2)
 11209  		v.AddArg(x)
 11210  		v.AddArg(y)
 11211  		return true
 11212  	}
 11213  	// match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y))
 11214  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 11215  	// result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y)
 11216  	for {
 11217  		off1 := v.AuxInt
 11218  		sym1 := v.Aux
 11219  		v_0 := v.Args[0]
 11220  		if v_0.Op != OpAMD64LEAQ2 {
 11221  			break
 11222  		}
 11223  		off2 := v_0.AuxInt
 11224  		sym2 := v_0.Aux
 11225  		y := v_0.Args[1]
 11226  		x := v_0.Args[0]
 11227  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 11228  			break
 11229  		}
 11230  		v.reset(OpAMD64LEAQ2)
 11231  		v.AuxInt = off1 + off2
 11232  		v.Aux = mergeSym(sym1, sym2)
 11233  		v.AddArg(x)
 11234  		v.AddArg(y)
 11235  		return true
 11236  	}
 11237  	// match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y))
 11238  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 11239  	// result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y)
 11240  	for {
 11241  		off1 := v.AuxInt
 11242  		sym1 := v.Aux
 11243  		v_0 := v.Args[0]
 11244  		if v_0.Op != OpAMD64LEAQ4 {
 11245  			break
 11246  		}
 11247  		off2 := v_0.AuxInt
 11248  		sym2 := v_0.Aux
 11249  		y := v_0.Args[1]
 11250  		x := v_0.Args[0]
 11251  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 11252  			break
 11253  		}
 11254  		v.reset(OpAMD64LEAQ4)
 11255  		v.AuxInt = off1 + off2
 11256  		v.Aux = mergeSym(sym1, sym2)
 11257  		v.AddArg(x)
 11258  		v.AddArg(y)
 11259  		return true
 11260  	}
 11261  	// match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y))
 11262  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 11263  	// result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y)
 11264  	for {
 11265  		off1 := v.AuxInt
 11266  		sym1 := v.Aux
 11267  		v_0 := v.Args[0]
 11268  		if v_0.Op != OpAMD64LEAQ8 {
 11269  			break
 11270  		}
 11271  		off2 := v_0.AuxInt
 11272  		sym2 := v_0.Aux
 11273  		y := v_0.Args[1]
 11274  		x := v_0.Args[0]
 11275  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 11276  			break
 11277  		}
 11278  		v.reset(OpAMD64LEAQ8)
 11279  		v.AuxInt = off1 + off2
 11280  		v.Aux = mergeSym(sym1, sym2)
 11281  		v.AddArg(x)
 11282  		v.AddArg(y)
 11283  		return true
 11284  	}
 11285  	return false
 11286  }
 11287  func rewriteValueAMD64_OpAMD64LEAQ1_0(v *Value) bool {
 11288  	// match: (LEAQ1 [c] {s} (ADDQconst [d] x) y)
 11289  	// cond: is32Bit(c+d) && x.Op != OpSB
 11290  	// result: (LEAQ1 [c+d] {s} x y)
 11291  	for {
 11292  		c := v.AuxInt
 11293  		s := v.Aux
 11294  		y := v.Args[1]
 11295  		v_0 := v.Args[0]
 11296  		if v_0.Op != OpAMD64ADDQconst {
 11297  			break
 11298  		}
 11299  		d := v_0.AuxInt
 11300  		x := v_0.Args[0]
 11301  		if !(is32Bit(c+d) && x.Op != OpSB) {
 11302  			break
 11303  		}
 11304  		v.reset(OpAMD64LEAQ1)
 11305  		v.AuxInt = c + d
 11306  		v.Aux = s
 11307  		v.AddArg(x)
 11308  		v.AddArg(y)
 11309  		return true
 11310  	}
 11311  	// match: (LEAQ1 [c] {s} y (ADDQconst [d] x))
 11312  	// cond: is32Bit(c+d) && x.Op != OpSB
 11313  	// result: (LEAQ1 [c+d] {s} x y)
 11314  	for {
 11315  		c := v.AuxInt
 11316  		s := v.Aux
 11317  		_ = v.Args[1]
 11318  		y := v.Args[0]
 11319  		v_1 := v.Args[1]
 11320  		if v_1.Op != OpAMD64ADDQconst {
 11321  			break
 11322  		}
 11323  		d := v_1.AuxInt
 11324  		x := v_1.Args[0]
 11325  		if !(is32Bit(c+d) && x.Op != OpSB) {
 11326  			break
 11327  		}
 11328  		v.reset(OpAMD64LEAQ1)
 11329  		v.AuxInt = c + d
 11330  		v.Aux = s
 11331  		v.AddArg(x)
 11332  		v.AddArg(y)
 11333  		return true
 11334  	}
 11335  	// match: (LEAQ1 [c] {s} x (SHLQconst [1] y))
 11336  	// cond:
 11337  	// result: (LEAQ2 [c] {s} x y)
 11338  	for {
 11339  		c := v.AuxInt
 11340  		s := v.Aux
 11341  		_ = v.Args[1]
 11342  		x := v.Args[0]
 11343  		v_1 := v.Args[1]
 11344  		if v_1.Op != OpAMD64SHLQconst {
 11345  			break
 11346  		}
 11347  		if v_1.AuxInt != 1 {
 11348  			break
 11349  		}
 11350  		y := v_1.Args[0]
 11351  		v.reset(OpAMD64LEAQ2)
 11352  		v.AuxInt = c
 11353  		v.Aux = s
 11354  		v.AddArg(x)
 11355  		v.AddArg(y)
 11356  		return true
 11357  	}
 11358  	// match: (LEAQ1 [c] {s} (SHLQconst [1] y) x)
 11359  	// cond:
 11360  	// result: (LEAQ2 [c] {s} x y)
 11361  	for {
 11362  		c := v.AuxInt
 11363  		s := v.Aux
 11364  		x := v.Args[1]
 11365  		v_0 := v.Args[0]
 11366  		if v_0.Op != OpAMD64SHLQconst {
 11367  			break
 11368  		}
 11369  		if v_0.AuxInt != 1 {
 11370  			break
 11371  		}
 11372  		y := v_0.Args[0]
 11373  		v.reset(OpAMD64LEAQ2)
 11374  		v.AuxInt = c
 11375  		v.Aux = s
 11376  		v.AddArg(x)
 11377  		v.AddArg(y)
 11378  		return true
 11379  	}
 11380  	// match: (LEAQ1 [c] {s} x (SHLQconst [2] y))
 11381  	// cond:
 11382  	// result: (LEAQ4 [c] {s} x y)
 11383  	for {
 11384  		c := v.AuxInt
 11385  		s := v.Aux
 11386  		_ = v.Args[1]
 11387  		x := v.Args[0]
 11388  		v_1 := v.Args[1]
 11389  		if v_1.Op != OpAMD64SHLQconst {
 11390  			break
 11391  		}
 11392  		if v_1.AuxInt != 2 {
 11393  			break
 11394  		}
 11395  		y := v_1.Args[0]
 11396  		v.reset(OpAMD64LEAQ4)
 11397  		v.AuxInt = c
 11398  		v.Aux = s
 11399  		v.AddArg(x)
 11400  		v.AddArg(y)
 11401  		return true
 11402  	}
 11403  	// match: (LEAQ1 [c] {s} (SHLQconst [2] y) x)
 11404  	// cond:
 11405  	// result: (LEAQ4 [c] {s} x y)
 11406  	for {
 11407  		c := v.AuxInt
 11408  		s := v.Aux
 11409  		x := v.Args[1]
 11410  		v_0 := v.Args[0]
 11411  		if v_0.Op != OpAMD64SHLQconst {
 11412  			break
 11413  		}
 11414  		if v_0.AuxInt != 2 {
 11415  			break
 11416  		}
 11417  		y := v_0.Args[0]
 11418  		v.reset(OpAMD64LEAQ4)
 11419  		v.AuxInt = c
 11420  		v.Aux = s
 11421  		v.AddArg(x)
 11422  		v.AddArg(y)
 11423  		return true
 11424  	}
 11425  	// match: (LEAQ1 [c] {s} x (SHLQconst [3] y))
 11426  	// cond:
 11427  	// result: (LEAQ8 [c] {s} x y)
 11428  	for {
 11429  		c := v.AuxInt
 11430  		s := v.Aux
 11431  		_ = v.Args[1]
 11432  		x := v.Args[0]
 11433  		v_1 := v.Args[1]
 11434  		if v_1.Op != OpAMD64SHLQconst {
 11435  			break
 11436  		}
 11437  		if v_1.AuxInt != 3 {
 11438  			break
 11439  		}
 11440  		y := v_1.Args[0]
 11441  		v.reset(OpAMD64LEAQ8)
 11442  		v.AuxInt = c
 11443  		v.Aux = s
 11444  		v.AddArg(x)
 11445  		v.AddArg(y)
 11446  		return true
 11447  	}
 11448  	// match: (LEAQ1 [c] {s} (SHLQconst [3] y) x)
 11449  	// cond:
 11450  	// result: (LEAQ8 [c] {s} x y)
 11451  	for {
 11452  		c := v.AuxInt
 11453  		s := v.Aux
 11454  		x := v.Args[1]
 11455  		v_0 := v.Args[0]
 11456  		if v_0.Op != OpAMD64SHLQconst {
 11457  			break
 11458  		}
 11459  		if v_0.AuxInt != 3 {
 11460  			break
 11461  		}
 11462  		y := v_0.Args[0]
 11463  		v.reset(OpAMD64LEAQ8)
 11464  		v.AuxInt = c
 11465  		v.Aux = s
 11466  		v.AddArg(x)
 11467  		v.AddArg(y)
 11468  		return true
 11469  	}
 11470  	// match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y)
 11471  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
 11472  	// result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y)
 11473  	for {
 11474  		off1 := v.AuxInt
 11475  		sym1 := v.Aux
 11476  		y := v.Args[1]
 11477  		v_0 := v.Args[0]
 11478  		if v_0.Op != OpAMD64LEAQ {
 11479  			break
 11480  		}
 11481  		off2 := v_0.AuxInt
 11482  		sym2 := v_0.Aux
 11483  		x := v_0.Args[0]
 11484  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
 11485  			break
 11486  		}
 11487  		v.reset(OpAMD64LEAQ1)
 11488  		v.AuxInt = off1 + off2
 11489  		v.Aux = mergeSym(sym1, sym2)
 11490  		v.AddArg(x)
 11491  		v.AddArg(y)
 11492  		return true
 11493  	}
 11494  	// match: (LEAQ1 [off1] {sym1} y (LEAQ [off2] {sym2} x))
 11495  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
 11496  	// result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y)
 11497  	for {
 11498  		off1 := v.AuxInt
 11499  		sym1 := v.Aux
 11500  		_ = v.Args[1]
 11501  		y := v.Args[0]
 11502  		v_1 := v.Args[1]
 11503  		if v_1.Op != OpAMD64LEAQ {
 11504  			break
 11505  		}
 11506  		off2 := v_1.AuxInt
 11507  		sym2 := v_1.Aux
 11508  		x := v_1.Args[0]
 11509  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
 11510  			break
 11511  		}
 11512  		v.reset(OpAMD64LEAQ1)
 11513  		v.AuxInt = off1 + off2
 11514  		v.Aux = mergeSym(sym1, sym2)
 11515  		v.AddArg(x)
 11516  		v.AddArg(y)
 11517  		return true
 11518  	}
 11519  	return false
 11520  }
 11521  func rewriteValueAMD64_OpAMD64LEAQ2_0(v *Value) bool {
 11522  	// match: (LEAQ2 [c] {s} (ADDQconst [d] x) y)
 11523  	// cond: is32Bit(c+d) && x.Op != OpSB
 11524  	// result: (LEAQ2 [c+d] {s} x y)
 11525  	for {
 11526  		c := v.AuxInt
 11527  		s := v.Aux
 11528  		y := v.Args[1]
 11529  		v_0 := v.Args[0]
 11530  		if v_0.Op != OpAMD64ADDQconst {
 11531  			break
 11532  		}
 11533  		d := v_0.AuxInt
 11534  		x := v_0.Args[0]
 11535  		if !(is32Bit(c+d) && x.Op != OpSB) {
 11536  			break
 11537  		}
 11538  		v.reset(OpAMD64LEAQ2)
 11539  		v.AuxInt = c + d
 11540  		v.Aux = s
 11541  		v.AddArg(x)
 11542  		v.AddArg(y)
 11543  		return true
 11544  	}
 11545  	// match: (LEAQ2 [c] {s} x (ADDQconst [d] y))
 11546  	// cond: is32Bit(c+2*d) && y.Op != OpSB
 11547  	// result: (LEAQ2 [c+2*d] {s} x y)
 11548  	for {
 11549  		c := v.AuxInt
 11550  		s := v.Aux
 11551  		_ = v.Args[1]
 11552  		x := v.Args[0]
 11553  		v_1 := v.Args[1]
 11554  		if v_1.Op != OpAMD64ADDQconst {
 11555  			break
 11556  		}
 11557  		d := v_1.AuxInt
 11558  		y := v_1.Args[0]
 11559  		if !(is32Bit(c+2*d) && y.Op != OpSB) {
 11560  			break
 11561  		}
 11562  		v.reset(OpAMD64LEAQ2)
 11563  		v.AuxInt = c + 2*d
 11564  		v.Aux = s
 11565  		v.AddArg(x)
 11566  		v.AddArg(y)
 11567  		return true
 11568  	}
 11569  	// match: (LEAQ2 [c] {s} x (SHLQconst [1] y))
 11570  	// cond:
 11571  	// result: (LEAQ4 [c] {s} x y)
 11572  	for {
 11573  		c := v.AuxInt
 11574  		s := v.Aux
 11575  		_ = v.Args[1]
 11576  		x := v.Args[0]
 11577  		v_1 := v.Args[1]
 11578  		if v_1.Op != OpAMD64SHLQconst {
 11579  			break
 11580  		}
 11581  		if v_1.AuxInt != 1 {
 11582  			break
 11583  		}
 11584  		y := v_1.Args[0]
 11585  		v.reset(OpAMD64LEAQ4)
 11586  		v.AuxInt = c
 11587  		v.Aux = s
 11588  		v.AddArg(x)
 11589  		v.AddArg(y)
 11590  		return true
 11591  	}
 11592  	// match: (LEAQ2 [c] {s} x (SHLQconst [2] y))
 11593  	// cond:
 11594  	// result: (LEAQ8 [c] {s} x y)
 11595  	for {
 11596  		c := v.AuxInt
 11597  		s := v.Aux
 11598  		_ = v.Args[1]
 11599  		x := v.Args[0]
 11600  		v_1 := v.Args[1]
 11601  		if v_1.Op != OpAMD64SHLQconst {
 11602  			break
 11603  		}
 11604  		if v_1.AuxInt != 2 {
 11605  			break
 11606  		}
 11607  		y := v_1.Args[0]
 11608  		v.reset(OpAMD64LEAQ8)
 11609  		v.AuxInt = c
 11610  		v.Aux = s
 11611  		v.AddArg(x)
 11612  		v.AddArg(y)
 11613  		return true
 11614  	}
 11615  	// match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y)
 11616  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
 11617  	// result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y)
 11618  	for {
 11619  		off1 := v.AuxInt
 11620  		sym1 := v.Aux
 11621  		y := v.Args[1]
 11622  		v_0 := v.Args[0]
 11623  		if v_0.Op != OpAMD64LEAQ {
 11624  			break
 11625  		}
 11626  		off2 := v_0.AuxInt
 11627  		sym2 := v_0.Aux
 11628  		x := v_0.Args[0]
 11629  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
 11630  			break
 11631  		}
 11632  		v.reset(OpAMD64LEAQ2)
 11633  		v.AuxInt = off1 + off2
 11634  		v.Aux = mergeSym(sym1, sym2)
 11635  		v.AddArg(x)
 11636  		v.AddArg(y)
 11637  		return true
 11638  	}
 11639  	return false
 11640  }
 11641  func rewriteValueAMD64_OpAMD64LEAQ4_0(v *Value) bool {
 11642  	// match: (LEAQ4 [c] {s} (ADDQconst [d] x) y)
 11643  	// cond: is32Bit(c+d) && x.Op != OpSB
 11644  	// result: (LEAQ4 [c+d] {s} x y)
 11645  	for {
 11646  		c := v.AuxInt
 11647  		s := v.Aux
 11648  		y := v.Args[1]
 11649  		v_0 := v.Args[0]
 11650  		if v_0.Op != OpAMD64ADDQconst {
 11651  			break
 11652  		}
 11653  		d := v_0.AuxInt
 11654  		x := v_0.Args[0]
 11655  		if !(is32Bit(c+d) && x.Op != OpSB) {
 11656  			break
 11657  		}
 11658  		v.reset(OpAMD64LEAQ4)
 11659  		v.AuxInt = c + d
 11660  		v.Aux = s
 11661  		v.AddArg(x)
 11662  		v.AddArg(y)
 11663  		return true
 11664  	}
 11665  	// match: (LEAQ4 [c] {s} x (ADDQconst [d] y))
 11666  	// cond: is32Bit(c+4*d) && y.Op != OpSB
 11667  	// result: (LEAQ4 [c+4*d] {s} x y)
 11668  	for {
 11669  		c := v.AuxInt
 11670  		s := v.Aux
 11671  		_ = v.Args[1]
 11672  		x := v.Args[0]
 11673  		v_1 := v.Args[1]
 11674  		if v_1.Op != OpAMD64ADDQconst {
 11675  			break
 11676  		}
 11677  		d := v_1.AuxInt
 11678  		y := v_1.Args[0]
 11679  		if !(is32Bit(c+4*d) && y.Op != OpSB) {
 11680  			break
 11681  		}
 11682  		v.reset(OpAMD64LEAQ4)
 11683  		v.AuxInt = c + 4*d
 11684  		v.Aux = s
 11685  		v.AddArg(x)
 11686  		v.AddArg(y)
 11687  		return true
 11688  	}
 11689  	// match: (LEAQ4 [c] {s} x (SHLQconst [1] y))
 11690  	// cond:
 11691  	// result: (LEAQ8 [c] {s} x y)
 11692  	for {
 11693  		c := v.AuxInt
 11694  		s := v.Aux
 11695  		_ = v.Args[1]
 11696  		x := v.Args[0]
 11697  		v_1 := v.Args[1]
 11698  		if v_1.Op != OpAMD64SHLQconst {
 11699  			break
 11700  		}
 11701  		if v_1.AuxInt != 1 {
 11702  			break
 11703  		}
 11704  		y := v_1.Args[0]
 11705  		v.reset(OpAMD64LEAQ8)
 11706  		v.AuxInt = c
 11707  		v.Aux = s
 11708  		v.AddArg(x)
 11709  		v.AddArg(y)
 11710  		return true
 11711  	}
 11712  	// match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y)
 11713  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
 11714  	// result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y)
 11715  	for {
 11716  		off1 := v.AuxInt
 11717  		sym1 := v.Aux
 11718  		y := v.Args[1]
 11719  		v_0 := v.Args[0]
 11720  		if v_0.Op != OpAMD64LEAQ {
 11721  			break
 11722  		}
 11723  		off2 := v_0.AuxInt
 11724  		sym2 := v_0.Aux
 11725  		x := v_0.Args[0]
 11726  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
 11727  			break
 11728  		}
 11729  		v.reset(OpAMD64LEAQ4)
 11730  		v.AuxInt = off1 + off2
 11731  		v.Aux = mergeSym(sym1, sym2)
 11732  		v.AddArg(x)
 11733  		v.AddArg(y)
 11734  		return true
 11735  	}
 11736  	return false
 11737  }
 11738  func rewriteValueAMD64_OpAMD64LEAQ8_0(v *Value) bool {
 11739  	// match: (LEAQ8 [c] {s} (ADDQconst [d] x) y)
 11740  	// cond: is32Bit(c+d) && x.Op != OpSB
 11741  	// result: (LEAQ8 [c+d] {s} x y)
 11742  	for {
 11743  		c := v.AuxInt
 11744  		s := v.Aux
 11745  		y := v.Args[1]
 11746  		v_0 := v.Args[0]
 11747  		if v_0.Op != OpAMD64ADDQconst {
 11748  			break
 11749  		}
 11750  		d := v_0.AuxInt
 11751  		x := v_0.Args[0]
 11752  		if !(is32Bit(c+d) && x.Op != OpSB) {
 11753  			break
 11754  		}
 11755  		v.reset(OpAMD64LEAQ8)
 11756  		v.AuxInt = c + d
 11757  		v.Aux = s
 11758  		v.AddArg(x)
 11759  		v.AddArg(y)
 11760  		return true
 11761  	}
 11762  	// match: (LEAQ8 [c] {s} x (ADDQconst [d] y))
 11763  	// cond: is32Bit(c+8*d) && y.Op != OpSB
 11764  	// result: (LEAQ8 [c+8*d] {s} x y)
 11765  	for {
 11766  		c := v.AuxInt
 11767  		s := v.Aux
 11768  		_ = v.Args[1]
 11769  		x := v.Args[0]
 11770  		v_1 := v.Args[1]
 11771  		if v_1.Op != OpAMD64ADDQconst {
 11772  			break
 11773  		}
 11774  		d := v_1.AuxInt
 11775  		y := v_1.Args[0]
 11776  		if !(is32Bit(c+8*d) && y.Op != OpSB) {
 11777  			break
 11778  		}
 11779  		v.reset(OpAMD64LEAQ8)
 11780  		v.AuxInt = c + 8*d
 11781  		v.Aux = s
 11782  		v.AddArg(x)
 11783  		v.AddArg(y)
 11784  		return true
 11785  	}
 11786  	// match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y)
 11787  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
 11788  	// result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y)
 11789  	for {
 11790  		off1 := v.AuxInt
 11791  		sym1 := v.Aux
 11792  		y := v.Args[1]
 11793  		v_0 := v.Args[0]
 11794  		if v_0.Op != OpAMD64LEAQ {
 11795  			break
 11796  		}
 11797  		off2 := v_0.AuxInt
 11798  		sym2 := v_0.Aux
 11799  		x := v_0.Args[0]
 11800  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
 11801  			break
 11802  		}
 11803  		v.reset(OpAMD64LEAQ8)
 11804  		v.AuxInt = off1 + off2
 11805  		v.Aux = mergeSym(sym1, sym2)
 11806  		v.AddArg(x)
 11807  		v.AddArg(y)
 11808  		return true
 11809  	}
 11810  	return false
 11811  }
 11812  func rewriteValueAMD64_OpAMD64MOVBQSX_0(v *Value) bool {
 11813  	b := v.Block
 11814  	// match: (MOVBQSX x:(MOVBload [off] {sym} ptr mem))
 11815  	// cond: x.Uses == 1 && clobber(x)
 11816  	// result: @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
 11817  	for {
 11818  		x := v.Args[0]
 11819  		if x.Op != OpAMD64MOVBload {
 11820  			break
 11821  		}
 11822  		off := x.AuxInt
 11823  		sym := x.Aux
 11824  		mem := x.Args[1]
 11825  		ptr := x.Args[0]
 11826  		if !(x.Uses == 1 && clobber(x)) {
 11827  			break
 11828  		}
 11829  		b = x.Block
 11830  		v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type)
 11831  		v.reset(OpCopy)
 11832  		v.AddArg(v0)
 11833  		v0.AuxInt = off
 11834  		v0.Aux = sym
 11835  		v0.AddArg(ptr)
 11836  		v0.AddArg(mem)
 11837  		return true
 11838  	}
 11839  	// match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem))
 11840  	// cond: x.Uses == 1 && clobber(x)
 11841  	// result: @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
 11842  	for {
 11843  		x := v.Args[0]
 11844  		if x.Op != OpAMD64MOVWload {
 11845  			break
 11846  		}
 11847  		off := x.AuxInt
 11848  		sym := x.Aux
 11849  		mem := x.Args[1]
 11850  		ptr := x.Args[0]
 11851  		if !(x.Uses == 1 && clobber(x)) {
 11852  			break
 11853  		}
 11854  		b = x.Block
 11855  		v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type)
 11856  		v.reset(OpCopy)
 11857  		v.AddArg(v0)
 11858  		v0.AuxInt = off
 11859  		v0.Aux = sym
 11860  		v0.AddArg(ptr)
 11861  		v0.AddArg(mem)
 11862  		return true
 11863  	}
 11864  	// match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem))
 11865  	// cond: x.Uses == 1 && clobber(x)
 11866  	// result: @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
 11867  	for {
 11868  		x := v.Args[0]
 11869  		if x.Op != OpAMD64MOVLload {
 11870  			break
 11871  		}
 11872  		off := x.AuxInt
 11873  		sym := x.Aux
 11874  		mem := x.Args[1]
 11875  		ptr := x.Args[0]
 11876  		if !(x.Uses == 1 && clobber(x)) {
 11877  			break
 11878  		}
 11879  		b = x.Block
 11880  		v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type)
 11881  		v.reset(OpCopy)
 11882  		v.AddArg(v0)
 11883  		v0.AuxInt = off
 11884  		v0.Aux = sym
 11885  		v0.AddArg(ptr)
 11886  		v0.AddArg(mem)
 11887  		return true
 11888  	}
 11889  	// match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem))
 11890  	// cond: x.Uses == 1 && clobber(x)
 11891  	// result: @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
 11892  	for {
 11893  		x := v.Args[0]
 11894  		if x.Op != OpAMD64MOVQload {
 11895  			break
 11896  		}
 11897  		off := x.AuxInt
 11898  		sym := x.Aux
 11899  		mem := x.Args[1]
 11900  		ptr := x.Args[0]
 11901  		if !(x.Uses == 1 && clobber(x)) {
 11902  			break
 11903  		}
 11904  		b = x.Block
 11905  		v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type)
 11906  		v.reset(OpCopy)
 11907  		v.AddArg(v0)
 11908  		v0.AuxInt = off
 11909  		v0.Aux = sym
 11910  		v0.AddArg(ptr)
 11911  		v0.AddArg(mem)
 11912  		return true
 11913  	}
 11914  	// match: (MOVBQSX (ANDLconst [c] x))
 11915  	// cond: c & 0x80 == 0
 11916  	// result: (ANDLconst [c & 0x7f] x)
 11917  	for {
 11918  		v_0 := v.Args[0]
 11919  		if v_0.Op != OpAMD64ANDLconst {
 11920  			break
 11921  		}
 11922  		c := v_0.AuxInt
 11923  		x := v_0.Args[0]
 11924  		if !(c&0x80 == 0) {
 11925  			break
 11926  		}
 11927  		v.reset(OpAMD64ANDLconst)
 11928  		v.AuxInt = c & 0x7f
 11929  		v.AddArg(x)
 11930  		return true
 11931  	}
 11932  	// match: (MOVBQSX (MOVBQSX x))
 11933  	// cond:
 11934  	// result: (MOVBQSX x)
 11935  	for {
 11936  		v_0 := v.Args[0]
 11937  		if v_0.Op != OpAMD64MOVBQSX {
 11938  			break
 11939  		}
 11940  		x := v_0.Args[0]
 11941  		v.reset(OpAMD64MOVBQSX)
 11942  		v.AddArg(x)
 11943  		return true
 11944  	}
 11945  	return false
 11946  }
 11947  func rewriteValueAMD64_OpAMD64MOVBQSXload_0(v *Value) bool {
 11948  	// match: (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _))
 11949  	// cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
 11950  	// result: (MOVBQSX x)
 11951  	for {
 11952  		off := v.AuxInt
 11953  		sym := v.Aux
 11954  		_ = v.Args[1]
 11955  		ptr := v.Args[0]
 11956  		v_1 := v.Args[1]
 11957  		if v_1.Op != OpAMD64MOVBstore {
 11958  			break
 11959  		}
 11960  		off2 := v_1.AuxInt
 11961  		sym2 := v_1.Aux
 11962  		_ = v_1.Args[2]
 11963  		ptr2 := v_1.Args[0]
 11964  		x := v_1.Args[1]
 11965  		if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
 11966  			break
 11967  		}
 11968  		v.reset(OpAMD64MOVBQSX)
 11969  		v.AddArg(x)
 11970  		return true
 11971  	}
 11972  	// match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
 11973  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 11974  	// result: (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem)
 11975  	for {
 11976  		off1 := v.AuxInt
 11977  		sym1 := v.Aux
 11978  		mem := v.Args[1]
 11979  		v_0 := v.Args[0]
 11980  		if v_0.Op != OpAMD64LEAQ {
 11981  			break
 11982  		}
 11983  		off2 := v_0.AuxInt
 11984  		sym2 := v_0.Aux
 11985  		base := v_0.Args[0]
 11986  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 11987  			break
 11988  		}
 11989  		v.reset(OpAMD64MOVBQSXload)
 11990  		v.AuxInt = off1 + off2
 11991  		v.Aux = mergeSym(sym1, sym2)
 11992  		v.AddArg(base)
 11993  		v.AddArg(mem)
 11994  		return true
 11995  	}
 11996  	return false
 11997  }
 11998  func rewriteValueAMD64_OpAMD64MOVBQZX_0(v *Value) bool {
 11999  	b := v.Block
 12000  	// match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem))
 12001  	// cond: x.Uses == 1 && clobber(x)
 12002  	// result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
 12003  	for {
 12004  		x := v.Args[0]
 12005  		if x.Op != OpAMD64MOVBload {
 12006  			break
 12007  		}
 12008  		off := x.AuxInt
 12009  		sym := x.Aux
 12010  		mem := x.Args[1]
 12011  		ptr := x.Args[0]
 12012  		if !(x.Uses == 1 && clobber(x)) {
 12013  			break
 12014  		}
 12015  		b = x.Block
 12016  		v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type)
 12017  		v.reset(OpCopy)
 12018  		v.AddArg(v0)
 12019  		v0.AuxInt = off
 12020  		v0.Aux = sym
 12021  		v0.AddArg(ptr)
 12022  		v0.AddArg(mem)
 12023  		return true
 12024  	}
 12025  	// match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem))
 12026  	// cond: x.Uses == 1 && clobber(x)
 12027  	// result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
 12028  	for {
 12029  		x := v.Args[0]
 12030  		if x.Op != OpAMD64MOVWload {
 12031  			break
 12032  		}
 12033  		off := x.AuxInt
 12034  		sym := x.Aux
 12035  		mem := x.Args[1]
 12036  		ptr := x.Args[0]
 12037  		if !(x.Uses == 1 && clobber(x)) {
 12038  			break
 12039  		}
 12040  		b = x.Block
 12041  		v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type)
 12042  		v.reset(OpCopy)
 12043  		v.AddArg(v0)
 12044  		v0.AuxInt = off
 12045  		v0.Aux = sym
 12046  		v0.AddArg(ptr)
 12047  		v0.AddArg(mem)
 12048  		return true
 12049  	}
 12050  	// match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem))
 12051  	// cond: x.Uses == 1 && clobber(x)
 12052  	// result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
 12053  	for {
 12054  		x := v.Args[0]
 12055  		if x.Op != OpAMD64MOVLload {
 12056  			break
 12057  		}
 12058  		off := x.AuxInt
 12059  		sym := x.Aux
 12060  		mem := x.Args[1]
 12061  		ptr := x.Args[0]
 12062  		if !(x.Uses == 1 && clobber(x)) {
 12063  			break
 12064  		}
 12065  		b = x.Block
 12066  		v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type)
 12067  		v.reset(OpCopy)
 12068  		v.AddArg(v0)
 12069  		v0.AuxInt = off
 12070  		v0.Aux = sym
 12071  		v0.AddArg(ptr)
 12072  		v0.AddArg(mem)
 12073  		return true
 12074  	}
 12075  	// match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem))
 12076  	// cond: x.Uses == 1 && clobber(x)
 12077  	// result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
 12078  	for {
 12079  		x := v.Args[0]
 12080  		if x.Op != OpAMD64MOVQload {
 12081  			break
 12082  		}
 12083  		off := x.AuxInt
 12084  		sym := x.Aux
 12085  		mem := x.Args[1]
 12086  		ptr := x.Args[0]
 12087  		if !(x.Uses == 1 && clobber(x)) {
 12088  			break
 12089  		}
 12090  		b = x.Block
 12091  		v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type)
 12092  		v.reset(OpCopy)
 12093  		v.AddArg(v0)
 12094  		v0.AuxInt = off
 12095  		v0.Aux = sym
 12096  		v0.AddArg(ptr)
 12097  		v0.AddArg(mem)
 12098  		return true
 12099  	}
 12100  	// match: (MOVBQZX x)
 12101  	// cond: zeroUpper56Bits(x,3)
 12102  	// result: x
 12103  	for {
 12104  		x := v.Args[0]
 12105  		if !(zeroUpper56Bits(x, 3)) {
 12106  			break
 12107  		}
 12108  		v.reset(OpCopy)
 12109  		v.Type = x.Type
 12110  		v.AddArg(x)
 12111  		return true
 12112  	}
 12113  	// match: (MOVBQZX x:(MOVBloadidx1 [off] {sym} ptr idx mem))
 12114  	// cond: x.Uses == 1 && clobber(x)
 12115  	// result: @x.Block (MOVBloadidx1 <v.Type> [off] {sym} ptr idx mem)
 12116  	for {
 12117  		x := v.Args[0]
 12118  		if x.Op != OpAMD64MOVBloadidx1 {
 12119  			break
 12120  		}
 12121  		off := x.AuxInt
 12122  		sym := x.Aux
 12123  		mem := x.Args[2]
 12124  		ptr := x.Args[0]
 12125  		idx := x.Args[1]
 12126  		if !(x.Uses == 1 && clobber(x)) {
 12127  			break
 12128  		}
 12129  		b = x.Block
 12130  		v0 := b.NewValue0(v.Pos, OpAMD64MOVBloadidx1, v.Type)
 12131  		v.reset(OpCopy)
 12132  		v.AddArg(v0)
 12133  		v0.AuxInt = off
 12134  		v0.Aux = sym
 12135  		v0.AddArg(ptr)
 12136  		v0.AddArg(idx)
 12137  		v0.AddArg(mem)
 12138  		return true
 12139  	}
 12140  	// match: (MOVBQZX (ANDLconst [c] x))
 12141  	// cond:
 12142  	// result: (ANDLconst [c & 0xff] x)
 12143  	for {
 12144  		v_0 := v.Args[0]
 12145  		if v_0.Op != OpAMD64ANDLconst {
 12146  			break
 12147  		}
 12148  		c := v_0.AuxInt
 12149  		x := v_0.Args[0]
 12150  		v.reset(OpAMD64ANDLconst)
 12151  		v.AuxInt = c & 0xff
 12152  		v.AddArg(x)
 12153  		return true
 12154  	}
 12155  	// match: (MOVBQZX (MOVBQZX x))
 12156  	// cond:
 12157  	// result: (MOVBQZX x)
 12158  	for {
 12159  		v_0 := v.Args[0]
 12160  		if v_0.Op != OpAMD64MOVBQZX {
 12161  			break
 12162  		}
 12163  		x := v_0.Args[0]
 12164  		v.reset(OpAMD64MOVBQZX)
 12165  		v.AddArg(x)
 12166  		return true
 12167  	}
 12168  	return false
 12169  }
 12170  func rewriteValueAMD64_OpAMD64MOVBatomicload_0(v *Value) bool {
 12171  	// match: (MOVBatomicload [off1] {sym} (ADDQconst [off2] ptr) mem)
 12172  	// cond: is32Bit(off1+off2)
 12173  	// result: (MOVBatomicload [off1+off2] {sym} ptr mem)
 12174  	for {
 12175  		off1 := v.AuxInt
 12176  		sym := v.Aux
 12177  		mem := v.Args[1]
 12178  		v_0 := v.Args[0]
 12179  		if v_0.Op != OpAMD64ADDQconst {
 12180  			break
 12181  		}
 12182  		off2 := v_0.AuxInt
 12183  		ptr := v_0.Args[0]
 12184  		if !(is32Bit(off1 + off2)) {
 12185  			break
 12186  		}
 12187  		v.reset(OpAMD64MOVBatomicload)
 12188  		v.AuxInt = off1 + off2
 12189  		v.Aux = sym
 12190  		v.AddArg(ptr)
 12191  		v.AddArg(mem)
 12192  		return true
 12193  	}
 12194  	// match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem)
 12195  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 12196  	// result: (MOVBatomicload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
 12197  	for {
 12198  		off1 := v.AuxInt
 12199  		sym1 := v.Aux
 12200  		mem := v.Args[1]
 12201  		v_0 := v.Args[0]
 12202  		if v_0.Op != OpAMD64LEAQ {
 12203  			break
 12204  		}
 12205  		off2 := v_0.AuxInt
 12206  		sym2 := v_0.Aux
 12207  		ptr := v_0.Args[0]
 12208  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 12209  			break
 12210  		}
 12211  		v.reset(OpAMD64MOVBatomicload)
 12212  		v.AuxInt = off1 + off2
 12213  		v.Aux = mergeSym(sym1, sym2)
 12214  		v.AddArg(ptr)
 12215  		v.AddArg(mem)
 12216  		return true
 12217  	}
 12218  	return false
 12219  }
 12220  func rewriteValueAMD64_OpAMD64MOVBload_0(v *Value) bool {
 12221  	// match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _))
 12222  	// cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
 12223  	// result: (MOVBQZX x)
 12224  	for {
 12225  		off := v.AuxInt
 12226  		sym := v.Aux
 12227  		_ = v.Args[1]
 12228  		ptr := v.Args[0]
 12229  		v_1 := v.Args[1]
 12230  		if v_1.Op != OpAMD64MOVBstore {
 12231  			break
 12232  		}
 12233  		off2 := v_1.AuxInt
 12234  		sym2 := v_1.Aux
 12235  		_ = v_1.Args[2]
 12236  		ptr2 := v_1.Args[0]
 12237  		x := v_1.Args[1]
 12238  		if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
 12239  			break
 12240  		}
 12241  		v.reset(OpAMD64MOVBQZX)
 12242  		v.AddArg(x)
 12243  		return true
 12244  	}
 12245  	// match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem)
 12246  	// cond: is32Bit(off1+off2)
 12247  	// result: (MOVBload [off1+off2] {sym} ptr mem)
 12248  	for {
 12249  		off1 := v.AuxInt
 12250  		sym := v.Aux
 12251  		mem := v.Args[1]
 12252  		v_0 := v.Args[0]
 12253  		if v_0.Op != OpAMD64ADDQconst {
 12254  			break
 12255  		}
 12256  		off2 := v_0.AuxInt
 12257  		ptr := v_0.Args[0]
 12258  		if !(is32Bit(off1 + off2)) {
 12259  			break
 12260  		}
 12261  		v.reset(OpAMD64MOVBload)
 12262  		v.AuxInt = off1 + off2
 12263  		v.Aux = sym
 12264  		v.AddArg(ptr)
 12265  		v.AddArg(mem)
 12266  		return true
 12267  	}
 12268  	// match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
 12269  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 12270  	// result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem)
 12271  	for {
 12272  		off1 := v.AuxInt
 12273  		sym1 := v.Aux
 12274  		mem := v.Args[1]
 12275  		v_0 := v.Args[0]
 12276  		if v_0.Op != OpAMD64LEAQ {
 12277  			break
 12278  		}
 12279  		off2 := v_0.AuxInt
 12280  		sym2 := v_0.Aux
 12281  		base := v_0.Args[0]
 12282  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 12283  			break
 12284  		}
 12285  		v.reset(OpAMD64MOVBload)
 12286  		v.AuxInt = off1 + off2
 12287  		v.Aux = mergeSym(sym1, sym2)
 12288  		v.AddArg(base)
 12289  		v.AddArg(mem)
 12290  		return true
 12291  	}
 12292  	// match: (MOVBload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem)
 12293  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 12294  	// result: (MOVBloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
 12295  	for {
 12296  		off1 := v.AuxInt
 12297  		sym1 := v.Aux
 12298  		mem := v.Args[1]
 12299  		v_0 := v.Args[0]
 12300  		if v_0.Op != OpAMD64LEAQ1 {
 12301  			break
 12302  		}
 12303  		off2 := v_0.AuxInt
 12304  		sym2 := v_0.Aux
 12305  		idx := v_0.Args[1]
 12306  		ptr := v_0.Args[0]
 12307  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 12308  			break
 12309  		}
 12310  		v.reset(OpAMD64MOVBloadidx1)
 12311  		v.AuxInt = off1 + off2
 12312  		v.Aux = mergeSym(sym1, sym2)
 12313  		v.AddArg(ptr)
 12314  		v.AddArg(idx)
 12315  		v.AddArg(mem)
 12316  		return true
 12317  	}
 12318  	// match: (MOVBload [off] {sym} (ADDQ ptr idx) mem)
 12319  	// cond: ptr.Op != OpSB
 12320  	// result: (MOVBloadidx1 [off] {sym} ptr idx mem)
 12321  	for {
 12322  		off := v.AuxInt
 12323  		sym := v.Aux
 12324  		mem := v.Args[1]
 12325  		v_0 := v.Args[0]
 12326  		if v_0.Op != OpAMD64ADDQ {
 12327  			break
 12328  		}
 12329  		idx := v_0.Args[1]
 12330  		ptr := v_0.Args[0]
 12331  		if !(ptr.Op != OpSB) {
 12332  			break
 12333  		}
 12334  		v.reset(OpAMD64MOVBloadidx1)
 12335  		v.AuxInt = off
 12336  		v.Aux = sym
 12337  		v.AddArg(ptr)
 12338  		v.AddArg(idx)
 12339  		v.AddArg(mem)
 12340  		return true
 12341  	}
 12342  	// match: (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
 12343  	// cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2)
 12344  	// result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem)
 12345  	for {
 12346  		off1 := v.AuxInt
 12347  		sym1 := v.Aux
 12348  		mem := v.Args[1]
 12349  		v_0 := v.Args[0]
 12350  		if v_0.Op != OpAMD64LEAL {
 12351  			break
 12352  		}
 12353  		off2 := v_0.AuxInt
 12354  		sym2 := v_0.Aux
 12355  		base := v_0.Args[0]
 12356  		if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) {
 12357  			break
 12358  		}
 12359  		v.reset(OpAMD64MOVBload)
 12360  		v.AuxInt = off1 + off2
 12361  		v.Aux = mergeSym(sym1, sym2)
 12362  		v.AddArg(base)
 12363  		v.AddArg(mem)
 12364  		return true
 12365  	}
 12366  	// match: (MOVBload [off1] {sym} (ADDLconst [off2] ptr) mem)
 12367  	// cond: is32Bit(off1+off2)
 12368  	// result: (MOVBload [off1+off2] {sym} ptr mem)
 12369  	for {
 12370  		off1 := v.AuxInt
 12371  		sym := v.Aux
 12372  		mem := v.Args[1]
 12373  		v_0 := v.Args[0]
 12374  		if v_0.Op != OpAMD64ADDLconst {
 12375  			break
 12376  		}
 12377  		off2 := v_0.AuxInt
 12378  		ptr := v_0.Args[0]
 12379  		if !(is32Bit(off1 + off2)) {
 12380  			break
 12381  		}
 12382  		v.reset(OpAMD64MOVBload)
 12383  		v.AuxInt = off1 + off2
 12384  		v.Aux = sym
 12385  		v.AddArg(ptr)
 12386  		v.AddArg(mem)
 12387  		return true
 12388  	}
 12389  	// match: (MOVBload [off] {sym} (SB) _)
 12390  	// cond: symIsRO(sym)
 12391  	// result: (MOVLconst [int64(read8(sym, off))])
 12392  	for {
 12393  		off := v.AuxInt
 12394  		sym := v.Aux
 12395  		_ = v.Args[1]
 12396  		v_0 := v.Args[0]
 12397  		if v_0.Op != OpSB {
 12398  			break
 12399  		}
 12400  		if !(symIsRO(sym)) {
 12401  			break
 12402  		}
 12403  		v.reset(OpAMD64MOVLconst)
 12404  		v.AuxInt = int64(read8(sym, off))
 12405  		return true
 12406  	}
 12407  	return false
 12408  }
 12409  func rewriteValueAMD64_OpAMD64MOVBloadidx1_0(v *Value) bool {
 12410  	// match: (MOVBloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem)
 12411  	// cond: is32Bit(c+d)
 12412  	// result: (MOVBloadidx1 [c+d] {sym} ptr idx mem)
 12413  	for {
 12414  		c := v.AuxInt
 12415  		sym := v.Aux
 12416  		mem := v.Args[2]
 12417  		v_0 := v.Args[0]
 12418  		if v_0.Op != OpAMD64ADDQconst {
 12419  			break
 12420  		}
 12421  		d := v_0.AuxInt
 12422  		ptr := v_0.Args[0]
 12423  		idx := v.Args[1]
 12424  		if !(is32Bit(c + d)) {
 12425  			break
 12426  		}
 12427  		v.reset(OpAMD64MOVBloadidx1)
 12428  		v.AuxInt = c + d
 12429  		v.Aux = sym
 12430  		v.AddArg(ptr)
 12431  		v.AddArg(idx)
 12432  		v.AddArg(mem)
 12433  		return true
 12434  	}
 12435  	// match: (MOVBloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem)
 12436  	// cond: is32Bit(c+d)
 12437  	// result: (MOVBloadidx1 [c+d] {sym} ptr idx mem)
 12438  	for {
 12439  		c := v.AuxInt
 12440  		sym := v.Aux
 12441  		mem := v.Args[2]
 12442  		idx := v.Args[0]
 12443  		v_1 := v.Args[1]
 12444  		if v_1.Op != OpAMD64ADDQconst {
 12445  			break
 12446  		}
 12447  		d := v_1.AuxInt
 12448  		ptr := v_1.Args[0]
 12449  		if !(is32Bit(c + d)) {
 12450  			break
 12451  		}
 12452  		v.reset(OpAMD64MOVBloadidx1)
 12453  		v.AuxInt = c + d
 12454  		v.Aux = sym
 12455  		v.AddArg(ptr)
 12456  		v.AddArg(idx)
 12457  		v.AddArg(mem)
 12458  		return true
 12459  	}
 12460  	// match: (MOVBloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem)
 12461  	// cond: is32Bit(c+d)
 12462  	// result: (MOVBloadidx1 [c+d] {sym} ptr idx mem)
 12463  	for {
 12464  		c := v.AuxInt
 12465  		sym := v.Aux
 12466  		mem := v.Args[2]
 12467  		ptr := v.Args[0]
 12468  		v_1 := v.Args[1]
 12469  		if v_1.Op != OpAMD64ADDQconst {
 12470  			break
 12471  		}
 12472  		d := v_1.AuxInt
 12473  		idx := v_1.Args[0]
 12474  		if !(is32Bit(c + d)) {
 12475  			break
 12476  		}
 12477  		v.reset(OpAMD64MOVBloadidx1)
 12478  		v.AuxInt = c + d
 12479  		v.Aux = sym
 12480  		v.AddArg(ptr)
 12481  		v.AddArg(idx)
 12482  		v.AddArg(mem)
 12483  		return true
 12484  	}
 12485  	// match: (MOVBloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem)
 12486  	// cond: is32Bit(c+d)
 12487  	// result: (MOVBloadidx1 [c+d] {sym} ptr idx mem)
 12488  	for {
 12489  		c := v.AuxInt
 12490  		sym := v.Aux
 12491  		mem := v.Args[2]
 12492  		v_0 := v.Args[0]
 12493  		if v_0.Op != OpAMD64ADDQconst {
 12494  			break
 12495  		}
 12496  		d := v_0.AuxInt
 12497  		idx := v_0.Args[0]
 12498  		ptr := v.Args[1]
 12499  		if !(is32Bit(c + d)) {
 12500  			break
 12501  		}
 12502  		v.reset(OpAMD64MOVBloadidx1)
 12503  		v.AuxInt = c + d
 12504  		v.Aux = sym
 12505  		v.AddArg(ptr)
 12506  		v.AddArg(idx)
 12507  		v.AddArg(mem)
 12508  		return true
 12509  	}
 12510  	// match: (MOVBloadidx1 [i] {s} p (MOVQconst [c]) mem)
 12511  	// cond: is32Bit(i+c)
 12512  	// result: (MOVBload [i+c] {s} p mem)
 12513  	for {
 12514  		i := v.AuxInt
 12515  		s := v.Aux
 12516  		mem := v.Args[2]
 12517  		p := v.Args[0]
 12518  		v_1 := v.Args[1]
 12519  		if v_1.Op != OpAMD64MOVQconst {
 12520  			break
 12521  		}
 12522  		c := v_1.AuxInt
 12523  		if !(is32Bit(i + c)) {
 12524  			break
 12525  		}
 12526  		v.reset(OpAMD64MOVBload)
 12527  		v.AuxInt = i + c
 12528  		v.Aux = s
 12529  		v.AddArg(p)
 12530  		v.AddArg(mem)
 12531  		return true
 12532  	}
 12533  	// match: (MOVBloadidx1 [i] {s} (MOVQconst [c]) p mem)
 12534  	// cond: is32Bit(i+c)
 12535  	// result: (MOVBload [i+c] {s} p mem)
 12536  	for {
 12537  		i := v.AuxInt
 12538  		s := v.Aux
 12539  		mem := v.Args[2]
 12540  		v_0 := v.Args[0]
 12541  		if v_0.Op != OpAMD64MOVQconst {
 12542  			break
 12543  		}
 12544  		c := v_0.AuxInt
 12545  		p := v.Args[1]
 12546  		if !(is32Bit(i + c)) {
 12547  			break
 12548  		}
 12549  		v.reset(OpAMD64MOVBload)
 12550  		v.AuxInt = i + c
 12551  		v.Aux = s
 12552  		v.AddArg(p)
 12553  		v.AddArg(mem)
 12554  		return true
 12555  	}
 12556  	return false
 12557  }
 12558  func rewriteValueAMD64_OpAMD64MOVBstore_0(v *Value) bool {
 12559  	// match: (MOVBstore [off] {sym} ptr y:(SETL x) mem)
 12560  	// cond: y.Uses == 1
 12561  	// result: (SETLstore [off] {sym} ptr x mem)
 12562  	for {
 12563  		off := v.AuxInt
 12564  		sym := v.Aux
 12565  		mem := v.Args[2]
 12566  		ptr := v.Args[0]
 12567  		y := v.Args[1]
 12568  		if y.Op != OpAMD64SETL {
 12569  			break
 12570  		}
 12571  		x := y.Args[0]
 12572  		if !(y.Uses == 1) {
 12573  			break
 12574  		}
 12575  		v.reset(OpAMD64SETLstore)
 12576  		v.AuxInt = off
 12577  		v.Aux = sym
 12578  		v.AddArg(ptr)
 12579  		v.AddArg(x)
 12580  		v.AddArg(mem)
 12581  		return true
 12582  	}
 12583  	// match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem)
 12584  	// cond: y.Uses == 1
 12585  	// result: (SETLEstore [off] {sym} ptr x mem)
 12586  	for {
 12587  		off := v.AuxInt
 12588  		sym := v.Aux
 12589  		mem := v.Args[2]
 12590  		ptr := v.Args[0]
 12591  		y := v.Args[1]
 12592  		if y.Op != OpAMD64SETLE {
 12593  			break
 12594  		}
 12595  		x := y.Args[0]
 12596  		if !(y.Uses == 1) {
 12597  			break
 12598  		}
 12599  		v.reset(OpAMD64SETLEstore)
 12600  		v.AuxInt = off
 12601  		v.Aux = sym
 12602  		v.AddArg(ptr)
 12603  		v.AddArg(x)
 12604  		v.AddArg(mem)
 12605  		return true
 12606  	}
 12607  	// match: (MOVBstore [off] {sym} ptr y:(SETG x) mem)
 12608  	// cond: y.Uses == 1
 12609  	// result: (SETGstore [off] {sym} ptr x mem)
 12610  	for {
 12611  		off := v.AuxInt
 12612  		sym := v.Aux
 12613  		mem := v.Args[2]
 12614  		ptr := v.Args[0]
 12615  		y := v.Args[1]
 12616  		if y.Op != OpAMD64SETG {
 12617  			break
 12618  		}
 12619  		x := y.Args[0]
 12620  		if !(y.Uses == 1) {
 12621  			break
 12622  		}
 12623  		v.reset(OpAMD64SETGstore)
 12624  		v.AuxInt = off
 12625  		v.Aux = sym
 12626  		v.AddArg(ptr)
 12627  		v.AddArg(x)
 12628  		v.AddArg(mem)
 12629  		return true
 12630  	}
 12631  	// match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem)
 12632  	// cond: y.Uses == 1
 12633  	// result: (SETGEstore [off] {sym} ptr x mem)
 12634  	for {
 12635  		off := v.AuxInt
 12636  		sym := v.Aux
 12637  		mem := v.Args[2]
 12638  		ptr := v.Args[0]
 12639  		y := v.Args[1]
 12640  		if y.Op != OpAMD64SETGE {
 12641  			break
 12642  		}
 12643  		x := y.Args[0]
 12644  		if !(y.Uses == 1) {
 12645  			break
 12646  		}
 12647  		v.reset(OpAMD64SETGEstore)
 12648  		v.AuxInt = off
 12649  		v.Aux = sym
 12650  		v.AddArg(ptr)
 12651  		v.AddArg(x)
 12652  		v.AddArg(mem)
 12653  		return true
 12654  	}
 12655  	// match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem)
 12656  	// cond: y.Uses == 1
 12657  	// result: (SETEQstore [off] {sym} ptr x mem)
 12658  	for {
 12659  		off := v.AuxInt
 12660  		sym := v.Aux
 12661  		mem := v.Args[2]
 12662  		ptr := v.Args[0]
 12663  		y := v.Args[1]
 12664  		if y.Op != OpAMD64SETEQ {
 12665  			break
 12666  		}
 12667  		x := y.Args[0]
 12668  		if !(y.Uses == 1) {
 12669  			break
 12670  		}
 12671  		v.reset(OpAMD64SETEQstore)
 12672  		v.AuxInt = off
 12673  		v.Aux = sym
 12674  		v.AddArg(ptr)
 12675  		v.AddArg(x)
 12676  		v.AddArg(mem)
 12677  		return true
 12678  	}
 12679  	// match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem)
 12680  	// cond: y.Uses == 1
 12681  	// result: (SETNEstore [off] {sym} ptr x mem)
 12682  	for {
 12683  		off := v.AuxInt
 12684  		sym := v.Aux
 12685  		mem := v.Args[2]
 12686  		ptr := v.Args[0]
 12687  		y := v.Args[1]
 12688  		if y.Op != OpAMD64SETNE {
 12689  			break
 12690  		}
 12691  		x := y.Args[0]
 12692  		if !(y.Uses == 1) {
 12693  			break
 12694  		}
 12695  		v.reset(OpAMD64SETNEstore)
 12696  		v.AuxInt = off
 12697  		v.Aux = sym
 12698  		v.AddArg(ptr)
 12699  		v.AddArg(x)
 12700  		v.AddArg(mem)
 12701  		return true
 12702  	}
 12703  	// match: (MOVBstore [off] {sym} ptr y:(SETB x) mem)
 12704  	// cond: y.Uses == 1
 12705  	// result: (SETBstore [off] {sym} ptr x mem)
 12706  	for {
 12707  		off := v.AuxInt
 12708  		sym := v.Aux
 12709  		mem := v.Args[2]
 12710  		ptr := v.Args[0]
 12711  		y := v.Args[1]
 12712  		if y.Op != OpAMD64SETB {
 12713  			break
 12714  		}
 12715  		x := y.Args[0]
 12716  		if !(y.Uses == 1) {
 12717  			break
 12718  		}
 12719  		v.reset(OpAMD64SETBstore)
 12720  		v.AuxInt = off
 12721  		v.Aux = sym
 12722  		v.AddArg(ptr)
 12723  		v.AddArg(x)
 12724  		v.AddArg(mem)
 12725  		return true
 12726  	}
 12727  	// match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem)
 12728  	// cond: y.Uses == 1
 12729  	// result: (SETBEstore [off] {sym} ptr x mem)
 12730  	for {
 12731  		off := v.AuxInt
 12732  		sym := v.Aux
 12733  		mem := v.Args[2]
 12734  		ptr := v.Args[0]
 12735  		y := v.Args[1]
 12736  		if y.Op != OpAMD64SETBE {
 12737  			break
 12738  		}
 12739  		x := y.Args[0]
 12740  		if !(y.Uses == 1) {
 12741  			break
 12742  		}
 12743  		v.reset(OpAMD64SETBEstore)
 12744  		v.AuxInt = off
 12745  		v.Aux = sym
 12746  		v.AddArg(ptr)
 12747  		v.AddArg(x)
 12748  		v.AddArg(mem)
 12749  		return true
 12750  	}
 12751  	// match: (MOVBstore [off] {sym} ptr y:(SETA x) mem)
 12752  	// cond: y.Uses == 1
 12753  	// result: (SETAstore [off] {sym} ptr x mem)
 12754  	for {
 12755  		off := v.AuxInt
 12756  		sym := v.Aux
 12757  		mem := v.Args[2]
 12758  		ptr := v.Args[0]
 12759  		y := v.Args[1]
 12760  		if y.Op != OpAMD64SETA {
 12761  			break
 12762  		}
 12763  		x := y.Args[0]
 12764  		if !(y.Uses == 1) {
 12765  			break
 12766  		}
 12767  		v.reset(OpAMD64SETAstore)
 12768  		v.AuxInt = off
 12769  		v.Aux = sym
 12770  		v.AddArg(ptr)
 12771  		v.AddArg(x)
 12772  		v.AddArg(mem)
 12773  		return true
 12774  	}
 12775  	// match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem)
 12776  	// cond: y.Uses == 1
 12777  	// result: (SETAEstore [off] {sym} ptr x mem)
 12778  	for {
 12779  		off := v.AuxInt
 12780  		sym := v.Aux
 12781  		mem := v.Args[2]
 12782  		ptr := v.Args[0]
 12783  		y := v.Args[1]
 12784  		if y.Op != OpAMD64SETAE {
 12785  			break
 12786  		}
 12787  		x := y.Args[0]
 12788  		if !(y.Uses == 1) {
 12789  			break
 12790  		}
 12791  		v.reset(OpAMD64SETAEstore)
 12792  		v.AuxInt = off
 12793  		v.Aux = sym
 12794  		v.AddArg(ptr)
 12795  		v.AddArg(x)
 12796  		v.AddArg(mem)
 12797  		return true
 12798  	}
 12799  	return false
 12800  }
 12801  func rewriteValueAMD64_OpAMD64MOVBstore_10(v *Value) bool {
 12802  	b := v.Block
 12803  	// match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem)
 12804  	// cond:
 12805  	// result: (MOVBstore [off] {sym} ptr x mem)
 12806  	for {
 12807  		off := v.AuxInt
 12808  		sym := v.Aux
 12809  		mem := v.Args[2]
 12810  		ptr := v.Args[0]
 12811  		v_1 := v.Args[1]
 12812  		if v_1.Op != OpAMD64MOVBQSX {
 12813  			break
 12814  		}
 12815  		x := v_1.Args[0]
 12816  		v.reset(OpAMD64MOVBstore)
 12817  		v.AuxInt = off
 12818  		v.Aux = sym
 12819  		v.AddArg(ptr)
 12820  		v.AddArg(x)
 12821  		v.AddArg(mem)
 12822  		return true
 12823  	}
 12824  	// match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem)
 12825  	// cond:
 12826  	// result: (MOVBstore [off] {sym} ptr x mem)
 12827  	for {
 12828  		off := v.AuxInt
 12829  		sym := v.Aux
 12830  		mem := v.Args[2]
 12831  		ptr := v.Args[0]
 12832  		v_1 := v.Args[1]
 12833  		if v_1.Op != OpAMD64MOVBQZX {
 12834  			break
 12835  		}
 12836  		x := v_1.Args[0]
 12837  		v.reset(OpAMD64MOVBstore)
 12838  		v.AuxInt = off
 12839  		v.Aux = sym
 12840  		v.AddArg(ptr)
 12841  		v.AddArg(x)
 12842  		v.AddArg(mem)
 12843  		return true
 12844  	}
 12845  	// match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem)
 12846  	// cond: is32Bit(off1+off2)
 12847  	// result: (MOVBstore [off1+off2] {sym} ptr val mem)
 12848  	for {
 12849  		off1 := v.AuxInt
 12850  		sym := v.Aux
 12851  		mem := v.Args[2]
 12852  		v_0 := v.Args[0]
 12853  		if v_0.Op != OpAMD64ADDQconst {
 12854  			break
 12855  		}
 12856  		off2 := v_0.AuxInt
 12857  		ptr := v_0.Args[0]
 12858  		val := v.Args[1]
 12859  		if !(is32Bit(off1 + off2)) {
 12860  			break
 12861  		}
 12862  		v.reset(OpAMD64MOVBstore)
 12863  		v.AuxInt = off1 + off2
 12864  		v.Aux = sym
 12865  		v.AddArg(ptr)
 12866  		v.AddArg(val)
 12867  		v.AddArg(mem)
 12868  		return true
 12869  	}
 12870  	// match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem)
 12871  	// cond: validOff(off)
 12872  	// result: (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem)
 12873  	for {
 12874  		off := v.AuxInt
 12875  		sym := v.Aux
 12876  		mem := v.Args[2]
 12877  		ptr := v.Args[0]
 12878  		v_1 := v.Args[1]
 12879  		if v_1.Op != OpAMD64MOVLconst {
 12880  			break
 12881  		}
 12882  		c := v_1.AuxInt
 12883  		if !(validOff(off)) {
 12884  			break
 12885  		}
 12886  		v.reset(OpAMD64MOVBstoreconst)
 12887  		v.AuxInt = makeValAndOff(int64(int8(c)), off)
 12888  		v.Aux = sym
 12889  		v.AddArg(ptr)
 12890  		v.AddArg(mem)
 12891  		return true
 12892  	}
 12893  	// match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem)
 12894  	// cond: validOff(off)
 12895  	// result: (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem)
 12896  	for {
 12897  		off := v.AuxInt
 12898  		sym := v.Aux
 12899  		mem := v.Args[2]
 12900  		ptr := v.Args[0]
 12901  		v_1 := v.Args[1]
 12902  		if v_1.Op != OpAMD64MOVQconst {
 12903  			break
 12904  		}
 12905  		c := v_1.AuxInt
 12906  		if !(validOff(off)) {
 12907  			break
 12908  		}
 12909  		v.reset(OpAMD64MOVBstoreconst)
 12910  		v.AuxInt = makeValAndOff(int64(int8(c)), off)
 12911  		v.Aux = sym
 12912  		v.AddArg(ptr)
 12913  		v.AddArg(mem)
 12914  		return true
 12915  	}
 12916  	// match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
 12917  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 12918  	// result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
 12919  	for {
 12920  		off1 := v.AuxInt
 12921  		sym1 := v.Aux
 12922  		mem := v.Args[2]
 12923  		v_0 := v.Args[0]
 12924  		if v_0.Op != OpAMD64LEAQ {
 12925  			break
 12926  		}
 12927  		off2 := v_0.AuxInt
 12928  		sym2 := v_0.Aux
 12929  		base := v_0.Args[0]
 12930  		val := v.Args[1]
 12931  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 12932  			break
 12933  		}
 12934  		v.reset(OpAMD64MOVBstore)
 12935  		v.AuxInt = off1 + off2
 12936  		v.Aux = mergeSym(sym1, sym2)
 12937  		v.AddArg(base)
 12938  		v.AddArg(val)
 12939  		v.AddArg(mem)
 12940  		return true
 12941  	}
 12942  	// match: (MOVBstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem)
 12943  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 12944  	// result: (MOVBstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
 12945  	for {
 12946  		off1 := v.AuxInt
 12947  		sym1 := v.Aux
 12948  		mem := v.Args[2]
 12949  		v_0 := v.Args[0]
 12950  		if v_0.Op != OpAMD64LEAQ1 {
 12951  			break
 12952  		}
 12953  		off2 := v_0.AuxInt
 12954  		sym2 := v_0.Aux
 12955  		idx := v_0.Args[1]
 12956  		ptr := v_0.Args[0]
 12957  		val := v.Args[1]
 12958  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 12959  			break
 12960  		}
 12961  		v.reset(OpAMD64MOVBstoreidx1)
 12962  		v.AuxInt = off1 + off2
 12963  		v.Aux = mergeSym(sym1, sym2)
 12964  		v.AddArg(ptr)
 12965  		v.AddArg(idx)
 12966  		v.AddArg(val)
 12967  		v.AddArg(mem)
 12968  		return true
 12969  	}
 12970  	// match: (MOVBstore [off] {sym} (ADDQ ptr idx) val mem)
 12971  	// cond: ptr.Op != OpSB
 12972  	// result: (MOVBstoreidx1 [off] {sym} ptr idx val mem)
 12973  	for {
 12974  		off := v.AuxInt
 12975  		sym := v.Aux
 12976  		mem := v.Args[2]
 12977  		v_0 := v.Args[0]
 12978  		if v_0.Op != OpAMD64ADDQ {
 12979  			break
 12980  		}
 12981  		idx := v_0.Args[1]
 12982  		ptr := v_0.Args[0]
 12983  		val := v.Args[1]
 12984  		if !(ptr.Op != OpSB) {
 12985  			break
 12986  		}
 12987  		v.reset(OpAMD64MOVBstoreidx1)
 12988  		v.AuxInt = off
 12989  		v.Aux = sym
 12990  		v.AddArg(ptr)
 12991  		v.AddArg(idx)
 12992  		v.AddArg(val)
 12993  		v.AddArg(mem)
 12994  		return true
 12995  	}
 12996  	// match: (MOVBstore [i] {s} p w x0:(MOVBstore [i-1] {s} p (SHRWconst [8] w) mem))
 12997  	// cond: x0.Uses == 1 && clobber(x0)
 12998  	// result: (MOVWstore [i-1] {s} p (ROLWconst <w.Type> [8] w) mem)
 12999  	for {
 13000  		i := v.AuxInt
 13001  		s := v.Aux
 13002  		_ = v.Args[2]
 13003  		p := v.Args[0]
 13004  		w := v.Args[1]
 13005  		x0 := v.Args[2]
 13006  		if x0.Op != OpAMD64MOVBstore {
 13007  			break
 13008  		}
 13009  		if x0.AuxInt != i-1 {
 13010  			break
 13011  		}
 13012  		if x0.Aux != s {
 13013  			break
 13014  		}
 13015  		mem := x0.Args[2]
 13016  		if p != x0.Args[0] {
 13017  			break
 13018  		}
 13019  		x0_1 := x0.Args[1]
 13020  		if x0_1.Op != OpAMD64SHRWconst {
 13021  			break
 13022  		}
 13023  		if x0_1.AuxInt != 8 {
 13024  			break
 13025  		}
 13026  		if w != x0_1.Args[0] {
 13027  			break
 13028  		}
 13029  		if !(x0.Uses == 1 && clobber(x0)) {
 13030  			break
 13031  		}
 13032  		v.reset(OpAMD64MOVWstore)
 13033  		v.AuxInt = i - 1
 13034  		v.Aux = s
 13035  		v.AddArg(p)
 13036  		v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type)
 13037  		v0.AuxInt = 8
 13038  		v0.AddArg(w)
 13039  		v.AddArg(v0)
 13040  		v.AddArg(mem)
 13041  		return true
 13042  	}
 13043  	// match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem))))
 13044  	// cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)
 13045  	// result: (MOVLstore [i-3] {s} p (BSWAPL <w.Type> w) mem)
 13046  	for {
 13047  		i := v.AuxInt
 13048  		s := v.Aux
 13049  		_ = v.Args[2]
 13050  		p := v.Args[0]
 13051  		w := v.Args[1]
 13052  		x2 := v.Args[2]
 13053  		if x2.Op != OpAMD64MOVBstore {
 13054  			break
 13055  		}
 13056  		if x2.AuxInt != i-1 {
 13057  			break
 13058  		}
 13059  		if x2.Aux != s {
 13060  			break
 13061  		}
 13062  		_ = x2.Args[2]
 13063  		if p != x2.Args[0] {
 13064  			break
 13065  		}
 13066  		x2_1 := x2.Args[1]
 13067  		if x2_1.Op != OpAMD64SHRLconst {
 13068  			break
 13069  		}
 13070  		if x2_1.AuxInt != 8 {
 13071  			break
 13072  		}
 13073  		if w != x2_1.Args[0] {
 13074  			break
 13075  		}
 13076  		x1 := x2.Args[2]
 13077  		if x1.Op != OpAMD64MOVBstore {
 13078  			break
 13079  		}
 13080  		if x1.AuxInt != i-2 {
 13081  			break
 13082  		}
 13083  		if x1.Aux != s {
 13084  			break
 13085  		}
 13086  		_ = x1.Args[2]
 13087  		if p != x1.Args[0] {
 13088  			break
 13089  		}
 13090  		x1_1 := x1.Args[1]
 13091  		if x1_1.Op != OpAMD64SHRLconst {
 13092  			break
 13093  		}
 13094  		if x1_1.AuxInt != 16 {
 13095  			break
 13096  		}
 13097  		if w != x1_1.Args[0] {
 13098  			break
 13099  		}
 13100  		x0 := x1.Args[2]
 13101  		if x0.Op != OpAMD64MOVBstore {
 13102  			break
 13103  		}
 13104  		if x0.AuxInt != i-3 {
 13105  			break
 13106  		}
 13107  		if x0.Aux != s {
 13108  			break
 13109  		}
 13110  		mem := x0.Args[2]
 13111  		if p != x0.Args[0] {
 13112  			break
 13113  		}
 13114  		x0_1 := x0.Args[1]
 13115  		if x0_1.Op != OpAMD64SHRLconst {
 13116  			break
 13117  		}
 13118  		if x0_1.AuxInt != 24 {
 13119  			break
 13120  		}
 13121  		if w != x0_1.Args[0] {
 13122  			break
 13123  		}
 13124  		if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) {
 13125  			break
 13126  		}
 13127  		v.reset(OpAMD64MOVLstore)
 13128  		v.AuxInt = i - 3
 13129  		v.Aux = s
 13130  		v.AddArg(p)
 13131  		v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type)
 13132  		v0.AddArg(w)
 13133  		v.AddArg(v0)
 13134  		v.AddArg(mem)
 13135  		return true
 13136  	}
 13137  	return false
 13138  }
 13139  func rewriteValueAMD64_OpAMD64MOVBstore_20(v *Value) bool {
 13140  	b := v.Block
 13141  	typ := &b.Func.Config.Types
 13142  	// match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem))))))))
 13143  	// cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)
 13144  	// result: (MOVQstore [i-7] {s} p (BSWAPQ <w.Type> w) mem)
 13145  	for {
 13146  		i := v.AuxInt
 13147  		s := v.Aux
 13148  		_ = v.Args[2]
 13149  		p := v.Args[0]
 13150  		w := v.Args[1]
 13151  		x6 := v.Args[2]
 13152  		if x6.Op != OpAMD64MOVBstore {
 13153  			break
 13154  		}
 13155  		if x6.AuxInt != i-1 {
 13156  			break
 13157  		}
 13158  		if x6.Aux != s {
 13159  			break
 13160  		}
 13161  		_ = x6.Args[2]
 13162  		if p != x6.Args[0] {
 13163  			break
 13164  		}
 13165  		x6_1 := x6.Args[1]
 13166  		if x6_1.Op != OpAMD64SHRQconst {
 13167  			break
 13168  		}
 13169  		if x6_1.AuxInt != 8 {
 13170  			break
 13171  		}
 13172  		if w != x6_1.Args[0] {
 13173  			break
 13174  		}
 13175  		x5 := x6.Args[2]
 13176  		if x5.Op != OpAMD64MOVBstore {
 13177  			break
 13178  		}
 13179  		if x5.AuxInt != i-2 {
 13180  			break
 13181  		}
 13182  		if x5.Aux != s {
 13183  			break
 13184  		}
 13185  		_ = x5.Args[2]
 13186  		if p != x5.Args[0] {
 13187  			break
 13188  		}
 13189  		x5_1 := x5.Args[1]
 13190  		if x5_1.Op != OpAMD64SHRQconst {
 13191  			break
 13192  		}
 13193  		if x5_1.AuxInt != 16 {
 13194  			break
 13195  		}
 13196  		if w != x5_1.Args[0] {
 13197  			break
 13198  		}
 13199  		x4 := x5.Args[2]
 13200  		if x4.Op != OpAMD64MOVBstore {
 13201  			break
 13202  		}
 13203  		if x4.AuxInt != i-3 {
 13204  			break
 13205  		}
 13206  		if x4.Aux != s {
 13207  			break
 13208  		}
 13209  		_ = x4.Args[2]
 13210  		if p != x4.Args[0] {
 13211  			break
 13212  		}
 13213  		x4_1 := x4.Args[1]
 13214  		if x4_1.Op != OpAMD64SHRQconst {
 13215  			break
 13216  		}
 13217  		if x4_1.AuxInt != 24 {
 13218  			break
 13219  		}
 13220  		if w != x4_1.Args[0] {
 13221  			break
 13222  		}
 13223  		x3 := x4.Args[2]
 13224  		if x3.Op != OpAMD64MOVBstore {
 13225  			break
 13226  		}
 13227  		if x3.AuxInt != i-4 {
 13228  			break
 13229  		}
 13230  		if x3.Aux != s {
 13231  			break
 13232  		}
 13233  		_ = x3.Args[2]
 13234  		if p != x3.Args[0] {
 13235  			break
 13236  		}
 13237  		x3_1 := x3.Args[1]
 13238  		if x3_1.Op != OpAMD64SHRQconst {
 13239  			break
 13240  		}
 13241  		if x3_1.AuxInt != 32 {
 13242  			break
 13243  		}
 13244  		if w != x3_1.Args[0] {
 13245  			break
 13246  		}
 13247  		x2 := x3.Args[2]
 13248  		if x2.Op != OpAMD64MOVBstore {
 13249  			break
 13250  		}
 13251  		if x2.AuxInt != i-5 {
 13252  			break
 13253  		}
 13254  		if x2.Aux != s {
 13255  			break
 13256  		}
 13257  		_ = x2.Args[2]
 13258  		if p != x2.Args[0] {
 13259  			break
 13260  		}
 13261  		x2_1 := x2.Args[1]
 13262  		if x2_1.Op != OpAMD64SHRQconst {
 13263  			break
 13264  		}
 13265  		if x2_1.AuxInt != 40 {
 13266  			break
 13267  		}
 13268  		if w != x2_1.Args[0] {
 13269  			break
 13270  		}
 13271  		x1 := x2.Args[2]
 13272  		if x1.Op != OpAMD64MOVBstore {
 13273  			break
 13274  		}
 13275  		if x1.AuxInt != i-6 {
 13276  			break
 13277  		}
 13278  		if x1.Aux != s {
 13279  			break
 13280  		}
 13281  		_ = x1.Args[2]
 13282  		if p != x1.Args[0] {
 13283  			break
 13284  		}
 13285  		x1_1 := x1.Args[1]
 13286  		if x1_1.Op != OpAMD64SHRQconst {
 13287  			break
 13288  		}
 13289  		if x1_1.AuxInt != 48 {
 13290  			break
 13291  		}
 13292  		if w != x1_1.Args[0] {
 13293  			break
 13294  		}
 13295  		x0 := x1.Args[2]
 13296  		if x0.Op != OpAMD64MOVBstore {
 13297  			break
 13298  		}
 13299  		if x0.AuxInt != i-7 {
 13300  			break
 13301  		}
 13302  		if x0.Aux != s {
 13303  			break
 13304  		}
 13305  		mem := x0.Args[2]
 13306  		if p != x0.Args[0] {
 13307  			break
 13308  		}
 13309  		x0_1 := x0.Args[1]
 13310  		if x0_1.Op != OpAMD64SHRQconst {
 13311  			break
 13312  		}
 13313  		if x0_1.AuxInt != 56 {
 13314  			break
 13315  		}
 13316  		if w != x0_1.Args[0] {
 13317  			break
 13318  		}
 13319  		if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) {
 13320  			break
 13321  		}
 13322  		v.reset(OpAMD64MOVQstore)
 13323  		v.AuxInt = i - 7
 13324  		v.Aux = s
 13325  		v.AddArg(p)
 13326  		v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type)
 13327  		v0.AddArg(w)
 13328  		v.AddArg(v0)
 13329  		v.AddArg(mem)
 13330  		return true
 13331  	}
 13332  	// match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem))
 13333  	// cond: x.Uses == 1 && clobber(x)
 13334  	// result: (MOVWstore [i-1] {s} p w mem)
 13335  	for {
 13336  		i := v.AuxInt
 13337  		s := v.Aux
 13338  		_ = v.Args[2]
 13339  		p := v.Args[0]
 13340  		v_1 := v.Args[1]
 13341  		if v_1.Op != OpAMD64SHRWconst {
 13342  			break
 13343  		}
 13344  		if v_1.AuxInt != 8 {
 13345  			break
 13346  		}
 13347  		w := v_1.Args[0]
 13348  		x := v.Args[2]
 13349  		if x.Op != OpAMD64MOVBstore {
 13350  			break
 13351  		}
 13352  		if x.AuxInt != i-1 {
 13353  			break
 13354  		}
 13355  		if x.Aux != s {
 13356  			break
 13357  		}
 13358  		mem := x.Args[2]
 13359  		if p != x.Args[0] {
 13360  			break
 13361  		}
 13362  		if w != x.Args[1] {
 13363  			break
 13364  		}
 13365  		if !(x.Uses == 1 && clobber(x)) {
 13366  			break
 13367  		}
 13368  		v.reset(OpAMD64MOVWstore)
 13369  		v.AuxInt = i - 1
 13370  		v.Aux = s
 13371  		v.AddArg(p)
 13372  		v.AddArg(w)
 13373  		v.AddArg(mem)
 13374  		return true
 13375  	}
 13376  	// match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem))
 13377  	// cond: x.Uses == 1 && clobber(x)
 13378  	// result: (MOVWstore [i-1] {s} p w mem)
 13379  	for {
 13380  		i := v.AuxInt
 13381  		s := v.Aux
 13382  		_ = v.Args[2]
 13383  		p := v.Args[0]
 13384  		v_1 := v.Args[1]
 13385  		if v_1.Op != OpAMD64SHRLconst {
 13386  			break
 13387  		}
 13388  		if v_1.AuxInt != 8 {
 13389  			break
 13390  		}
 13391  		w := v_1.Args[0]
 13392  		x := v.Args[2]
 13393  		if x.Op != OpAMD64MOVBstore {
 13394  			break
 13395  		}
 13396  		if x.AuxInt != i-1 {
 13397  			break
 13398  		}
 13399  		if x.Aux != s {
 13400  			break
 13401  		}
 13402  		mem := x.Args[2]
 13403  		if p != x.Args[0] {
 13404  			break
 13405  		}
 13406  		if w != x.Args[1] {
 13407  			break
 13408  		}
 13409  		if !(x.Uses == 1 && clobber(x)) {
 13410  			break
 13411  		}
 13412  		v.reset(OpAMD64MOVWstore)
 13413  		v.AuxInt = i - 1
 13414  		v.Aux = s
 13415  		v.AddArg(p)
 13416  		v.AddArg(w)
 13417  		v.AddArg(mem)
 13418  		return true
 13419  	}
 13420  	// match: (MOVBstore [i] {s} p (SHRQconst [8] w) x:(MOVBstore [i-1] {s} p w mem))
 13421  	// cond: x.Uses == 1 && clobber(x)
 13422  	/