Source file src/cmd/compile/internal/ssa/rewrite386.go

Documentation: cmd/compile/internal/ssa

     1  // Code generated from gen/386.rules; DO NOT EDIT.
     2  // generated with: cd gen; go run *.go
     3  
     4  package ssa
     5  
     6  import "fmt"
     7  import "math"
     8  import "cmd/internal/obj"
     9  import "cmd/internal/objabi"
    10  import "cmd/compile/internal/types"
    11  
    12  var _ = fmt.Println   // in case not otherwise used
    13  var _ = math.MinInt8  // in case not otherwise used
    14  var _ = obj.ANOP      // in case not otherwise used
    15  var _ = objabi.GOROOT // in case not otherwise used
    16  var _ = types.TypeMem // in case not otherwise used
    17  
    18  func rewriteValue386(v *Value) bool {
    19  	switch v.Op {
    20  	case Op386ADCL:
    21  		return rewriteValue386_Op386ADCL_0(v)
    22  	case Op386ADDL:
    23  		return rewriteValue386_Op386ADDL_0(v) || rewriteValue386_Op386ADDL_10(v) || rewriteValue386_Op386ADDL_20(v)
    24  	case Op386ADDLcarry:
    25  		return rewriteValue386_Op386ADDLcarry_0(v)
    26  	case Op386ADDLconst:
    27  		return rewriteValue386_Op386ADDLconst_0(v)
    28  	case Op386ADDLconstmodify:
    29  		return rewriteValue386_Op386ADDLconstmodify_0(v)
    30  	case Op386ADDLconstmodifyidx4:
    31  		return rewriteValue386_Op386ADDLconstmodifyidx4_0(v)
    32  	case Op386ADDLload:
    33  		return rewriteValue386_Op386ADDLload_0(v)
    34  	case Op386ADDLloadidx4:
    35  		return rewriteValue386_Op386ADDLloadidx4_0(v)
    36  	case Op386ADDLmodify:
    37  		return rewriteValue386_Op386ADDLmodify_0(v)
    38  	case Op386ADDLmodifyidx4:
    39  		return rewriteValue386_Op386ADDLmodifyidx4_0(v)
    40  	case Op386ADDSD:
    41  		return rewriteValue386_Op386ADDSD_0(v)
    42  	case Op386ADDSDload:
    43  		return rewriteValue386_Op386ADDSDload_0(v)
    44  	case Op386ADDSS:
    45  		return rewriteValue386_Op386ADDSS_0(v)
    46  	case Op386ADDSSload:
    47  		return rewriteValue386_Op386ADDSSload_0(v)
    48  	case Op386ANDL:
    49  		return rewriteValue386_Op386ANDL_0(v)
    50  	case Op386ANDLconst:
    51  		return rewriteValue386_Op386ANDLconst_0(v)
    52  	case Op386ANDLconstmodify:
    53  		return rewriteValue386_Op386ANDLconstmodify_0(v)
    54  	case Op386ANDLconstmodifyidx4:
    55  		return rewriteValue386_Op386ANDLconstmodifyidx4_0(v)
    56  	case Op386ANDLload:
    57  		return rewriteValue386_Op386ANDLload_0(v)
    58  	case Op386ANDLloadidx4:
    59  		return rewriteValue386_Op386ANDLloadidx4_0(v)
    60  	case Op386ANDLmodify:
    61  		return rewriteValue386_Op386ANDLmodify_0(v)
    62  	case Op386ANDLmodifyidx4:
    63  		return rewriteValue386_Op386ANDLmodifyidx4_0(v)
    64  	case Op386CMPB:
    65  		return rewriteValue386_Op386CMPB_0(v)
    66  	case Op386CMPBconst:
    67  		return rewriteValue386_Op386CMPBconst_0(v)
    68  	case Op386CMPBload:
    69  		return rewriteValue386_Op386CMPBload_0(v)
    70  	case Op386CMPL:
    71  		return rewriteValue386_Op386CMPL_0(v)
    72  	case Op386CMPLconst:
    73  		return rewriteValue386_Op386CMPLconst_0(v) || rewriteValue386_Op386CMPLconst_10(v)
    74  	case Op386CMPLload:
    75  		return rewriteValue386_Op386CMPLload_0(v)
    76  	case Op386CMPW:
    77  		return rewriteValue386_Op386CMPW_0(v)
    78  	case Op386CMPWconst:
    79  		return rewriteValue386_Op386CMPWconst_0(v)
    80  	case Op386CMPWload:
    81  		return rewriteValue386_Op386CMPWload_0(v)
    82  	case Op386DIVSD:
    83  		return rewriteValue386_Op386DIVSD_0(v)
    84  	case Op386DIVSDload:
    85  		return rewriteValue386_Op386DIVSDload_0(v)
    86  	case Op386DIVSS:
    87  		return rewriteValue386_Op386DIVSS_0(v)
    88  	case Op386DIVSSload:
    89  		return rewriteValue386_Op386DIVSSload_0(v)
    90  	case Op386LEAL:
    91  		return rewriteValue386_Op386LEAL_0(v)
    92  	case Op386LEAL1:
    93  		return rewriteValue386_Op386LEAL1_0(v)
    94  	case Op386LEAL2:
    95  		return rewriteValue386_Op386LEAL2_0(v)
    96  	case Op386LEAL4:
    97  		return rewriteValue386_Op386LEAL4_0(v)
    98  	case Op386LEAL8:
    99  		return rewriteValue386_Op386LEAL8_0(v)
   100  	case Op386MOVBLSX:
   101  		return rewriteValue386_Op386MOVBLSX_0(v)
   102  	case Op386MOVBLSXload:
   103  		return rewriteValue386_Op386MOVBLSXload_0(v)
   104  	case Op386MOVBLZX:
   105  		return rewriteValue386_Op386MOVBLZX_0(v)
   106  	case Op386MOVBload:
   107  		return rewriteValue386_Op386MOVBload_0(v)
   108  	case Op386MOVBloadidx1:
   109  		return rewriteValue386_Op386MOVBloadidx1_0(v)
   110  	case Op386MOVBstore:
   111  		return rewriteValue386_Op386MOVBstore_0(v) || rewriteValue386_Op386MOVBstore_10(v)
   112  	case Op386MOVBstoreconst:
   113  		return rewriteValue386_Op386MOVBstoreconst_0(v)
   114  	case Op386MOVBstoreconstidx1:
   115  		return rewriteValue386_Op386MOVBstoreconstidx1_0(v)
   116  	case Op386MOVBstoreidx1:
   117  		return rewriteValue386_Op386MOVBstoreidx1_0(v) || rewriteValue386_Op386MOVBstoreidx1_10(v) || rewriteValue386_Op386MOVBstoreidx1_20(v)
   118  	case Op386MOVLload:
   119  		return rewriteValue386_Op386MOVLload_0(v)
   120  	case Op386MOVLloadidx1:
   121  		return rewriteValue386_Op386MOVLloadidx1_0(v)
   122  	case Op386MOVLloadidx4:
   123  		return rewriteValue386_Op386MOVLloadidx4_0(v)
   124  	case Op386MOVLstore:
   125  		return rewriteValue386_Op386MOVLstore_0(v) || rewriteValue386_Op386MOVLstore_10(v) || rewriteValue386_Op386MOVLstore_20(v)
   126  	case Op386MOVLstoreconst:
   127  		return rewriteValue386_Op386MOVLstoreconst_0(v)
   128  	case Op386MOVLstoreconstidx1:
   129  		return rewriteValue386_Op386MOVLstoreconstidx1_0(v)
   130  	case Op386MOVLstoreconstidx4:
   131  		return rewriteValue386_Op386MOVLstoreconstidx4_0(v)
   132  	case Op386MOVLstoreidx1:
   133  		return rewriteValue386_Op386MOVLstoreidx1_0(v)
   134  	case Op386MOVLstoreidx4:
   135  		return rewriteValue386_Op386MOVLstoreidx4_0(v) || rewriteValue386_Op386MOVLstoreidx4_10(v)
   136  	case Op386MOVSDconst:
   137  		return rewriteValue386_Op386MOVSDconst_0(v)
   138  	case Op386MOVSDload:
   139  		return rewriteValue386_Op386MOVSDload_0(v)
   140  	case Op386MOVSDloadidx1:
   141  		return rewriteValue386_Op386MOVSDloadidx1_0(v)
   142  	case Op386MOVSDloadidx8:
   143  		return rewriteValue386_Op386MOVSDloadidx8_0(v)
   144  	case Op386MOVSDstore:
   145  		return rewriteValue386_Op386MOVSDstore_0(v)
   146  	case Op386MOVSDstoreidx1:
   147  		return rewriteValue386_Op386MOVSDstoreidx1_0(v)
   148  	case Op386MOVSDstoreidx8:
   149  		return rewriteValue386_Op386MOVSDstoreidx8_0(v)
   150  	case Op386MOVSSconst:
   151  		return rewriteValue386_Op386MOVSSconst_0(v)
   152  	case Op386MOVSSload:
   153  		return rewriteValue386_Op386MOVSSload_0(v)
   154  	case Op386MOVSSloadidx1:
   155  		return rewriteValue386_Op386MOVSSloadidx1_0(v)
   156  	case Op386MOVSSloadidx4:
   157  		return rewriteValue386_Op386MOVSSloadidx4_0(v)
   158  	case Op386MOVSSstore:
   159  		return rewriteValue386_Op386MOVSSstore_0(v)
   160  	case Op386MOVSSstoreidx1:
   161  		return rewriteValue386_Op386MOVSSstoreidx1_0(v)
   162  	case Op386MOVSSstoreidx4:
   163  		return rewriteValue386_Op386MOVSSstoreidx4_0(v)
   164  	case Op386MOVWLSX:
   165  		return rewriteValue386_Op386MOVWLSX_0(v)
   166  	case Op386MOVWLSXload:
   167  		return rewriteValue386_Op386MOVWLSXload_0(v)
   168  	case Op386MOVWLZX:
   169  		return rewriteValue386_Op386MOVWLZX_0(v)
   170  	case Op386MOVWload:
   171  		return rewriteValue386_Op386MOVWload_0(v)
   172  	case Op386MOVWloadidx1:
   173  		return rewriteValue386_Op386MOVWloadidx1_0(v)
   174  	case Op386MOVWloadidx2:
   175  		return rewriteValue386_Op386MOVWloadidx2_0(v)
   176  	case Op386MOVWstore:
   177  		return rewriteValue386_Op386MOVWstore_0(v)
   178  	case Op386MOVWstoreconst:
   179  		return rewriteValue386_Op386MOVWstoreconst_0(v)
   180  	case Op386MOVWstoreconstidx1:
   181  		return rewriteValue386_Op386MOVWstoreconstidx1_0(v)
   182  	case Op386MOVWstoreconstidx2:
   183  		return rewriteValue386_Op386MOVWstoreconstidx2_0(v)
   184  	case Op386MOVWstoreidx1:
   185  		return rewriteValue386_Op386MOVWstoreidx1_0(v) || rewriteValue386_Op386MOVWstoreidx1_10(v)
   186  	case Op386MOVWstoreidx2:
   187  		return rewriteValue386_Op386MOVWstoreidx2_0(v)
   188  	case Op386MULL:
   189  		return rewriteValue386_Op386MULL_0(v)
   190  	case Op386MULLconst:
   191  		return rewriteValue386_Op386MULLconst_0(v) || rewriteValue386_Op386MULLconst_10(v) || rewriteValue386_Op386MULLconst_20(v) || rewriteValue386_Op386MULLconst_30(v)
   192  	case Op386MULLload:
   193  		return rewriteValue386_Op386MULLload_0(v)
   194  	case Op386MULLloadidx4:
   195  		return rewriteValue386_Op386MULLloadidx4_0(v)
   196  	case Op386MULSD:
   197  		return rewriteValue386_Op386MULSD_0(v)
   198  	case Op386MULSDload:
   199  		return rewriteValue386_Op386MULSDload_0(v)
   200  	case Op386MULSS:
   201  		return rewriteValue386_Op386MULSS_0(v)
   202  	case Op386MULSSload:
   203  		return rewriteValue386_Op386MULSSload_0(v)
   204  	case Op386NEGL:
   205  		return rewriteValue386_Op386NEGL_0(v)
   206  	case Op386NOTL:
   207  		return rewriteValue386_Op386NOTL_0(v)
   208  	case Op386ORL:
   209  		return rewriteValue386_Op386ORL_0(v) || rewriteValue386_Op386ORL_10(v) || rewriteValue386_Op386ORL_20(v) || rewriteValue386_Op386ORL_30(v) || rewriteValue386_Op386ORL_40(v) || rewriteValue386_Op386ORL_50(v)
   210  	case Op386ORLconst:
   211  		return rewriteValue386_Op386ORLconst_0(v)
   212  	case Op386ORLconstmodify:
   213  		return rewriteValue386_Op386ORLconstmodify_0(v)
   214  	case Op386ORLconstmodifyidx4:
   215  		return rewriteValue386_Op386ORLconstmodifyidx4_0(v)
   216  	case Op386ORLload:
   217  		return rewriteValue386_Op386ORLload_0(v)
   218  	case Op386ORLloadidx4:
   219  		return rewriteValue386_Op386ORLloadidx4_0(v)
   220  	case Op386ORLmodify:
   221  		return rewriteValue386_Op386ORLmodify_0(v)
   222  	case Op386ORLmodifyidx4:
   223  		return rewriteValue386_Op386ORLmodifyidx4_0(v)
   224  	case Op386ROLBconst:
   225  		return rewriteValue386_Op386ROLBconst_0(v)
   226  	case Op386ROLLconst:
   227  		return rewriteValue386_Op386ROLLconst_0(v)
   228  	case Op386ROLWconst:
   229  		return rewriteValue386_Op386ROLWconst_0(v)
   230  	case Op386SARB:
   231  		return rewriteValue386_Op386SARB_0(v)
   232  	case Op386SARBconst:
   233  		return rewriteValue386_Op386SARBconst_0(v)
   234  	case Op386SARL:
   235  		return rewriteValue386_Op386SARL_0(v)
   236  	case Op386SARLconst:
   237  		return rewriteValue386_Op386SARLconst_0(v)
   238  	case Op386SARW:
   239  		return rewriteValue386_Op386SARW_0(v)
   240  	case Op386SARWconst:
   241  		return rewriteValue386_Op386SARWconst_0(v)
   242  	case Op386SBBL:
   243  		return rewriteValue386_Op386SBBL_0(v)
   244  	case Op386SBBLcarrymask:
   245  		return rewriteValue386_Op386SBBLcarrymask_0(v)
   246  	case Op386SETA:
   247  		return rewriteValue386_Op386SETA_0(v)
   248  	case Op386SETAE:
   249  		return rewriteValue386_Op386SETAE_0(v)
   250  	case Op386SETB:
   251  		return rewriteValue386_Op386SETB_0(v)
   252  	case Op386SETBE:
   253  		return rewriteValue386_Op386SETBE_0(v)
   254  	case Op386SETEQ:
   255  		return rewriteValue386_Op386SETEQ_0(v)
   256  	case Op386SETG:
   257  		return rewriteValue386_Op386SETG_0(v)
   258  	case Op386SETGE:
   259  		return rewriteValue386_Op386SETGE_0(v)
   260  	case Op386SETL:
   261  		return rewriteValue386_Op386SETL_0(v)
   262  	case Op386SETLE:
   263  		return rewriteValue386_Op386SETLE_0(v)
   264  	case Op386SETNE:
   265  		return rewriteValue386_Op386SETNE_0(v)
   266  	case Op386SHLL:
   267  		return rewriteValue386_Op386SHLL_0(v)
   268  	case Op386SHLLconst:
   269  		return rewriteValue386_Op386SHLLconst_0(v)
   270  	case Op386SHRB:
   271  		return rewriteValue386_Op386SHRB_0(v)
   272  	case Op386SHRBconst:
   273  		return rewriteValue386_Op386SHRBconst_0(v)
   274  	case Op386SHRL:
   275  		return rewriteValue386_Op386SHRL_0(v)
   276  	case Op386SHRLconst:
   277  		return rewriteValue386_Op386SHRLconst_0(v)
   278  	case Op386SHRW:
   279  		return rewriteValue386_Op386SHRW_0(v)
   280  	case Op386SHRWconst:
   281  		return rewriteValue386_Op386SHRWconst_0(v)
   282  	case Op386SUBL:
   283  		return rewriteValue386_Op386SUBL_0(v)
   284  	case Op386SUBLcarry:
   285  		return rewriteValue386_Op386SUBLcarry_0(v)
   286  	case Op386SUBLconst:
   287  		return rewriteValue386_Op386SUBLconst_0(v)
   288  	case Op386SUBLload:
   289  		return rewriteValue386_Op386SUBLload_0(v)
   290  	case Op386SUBLloadidx4:
   291  		return rewriteValue386_Op386SUBLloadidx4_0(v)
   292  	case Op386SUBLmodify:
   293  		return rewriteValue386_Op386SUBLmodify_0(v)
   294  	case Op386SUBLmodifyidx4:
   295  		return rewriteValue386_Op386SUBLmodifyidx4_0(v)
   296  	case Op386SUBSD:
   297  		return rewriteValue386_Op386SUBSD_0(v)
   298  	case Op386SUBSDload:
   299  		return rewriteValue386_Op386SUBSDload_0(v)
   300  	case Op386SUBSS:
   301  		return rewriteValue386_Op386SUBSS_0(v)
   302  	case Op386SUBSSload:
   303  		return rewriteValue386_Op386SUBSSload_0(v)
   304  	case Op386XORL:
   305  		return rewriteValue386_Op386XORL_0(v) || rewriteValue386_Op386XORL_10(v)
   306  	case Op386XORLconst:
   307  		return rewriteValue386_Op386XORLconst_0(v)
   308  	case Op386XORLconstmodify:
   309  		return rewriteValue386_Op386XORLconstmodify_0(v)
   310  	case Op386XORLconstmodifyidx4:
   311  		return rewriteValue386_Op386XORLconstmodifyidx4_0(v)
   312  	case Op386XORLload:
   313  		return rewriteValue386_Op386XORLload_0(v)
   314  	case Op386XORLloadidx4:
   315  		return rewriteValue386_Op386XORLloadidx4_0(v)
   316  	case Op386XORLmodify:
   317  		return rewriteValue386_Op386XORLmodify_0(v)
   318  	case Op386XORLmodifyidx4:
   319  		return rewriteValue386_Op386XORLmodifyidx4_0(v)
   320  	case OpAdd16:
   321  		return rewriteValue386_OpAdd16_0(v)
   322  	case OpAdd32:
   323  		return rewriteValue386_OpAdd32_0(v)
   324  	case OpAdd32F:
   325  		return rewriteValue386_OpAdd32F_0(v)
   326  	case OpAdd32carry:
   327  		return rewriteValue386_OpAdd32carry_0(v)
   328  	case OpAdd32withcarry:
   329  		return rewriteValue386_OpAdd32withcarry_0(v)
   330  	case OpAdd64F:
   331  		return rewriteValue386_OpAdd64F_0(v)
   332  	case OpAdd8:
   333  		return rewriteValue386_OpAdd8_0(v)
   334  	case OpAddPtr:
   335  		return rewriteValue386_OpAddPtr_0(v)
   336  	case OpAddr:
   337  		return rewriteValue386_OpAddr_0(v)
   338  	case OpAnd16:
   339  		return rewriteValue386_OpAnd16_0(v)
   340  	case OpAnd32:
   341  		return rewriteValue386_OpAnd32_0(v)
   342  	case OpAnd8:
   343  		return rewriteValue386_OpAnd8_0(v)
   344  	case OpAndB:
   345  		return rewriteValue386_OpAndB_0(v)
   346  	case OpAvg32u:
   347  		return rewriteValue386_OpAvg32u_0(v)
   348  	case OpBswap32:
   349  		return rewriteValue386_OpBswap32_0(v)
   350  	case OpClosureCall:
   351  		return rewriteValue386_OpClosureCall_0(v)
   352  	case OpCom16:
   353  		return rewriteValue386_OpCom16_0(v)
   354  	case OpCom32:
   355  		return rewriteValue386_OpCom32_0(v)
   356  	case OpCom8:
   357  		return rewriteValue386_OpCom8_0(v)
   358  	case OpConst16:
   359  		return rewriteValue386_OpConst16_0(v)
   360  	case OpConst32:
   361  		return rewriteValue386_OpConst32_0(v)
   362  	case OpConst32F:
   363  		return rewriteValue386_OpConst32F_0(v)
   364  	case OpConst64F:
   365  		return rewriteValue386_OpConst64F_0(v)
   366  	case OpConst8:
   367  		return rewriteValue386_OpConst8_0(v)
   368  	case OpConstBool:
   369  		return rewriteValue386_OpConstBool_0(v)
   370  	case OpConstNil:
   371  		return rewriteValue386_OpConstNil_0(v)
   372  	case OpCvt32Fto32:
   373  		return rewriteValue386_OpCvt32Fto32_0(v)
   374  	case OpCvt32Fto64F:
   375  		return rewriteValue386_OpCvt32Fto64F_0(v)
   376  	case OpCvt32to32F:
   377  		return rewriteValue386_OpCvt32to32F_0(v)
   378  	case OpCvt32to64F:
   379  		return rewriteValue386_OpCvt32to64F_0(v)
   380  	case OpCvt64Fto32:
   381  		return rewriteValue386_OpCvt64Fto32_0(v)
   382  	case OpCvt64Fto32F:
   383  		return rewriteValue386_OpCvt64Fto32F_0(v)
   384  	case OpDiv16:
   385  		return rewriteValue386_OpDiv16_0(v)
   386  	case OpDiv16u:
   387  		return rewriteValue386_OpDiv16u_0(v)
   388  	case OpDiv32:
   389  		return rewriteValue386_OpDiv32_0(v)
   390  	case OpDiv32F:
   391  		return rewriteValue386_OpDiv32F_0(v)
   392  	case OpDiv32u:
   393  		return rewriteValue386_OpDiv32u_0(v)
   394  	case OpDiv64F:
   395  		return rewriteValue386_OpDiv64F_0(v)
   396  	case OpDiv8:
   397  		return rewriteValue386_OpDiv8_0(v)
   398  	case OpDiv8u:
   399  		return rewriteValue386_OpDiv8u_0(v)
   400  	case OpEq16:
   401  		return rewriteValue386_OpEq16_0(v)
   402  	case OpEq32:
   403  		return rewriteValue386_OpEq32_0(v)
   404  	case OpEq32F:
   405  		return rewriteValue386_OpEq32F_0(v)
   406  	case OpEq64F:
   407  		return rewriteValue386_OpEq64F_0(v)
   408  	case OpEq8:
   409  		return rewriteValue386_OpEq8_0(v)
   410  	case OpEqB:
   411  		return rewriteValue386_OpEqB_0(v)
   412  	case OpEqPtr:
   413  		return rewriteValue386_OpEqPtr_0(v)
   414  	case OpGeq16:
   415  		return rewriteValue386_OpGeq16_0(v)
   416  	case OpGeq16U:
   417  		return rewriteValue386_OpGeq16U_0(v)
   418  	case OpGeq32:
   419  		return rewriteValue386_OpGeq32_0(v)
   420  	case OpGeq32F:
   421  		return rewriteValue386_OpGeq32F_0(v)
   422  	case OpGeq32U:
   423  		return rewriteValue386_OpGeq32U_0(v)
   424  	case OpGeq64F:
   425  		return rewriteValue386_OpGeq64F_0(v)
   426  	case OpGeq8:
   427  		return rewriteValue386_OpGeq8_0(v)
   428  	case OpGeq8U:
   429  		return rewriteValue386_OpGeq8U_0(v)
   430  	case OpGetCallerPC:
   431  		return rewriteValue386_OpGetCallerPC_0(v)
   432  	case OpGetCallerSP:
   433  		return rewriteValue386_OpGetCallerSP_0(v)
   434  	case OpGetClosurePtr:
   435  		return rewriteValue386_OpGetClosurePtr_0(v)
   436  	case OpGetG:
   437  		return rewriteValue386_OpGetG_0(v)
   438  	case OpGreater16:
   439  		return rewriteValue386_OpGreater16_0(v)
   440  	case OpGreater16U:
   441  		return rewriteValue386_OpGreater16U_0(v)
   442  	case OpGreater32:
   443  		return rewriteValue386_OpGreater32_0(v)
   444  	case OpGreater32F:
   445  		return rewriteValue386_OpGreater32F_0(v)
   446  	case OpGreater32U:
   447  		return rewriteValue386_OpGreater32U_0(v)
   448  	case OpGreater64F:
   449  		return rewriteValue386_OpGreater64F_0(v)
   450  	case OpGreater8:
   451  		return rewriteValue386_OpGreater8_0(v)
   452  	case OpGreater8U:
   453  		return rewriteValue386_OpGreater8U_0(v)
   454  	case OpHmul32:
   455  		return rewriteValue386_OpHmul32_0(v)
   456  	case OpHmul32u:
   457  		return rewriteValue386_OpHmul32u_0(v)
   458  	case OpInterCall:
   459  		return rewriteValue386_OpInterCall_0(v)
   460  	case OpIsInBounds:
   461  		return rewriteValue386_OpIsInBounds_0(v)
   462  	case OpIsNonNil:
   463  		return rewriteValue386_OpIsNonNil_0(v)
   464  	case OpIsSliceInBounds:
   465  		return rewriteValue386_OpIsSliceInBounds_0(v)
   466  	case OpLeq16:
   467  		return rewriteValue386_OpLeq16_0(v)
   468  	case OpLeq16U:
   469  		return rewriteValue386_OpLeq16U_0(v)
   470  	case OpLeq32:
   471  		return rewriteValue386_OpLeq32_0(v)
   472  	case OpLeq32F:
   473  		return rewriteValue386_OpLeq32F_0(v)
   474  	case OpLeq32U:
   475  		return rewriteValue386_OpLeq32U_0(v)
   476  	case OpLeq64F:
   477  		return rewriteValue386_OpLeq64F_0(v)
   478  	case OpLeq8:
   479  		return rewriteValue386_OpLeq8_0(v)
   480  	case OpLeq8U:
   481  		return rewriteValue386_OpLeq8U_0(v)
   482  	case OpLess16:
   483  		return rewriteValue386_OpLess16_0(v)
   484  	case OpLess16U:
   485  		return rewriteValue386_OpLess16U_0(v)
   486  	case OpLess32:
   487  		return rewriteValue386_OpLess32_0(v)
   488  	case OpLess32F:
   489  		return rewriteValue386_OpLess32F_0(v)
   490  	case OpLess32U:
   491  		return rewriteValue386_OpLess32U_0(v)
   492  	case OpLess64F:
   493  		return rewriteValue386_OpLess64F_0(v)
   494  	case OpLess8:
   495  		return rewriteValue386_OpLess8_0(v)
   496  	case OpLess8U:
   497  		return rewriteValue386_OpLess8U_0(v)
   498  	case OpLoad:
   499  		return rewriteValue386_OpLoad_0(v)
   500  	case OpLocalAddr:
   501  		return rewriteValue386_OpLocalAddr_0(v)
   502  	case OpLsh16x16:
   503  		return rewriteValue386_OpLsh16x16_0(v)
   504  	case OpLsh16x32:
   505  		return rewriteValue386_OpLsh16x32_0(v)
   506  	case OpLsh16x64:
   507  		return rewriteValue386_OpLsh16x64_0(v)
   508  	case OpLsh16x8:
   509  		return rewriteValue386_OpLsh16x8_0(v)
   510  	case OpLsh32x16:
   511  		return rewriteValue386_OpLsh32x16_0(v)
   512  	case OpLsh32x32:
   513  		return rewriteValue386_OpLsh32x32_0(v)
   514  	case OpLsh32x64:
   515  		return rewriteValue386_OpLsh32x64_0(v)
   516  	case OpLsh32x8:
   517  		return rewriteValue386_OpLsh32x8_0(v)
   518  	case OpLsh8x16:
   519  		return rewriteValue386_OpLsh8x16_0(v)
   520  	case OpLsh8x32:
   521  		return rewriteValue386_OpLsh8x32_0(v)
   522  	case OpLsh8x64:
   523  		return rewriteValue386_OpLsh8x64_0(v)
   524  	case OpLsh8x8:
   525  		return rewriteValue386_OpLsh8x8_0(v)
   526  	case OpMod16:
   527  		return rewriteValue386_OpMod16_0(v)
   528  	case OpMod16u:
   529  		return rewriteValue386_OpMod16u_0(v)
   530  	case OpMod32:
   531  		return rewriteValue386_OpMod32_0(v)
   532  	case OpMod32u:
   533  		return rewriteValue386_OpMod32u_0(v)
   534  	case OpMod8:
   535  		return rewriteValue386_OpMod8_0(v)
   536  	case OpMod8u:
   537  		return rewriteValue386_OpMod8u_0(v)
   538  	case OpMove:
   539  		return rewriteValue386_OpMove_0(v) || rewriteValue386_OpMove_10(v)
   540  	case OpMul16:
   541  		return rewriteValue386_OpMul16_0(v)
   542  	case OpMul32:
   543  		return rewriteValue386_OpMul32_0(v)
   544  	case OpMul32F:
   545  		return rewriteValue386_OpMul32F_0(v)
   546  	case OpMul32uhilo:
   547  		return rewriteValue386_OpMul32uhilo_0(v)
   548  	case OpMul64F:
   549  		return rewriteValue386_OpMul64F_0(v)
   550  	case OpMul8:
   551  		return rewriteValue386_OpMul8_0(v)
   552  	case OpNeg16:
   553  		return rewriteValue386_OpNeg16_0(v)
   554  	case OpNeg32:
   555  		return rewriteValue386_OpNeg32_0(v)
   556  	case OpNeg32F:
   557  		return rewriteValue386_OpNeg32F_0(v)
   558  	case OpNeg64F:
   559  		return rewriteValue386_OpNeg64F_0(v)
   560  	case OpNeg8:
   561  		return rewriteValue386_OpNeg8_0(v)
   562  	case OpNeq16:
   563  		return rewriteValue386_OpNeq16_0(v)
   564  	case OpNeq32:
   565  		return rewriteValue386_OpNeq32_0(v)
   566  	case OpNeq32F:
   567  		return rewriteValue386_OpNeq32F_0(v)
   568  	case OpNeq64F:
   569  		return rewriteValue386_OpNeq64F_0(v)
   570  	case OpNeq8:
   571  		return rewriteValue386_OpNeq8_0(v)
   572  	case OpNeqB:
   573  		return rewriteValue386_OpNeqB_0(v)
   574  	case OpNeqPtr:
   575  		return rewriteValue386_OpNeqPtr_0(v)
   576  	case OpNilCheck:
   577  		return rewriteValue386_OpNilCheck_0(v)
   578  	case OpNot:
   579  		return rewriteValue386_OpNot_0(v)
   580  	case OpOffPtr:
   581  		return rewriteValue386_OpOffPtr_0(v)
   582  	case OpOr16:
   583  		return rewriteValue386_OpOr16_0(v)
   584  	case OpOr32:
   585  		return rewriteValue386_OpOr32_0(v)
   586  	case OpOr8:
   587  		return rewriteValue386_OpOr8_0(v)
   588  	case OpOrB:
   589  		return rewriteValue386_OpOrB_0(v)
   590  	case OpPanicBounds:
   591  		return rewriteValue386_OpPanicBounds_0(v)
   592  	case OpPanicExtend:
   593  		return rewriteValue386_OpPanicExtend_0(v)
   594  	case OpRotateLeft16:
   595  		return rewriteValue386_OpRotateLeft16_0(v)
   596  	case OpRotateLeft32:
   597  		return rewriteValue386_OpRotateLeft32_0(v)
   598  	case OpRotateLeft8:
   599  		return rewriteValue386_OpRotateLeft8_0(v)
   600  	case OpRound32F:
   601  		return rewriteValue386_OpRound32F_0(v)
   602  	case OpRound64F:
   603  		return rewriteValue386_OpRound64F_0(v)
   604  	case OpRsh16Ux16:
   605  		return rewriteValue386_OpRsh16Ux16_0(v)
   606  	case OpRsh16Ux32:
   607  		return rewriteValue386_OpRsh16Ux32_0(v)
   608  	case OpRsh16Ux64:
   609  		return rewriteValue386_OpRsh16Ux64_0(v)
   610  	case OpRsh16Ux8:
   611  		return rewriteValue386_OpRsh16Ux8_0(v)
   612  	case OpRsh16x16:
   613  		return rewriteValue386_OpRsh16x16_0(v)
   614  	case OpRsh16x32:
   615  		return rewriteValue386_OpRsh16x32_0(v)
   616  	case OpRsh16x64:
   617  		return rewriteValue386_OpRsh16x64_0(v)
   618  	case OpRsh16x8:
   619  		return rewriteValue386_OpRsh16x8_0(v)
   620  	case OpRsh32Ux16:
   621  		return rewriteValue386_OpRsh32Ux16_0(v)
   622  	case OpRsh32Ux32:
   623  		return rewriteValue386_OpRsh32Ux32_0(v)
   624  	case OpRsh32Ux64:
   625  		return rewriteValue386_OpRsh32Ux64_0(v)
   626  	case OpRsh32Ux8:
   627  		return rewriteValue386_OpRsh32Ux8_0(v)
   628  	case OpRsh32x16:
   629  		return rewriteValue386_OpRsh32x16_0(v)
   630  	case OpRsh32x32:
   631  		return rewriteValue386_OpRsh32x32_0(v)
   632  	case OpRsh32x64:
   633  		return rewriteValue386_OpRsh32x64_0(v)
   634  	case OpRsh32x8:
   635  		return rewriteValue386_OpRsh32x8_0(v)
   636  	case OpRsh8Ux16:
   637  		return rewriteValue386_OpRsh8Ux16_0(v)
   638  	case OpRsh8Ux32:
   639  		return rewriteValue386_OpRsh8Ux32_0(v)
   640  	case OpRsh8Ux64:
   641  		return rewriteValue386_OpRsh8Ux64_0(v)
   642  	case OpRsh8Ux8:
   643  		return rewriteValue386_OpRsh8Ux8_0(v)
   644  	case OpRsh8x16:
   645  		return rewriteValue386_OpRsh8x16_0(v)
   646  	case OpRsh8x32:
   647  		return rewriteValue386_OpRsh8x32_0(v)
   648  	case OpRsh8x64:
   649  		return rewriteValue386_OpRsh8x64_0(v)
   650  	case OpRsh8x8:
   651  		return rewriteValue386_OpRsh8x8_0(v)
   652  	case OpSelect0:
   653  		return rewriteValue386_OpSelect0_0(v)
   654  	case OpSelect1:
   655  		return rewriteValue386_OpSelect1_0(v)
   656  	case OpSignExt16to32:
   657  		return rewriteValue386_OpSignExt16to32_0(v)
   658  	case OpSignExt8to16:
   659  		return rewriteValue386_OpSignExt8to16_0(v)
   660  	case OpSignExt8to32:
   661  		return rewriteValue386_OpSignExt8to32_0(v)
   662  	case OpSignmask:
   663  		return rewriteValue386_OpSignmask_0(v)
   664  	case OpSlicemask:
   665  		return rewriteValue386_OpSlicemask_0(v)
   666  	case OpSqrt:
   667  		return rewriteValue386_OpSqrt_0(v)
   668  	case OpStaticCall:
   669  		return rewriteValue386_OpStaticCall_0(v)
   670  	case OpStore:
   671  		return rewriteValue386_OpStore_0(v)
   672  	case OpSub16:
   673  		return rewriteValue386_OpSub16_0(v)
   674  	case OpSub32:
   675  		return rewriteValue386_OpSub32_0(v)
   676  	case OpSub32F:
   677  		return rewriteValue386_OpSub32F_0(v)
   678  	case OpSub32carry:
   679  		return rewriteValue386_OpSub32carry_0(v)
   680  	case OpSub32withcarry:
   681  		return rewriteValue386_OpSub32withcarry_0(v)
   682  	case OpSub64F:
   683  		return rewriteValue386_OpSub64F_0(v)
   684  	case OpSub8:
   685  		return rewriteValue386_OpSub8_0(v)
   686  	case OpSubPtr:
   687  		return rewriteValue386_OpSubPtr_0(v)
   688  	case OpTrunc16to8:
   689  		return rewriteValue386_OpTrunc16to8_0(v)
   690  	case OpTrunc32to16:
   691  		return rewriteValue386_OpTrunc32to16_0(v)
   692  	case OpTrunc32to8:
   693  		return rewriteValue386_OpTrunc32to8_0(v)
   694  	case OpWB:
   695  		return rewriteValue386_OpWB_0(v)
   696  	case OpXor16:
   697  		return rewriteValue386_OpXor16_0(v)
   698  	case OpXor32:
   699  		return rewriteValue386_OpXor32_0(v)
   700  	case OpXor8:
   701  		return rewriteValue386_OpXor8_0(v)
   702  	case OpZero:
   703  		return rewriteValue386_OpZero_0(v) || rewriteValue386_OpZero_10(v)
   704  	case OpZeroExt16to32:
   705  		return rewriteValue386_OpZeroExt16to32_0(v)
   706  	case OpZeroExt8to16:
   707  		return rewriteValue386_OpZeroExt8to16_0(v)
   708  	case OpZeroExt8to32:
   709  		return rewriteValue386_OpZeroExt8to32_0(v)
   710  	case OpZeromask:
   711  		return rewriteValue386_OpZeromask_0(v)
   712  	}
   713  	return false
   714  }
   715  func rewriteValue386_Op386ADCL_0(v *Value) bool {
   716  	// match: (ADCL x (MOVLconst [c]) f)
   717  	// cond:
   718  	// result: (ADCLconst [c] x f)
   719  	for {
   720  		f := v.Args[2]
   721  		x := v.Args[0]
   722  		v_1 := v.Args[1]
   723  		if v_1.Op != Op386MOVLconst {
   724  			break
   725  		}
   726  		c := v_1.AuxInt
   727  		v.reset(Op386ADCLconst)
   728  		v.AuxInt = c
   729  		v.AddArg(x)
   730  		v.AddArg(f)
   731  		return true
   732  	}
   733  	// match: (ADCL (MOVLconst [c]) x f)
   734  	// cond:
   735  	// result: (ADCLconst [c] x f)
   736  	for {
   737  		f := v.Args[2]
   738  		v_0 := v.Args[0]
   739  		if v_0.Op != Op386MOVLconst {
   740  			break
   741  		}
   742  		c := v_0.AuxInt
   743  		x := v.Args[1]
   744  		v.reset(Op386ADCLconst)
   745  		v.AuxInt = c
   746  		v.AddArg(x)
   747  		v.AddArg(f)
   748  		return true
   749  	}
   750  	// match: (ADCL (MOVLconst [c]) x f)
   751  	// cond:
   752  	// result: (ADCLconst [c] x f)
   753  	for {
   754  		f := v.Args[2]
   755  		v_0 := v.Args[0]
   756  		if v_0.Op != Op386MOVLconst {
   757  			break
   758  		}
   759  		c := v_0.AuxInt
   760  		x := v.Args[1]
   761  		v.reset(Op386ADCLconst)
   762  		v.AuxInt = c
   763  		v.AddArg(x)
   764  		v.AddArg(f)
   765  		return true
   766  	}
   767  	// match: (ADCL x (MOVLconst [c]) f)
   768  	// cond:
   769  	// result: (ADCLconst [c] x f)
   770  	for {
   771  		f := v.Args[2]
   772  		x := v.Args[0]
   773  		v_1 := v.Args[1]
   774  		if v_1.Op != Op386MOVLconst {
   775  			break
   776  		}
   777  		c := v_1.AuxInt
   778  		v.reset(Op386ADCLconst)
   779  		v.AuxInt = c
   780  		v.AddArg(x)
   781  		v.AddArg(f)
   782  		return true
   783  	}
   784  	return false
   785  }
   786  func rewriteValue386_Op386ADDL_0(v *Value) bool {
   787  	// match: (ADDL x (MOVLconst [c]))
   788  	// cond:
   789  	// result: (ADDLconst [c] x)
   790  	for {
   791  		_ = v.Args[1]
   792  		x := v.Args[0]
   793  		v_1 := v.Args[1]
   794  		if v_1.Op != Op386MOVLconst {
   795  			break
   796  		}
   797  		c := v_1.AuxInt
   798  		v.reset(Op386ADDLconst)
   799  		v.AuxInt = c
   800  		v.AddArg(x)
   801  		return true
   802  	}
   803  	// match: (ADDL (MOVLconst [c]) x)
   804  	// cond:
   805  	// result: (ADDLconst [c] x)
   806  	for {
   807  		x := v.Args[1]
   808  		v_0 := v.Args[0]
   809  		if v_0.Op != Op386MOVLconst {
   810  			break
   811  		}
   812  		c := v_0.AuxInt
   813  		v.reset(Op386ADDLconst)
   814  		v.AuxInt = c
   815  		v.AddArg(x)
   816  		return true
   817  	}
   818  	// match: (ADDL (SHLLconst [c] x) (SHRLconst [d] x))
   819  	// cond: d == 32-c
   820  	// result: (ROLLconst [c] x)
   821  	for {
   822  		_ = v.Args[1]
   823  		v_0 := v.Args[0]
   824  		if v_0.Op != Op386SHLLconst {
   825  			break
   826  		}
   827  		c := v_0.AuxInt
   828  		x := v_0.Args[0]
   829  		v_1 := v.Args[1]
   830  		if v_1.Op != Op386SHRLconst {
   831  			break
   832  		}
   833  		d := v_1.AuxInt
   834  		if x != v_1.Args[0] {
   835  			break
   836  		}
   837  		if !(d == 32-c) {
   838  			break
   839  		}
   840  		v.reset(Op386ROLLconst)
   841  		v.AuxInt = c
   842  		v.AddArg(x)
   843  		return true
   844  	}
   845  	// match: (ADDL (SHRLconst [d] x) (SHLLconst [c] x))
   846  	// cond: d == 32-c
   847  	// result: (ROLLconst [c] x)
   848  	for {
   849  		_ = v.Args[1]
   850  		v_0 := v.Args[0]
   851  		if v_0.Op != Op386SHRLconst {
   852  			break
   853  		}
   854  		d := v_0.AuxInt
   855  		x := v_0.Args[0]
   856  		v_1 := v.Args[1]
   857  		if v_1.Op != Op386SHLLconst {
   858  			break
   859  		}
   860  		c := v_1.AuxInt
   861  		if x != v_1.Args[0] {
   862  			break
   863  		}
   864  		if !(d == 32-c) {
   865  			break
   866  		}
   867  		v.reset(Op386ROLLconst)
   868  		v.AuxInt = c
   869  		v.AddArg(x)
   870  		return true
   871  	}
   872  	// match: (ADDL <t> (SHLLconst x [c]) (SHRWconst x [d]))
   873  	// cond: c < 16 && d == 16-c && t.Size() == 2
   874  	// result: (ROLWconst x [c])
   875  	for {
   876  		t := v.Type
   877  		_ = v.Args[1]
   878  		v_0 := v.Args[0]
   879  		if v_0.Op != Op386SHLLconst {
   880  			break
   881  		}
   882  		c := v_0.AuxInt
   883  		x := v_0.Args[0]
   884  		v_1 := v.Args[1]
   885  		if v_1.Op != Op386SHRWconst {
   886  			break
   887  		}
   888  		d := v_1.AuxInt
   889  		if x != v_1.Args[0] {
   890  			break
   891  		}
   892  		if !(c < 16 && d == 16-c && t.Size() == 2) {
   893  			break
   894  		}
   895  		v.reset(Op386ROLWconst)
   896  		v.AuxInt = c
   897  		v.AddArg(x)
   898  		return true
   899  	}
   900  	// match: (ADDL <t> (SHRWconst x [d]) (SHLLconst x [c]))
   901  	// cond: c < 16 && d == 16-c && t.Size() == 2
   902  	// result: (ROLWconst x [c])
   903  	for {
   904  		t := v.Type
   905  		_ = v.Args[1]
   906  		v_0 := v.Args[0]
   907  		if v_0.Op != Op386SHRWconst {
   908  			break
   909  		}
   910  		d := v_0.AuxInt
   911  		x := v_0.Args[0]
   912  		v_1 := v.Args[1]
   913  		if v_1.Op != Op386SHLLconst {
   914  			break
   915  		}
   916  		c := v_1.AuxInt
   917  		if x != v_1.Args[0] {
   918  			break
   919  		}
   920  		if !(c < 16 && d == 16-c && t.Size() == 2) {
   921  			break
   922  		}
   923  		v.reset(Op386ROLWconst)
   924  		v.AuxInt = c
   925  		v.AddArg(x)
   926  		return true
   927  	}
   928  	// match: (ADDL <t> (SHLLconst x [c]) (SHRBconst x [d]))
   929  	// cond: c < 8 && d == 8-c && t.Size() == 1
   930  	// result: (ROLBconst x [c])
   931  	for {
   932  		t := v.Type
   933  		_ = v.Args[1]
   934  		v_0 := v.Args[0]
   935  		if v_0.Op != Op386SHLLconst {
   936  			break
   937  		}
   938  		c := v_0.AuxInt
   939  		x := v_0.Args[0]
   940  		v_1 := v.Args[1]
   941  		if v_1.Op != Op386SHRBconst {
   942  			break
   943  		}
   944  		d := v_1.AuxInt
   945  		if x != v_1.Args[0] {
   946  			break
   947  		}
   948  		if !(c < 8 && d == 8-c && t.Size() == 1) {
   949  			break
   950  		}
   951  		v.reset(Op386ROLBconst)
   952  		v.AuxInt = c
   953  		v.AddArg(x)
   954  		return true
   955  	}
   956  	// match: (ADDL <t> (SHRBconst x [d]) (SHLLconst x [c]))
   957  	// cond: c < 8 && d == 8-c && t.Size() == 1
   958  	// result: (ROLBconst x [c])
   959  	for {
   960  		t := v.Type
   961  		_ = v.Args[1]
   962  		v_0 := v.Args[0]
   963  		if v_0.Op != Op386SHRBconst {
   964  			break
   965  		}
   966  		d := v_0.AuxInt
   967  		x := v_0.Args[0]
   968  		v_1 := v.Args[1]
   969  		if v_1.Op != Op386SHLLconst {
   970  			break
   971  		}
   972  		c := v_1.AuxInt
   973  		if x != v_1.Args[0] {
   974  			break
   975  		}
   976  		if !(c < 8 && d == 8-c && t.Size() == 1) {
   977  			break
   978  		}
   979  		v.reset(Op386ROLBconst)
   980  		v.AuxInt = c
   981  		v.AddArg(x)
   982  		return true
   983  	}
   984  	// match: (ADDL x (SHLLconst [3] y))
   985  	// cond:
   986  	// result: (LEAL8 x y)
   987  	for {
   988  		_ = v.Args[1]
   989  		x := v.Args[0]
   990  		v_1 := v.Args[1]
   991  		if v_1.Op != Op386SHLLconst {
   992  			break
   993  		}
   994  		if v_1.AuxInt != 3 {
   995  			break
   996  		}
   997  		y := v_1.Args[0]
   998  		v.reset(Op386LEAL8)
   999  		v.AddArg(x)
  1000  		v.AddArg(y)
  1001  		return true
  1002  	}
  1003  	// match: (ADDL (SHLLconst [3] y) x)
  1004  	// cond:
  1005  	// result: (LEAL8 x y)
  1006  	for {
  1007  		x := v.Args[1]
  1008  		v_0 := v.Args[0]
  1009  		if v_0.Op != Op386SHLLconst {
  1010  			break
  1011  		}
  1012  		if v_0.AuxInt != 3 {
  1013  			break
  1014  		}
  1015  		y := v_0.Args[0]
  1016  		v.reset(Op386LEAL8)
  1017  		v.AddArg(x)
  1018  		v.AddArg(y)
  1019  		return true
  1020  	}
  1021  	return false
  1022  }
  1023  func rewriteValue386_Op386ADDL_10(v *Value) bool {
  1024  	// match: (ADDL x (SHLLconst [2] y))
  1025  	// cond:
  1026  	// result: (LEAL4 x y)
  1027  	for {
  1028  		_ = v.Args[1]
  1029  		x := v.Args[0]
  1030  		v_1 := v.Args[1]
  1031  		if v_1.Op != Op386SHLLconst {
  1032  			break
  1033  		}
  1034  		if v_1.AuxInt != 2 {
  1035  			break
  1036  		}
  1037  		y := v_1.Args[0]
  1038  		v.reset(Op386LEAL4)
  1039  		v.AddArg(x)
  1040  		v.AddArg(y)
  1041  		return true
  1042  	}
  1043  	// match: (ADDL (SHLLconst [2] y) x)
  1044  	// cond:
  1045  	// result: (LEAL4 x y)
  1046  	for {
  1047  		x := v.Args[1]
  1048  		v_0 := v.Args[0]
  1049  		if v_0.Op != Op386SHLLconst {
  1050  			break
  1051  		}
  1052  		if v_0.AuxInt != 2 {
  1053  			break
  1054  		}
  1055  		y := v_0.Args[0]
  1056  		v.reset(Op386LEAL4)
  1057  		v.AddArg(x)
  1058  		v.AddArg(y)
  1059  		return true
  1060  	}
  1061  	// match: (ADDL x (SHLLconst [1] y))
  1062  	// cond:
  1063  	// result: (LEAL2 x y)
  1064  	for {
  1065  		_ = v.Args[1]
  1066  		x := v.Args[0]
  1067  		v_1 := v.Args[1]
  1068  		if v_1.Op != Op386SHLLconst {
  1069  			break
  1070  		}
  1071  		if v_1.AuxInt != 1 {
  1072  			break
  1073  		}
  1074  		y := v_1.Args[0]
  1075  		v.reset(Op386LEAL2)
  1076  		v.AddArg(x)
  1077  		v.AddArg(y)
  1078  		return true
  1079  	}
  1080  	// match: (ADDL (SHLLconst [1] y) x)
  1081  	// cond:
  1082  	// result: (LEAL2 x y)
  1083  	for {
  1084  		x := v.Args[1]
  1085  		v_0 := v.Args[0]
  1086  		if v_0.Op != Op386SHLLconst {
  1087  			break
  1088  		}
  1089  		if v_0.AuxInt != 1 {
  1090  			break
  1091  		}
  1092  		y := v_0.Args[0]
  1093  		v.reset(Op386LEAL2)
  1094  		v.AddArg(x)
  1095  		v.AddArg(y)
  1096  		return true
  1097  	}
  1098  	// match: (ADDL x (ADDL y y))
  1099  	// cond:
  1100  	// result: (LEAL2 x y)
  1101  	for {
  1102  		_ = v.Args[1]
  1103  		x := v.Args[0]
  1104  		v_1 := v.Args[1]
  1105  		if v_1.Op != Op386ADDL {
  1106  			break
  1107  		}
  1108  		y := v_1.Args[1]
  1109  		if y != v_1.Args[0] {
  1110  			break
  1111  		}
  1112  		v.reset(Op386LEAL2)
  1113  		v.AddArg(x)
  1114  		v.AddArg(y)
  1115  		return true
  1116  	}
  1117  	// match: (ADDL (ADDL y y) x)
  1118  	// cond:
  1119  	// result: (LEAL2 x y)
  1120  	for {
  1121  		x := v.Args[1]
  1122  		v_0 := v.Args[0]
  1123  		if v_0.Op != Op386ADDL {
  1124  			break
  1125  		}
  1126  		y := v_0.Args[1]
  1127  		if y != v_0.Args[0] {
  1128  			break
  1129  		}
  1130  		v.reset(Op386LEAL2)
  1131  		v.AddArg(x)
  1132  		v.AddArg(y)
  1133  		return true
  1134  	}
  1135  	// match: (ADDL x (ADDL x y))
  1136  	// cond:
  1137  	// result: (LEAL2 y x)
  1138  	for {
  1139  		_ = v.Args[1]
  1140  		x := v.Args[0]
  1141  		v_1 := v.Args[1]
  1142  		if v_1.Op != Op386ADDL {
  1143  			break
  1144  		}
  1145  		y := v_1.Args[1]
  1146  		if x != v_1.Args[0] {
  1147  			break
  1148  		}
  1149  		v.reset(Op386LEAL2)
  1150  		v.AddArg(y)
  1151  		v.AddArg(x)
  1152  		return true
  1153  	}
  1154  	// match: (ADDL x (ADDL y x))
  1155  	// cond:
  1156  	// result: (LEAL2 y x)
  1157  	for {
  1158  		_ = v.Args[1]
  1159  		x := v.Args[0]
  1160  		v_1 := v.Args[1]
  1161  		if v_1.Op != Op386ADDL {
  1162  			break
  1163  		}
  1164  		_ = v_1.Args[1]
  1165  		y := v_1.Args[0]
  1166  		if x != v_1.Args[1] {
  1167  			break
  1168  		}
  1169  		v.reset(Op386LEAL2)
  1170  		v.AddArg(y)
  1171  		v.AddArg(x)
  1172  		return true
  1173  	}
  1174  	// match: (ADDL (ADDL x y) x)
  1175  	// cond:
  1176  	// result: (LEAL2 y x)
  1177  	for {
  1178  		x := v.Args[1]
  1179  		v_0 := v.Args[0]
  1180  		if v_0.Op != Op386ADDL {
  1181  			break
  1182  		}
  1183  		y := v_0.Args[1]
  1184  		if x != v_0.Args[0] {
  1185  			break
  1186  		}
  1187  		v.reset(Op386LEAL2)
  1188  		v.AddArg(y)
  1189  		v.AddArg(x)
  1190  		return true
  1191  	}
  1192  	// match: (ADDL (ADDL y x) x)
  1193  	// cond:
  1194  	// result: (LEAL2 y x)
  1195  	for {
  1196  		x := v.Args[1]
  1197  		v_0 := v.Args[0]
  1198  		if v_0.Op != Op386ADDL {
  1199  			break
  1200  		}
  1201  		_ = v_0.Args[1]
  1202  		y := v_0.Args[0]
  1203  		if x != v_0.Args[1] {
  1204  			break
  1205  		}
  1206  		v.reset(Op386LEAL2)
  1207  		v.AddArg(y)
  1208  		v.AddArg(x)
  1209  		return true
  1210  	}
  1211  	return false
  1212  }
  1213  func rewriteValue386_Op386ADDL_20(v *Value) bool {
  1214  	// match: (ADDL (ADDLconst [c] x) y)
  1215  	// cond:
  1216  	// result: (LEAL1 [c] x y)
  1217  	for {
  1218  		y := v.Args[1]
  1219  		v_0 := v.Args[0]
  1220  		if v_0.Op != Op386ADDLconst {
  1221  			break
  1222  		}
  1223  		c := v_0.AuxInt
  1224  		x := v_0.Args[0]
  1225  		v.reset(Op386LEAL1)
  1226  		v.AuxInt = c
  1227  		v.AddArg(x)
  1228  		v.AddArg(y)
  1229  		return true
  1230  	}
  1231  	// match: (ADDL y (ADDLconst [c] x))
  1232  	// cond:
  1233  	// result: (LEAL1 [c] x y)
  1234  	for {
  1235  		_ = v.Args[1]
  1236  		y := v.Args[0]
  1237  		v_1 := v.Args[1]
  1238  		if v_1.Op != Op386ADDLconst {
  1239  			break
  1240  		}
  1241  		c := v_1.AuxInt
  1242  		x := v_1.Args[0]
  1243  		v.reset(Op386LEAL1)
  1244  		v.AuxInt = c
  1245  		v.AddArg(x)
  1246  		v.AddArg(y)
  1247  		return true
  1248  	}
  1249  	// match: (ADDL x (LEAL [c] {s} y))
  1250  	// cond: x.Op != OpSB && y.Op != OpSB
  1251  	// result: (LEAL1 [c] {s} x y)
  1252  	for {
  1253  		_ = v.Args[1]
  1254  		x := v.Args[0]
  1255  		v_1 := v.Args[1]
  1256  		if v_1.Op != Op386LEAL {
  1257  			break
  1258  		}
  1259  		c := v_1.AuxInt
  1260  		s := v_1.Aux
  1261  		y := v_1.Args[0]
  1262  		if !(x.Op != OpSB && y.Op != OpSB) {
  1263  			break
  1264  		}
  1265  		v.reset(Op386LEAL1)
  1266  		v.AuxInt = c
  1267  		v.Aux = s
  1268  		v.AddArg(x)
  1269  		v.AddArg(y)
  1270  		return true
  1271  	}
  1272  	// match: (ADDL (LEAL [c] {s} y) x)
  1273  	// cond: x.Op != OpSB && y.Op != OpSB
  1274  	// result: (LEAL1 [c] {s} x y)
  1275  	for {
  1276  		x := v.Args[1]
  1277  		v_0 := v.Args[0]
  1278  		if v_0.Op != Op386LEAL {
  1279  			break
  1280  		}
  1281  		c := v_0.AuxInt
  1282  		s := v_0.Aux
  1283  		y := v_0.Args[0]
  1284  		if !(x.Op != OpSB && y.Op != OpSB) {
  1285  			break
  1286  		}
  1287  		v.reset(Op386LEAL1)
  1288  		v.AuxInt = c
  1289  		v.Aux = s
  1290  		v.AddArg(x)
  1291  		v.AddArg(y)
  1292  		return true
  1293  	}
  1294  	// match: (ADDL x l:(MOVLload [off] {sym} ptr mem))
  1295  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  1296  	// result: (ADDLload x [off] {sym} ptr mem)
  1297  	for {
  1298  		_ = v.Args[1]
  1299  		x := v.Args[0]
  1300  		l := v.Args[1]
  1301  		if l.Op != Op386MOVLload {
  1302  			break
  1303  		}
  1304  		off := l.AuxInt
  1305  		sym := l.Aux
  1306  		mem := l.Args[1]
  1307  		ptr := l.Args[0]
  1308  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  1309  			break
  1310  		}
  1311  		v.reset(Op386ADDLload)
  1312  		v.AuxInt = off
  1313  		v.Aux = sym
  1314  		v.AddArg(x)
  1315  		v.AddArg(ptr)
  1316  		v.AddArg(mem)
  1317  		return true
  1318  	}
  1319  	// match: (ADDL l:(MOVLload [off] {sym} ptr mem) x)
  1320  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  1321  	// result: (ADDLload x [off] {sym} ptr mem)
  1322  	for {
  1323  		x := v.Args[1]
  1324  		l := v.Args[0]
  1325  		if l.Op != Op386MOVLload {
  1326  			break
  1327  		}
  1328  		off := l.AuxInt
  1329  		sym := l.Aux
  1330  		mem := l.Args[1]
  1331  		ptr := l.Args[0]
  1332  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  1333  			break
  1334  		}
  1335  		v.reset(Op386ADDLload)
  1336  		v.AuxInt = off
  1337  		v.Aux = sym
  1338  		v.AddArg(x)
  1339  		v.AddArg(ptr)
  1340  		v.AddArg(mem)
  1341  		return true
  1342  	}
  1343  	// match: (ADDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem))
  1344  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  1345  	// result: (ADDLloadidx4 x [off] {sym} ptr idx mem)
  1346  	for {
  1347  		_ = v.Args[1]
  1348  		x := v.Args[0]
  1349  		l := v.Args[1]
  1350  		if l.Op != Op386MOVLloadidx4 {
  1351  			break
  1352  		}
  1353  		off := l.AuxInt
  1354  		sym := l.Aux
  1355  		mem := l.Args[2]
  1356  		ptr := l.Args[0]
  1357  		idx := l.Args[1]
  1358  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  1359  			break
  1360  		}
  1361  		v.reset(Op386ADDLloadidx4)
  1362  		v.AuxInt = off
  1363  		v.Aux = sym
  1364  		v.AddArg(x)
  1365  		v.AddArg(ptr)
  1366  		v.AddArg(idx)
  1367  		v.AddArg(mem)
  1368  		return true
  1369  	}
  1370  	// match: (ADDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x)
  1371  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  1372  	// result: (ADDLloadidx4 x [off] {sym} ptr idx mem)
  1373  	for {
  1374  		x := v.Args[1]
  1375  		l := v.Args[0]
  1376  		if l.Op != Op386MOVLloadidx4 {
  1377  			break
  1378  		}
  1379  		off := l.AuxInt
  1380  		sym := l.Aux
  1381  		mem := l.Args[2]
  1382  		ptr := l.Args[0]
  1383  		idx := l.Args[1]
  1384  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  1385  			break
  1386  		}
  1387  		v.reset(Op386ADDLloadidx4)
  1388  		v.AuxInt = off
  1389  		v.Aux = sym
  1390  		v.AddArg(x)
  1391  		v.AddArg(ptr)
  1392  		v.AddArg(idx)
  1393  		v.AddArg(mem)
  1394  		return true
  1395  	}
  1396  	// match: (ADDL x (NEGL y))
  1397  	// cond:
  1398  	// result: (SUBL x y)
  1399  	for {
  1400  		_ = v.Args[1]
  1401  		x := v.Args[0]
  1402  		v_1 := v.Args[1]
  1403  		if v_1.Op != Op386NEGL {
  1404  			break
  1405  		}
  1406  		y := v_1.Args[0]
  1407  		v.reset(Op386SUBL)
  1408  		v.AddArg(x)
  1409  		v.AddArg(y)
  1410  		return true
  1411  	}
  1412  	// match: (ADDL (NEGL y) x)
  1413  	// cond:
  1414  	// result: (SUBL x y)
  1415  	for {
  1416  		x := v.Args[1]
  1417  		v_0 := v.Args[0]
  1418  		if v_0.Op != Op386NEGL {
  1419  			break
  1420  		}
  1421  		y := v_0.Args[0]
  1422  		v.reset(Op386SUBL)
  1423  		v.AddArg(x)
  1424  		v.AddArg(y)
  1425  		return true
  1426  	}
  1427  	return false
  1428  }
  1429  func rewriteValue386_Op386ADDLcarry_0(v *Value) bool {
  1430  	// match: (ADDLcarry x (MOVLconst [c]))
  1431  	// cond:
  1432  	// result: (ADDLconstcarry [c] x)
  1433  	for {
  1434  		_ = v.Args[1]
  1435  		x := v.Args[0]
  1436  		v_1 := v.Args[1]
  1437  		if v_1.Op != Op386MOVLconst {
  1438  			break
  1439  		}
  1440  		c := v_1.AuxInt
  1441  		v.reset(Op386ADDLconstcarry)
  1442  		v.AuxInt = c
  1443  		v.AddArg(x)
  1444  		return true
  1445  	}
  1446  	// match: (ADDLcarry (MOVLconst [c]) x)
  1447  	// cond:
  1448  	// result: (ADDLconstcarry [c] x)
  1449  	for {
  1450  		x := v.Args[1]
  1451  		v_0 := v.Args[0]
  1452  		if v_0.Op != Op386MOVLconst {
  1453  			break
  1454  		}
  1455  		c := v_0.AuxInt
  1456  		v.reset(Op386ADDLconstcarry)
  1457  		v.AuxInt = c
  1458  		v.AddArg(x)
  1459  		return true
  1460  	}
  1461  	return false
  1462  }
  1463  func rewriteValue386_Op386ADDLconst_0(v *Value) bool {
  1464  	// match: (ADDLconst [c] (ADDL x y))
  1465  	// cond:
  1466  	// result: (LEAL1 [c] x y)
  1467  	for {
  1468  		c := v.AuxInt
  1469  		v_0 := v.Args[0]
  1470  		if v_0.Op != Op386ADDL {
  1471  			break
  1472  		}
  1473  		y := v_0.Args[1]
  1474  		x := v_0.Args[0]
  1475  		v.reset(Op386LEAL1)
  1476  		v.AuxInt = c
  1477  		v.AddArg(x)
  1478  		v.AddArg(y)
  1479  		return true
  1480  	}
  1481  	// match: (ADDLconst [c] (LEAL [d] {s} x))
  1482  	// cond: is32Bit(c+d)
  1483  	// result: (LEAL [c+d] {s} x)
  1484  	for {
  1485  		c := v.AuxInt
  1486  		v_0 := v.Args[0]
  1487  		if v_0.Op != Op386LEAL {
  1488  			break
  1489  		}
  1490  		d := v_0.AuxInt
  1491  		s := v_0.Aux
  1492  		x := v_0.Args[0]
  1493  		if !(is32Bit(c + d)) {
  1494  			break
  1495  		}
  1496  		v.reset(Op386LEAL)
  1497  		v.AuxInt = c + d
  1498  		v.Aux = s
  1499  		v.AddArg(x)
  1500  		return true
  1501  	}
  1502  	// match: (ADDLconst [c] (LEAL1 [d] {s} x y))
  1503  	// cond: is32Bit(c+d)
  1504  	// result: (LEAL1 [c+d] {s} x y)
  1505  	for {
  1506  		c := v.AuxInt
  1507  		v_0 := v.Args[0]
  1508  		if v_0.Op != Op386LEAL1 {
  1509  			break
  1510  		}
  1511  		d := v_0.AuxInt
  1512  		s := v_0.Aux
  1513  		y := v_0.Args[1]
  1514  		x := v_0.Args[0]
  1515  		if !(is32Bit(c + d)) {
  1516  			break
  1517  		}
  1518  		v.reset(Op386LEAL1)
  1519  		v.AuxInt = c + d
  1520  		v.Aux = s
  1521  		v.AddArg(x)
  1522  		v.AddArg(y)
  1523  		return true
  1524  	}
  1525  	// match: (ADDLconst [c] (LEAL2 [d] {s} x y))
  1526  	// cond: is32Bit(c+d)
  1527  	// result: (LEAL2 [c+d] {s} x y)
  1528  	for {
  1529  		c := v.AuxInt
  1530  		v_0 := v.Args[0]
  1531  		if v_0.Op != Op386LEAL2 {
  1532  			break
  1533  		}
  1534  		d := v_0.AuxInt
  1535  		s := v_0.Aux
  1536  		y := v_0.Args[1]
  1537  		x := v_0.Args[0]
  1538  		if !(is32Bit(c + d)) {
  1539  			break
  1540  		}
  1541  		v.reset(Op386LEAL2)
  1542  		v.AuxInt = c + d
  1543  		v.Aux = s
  1544  		v.AddArg(x)
  1545  		v.AddArg(y)
  1546  		return true
  1547  	}
  1548  	// match: (ADDLconst [c] (LEAL4 [d] {s} x y))
  1549  	// cond: is32Bit(c+d)
  1550  	// result: (LEAL4 [c+d] {s} x y)
  1551  	for {
  1552  		c := v.AuxInt
  1553  		v_0 := v.Args[0]
  1554  		if v_0.Op != Op386LEAL4 {
  1555  			break
  1556  		}
  1557  		d := v_0.AuxInt
  1558  		s := v_0.Aux
  1559  		y := v_0.Args[1]
  1560  		x := v_0.Args[0]
  1561  		if !(is32Bit(c + d)) {
  1562  			break
  1563  		}
  1564  		v.reset(Op386LEAL4)
  1565  		v.AuxInt = c + d
  1566  		v.Aux = s
  1567  		v.AddArg(x)
  1568  		v.AddArg(y)
  1569  		return true
  1570  	}
  1571  	// match: (ADDLconst [c] (LEAL8 [d] {s} x y))
  1572  	// cond: is32Bit(c+d)
  1573  	// result: (LEAL8 [c+d] {s} x y)
  1574  	for {
  1575  		c := v.AuxInt
  1576  		v_0 := v.Args[0]
  1577  		if v_0.Op != Op386LEAL8 {
  1578  			break
  1579  		}
  1580  		d := v_0.AuxInt
  1581  		s := v_0.Aux
  1582  		y := v_0.Args[1]
  1583  		x := v_0.Args[0]
  1584  		if !(is32Bit(c + d)) {
  1585  			break
  1586  		}
  1587  		v.reset(Op386LEAL8)
  1588  		v.AuxInt = c + d
  1589  		v.Aux = s
  1590  		v.AddArg(x)
  1591  		v.AddArg(y)
  1592  		return true
  1593  	}
  1594  	// match: (ADDLconst [c] x)
  1595  	// cond: int32(c)==0
  1596  	// result: x
  1597  	for {
  1598  		c := v.AuxInt
  1599  		x := v.Args[0]
  1600  		if !(int32(c) == 0) {
  1601  			break
  1602  		}
  1603  		v.reset(OpCopy)
  1604  		v.Type = x.Type
  1605  		v.AddArg(x)
  1606  		return true
  1607  	}
  1608  	// match: (ADDLconst [c] (MOVLconst [d]))
  1609  	// cond:
  1610  	// result: (MOVLconst [int64(int32(c+d))])
  1611  	for {
  1612  		c := v.AuxInt
  1613  		v_0 := v.Args[0]
  1614  		if v_0.Op != Op386MOVLconst {
  1615  			break
  1616  		}
  1617  		d := v_0.AuxInt
  1618  		v.reset(Op386MOVLconst)
  1619  		v.AuxInt = int64(int32(c + d))
  1620  		return true
  1621  	}
  1622  	// match: (ADDLconst [c] (ADDLconst [d] x))
  1623  	// cond:
  1624  	// result: (ADDLconst [int64(int32(c+d))] x)
  1625  	for {
  1626  		c := v.AuxInt
  1627  		v_0 := v.Args[0]
  1628  		if v_0.Op != Op386ADDLconst {
  1629  			break
  1630  		}
  1631  		d := v_0.AuxInt
  1632  		x := v_0.Args[0]
  1633  		v.reset(Op386ADDLconst)
  1634  		v.AuxInt = int64(int32(c + d))
  1635  		v.AddArg(x)
  1636  		return true
  1637  	}
  1638  	return false
  1639  }
  1640  func rewriteValue386_Op386ADDLconstmodify_0(v *Value) bool {
  1641  	b := v.Block
  1642  	config := b.Func.Config
  1643  	// match: (ADDLconstmodify [valoff1] {sym} (ADDLconst [off2] base) mem)
  1644  	// cond: ValAndOff(valoff1).canAdd(off2)
  1645  	// result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  1646  	for {
  1647  		valoff1 := v.AuxInt
  1648  		sym := v.Aux
  1649  		mem := v.Args[1]
  1650  		v_0 := v.Args[0]
  1651  		if v_0.Op != Op386ADDLconst {
  1652  			break
  1653  		}
  1654  		off2 := v_0.AuxInt
  1655  		base := v_0.Args[0]
  1656  		if !(ValAndOff(valoff1).canAdd(off2)) {
  1657  			break
  1658  		}
  1659  		v.reset(Op386ADDLconstmodify)
  1660  		v.AuxInt = ValAndOff(valoff1).add(off2)
  1661  		v.Aux = sym
  1662  		v.AddArg(base)
  1663  		v.AddArg(mem)
  1664  		return true
  1665  	}
  1666  	// match: (ADDLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem)
  1667  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  1668  	// result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  1669  	for {
  1670  		valoff1 := v.AuxInt
  1671  		sym1 := v.Aux
  1672  		mem := v.Args[1]
  1673  		v_0 := v.Args[0]
  1674  		if v_0.Op != Op386LEAL {
  1675  			break
  1676  		}
  1677  		off2 := v_0.AuxInt
  1678  		sym2 := v_0.Aux
  1679  		base := v_0.Args[0]
  1680  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  1681  			break
  1682  		}
  1683  		v.reset(Op386ADDLconstmodify)
  1684  		v.AuxInt = ValAndOff(valoff1).add(off2)
  1685  		v.Aux = mergeSym(sym1, sym2)
  1686  		v.AddArg(base)
  1687  		v.AddArg(mem)
  1688  		return true
  1689  	}
  1690  	return false
  1691  }
  1692  func rewriteValue386_Op386ADDLconstmodifyidx4_0(v *Value) bool {
  1693  	b := v.Block
  1694  	config := b.Func.Config
  1695  	// match: (ADDLconstmodifyidx4 [valoff1] {sym} (ADDLconst [off2] base) idx mem)
  1696  	// cond: ValAndOff(valoff1).canAdd(off2)
  1697  	// result: (ADDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {sym} base idx mem)
  1698  	for {
  1699  		valoff1 := v.AuxInt
  1700  		sym := v.Aux
  1701  		mem := v.Args[2]
  1702  		v_0 := v.Args[0]
  1703  		if v_0.Op != Op386ADDLconst {
  1704  			break
  1705  		}
  1706  		off2 := v_0.AuxInt
  1707  		base := v_0.Args[0]
  1708  		idx := v.Args[1]
  1709  		if !(ValAndOff(valoff1).canAdd(off2)) {
  1710  			break
  1711  		}
  1712  		v.reset(Op386ADDLconstmodifyidx4)
  1713  		v.AuxInt = ValAndOff(valoff1).add(off2)
  1714  		v.Aux = sym
  1715  		v.AddArg(base)
  1716  		v.AddArg(idx)
  1717  		v.AddArg(mem)
  1718  		return true
  1719  	}
  1720  	// match: (ADDLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem)
  1721  	// cond: ValAndOff(valoff1).canAdd(off2*4)
  1722  	// result: (ADDLconstmodifyidx4 [ValAndOff(valoff1).add(off2*4)] {sym} base idx mem)
  1723  	for {
  1724  		valoff1 := v.AuxInt
  1725  		sym := v.Aux
  1726  		mem := v.Args[2]
  1727  		base := v.Args[0]
  1728  		v_1 := v.Args[1]
  1729  		if v_1.Op != Op386ADDLconst {
  1730  			break
  1731  		}
  1732  		off2 := v_1.AuxInt
  1733  		idx := v_1.Args[0]
  1734  		if !(ValAndOff(valoff1).canAdd(off2 * 4)) {
  1735  			break
  1736  		}
  1737  		v.reset(Op386ADDLconstmodifyidx4)
  1738  		v.AuxInt = ValAndOff(valoff1).add(off2 * 4)
  1739  		v.Aux = sym
  1740  		v.AddArg(base)
  1741  		v.AddArg(idx)
  1742  		v.AddArg(mem)
  1743  		return true
  1744  	}
  1745  	// match: (ADDLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem)
  1746  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  1747  	// result: (ADDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base idx mem)
  1748  	for {
  1749  		valoff1 := v.AuxInt
  1750  		sym1 := v.Aux
  1751  		mem := v.Args[2]
  1752  		v_0 := v.Args[0]
  1753  		if v_0.Op != Op386LEAL {
  1754  			break
  1755  		}
  1756  		off2 := v_0.AuxInt
  1757  		sym2 := v_0.Aux
  1758  		base := v_0.Args[0]
  1759  		idx := v.Args[1]
  1760  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  1761  			break
  1762  		}
  1763  		v.reset(Op386ADDLconstmodifyidx4)
  1764  		v.AuxInt = ValAndOff(valoff1).add(off2)
  1765  		v.Aux = mergeSym(sym1, sym2)
  1766  		v.AddArg(base)
  1767  		v.AddArg(idx)
  1768  		v.AddArg(mem)
  1769  		return true
  1770  	}
  1771  	return false
  1772  }
  1773  func rewriteValue386_Op386ADDLload_0(v *Value) bool {
  1774  	b := v.Block
  1775  	config := b.Func.Config
  1776  	// match: (ADDLload [off1] {sym} val (ADDLconst [off2] base) mem)
  1777  	// cond: is32Bit(off1+off2)
  1778  	// result: (ADDLload [off1+off2] {sym} val base mem)
  1779  	for {
  1780  		off1 := v.AuxInt
  1781  		sym := v.Aux
  1782  		mem := v.Args[2]
  1783  		val := v.Args[0]
  1784  		v_1 := v.Args[1]
  1785  		if v_1.Op != Op386ADDLconst {
  1786  			break
  1787  		}
  1788  		off2 := v_1.AuxInt
  1789  		base := v_1.Args[0]
  1790  		if !(is32Bit(off1 + off2)) {
  1791  			break
  1792  		}
  1793  		v.reset(Op386ADDLload)
  1794  		v.AuxInt = off1 + off2
  1795  		v.Aux = sym
  1796  		v.AddArg(val)
  1797  		v.AddArg(base)
  1798  		v.AddArg(mem)
  1799  		return true
  1800  	}
  1801  	// match: (ADDLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
  1802  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  1803  	// result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  1804  	for {
  1805  		off1 := v.AuxInt
  1806  		sym1 := v.Aux
  1807  		mem := v.Args[2]
  1808  		val := v.Args[0]
  1809  		v_1 := v.Args[1]
  1810  		if v_1.Op != Op386LEAL {
  1811  			break
  1812  		}
  1813  		off2 := v_1.AuxInt
  1814  		sym2 := v_1.Aux
  1815  		base := v_1.Args[0]
  1816  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  1817  			break
  1818  		}
  1819  		v.reset(Op386ADDLload)
  1820  		v.AuxInt = off1 + off2
  1821  		v.Aux = mergeSym(sym1, sym2)
  1822  		v.AddArg(val)
  1823  		v.AddArg(base)
  1824  		v.AddArg(mem)
  1825  		return true
  1826  	}
  1827  	// match: (ADDLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem)
  1828  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  1829  	// result: (ADDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem)
  1830  	for {
  1831  		off1 := v.AuxInt
  1832  		sym1 := v.Aux
  1833  		mem := v.Args[2]
  1834  		val := v.Args[0]
  1835  		v_1 := v.Args[1]
  1836  		if v_1.Op != Op386LEAL4 {
  1837  			break
  1838  		}
  1839  		off2 := v_1.AuxInt
  1840  		sym2 := v_1.Aux
  1841  		idx := v_1.Args[1]
  1842  		ptr := v_1.Args[0]
  1843  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  1844  			break
  1845  		}
  1846  		v.reset(Op386ADDLloadidx4)
  1847  		v.AuxInt = off1 + off2
  1848  		v.Aux = mergeSym(sym1, sym2)
  1849  		v.AddArg(val)
  1850  		v.AddArg(ptr)
  1851  		v.AddArg(idx)
  1852  		v.AddArg(mem)
  1853  		return true
  1854  	}
  1855  	return false
  1856  }
  1857  func rewriteValue386_Op386ADDLloadidx4_0(v *Value) bool {
  1858  	b := v.Block
  1859  	config := b.Func.Config
  1860  	// match: (ADDLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem)
  1861  	// cond: is32Bit(off1+off2)
  1862  	// result: (ADDLloadidx4 [off1+off2] {sym} val base idx mem)
  1863  	for {
  1864  		off1 := v.AuxInt
  1865  		sym := v.Aux
  1866  		mem := v.Args[3]
  1867  		val := v.Args[0]
  1868  		v_1 := v.Args[1]
  1869  		if v_1.Op != Op386ADDLconst {
  1870  			break
  1871  		}
  1872  		off2 := v_1.AuxInt
  1873  		base := v_1.Args[0]
  1874  		idx := v.Args[2]
  1875  		if !(is32Bit(off1 + off2)) {
  1876  			break
  1877  		}
  1878  		v.reset(Op386ADDLloadidx4)
  1879  		v.AuxInt = off1 + off2
  1880  		v.Aux = sym
  1881  		v.AddArg(val)
  1882  		v.AddArg(base)
  1883  		v.AddArg(idx)
  1884  		v.AddArg(mem)
  1885  		return true
  1886  	}
  1887  	// match: (ADDLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem)
  1888  	// cond: is32Bit(off1+off2*4)
  1889  	// result: (ADDLloadidx4 [off1+off2*4] {sym} val base idx mem)
  1890  	for {
  1891  		off1 := v.AuxInt
  1892  		sym := v.Aux
  1893  		mem := v.Args[3]
  1894  		val := v.Args[0]
  1895  		base := v.Args[1]
  1896  		v_2 := v.Args[2]
  1897  		if v_2.Op != Op386ADDLconst {
  1898  			break
  1899  		}
  1900  		off2 := v_2.AuxInt
  1901  		idx := v_2.Args[0]
  1902  		if !(is32Bit(off1 + off2*4)) {
  1903  			break
  1904  		}
  1905  		v.reset(Op386ADDLloadidx4)
  1906  		v.AuxInt = off1 + off2*4
  1907  		v.Aux = sym
  1908  		v.AddArg(val)
  1909  		v.AddArg(base)
  1910  		v.AddArg(idx)
  1911  		v.AddArg(mem)
  1912  		return true
  1913  	}
  1914  	// match: (ADDLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem)
  1915  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  1916  	// result: (ADDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem)
  1917  	for {
  1918  		off1 := v.AuxInt
  1919  		sym1 := v.Aux
  1920  		mem := v.Args[3]
  1921  		val := v.Args[0]
  1922  		v_1 := v.Args[1]
  1923  		if v_1.Op != Op386LEAL {
  1924  			break
  1925  		}
  1926  		off2 := v_1.AuxInt
  1927  		sym2 := v_1.Aux
  1928  		base := v_1.Args[0]
  1929  		idx := v.Args[2]
  1930  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  1931  			break
  1932  		}
  1933  		v.reset(Op386ADDLloadidx4)
  1934  		v.AuxInt = off1 + off2
  1935  		v.Aux = mergeSym(sym1, sym2)
  1936  		v.AddArg(val)
  1937  		v.AddArg(base)
  1938  		v.AddArg(idx)
  1939  		v.AddArg(mem)
  1940  		return true
  1941  	}
  1942  	return false
  1943  }
  1944  func rewriteValue386_Op386ADDLmodify_0(v *Value) bool {
  1945  	b := v.Block
  1946  	config := b.Func.Config
  1947  	// match: (ADDLmodify [off1] {sym} (ADDLconst [off2] base) val mem)
  1948  	// cond: is32Bit(off1+off2)
  1949  	// result: (ADDLmodify [off1+off2] {sym} base val mem)
  1950  	for {
  1951  		off1 := v.AuxInt
  1952  		sym := v.Aux
  1953  		mem := v.Args[2]
  1954  		v_0 := v.Args[0]
  1955  		if v_0.Op != Op386ADDLconst {
  1956  			break
  1957  		}
  1958  		off2 := v_0.AuxInt
  1959  		base := v_0.Args[0]
  1960  		val := v.Args[1]
  1961  		if !(is32Bit(off1 + off2)) {
  1962  			break
  1963  		}
  1964  		v.reset(Op386ADDLmodify)
  1965  		v.AuxInt = off1 + off2
  1966  		v.Aux = sym
  1967  		v.AddArg(base)
  1968  		v.AddArg(val)
  1969  		v.AddArg(mem)
  1970  		return true
  1971  	}
  1972  	// match: (ADDLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
  1973  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  1974  	// result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  1975  	for {
  1976  		off1 := v.AuxInt
  1977  		sym1 := v.Aux
  1978  		mem := v.Args[2]
  1979  		v_0 := v.Args[0]
  1980  		if v_0.Op != Op386LEAL {
  1981  			break
  1982  		}
  1983  		off2 := v_0.AuxInt
  1984  		sym2 := v_0.Aux
  1985  		base := v_0.Args[0]
  1986  		val := v.Args[1]
  1987  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  1988  			break
  1989  		}
  1990  		v.reset(Op386ADDLmodify)
  1991  		v.AuxInt = off1 + off2
  1992  		v.Aux = mergeSym(sym1, sym2)
  1993  		v.AddArg(base)
  1994  		v.AddArg(val)
  1995  		v.AddArg(mem)
  1996  		return true
  1997  	}
  1998  	return false
  1999  }
  2000  func rewriteValue386_Op386ADDLmodifyidx4_0(v *Value) bool {
  2001  	b := v.Block
  2002  	config := b.Func.Config
  2003  	// match: (ADDLmodifyidx4 [off1] {sym} (ADDLconst [off2] base) idx val mem)
  2004  	// cond: is32Bit(off1+off2)
  2005  	// result: (ADDLmodifyidx4 [off1+off2] {sym} base idx val mem)
  2006  	for {
  2007  		off1 := v.AuxInt
  2008  		sym := v.Aux
  2009  		mem := v.Args[3]
  2010  		v_0 := v.Args[0]
  2011  		if v_0.Op != Op386ADDLconst {
  2012  			break
  2013  		}
  2014  		off2 := v_0.AuxInt
  2015  		base := v_0.Args[0]
  2016  		idx := v.Args[1]
  2017  		val := v.Args[2]
  2018  		if !(is32Bit(off1 + off2)) {
  2019  			break
  2020  		}
  2021  		v.reset(Op386ADDLmodifyidx4)
  2022  		v.AuxInt = off1 + off2
  2023  		v.Aux = sym
  2024  		v.AddArg(base)
  2025  		v.AddArg(idx)
  2026  		v.AddArg(val)
  2027  		v.AddArg(mem)
  2028  		return true
  2029  	}
  2030  	// match: (ADDLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem)
  2031  	// cond: is32Bit(off1+off2*4)
  2032  	// result: (ADDLmodifyidx4 [off1+off2*4] {sym} base idx val mem)
  2033  	for {
  2034  		off1 := v.AuxInt
  2035  		sym := v.Aux
  2036  		mem := v.Args[3]
  2037  		base := v.Args[0]
  2038  		v_1 := v.Args[1]
  2039  		if v_1.Op != Op386ADDLconst {
  2040  			break
  2041  		}
  2042  		off2 := v_1.AuxInt
  2043  		idx := v_1.Args[0]
  2044  		val := v.Args[2]
  2045  		if !(is32Bit(off1 + off2*4)) {
  2046  			break
  2047  		}
  2048  		v.reset(Op386ADDLmodifyidx4)
  2049  		v.AuxInt = off1 + off2*4
  2050  		v.Aux = sym
  2051  		v.AddArg(base)
  2052  		v.AddArg(idx)
  2053  		v.AddArg(val)
  2054  		v.AddArg(mem)
  2055  		return true
  2056  	}
  2057  	// match: (ADDLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem)
  2058  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2059  	// result: (ADDLmodifyidx4 [off1+off2] {mergeSym(sym1,sym2)} base idx val mem)
  2060  	for {
  2061  		off1 := v.AuxInt
  2062  		sym1 := v.Aux
  2063  		mem := v.Args[3]
  2064  		v_0 := v.Args[0]
  2065  		if v_0.Op != Op386LEAL {
  2066  			break
  2067  		}
  2068  		off2 := v_0.AuxInt
  2069  		sym2 := v_0.Aux
  2070  		base := v_0.Args[0]
  2071  		idx := v.Args[1]
  2072  		val := v.Args[2]
  2073  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2074  			break
  2075  		}
  2076  		v.reset(Op386ADDLmodifyidx4)
  2077  		v.AuxInt = off1 + off2
  2078  		v.Aux = mergeSym(sym1, sym2)
  2079  		v.AddArg(base)
  2080  		v.AddArg(idx)
  2081  		v.AddArg(val)
  2082  		v.AddArg(mem)
  2083  		return true
  2084  	}
  2085  	// match: (ADDLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem)
  2086  	// cond: validValAndOff(c,off)
  2087  	// result: (ADDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem)
  2088  	for {
  2089  		off := v.AuxInt
  2090  		sym := v.Aux
  2091  		mem := v.Args[3]
  2092  		ptr := v.Args[0]
  2093  		idx := v.Args[1]
  2094  		v_2 := v.Args[2]
  2095  		if v_2.Op != Op386MOVLconst {
  2096  			break
  2097  		}
  2098  		c := v_2.AuxInt
  2099  		if !(validValAndOff(c, off)) {
  2100  			break
  2101  		}
  2102  		v.reset(Op386ADDLconstmodifyidx4)
  2103  		v.AuxInt = makeValAndOff(c, off)
  2104  		v.Aux = sym
  2105  		v.AddArg(ptr)
  2106  		v.AddArg(idx)
  2107  		v.AddArg(mem)
  2108  		return true
  2109  	}
  2110  	return false
  2111  }
  2112  func rewriteValue386_Op386ADDSD_0(v *Value) bool {
  2113  	b := v.Block
  2114  	config := b.Func.Config
  2115  	// match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem))
  2116  	// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
  2117  	// result: (ADDSDload x [off] {sym} ptr mem)
  2118  	for {
  2119  		_ = v.Args[1]
  2120  		x := v.Args[0]
  2121  		l := v.Args[1]
  2122  		if l.Op != Op386MOVSDload {
  2123  			break
  2124  		}
  2125  		off := l.AuxInt
  2126  		sym := l.Aux
  2127  		mem := l.Args[1]
  2128  		ptr := l.Args[0]
  2129  		if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
  2130  			break
  2131  		}
  2132  		v.reset(Op386ADDSDload)
  2133  		v.AuxInt = off
  2134  		v.Aux = sym
  2135  		v.AddArg(x)
  2136  		v.AddArg(ptr)
  2137  		v.AddArg(mem)
  2138  		return true
  2139  	}
  2140  	// match: (ADDSD l:(MOVSDload [off] {sym} ptr mem) x)
  2141  	// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
  2142  	// result: (ADDSDload x [off] {sym} ptr mem)
  2143  	for {
  2144  		x := v.Args[1]
  2145  		l := v.Args[0]
  2146  		if l.Op != Op386MOVSDload {
  2147  			break
  2148  		}
  2149  		off := l.AuxInt
  2150  		sym := l.Aux
  2151  		mem := l.Args[1]
  2152  		ptr := l.Args[0]
  2153  		if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
  2154  			break
  2155  		}
  2156  		v.reset(Op386ADDSDload)
  2157  		v.AuxInt = off
  2158  		v.Aux = sym
  2159  		v.AddArg(x)
  2160  		v.AddArg(ptr)
  2161  		v.AddArg(mem)
  2162  		return true
  2163  	}
  2164  	return false
  2165  }
  2166  func rewriteValue386_Op386ADDSDload_0(v *Value) bool {
  2167  	b := v.Block
  2168  	config := b.Func.Config
  2169  	// match: (ADDSDload [off1] {sym} val (ADDLconst [off2] base) mem)
  2170  	// cond: is32Bit(off1+off2)
  2171  	// result: (ADDSDload [off1+off2] {sym} val base mem)
  2172  	for {
  2173  		off1 := v.AuxInt
  2174  		sym := v.Aux
  2175  		mem := v.Args[2]
  2176  		val := v.Args[0]
  2177  		v_1 := v.Args[1]
  2178  		if v_1.Op != Op386ADDLconst {
  2179  			break
  2180  		}
  2181  		off2 := v_1.AuxInt
  2182  		base := v_1.Args[0]
  2183  		if !(is32Bit(off1 + off2)) {
  2184  			break
  2185  		}
  2186  		v.reset(Op386ADDSDload)
  2187  		v.AuxInt = off1 + off2
  2188  		v.Aux = sym
  2189  		v.AddArg(val)
  2190  		v.AddArg(base)
  2191  		v.AddArg(mem)
  2192  		return true
  2193  	}
  2194  	// match: (ADDSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
  2195  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2196  	// result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  2197  	for {
  2198  		off1 := v.AuxInt
  2199  		sym1 := v.Aux
  2200  		mem := v.Args[2]
  2201  		val := v.Args[0]
  2202  		v_1 := v.Args[1]
  2203  		if v_1.Op != Op386LEAL {
  2204  			break
  2205  		}
  2206  		off2 := v_1.AuxInt
  2207  		sym2 := v_1.Aux
  2208  		base := v_1.Args[0]
  2209  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2210  			break
  2211  		}
  2212  		v.reset(Op386ADDSDload)
  2213  		v.AuxInt = off1 + off2
  2214  		v.Aux = mergeSym(sym1, sym2)
  2215  		v.AddArg(val)
  2216  		v.AddArg(base)
  2217  		v.AddArg(mem)
  2218  		return true
  2219  	}
  2220  	return false
  2221  }
  2222  func rewriteValue386_Op386ADDSS_0(v *Value) bool {
  2223  	b := v.Block
  2224  	config := b.Func.Config
  2225  	// match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem))
  2226  	// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
  2227  	// result: (ADDSSload x [off] {sym} ptr mem)
  2228  	for {
  2229  		_ = v.Args[1]
  2230  		x := v.Args[0]
  2231  		l := v.Args[1]
  2232  		if l.Op != Op386MOVSSload {
  2233  			break
  2234  		}
  2235  		off := l.AuxInt
  2236  		sym := l.Aux
  2237  		mem := l.Args[1]
  2238  		ptr := l.Args[0]
  2239  		if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
  2240  			break
  2241  		}
  2242  		v.reset(Op386ADDSSload)
  2243  		v.AuxInt = off
  2244  		v.Aux = sym
  2245  		v.AddArg(x)
  2246  		v.AddArg(ptr)
  2247  		v.AddArg(mem)
  2248  		return true
  2249  	}
  2250  	// match: (ADDSS l:(MOVSSload [off] {sym} ptr mem) x)
  2251  	// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
  2252  	// result: (ADDSSload x [off] {sym} ptr mem)
  2253  	for {
  2254  		x := v.Args[1]
  2255  		l := v.Args[0]
  2256  		if l.Op != Op386MOVSSload {
  2257  			break
  2258  		}
  2259  		off := l.AuxInt
  2260  		sym := l.Aux
  2261  		mem := l.Args[1]
  2262  		ptr := l.Args[0]
  2263  		if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
  2264  			break
  2265  		}
  2266  		v.reset(Op386ADDSSload)
  2267  		v.AuxInt = off
  2268  		v.Aux = sym
  2269  		v.AddArg(x)
  2270  		v.AddArg(ptr)
  2271  		v.AddArg(mem)
  2272  		return true
  2273  	}
  2274  	return false
  2275  }
  2276  func rewriteValue386_Op386ADDSSload_0(v *Value) bool {
  2277  	b := v.Block
  2278  	config := b.Func.Config
  2279  	// match: (ADDSSload [off1] {sym} val (ADDLconst [off2] base) mem)
  2280  	// cond: is32Bit(off1+off2)
  2281  	// result: (ADDSSload [off1+off2] {sym} val base mem)
  2282  	for {
  2283  		off1 := v.AuxInt
  2284  		sym := v.Aux
  2285  		mem := v.Args[2]
  2286  		val := v.Args[0]
  2287  		v_1 := v.Args[1]
  2288  		if v_1.Op != Op386ADDLconst {
  2289  			break
  2290  		}
  2291  		off2 := v_1.AuxInt
  2292  		base := v_1.Args[0]
  2293  		if !(is32Bit(off1 + off2)) {
  2294  			break
  2295  		}
  2296  		v.reset(Op386ADDSSload)
  2297  		v.AuxInt = off1 + off2
  2298  		v.Aux = sym
  2299  		v.AddArg(val)
  2300  		v.AddArg(base)
  2301  		v.AddArg(mem)
  2302  		return true
  2303  	}
  2304  	// match: (ADDSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
  2305  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2306  	// result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  2307  	for {
  2308  		off1 := v.AuxInt
  2309  		sym1 := v.Aux
  2310  		mem := v.Args[2]
  2311  		val := v.Args[0]
  2312  		v_1 := v.Args[1]
  2313  		if v_1.Op != Op386LEAL {
  2314  			break
  2315  		}
  2316  		off2 := v_1.AuxInt
  2317  		sym2 := v_1.Aux
  2318  		base := v_1.Args[0]
  2319  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2320  			break
  2321  		}
  2322  		v.reset(Op386ADDSSload)
  2323  		v.AuxInt = off1 + off2
  2324  		v.Aux = mergeSym(sym1, sym2)
  2325  		v.AddArg(val)
  2326  		v.AddArg(base)
  2327  		v.AddArg(mem)
  2328  		return true
  2329  	}
  2330  	return false
  2331  }
  2332  func rewriteValue386_Op386ANDL_0(v *Value) bool {
  2333  	// match: (ANDL x (MOVLconst [c]))
  2334  	// cond:
  2335  	// result: (ANDLconst [c] x)
  2336  	for {
  2337  		_ = v.Args[1]
  2338  		x := v.Args[0]
  2339  		v_1 := v.Args[1]
  2340  		if v_1.Op != Op386MOVLconst {
  2341  			break
  2342  		}
  2343  		c := v_1.AuxInt
  2344  		v.reset(Op386ANDLconst)
  2345  		v.AuxInt = c
  2346  		v.AddArg(x)
  2347  		return true
  2348  	}
  2349  	// match: (ANDL (MOVLconst [c]) x)
  2350  	// cond:
  2351  	// result: (ANDLconst [c] x)
  2352  	for {
  2353  		x := v.Args[1]
  2354  		v_0 := v.Args[0]
  2355  		if v_0.Op != Op386MOVLconst {
  2356  			break
  2357  		}
  2358  		c := v_0.AuxInt
  2359  		v.reset(Op386ANDLconst)
  2360  		v.AuxInt = c
  2361  		v.AddArg(x)
  2362  		return true
  2363  	}
  2364  	// match: (ANDL x l:(MOVLload [off] {sym} ptr mem))
  2365  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  2366  	// result: (ANDLload x [off] {sym} ptr mem)
  2367  	for {
  2368  		_ = v.Args[1]
  2369  		x := v.Args[0]
  2370  		l := v.Args[1]
  2371  		if l.Op != Op386MOVLload {
  2372  			break
  2373  		}
  2374  		off := l.AuxInt
  2375  		sym := l.Aux
  2376  		mem := l.Args[1]
  2377  		ptr := l.Args[0]
  2378  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  2379  			break
  2380  		}
  2381  		v.reset(Op386ANDLload)
  2382  		v.AuxInt = off
  2383  		v.Aux = sym
  2384  		v.AddArg(x)
  2385  		v.AddArg(ptr)
  2386  		v.AddArg(mem)
  2387  		return true
  2388  	}
  2389  	// match: (ANDL l:(MOVLload [off] {sym} ptr mem) x)
  2390  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  2391  	// result: (ANDLload x [off] {sym} ptr mem)
  2392  	for {
  2393  		x := v.Args[1]
  2394  		l := v.Args[0]
  2395  		if l.Op != Op386MOVLload {
  2396  			break
  2397  		}
  2398  		off := l.AuxInt
  2399  		sym := l.Aux
  2400  		mem := l.Args[1]
  2401  		ptr := l.Args[0]
  2402  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  2403  			break
  2404  		}
  2405  		v.reset(Op386ANDLload)
  2406  		v.AuxInt = off
  2407  		v.Aux = sym
  2408  		v.AddArg(x)
  2409  		v.AddArg(ptr)
  2410  		v.AddArg(mem)
  2411  		return true
  2412  	}
  2413  	// match: (ANDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem))
  2414  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  2415  	// result: (ANDLloadidx4 x [off] {sym} ptr idx mem)
  2416  	for {
  2417  		_ = v.Args[1]
  2418  		x := v.Args[0]
  2419  		l := v.Args[1]
  2420  		if l.Op != Op386MOVLloadidx4 {
  2421  			break
  2422  		}
  2423  		off := l.AuxInt
  2424  		sym := l.Aux
  2425  		mem := l.Args[2]
  2426  		ptr := l.Args[0]
  2427  		idx := l.Args[1]
  2428  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  2429  			break
  2430  		}
  2431  		v.reset(Op386ANDLloadidx4)
  2432  		v.AuxInt = off
  2433  		v.Aux = sym
  2434  		v.AddArg(x)
  2435  		v.AddArg(ptr)
  2436  		v.AddArg(idx)
  2437  		v.AddArg(mem)
  2438  		return true
  2439  	}
  2440  	// match: (ANDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x)
  2441  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  2442  	// result: (ANDLloadidx4 x [off] {sym} ptr idx mem)
  2443  	for {
  2444  		x := v.Args[1]
  2445  		l := v.Args[0]
  2446  		if l.Op != Op386MOVLloadidx4 {
  2447  			break
  2448  		}
  2449  		off := l.AuxInt
  2450  		sym := l.Aux
  2451  		mem := l.Args[2]
  2452  		ptr := l.Args[0]
  2453  		idx := l.Args[1]
  2454  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  2455  			break
  2456  		}
  2457  		v.reset(Op386ANDLloadidx4)
  2458  		v.AuxInt = off
  2459  		v.Aux = sym
  2460  		v.AddArg(x)
  2461  		v.AddArg(ptr)
  2462  		v.AddArg(idx)
  2463  		v.AddArg(mem)
  2464  		return true
  2465  	}
  2466  	// match: (ANDL x x)
  2467  	// cond:
  2468  	// result: x
  2469  	for {
  2470  		x := v.Args[1]
  2471  		if x != v.Args[0] {
  2472  			break
  2473  		}
  2474  		v.reset(OpCopy)
  2475  		v.Type = x.Type
  2476  		v.AddArg(x)
  2477  		return true
  2478  	}
  2479  	return false
  2480  }
  2481  func rewriteValue386_Op386ANDLconst_0(v *Value) bool {
  2482  	// match: (ANDLconst [c] (ANDLconst [d] x))
  2483  	// cond:
  2484  	// result: (ANDLconst [c & d] x)
  2485  	for {
  2486  		c := v.AuxInt
  2487  		v_0 := v.Args[0]
  2488  		if v_0.Op != Op386ANDLconst {
  2489  			break
  2490  		}
  2491  		d := v_0.AuxInt
  2492  		x := v_0.Args[0]
  2493  		v.reset(Op386ANDLconst)
  2494  		v.AuxInt = c & d
  2495  		v.AddArg(x)
  2496  		return true
  2497  	}
  2498  	// match: (ANDLconst [c] _)
  2499  	// cond: int32(c)==0
  2500  	// result: (MOVLconst [0])
  2501  	for {
  2502  		c := v.AuxInt
  2503  		if !(int32(c) == 0) {
  2504  			break
  2505  		}
  2506  		v.reset(Op386MOVLconst)
  2507  		v.AuxInt = 0
  2508  		return true
  2509  	}
  2510  	// match: (ANDLconst [c] x)
  2511  	// cond: int32(c)==-1
  2512  	// result: x
  2513  	for {
  2514  		c := v.AuxInt
  2515  		x := v.Args[0]
  2516  		if !(int32(c) == -1) {
  2517  			break
  2518  		}
  2519  		v.reset(OpCopy)
  2520  		v.Type = x.Type
  2521  		v.AddArg(x)
  2522  		return true
  2523  	}
  2524  	// match: (ANDLconst [c] (MOVLconst [d]))
  2525  	// cond:
  2526  	// result: (MOVLconst [c&d])
  2527  	for {
  2528  		c := v.AuxInt
  2529  		v_0 := v.Args[0]
  2530  		if v_0.Op != Op386MOVLconst {
  2531  			break
  2532  		}
  2533  		d := v_0.AuxInt
  2534  		v.reset(Op386MOVLconst)
  2535  		v.AuxInt = c & d
  2536  		return true
  2537  	}
  2538  	return false
  2539  }
  2540  func rewriteValue386_Op386ANDLconstmodify_0(v *Value) bool {
  2541  	b := v.Block
  2542  	config := b.Func.Config
  2543  	// match: (ANDLconstmodify [valoff1] {sym} (ADDLconst [off2] base) mem)
  2544  	// cond: ValAndOff(valoff1).canAdd(off2)
  2545  	// result: (ANDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  2546  	for {
  2547  		valoff1 := v.AuxInt
  2548  		sym := v.Aux
  2549  		mem := v.Args[1]
  2550  		v_0 := v.Args[0]
  2551  		if v_0.Op != Op386ADDLconst {
  2552  			break
  2553  		}
  2554  		off2 := v_0.AuxInt
  2555  		base := v_0.Args[0]
  2556  		if !(ValAndOff(valoff1).canAdd(off2)) {
  2557  			break
  2558  		}
  2559  		v.reset(Op386ANDLconstmodify)
  2560  		v.AuxInt = ValAndOff(valoff1).add(off2)
  2561  		v.Aux = sym
  2562  		v.AddArg(base)
  2563  		v.AddArg(mem)
  2564  		return true
  2565  	}
  2566  	// match: (ANDLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem)
  2567  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2568  	// result: (ANDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  2569  	for {
  2570  		valoff1 := v.AuxInt
  2571  		sym1 := v.Aux
  2572  		mem := v.Args[1]
  2573  		v_0 := v.Args[0]
  2574  		if v_0.Op != Op386LEAL {
  2575  			break
  2576  		}
  2577  		off2 := v_0.AuxInt
  2578  		sym2 := v_0.Aux
  2579  		base := v_0.Args[0]
  2580  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2581  			break
  2582  		}
  2583  		v.reset(Op386ANDLconstmodify)
  2584  		v.AuxInt = ValAndOff(valoff1).add(off2)
  2585  		v.Aux = mergeSym(sym1, sym2)
  2586  		v.AddArg(base)
  2587  		v.AddArg(mem)
  2588  		return true
  2589  	}
  2590  	return false
  2591  }
  2592  func rewriteValue386_Op386ANDLconstmodifyidx4_0(v *Value) bool {
  2593  	b := v.Block
  2594  	config := b.Func.Config
  2595  	// match: (ANDLconstmodifyidx4 [valoff1] {sym} (ADDLconst [off2] base) idx mem)
  2596  	// cond: ValAndOff(valoff1).canAdd(off2)
  2597  	// result: (ANDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {sym} base idx mem)
  2598  	for {
  2599  		valoff1 := v.AuxInt
  2600  		sym := v.Aux
  2601  		mem := v.Args[2]
  2602  		v_0 := v.Args[0]
  2603  		if v_0.Op != Op386ADDLconst {
  2604  			break
  2605  		}
  2606  		off2 := v_0.AuxInt
  2607  		base := v_0.Args[0]
  2608  		idx := v.Args[1]
  2609  		if !(ValAndOff(valoff1).canAdd(off2)) {
  2610  			break
  2611  		}
  2612  		v.reset(Op386ANDLconstmodifyidx4)
  2613  		v.AuxInt = ValAndOff(valoff1).add(off2)
  2614  		v.Aux = sym
  2615  		v.AddArg(base)
  2616  		v.AddArg(idx)
  2617  		v.AddArg(mem)
  2618  		return true
  2619  	}
  2620  	// match: (ANDLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem)
  2621  	// cond: ValAndOff(valoff1).canAdd(off2*4)
  2622  	// result: (ANDLconstmodifyidx4 [ValAndOff(valoff1).add(off2*4)] {sym} base idx mem)
  2623  	for {
  2624  		valoff1 := v.AuxInt
  2625  		sym := v.Aux
  2626  		mem := v.Args[2]
  2627  		base := v.Args[0]
  2628  		v_1 := v.Args[1]
  2629  		if v_1.Op != Op386ADDLconst {
  2630  			break
  2631  		}
  2632  		off2 := v_1.AuxInt
  2633  		idx := v_1.Args[0]
  2634  		if !(ValAndOff(valoff1).canAdd(off2 * 4)) {
  2635  			break
  2636  		}
  2637  		v.reset(Op386ANDLconstmodifyidx4)
  2638  		v.AuxInt = ValAndOff(valoff1).add(off2 * 4)
  2639  		v.Aux = sym
  2640  		v.AddArg(base)
  2641  		v.AddArg(idx)
  2642  		v.AddArg(mem)
  2643  		return true
  2644  	}
  2645  	// match: (ANDLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem)
  2646  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2647  	// result: (ANDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base idx mem)
  2648  	for {
  2649  		valoff1 := v.AuxInt
  2650  		sym1 := v.Aux
  2651  		mem := v.Args[2]
  2652  		v_0 := v.Args[0]
  2653  		if v_0.Op != Op386LEAL {
  2654  			break
  2655  		}
  2656  		off2 := v_0.AuxInt
  2657  		sym2 := v_0.Aux
  2658  		base := v_0.Args[0]
  2659  		idx := v.Args[1]
  2660  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2661  			break
  2662  		}
  2663  		v.reset(Op386ANDLconstmodifyidx4)
  2664  		v.AuxInt = ValAndOff(valoff1).add(off2)
  2665  		v.Aux = mergeSym(sym1, sym2)
  2666  		v.AddArg(base)
  2667  		v.AddArg(idx)
  2668  		v.AddArg(mem)
  2669  		return true
  2670  	}
  2671  	return false
  2672  }
  2673  func rewriteValue386_Op386ANDLload_0(v *Value) bool {
  2674  	b := v.Block
  2675  	config := b.Func.Config
  2676  	// match: (ANDLload [off1] {sym} val (ADDLconst [off2] base) mem)
  2677  	// cond: is32Bit(off1+off2)
  2678  	// result: (ANDLload [off1+off2] {sym} val base mem)
  2679  	for {
  2680  		off1 := v.AuxInt
  2681  		sym := v.Aux
  2682  		mem := v.Args[2]
  2683  		val := v.Args[0]
  2684  		v_1 := v.Args[1]
  2685  		if v_1.Op != Op386ADDLconst {
  2686  			break
  2687  		}
  2688  		off2 := v_1.AuxInt
  2689  		base := v_1.Args[0]
  2690  		if !(is32Bit(off1 + off2)) {
  2691  			break
  2692  		}
  2693  		v.reset(Op386ANDLload)
  2694  		v.AuxInt = off1 + off2
  2695  		v.Aux = sym
  2696  		v.AddArg(val)
  2697  		v.AddArg(base)
  2698  		v.AddArg(mem)
  2699  		return true
  2700  	}
  2701  	// match: (ANDLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
  2702  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2703  	// result: (ANDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  2704  	for {
  2705  		off1 := v.AuxInt
  2706  		sym1 := v.Aux
  2707  		mem := v.Args[2]
  2708  		val := v.Args[0]
  2709  		v_1 := v.Args[1]
  2710  		if v_1.Op != Op386LEAL {
  2711  			break
  2712  		}
  2713  		off2 := v_1.AuxInt
  2714  		sym2 := v_1.Aux
  2715  		base := v_1.Args[0]
  2716  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2717  			break
  2718  		}
  2719  		v.reset(Op386ANDLload)
  2720  		v.AuxInt = off1 + off2
  2721  		v.Aux = mergeSym(sym1, sym2)
  2722  		v.AddArg(val)
  2723  		v.AddArg(base)
  2724  		v.AddArg(mem)
  2725  		return true
  2726  	}
  2727  	// match: (ANDLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem)
  2728  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  2729  	// result: (ANDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem)
  2730  	for {
  2731  		off1 := v.AuxInt
  2732  		sym1 := v.Aux
  2733  		mem := v.Args[2]
  2734  		val := v.Args[0]
  2735  		v_1 := v.Args[1]
  2736  		if v_1.Op != Op386LEAL4 {
  2737  			break
  2738  		}
  2739  		off2 := v_1.AuxInt
  2740  		sym2 := v_1.Aux
  2741  		idx := v_1.Args[1]
  2742  		ptr := v_1.Args[0]
  2743  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  2744  			break
  2745  		}
  2746  		v.reset(Op386ANDLloadidx4)
  2747  		v.AuxInt = off1 + off2
  2748  		v.Aux = mergeSym(sym1, sym2)
  2749  		v.AddArg(val)
  2750  		v.AddArg(ptr)
  2751  		v.AddArg(idx)
  2752  		v.AddArg(mem)
  2753  		return true
  2754  	}
  2755  	return false
  2756  }
  2757  func rewriteValue386_Op386ANDLloadidx4_0(v *Value) bool {
  2758  	b := v.Block
  2759  	config := b.Func.Config
  2760  	// match: (ANDLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem)
  2761  	// cond: is32Bit(off1+off2)
  2762  	// result: (ANDLloadidx4 [off1+off2] {sym} val base idx mem)
  2763  	for {
  2764  		off1 := v.AuxInt
  2765  		sym := v.Aux
  2766  		mem := v.Args[3]
  2767  		val := v.Args[0]
  2768  		v_1 := v.Args[1]
  2769  		if v_1.Op != Op386ADDLconst {
  2770  			break
  2771  		}
  2772  		off2 := v_1.AuxInt
  2773  		base := v_1.Args[0]
  2774  		idx := v.Args[2]
  2775  		if !(is32Bit(off1 + off2)) {
  2776  			break
  2777  		}
  2778  		v.reset(Op386ANDLloadidx4)
  2779  		v.AuxInt = off1 + off2
  2780  		v.Aux = sym
  2781  		v.AddArg(val)
  2782  		v.AddArg(base)
  2783  		v.AddArg(idx)
  2784  		v.AddArg(mem)
  2785  		return true
  2786  	}
  2787  	// match: (ANDLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem)
  2788  	// cond: is32Bit(off1+off2*4)
  2789  	// result: (ANDLloadidx4 [off1+off2*4] {sym} val base idx mem)
  2790  	for {
  2791  		off1 := v.AuxInt
  2792  		sym := v.Aux
  2793  		mem := v.Args[3]
  2794  		val := v.Args[0]
  2795  		base := v.Args[1]
  2796  		v_2 := v.Args[2]
  2797  		if v_2.Op != Op386ADDLconst {
  2798  			break
  2799  		}
  2800  		off2 := v_2.AuxInt
  2801  		idx := v_2.Args[0]
  2802  		if !(is32Bit(off1 + off2*4)) {
  2803  			break
  2804  		}
  2805  		v.reset(Op386ANDLloadidx4)
  2806  		v.AuxInt = off1 + off2*4
  2807  		v.Aux = sym
  2808  		v.AddArg(val)
  2809  		v.AddArg(base)
  2810  		v.AddArg(idx)
  2811  		v.AddArg(mem)
  2812  		return true
  2813  	}
  2814  	// match: (ANDLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem)
  2815  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2816  	// result: (ANDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem)
  2817  	for {
  2818  		off1 := v.AuxInt
  2819  		sym1 := v.Aux
  2820  		mem := v.Args[3]
  2821  		val := v.Args[0]
  2822  		v_1 := v.Args[1]
  2823  		if v_1.Op != Op386LEAL {
  2824  			break
  2825  		}
  2826  		off2 := v_1.AuxInt
  2827  		sym2 := v_1.Aux
  2828  		base := v_1.Args[0]
  2829  		idx := v.Args[2]
  2830  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2831  			break
  2832  		}
  2833  		v.reset(Op386ANDLloadidx4)
  2834  		v.AuxInt = off1 + off2
  2835  		v.Aux = mergeSym(sym1, sym2)
  2836  		v.AddArg(val)
  2837  		v.AddArg(base)
  2838  		v.AddArg(idx)
  2839  		v.AddArg(mem)
  2840  		return true
  2841  	}
  2842  	return false
  2843  }
  2844  func rewriteValue386_Op386ANDLmodify_0(v *Value) bool {
  2845  	b := v.Block
  2846  	config := b.Func.Config
  2847  	// match: (ANDLmodify [off1] {sym} (ADDLconst [off2] base) val mem)
  2848  	// cond: is32Bit(off1+off2)
  2849  	// result: (ANDLmodify [off1+off2] {sym} base val mem)
  2850  	for {
  2851  		off1 := v.AuxInt
  2852  		sym := v.Aux
  2853  		mem := v.Args[2]
  2854  		v_0 := v.Args[0]
  2855  		if v_0.Op != Op386ADDLconst {
  2856  			break
  2857  		}
  2858  		off2 := v_0.AuxInt
  2859  		base := v_0.Args[0]
  2860  		val := v.Args[1]
  2861  		if !(is32Bit(off1 + off2)) {
  2862  			break
  2863  		}
  2864  		v.reset(Op386ANDLmodify)
  2865  		v.AuxInt = off1 + off2
  2866  		v.Aux = sym
  2867  		v.AddArg(base)
  2868  		v.AddArg(val)
  2869  		v.AddArg(mem)
  2870  		return true
  2871  	}
  2872  	// match: (ANDLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
  2873  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2874  	// result: (ANDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  2875  	for {
  2876  		off1 := v.AuxInt
  2877  		sym1 := v.Aux
  2878  		mem := v.Args[2]
  2879  		v_0 := v.Args[0]
  2880  		if v_0.Op != Op386LEAL {
  2881  			break
  2882  		}
  2883  		off2 := v_0.AuxInt
  2884  		sym2 := v_0.Aux
  2885  		base := v_0.Args[0]
  2886  		val := v.Args[1]
  2887  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2888  			break
  2889  		}
  2890  		v.reset(Op386ANDLmodify)
  2891  		v.AuxInt = off1 + off2
  2892  		v.Aux = mergeSym(sym1, sym2)
  2893  		v.AddArg(base)
  2894  		v.AddArg(val)
  2895  		v.AddArg(mem)
  2896  		return true
  2897  	}
  2898  	return false
  2899  }
  2900  func rewriteValue386_Op386ANDLmodifyidx4_0(v *Value) bool {
  2901  	b := v.Block
  2902  	config := b.Func.Config
  2903  	// match: (ANDLmodifyidx4 [off1] {sym} (ADDLconst [off2] base) idx val mem)
  2904  	// cond: is32Bit(off1+off2)
  2905  	// result: (ANDLmodifyidx4 [off1+off2] {sym} base idx val mem)
  2906  	for {
  2907  		off1 := v.AuxInt
  2908  		sym := v.Aux
  2909  		mem := v.Args[3]
  2910  		v_0 := v.Args[0]
  2911  		if v_0.Op != Op386ADDLconst {
  2912  			break
  2913  		}
  2914  		off2 := v_0.AuxInt
  2915  		base := v_0.Args[0]
  2916  		idx := v.Args[1]
  2917  		val := v.Args[2]
  2918  		if !(is32Bit(off1 + off2)) {
  2919  			break
  2920  		}
  2921  		v.reset(Op386ANDLmodifyidx4)
  2922  		v.AuxInt = off1 + off2
  2923  		v.Aux = sym
  2924  		v.AddArg(base)
  2925  		v.AddArg(idx)
  2926  		v.AddArg(val)
  2927  		v.AddArg(mem)
  2928  		return true
  2929  	}
  2930  	// match: (ANDLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem)
  2931  	// cond: is32Bit(off1+off2*4)
  2932  	// result: (ANDLmodifyidx4 [off1+off2*4] {sym} base idx val mem)
  2933  	for {
  2934  		off1 := v.AuxInt
  2935  		sym := v.Aux
  2936  		mem := v.Args[3]
  2937  		base := v.Args[0]
  2938  		v_1 := v.Args[1]
  2939  		if v_1.Op != Op386ADDLconst {
  2940  			break
  2941  		}
  2942  		off2 := v_1.AuxInt
  2943  		idx := v_1.Args[0]
  2944  		val := v.Args[2]
  2945  		if !(is32Bit(off1 + off2*4)) {
  2946  			break
  2947  		}
  2948  		v.reset(Op386ANDLmodifyidx4)
  2949  		v.AuxInt = off1 + off2*4
  2950  		v.Aux = sym
  2951  		v.AddArg(base)
  2952  		v.AddArg(idx)
  2953  		v.AddArg(val)
  2954  		v.AddArg(mem)
  2955  		return true
  2956  	}
  2957  	// match: (ANDLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem)
  2958  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2959  	// result: (ANDLmodifyidx4 [off1+off2] {mergeSym(sym1,sym2)} base idx val mem)
  2960  	for {
  2961  		off1 := v.AuxInt
  2962  		sym1 := v.Aux
  2963  		mem := v.Args[3]
  2964  		v_0 := v.Args[0]
  2965  		if v_0.Op != Op386LEAL {
  2966  			break
  2967  		}
  2968  		off2 := v_0.AuxInt
  2969  		sym2 := v_0.Aux
  2970  		base := v_0.Args[0]
  2971  		idx := v.Args[1]
  2972  		val := v.Args[2]
  2973  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2974  			break
  2975  		}
  2976  		v.reset(Op386ANDLmodifyidx4)
  2977  		v.AuxInt = off1 + off2
  2978  		v.Aux = mergeSym(sym1, sym2)
  2979  		v.AddArg(base)
  2980  		v.AddArg(idx)
  2981  		v.AddArg(val)
  2982  		v.AddArg(mem)
  2983  		return true
  2984  	}
  2985  	// match: (ANDLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem)
  2986  	// cond: validValAndOff(c,off)
  2987  	// result: (ANDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem)
  2988  	for {
  2989  		off := v.AuxInt
  2990  		sym := v.Aux
  2991  		mem := v.Args[3]
  2992  		ptr := v.Args[0]
  2993  		idx := v.Args[1]
  2994  		v_2 := v.Args[2]
  2995  		if v_2.Op != Op386MOVLconst {
  2996  			break
  2997  		}
  2998  		c := v_2.AuxInt
  2999  		if !(validValAndOff(c, off)) {
  3000  			break
  3001  		}
  3002  		v.reset(Op386ANDLconstmodifyidx4)
  3003  		v.AuxInt = makeValAndOff(c, off)
  3004  		v.Aux = sym
  3005  		v.AddArg(ptr)
  3006  		v.AddArg(idx)
  3007  		v.AddArg(mem)
  3008  		return true
  3009  	}
  3010  	return false
  3011  }
  3012  func rewriteValue386_Op386CMPB_0(v *Value) bool {
  3013  	b := v.Block
  3014  	// match: (CMPB x (MOVLconst [c]))
  3015  	// cond:
  3016  	// result: (CMPBconst x [int64(int8(c))])
  3017  	for {
  3018  		_ = v.Args[1]
  3019  		x := v.Args[0]
  3020  		v_1 := v.Args[1]
  3021  		if v_1.Op != Op386MOVLconst {
  3022  			break
  3023  		}
  3024  		c := v_1.AuxInt
  3025  		v.reset(Op386CMPBconst)
  3026  		v.AuxInt = int64(int8(c))
  3027  		v.AddArg(x)
  3028  		return true
  3029  	}
  3030  	// match: (CMPB (MOVLconst [c]) x)
  3031  	// cond:
  3032  	// result: (InvertFlags (CMPBconst x [int64(int8(c))]))
  3033  	for {
  3034  		x := v.Args[1]
  3035  		v_0 := v.Args[0]
  3036  		if v_0.Op != Op386MOVLconst {
  3037  			break
  3038  		}
  3039  		c := v_0.AuxInt
  3040  		v.reset(Op386InvertFlags)
  3041  		v0 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags)
  3042  		v0.AuxInt = int64(int8(c))
  3043  		v0.AddArg(x)
  3044  		v.AddArg(v0)
  3045  		return true
  3046  	}
  3047  	// match: (CMPB l:(MOVBload {sym} [off] ptr mem) x)
  3048  	// cond: canMergeLoad(v, l) && clobber(l)
  3049  	// result: (CMPBload {sym} [off] ptr x mem)
  3050  	for {
  3051  		x := v.Args[1]
  3052  		l := v.Args[0]
  3053  		if l.Op != Op386MOVBload {
  3054  			break
  3055  		}
  3056  		off := l.AuxInt
  3057  		sym := l.Aux
  3058  		mem := l.Args[1]
  3059  		ptr := l.Args[0]
  3060  		if !(canMergeLoad(v, l) && clobber(l)) {
  3061  			break
  3062  		}
  3063  		v.reset(Op386CMPBload)
  3064  		v.AuxInt = off
  3065  		v.Aux = sym
  3066  		v.AddArg(ptr)
  3067  		v.AddArg(x)
  3068  		v.AddArg(mem)
  3069  		return true
  3070  	}
  3071  	// match: (CMPB x l:(MOVBload {sym} [off] ptr mem))
  3072  	// cond: canMergeLoad(v, l) && clobber(l)
  3073  	// result: (InvertFlags (CMPBload {sym} [off] ptr x mem))
  3074  	for {
  3075  		_ = v.Args[1]
  3076  		x := v.Args[0]
  3077  		l := v.Args[1]
  3078  		if l.Op != Op386MOVBload {
  3079  			break
  3080  		}
  3081  		off := l.AuxInt
  3082  		sym := l.Aux
  3083  		mem := l.Args[1]
  3084  		ptr := l.Args[0]
  3085  		if !(canMergeLoad(v, l) && clobber(l)) {
  3086  			break
  3087  		}
  3088  		v.reset(Op386InvertFlags)
  3089  		v0 := b.NewValue0(l.Pos, Op386CMPBload, types.TypeFlags)
  3090  		v0.AuxInt = off
  3091  		v0.Aux = sym
  3092  		v0.AddArg(ptr)
  3093  		v0.AddArg(x)
  3094  		v0.AddArg(mem)
  3095  		v.AddArg(v0)
  3096  		return true
  3097  	}
  3098  	return false
  3099  }
  3100  func rewriteValue386_Op386CMPBconst_0(v *Value) bool {
  3101  	b := v.Block
  3102  	// match: (CMPBconst (MOVLconst [x]) [y])
  3103  	// cond: int8(x)==int8(y)
  3104  	// result: (FlagEQ)
  3105  	for {
  3106  		y := v.AuxInt
  3107  		v_0 := v.Args[0]
  3108  		if v_0.Op != Op386MOVLconst {
  3109  			break
  3110  		}
  3111  		x := v_0.AuxInt
  3112  		if !(int8(x) == int8(y)) {
  3113  			break
  3114  		}
  3115  		v.reset(Op386FlagEQ)
  3116  		return true
  3117  	}
  3118  	// match: (CMPBconst (MOVLconst [x]) [y])
  3119  	// cond: int8(x)<int8(y) && uint8(x)<uint8(y)
  3120  	// result: (FlagLT_ULT)
  3121  	for {
  3122  		y := v.AuxInt
  3123  		v_0 := v.Args[0]
  3124  		if v_0.Op != Op386MOVLconst {
  3125  			break
  3126  		}
  3127  		x := v_0.AuxInt
  3128  		if !(int8(x) < int8(y) && uint8(x) < uint8(y)) {
  3129  			break
  3130  		}
  3131  		v.reset(Op386FlagLT_ULT)
  3132  		return true
  3133  	}
  3134  	// match: (CMPBconst (MOVLconst [x]) [y])
  3135  	// cond: int8(x)<int8(y) && uint8(x)>uint8(y)
  3136  	// result: (FlagLT_UGT)
  3137  	for {
  3138  		y := v.AuxInt
  3139  		v_0 := v.Args[0]
  3140  		if v_0.Op != Op386MOVLconst {
  3141  			break
  3142  		}
  3143  		x := v_0.AuxInt
  3144  		if !(int8(x) < int8(y) && uint8(x) > uint8(y)) {
  3145  			break
  3146  		}
  3147  		v.reset(Op386FlagLT_UGT)
  3148  		return true
  3149  	}
  3150  	// match: (CMPBconst (MOVLconst [x]) [y])
  3151  	// cond: int8(x)>int8(y) && uint8(x)<uint8(y)
  3152  	// result: (FlagGT_ULT)
  3153  	for {
  3154  		y := v.AuxInt
  3155  		v_0 := v.Args[0]
  3156  		if v_0.Op != Op386MOVLconst {
  3157  			break
  3158  		}
  3159  		x := v_0.AuxInt
  3160  		if !(int8(x) > int8(y) && uint8(x) < uint8(y)) {
  3161  			break
  3162  		}
  3163  		v.reset(Op386FlagGT_ULT)
  3164  		return true
  3165  	}
  3166  	// match: (CMPBconst (MOVLconst [x]) [y])
  3167  	// cond: int8(x)>int8(y) && uint8(x)>uint8(y)
  3168  	// result: (FlagGT_UGT)
  3169  	for {
  3170  		y := v.AuxInt
  3171  		v_0 := v.Args[0]
  3172  		if v_0.Op != Op386MOVLconst {
  3173  			break
  3174  		}
  3175  		x := v_0.AuxInt
  3176  		if !(int8(x) > int8(y) && uint8(x) > uint8(y)) {
  3177  			break
  3178  		}
  3179  		v.reset(Op386FlagGT_UGT)
  3180  		return true
  3181  	}
  3182  	// match: (CMPBconst (ANDLconst _ [m]) [n])
  3183  	// cond: 0 <= int8(m) && int8(m) < int8(n)
  3184  	// result: (FlagLT_ULT)
  3185  	for {
  3186  		n := v.AuxInt
  3187  		v_0 := v.Args[0]
  3188  		if v_0.Op != Op386ANDLconst {
  3189  			break
  3190  		}
  3191  		m := v_0.AuxInt
  3192  		if !(0 <= int8(m) && int8(m) < int8(n)) {
  3193  			break
  3194  		}
  3195  		v.reset(Op386FlagLT_ULT)
  3196  		return true
  3197  	}
  3198  	// match: (CMPBconst l:(ANDL x y) [0])
  3199  	// cond: l.Uses==1
  3200  	// result: (TESTB x y)
  3201  	for {
  3202  		if v.AuxInt != 0 {
  3203  			break
  3204  		}
  3205  		l := v.Args[0]
  3206  		if l.Op != Op386ANDL {
  3207  			break
  3208  		}
  3209  		y := l.Args[1]
  3210  		x := l.Args[0]
  3211  		if !(l.Uses == 1) {
  3212  			break
  3213  		}
  3214  		v.reset(Op386TESTB)
  3215  		v.AddArg(x)
  3216  		v.AddArg(y)
  3217  		return true
  3218  	}
  3219  	// match: (CMPBconst l:(ANDLconst [c] x) [0])
  3220  	// cond: l.Uses==1
  3221  	// result: (TESTBconst [int64(int8(c))] x)
  3222  	for {
  3223  		if v.AuxInt != 0 {
  3224  			break
  3225  		}
  3226  		l := v.Args[0]
  3227  		if l.Op != Op386ANDLconst {
  3228  			break
  3229  		}
  3230  		c := l.AuxInt
  3231  		x := l.Args[0]
  3232  		if !(l.Uses == 1) {
  3233  			break
  3234  		}
  3235  		v.reset(Op386TESTBconst)
  3236  		v.AuxInt = int64(int8(c))
  3237  		v.AddArg(x)
  3238  		return true
  3239  	}
  3240  	// match: (CMPBconst x [0])
  3241  	// cond:
  3242  	// result: (TESTB x x)
  3243  	for {
  3244  		if v.AuxInt != 0 {
  3245  			break
  3246  		}
  3247  		x := v.Args[0]
  3248  		v.reset(Op386TESTB)
  3249  		v.AddArg(x)
  3250  		v.AddArg(x)
  3251  		return true
  3252  	}
  3253  	// match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c])
  3254  	// cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l)
  3255  	// result: @l.Block (CMPBconstload {sym} [makeValAndOff(c,off)] ptr mem)
  3256  	for {
  3257  		c := v.AuxInt
  3258  		l := v.Args[0]
  3259  		if l.Op != Op386MOVBload {
  3260  			break
  3261  		}
  3262  		off := l.AuxInt
  3263  		sym := l.Aux
  3264  		mem := l.Args[1]
  3265  		ptr := l.Args[0]
  3266  		if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) {
  3267  			break
  3268  		}
  3269  		b = l.Block
  3270  		v0 := b.NewValue0(l.Pos, Op386CMPBconstload, types.TypeFlags)
  3271  		v.reset(OpCopy)
  3272  		v.AddArg(v0)
  3273  		v0.AuxInt = makeValAndOff(c, off)
  3274  		v0.Aux = sym
  3275  		v0.AddArg(ptr)
  3276  		v0.AddArg(mem)
  3277  		return true
  3278  	}
  3279  	return false
  3280  }
  3281  func rewriteValue386_Op386CMPBload_0(v *Value) bool {
  3282  	// match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem)
  3283  	// cond: validValAndOff(int64(int8(c)),off)
  3284  	// result: (CMPBconstload {sym} [makeValAndOff(int64(int8(c)),off)] ptr mem)
  3285  	for {
  3286  		off := v.AuxInt
  3287  		sym := v.Aux
  3288  		mem := v.Args[2]
  3289  		ptr := v.Args[0]
  3290  		v_1 := v.Args[1]
  3291  		if v_1.Op != Op386MOVLconst {
  3292  			break
  3293  		}
  3294  		c := v_1.AuxInt
  3295  		if !(validValAndOff(int64(int8(c)), off)) {
  3296  			break
  3297  		}
  3298  		v.reset(Op386CMPBconstload)
  3299  		v.AuxInt = makeValAndOff(int64(int8(c)), off)
  3300  		v.Aux = sym
  3301  		v.AddArg(ptr)
  3302  		v.AddArg(mem)
  3303  		return true
  3304  	}
  3305  	return false
  3306  }
  3307  func rewriteValue386_Op386CMPL_0(v *Value) bool {
  3308  	b := v.Block
  3309  	// match: (CMPL x (MOVLconst [c]))
  3310  	// cond:
  3311  	// result: (CMPLconst x [c])
  3312  	for {
  3313  		_ = v.Args[1]
  3314  		x := v.Args[0]
  3315  		v_1 := v.Args[1]
  3316  		if v_1.Op != Op386MOVLconst {
  3317  			break
  3318  		}
  3319  		c := v_1.AuxInt
  3320  		v.reset(Op386CMPLconst)
  3321  		v.AuxInt = c
  3322  		v.AddArg(x)
  3323  		return true
  3324  	}
  3325  	// match: (CMPL (MOVLconst [c]) x)
  3326  	// cond:
  3327  	// result: (InvertFlags (CMPLconst x [c]))
  3328  	for {
  3329  		x := v.Args[1]
  3330  		v_0 := v.Args[0]
  3331  		if v_0.Op != Op386MOVLconst {
  3332  			break
  3333  		}
  3334  		c := v_0.AuxInt
  3335  		v.reset(Op386InvertFlags)
  3336  		v0 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags)
  3337  		v0.AuxInt = c
  3338  		v0.AddArg(x)
  3339  		v.AddArg(v0)
  3340  		return true
  3341  	}
  3342  	// match: (CMPL l:(MOVLload {sym} [off] ptr mem) x)
  3343  	// cond: canMergeLoad(v, l) && clobber(l)
  3344  	// result: (CMPLload {sym} [off] ptr x mem)
  3345  	for {
  3346  		x := v.Args[1]
  3347  		l := v.Args[0]
  3348  		if l.Op != Op386MOVLload {
  3349  			break
  3350  		}
  3351  		off := l.AuxInt
  3352  		sym := l.Aux
  3353  		mem := l.Args[1]
  3354  		ptr := l.Args[0]
  3355  		if !(canMergeLoad(v, l) && clobber(l)) {
  3356  			break
  3357  		}
  3358  		v.reset(Op386CMPLload)
  3359  		v.AuxInt = off
  3360  		v.Aux = sym
  3361  		v.AddArg(ptr)
  3362  		v.AddArg(x)
  3363  		v.AddArg(mem)
  3364  		return true
  3365  	}
  3366  	// match: (CMPL x l:(MOVLload {sym} [off] ptr mem))
  3367  	// cond: canMergeLoad(v, l) && clobber(l)
  3368  	// result: (InvertFlags (CMPLload {sym} [off] ptr x mem))
  3369  	for {
  3370  		_ = v.Args[1]
  3371  		x := v.Args[0]
  3372  		l := v.Args[1]
  3373  		if l.Op != Op386MOVLload {
  3374  			break
  3375  		}
  3376  		off := l.AuxInt
  3377  		sym := l.Aux
  3378  		mem := l.Args[1]
  3379  		ptr := l.Args[0]
  3380  		if !(canMergeLoad(v, l) && clobber(l)) {
  3381  			break
  3382  		}
  3383  		v.reset(Op386InvertFlags)
  3384  		v0 := b.NewValue0(l.Pos, Op386CMPLload, types.TypeFlags)
  3385  		v0.AuxInt = off
  3386  		v0.Aux = sym
  3387  		v0.AddArg(ptr)
  3388  		v0.AddArg(x)
  3389  		v0.AddArg(mem)
  3390  		v.AddArg(v0)
  3391  		return true
  3392  	}
  3393  	return false
  3394  }
  3395  func rewriteValue386_Op386CMPLconst_0(v *Value) bool {
  3396  	// match: (CMPLconst (MOVLconst [x]) [y])
  3397  	// cond: int32(x)==int32(y)
  3398  	// result: (FlagEQ)
  3399  	for {
  3400  		y := v.AuxInt
  3401  		v_0 := v.Args[0]
  3402  		if v_0.Op != Op386MOVLconst {
  3403  			break
  3404  		}
  3405  		x := v_0.AuxInt
  3406  		if !(int32(x) == int32(y)) {
  3407  			break
  3408  		}
  3409  		v.reset(Op386FlagEQ)
  3410  		return true
  3411  	}
  3412  	// match: (CMPLconst (MOVLconst [x]) [y])
  3413  	// cond: int32(x)<int32(y) && uint32(x)<uint32(y)
  3414  	// result: (FlagLT_ULT)
  3415  	for {
  3416  		y := v.AuxInt
  3417  		v_0 := v.Args[0]
  3418  		if v_0.Op != Op386MOVLconst {
  3419  			break
  3420  		}
  3421  		x := v_0.AuxInt
  3422  		if !(int32(x) < int32(y) && uint32(x) < uint32(y)) {
  3423  			break
  3424  		}
  3425  		v.reset(Op386FlagLT_ULT)
  3426  		return true
  3427  	}
  3428  	// match: (CMPLconst (MOVLconst [x]) [y])
  3429  	// cond: int32(x)<int32(y) && uint32(x)>uint32(y)
  3430  	// result: (FlagLT_UGT)
  3431  	for {
  3432  		y := v.AuxInt
  3433  		v_0 := v.Args[0]
  3434  		if v_0.Op != Op386MOVLconst {
  3435  			break
  3436  		}
  3437  		x := v_0.AuxInt
  3438  		if !(int32(x) < int32(y) && uint32(x) > uint32(y)) {
  3439  			break
  3440  		}
  3441  		v.reset(Op386FlagLT_UGT)
  3442  		return true
  3443  	}
  3444  	// match: (CMPLconst (MOVLconst [x]) [y])
  3445  	// cond: int32(x)>int32(y) && uint32(x)<uint32(y)
  3446  	// result: (FlagGT_ULT)
  3447  	for {
  3448  		y := v.AuxInt
  3449  		v_0 := v.Args[0]
  3450  		if v_0.Op != Op386MOVLconst {
  3451  			break
  3452  		}
  3453  		x := v_0.AuxInt
  3454  		if !(int32(x) > int32(y) && uint32(x) < uint32(y)) {
  3455  			break
  3456  		}
  3457  		v.reset(Op386FlagGT_ULT)
  3458  		return true
  3459  	}
  3460  	// match: (CMPLconst (MOVLconst [x]) [y])
  3461  	// cond: int32(x)>int32(y) && uint32(x)>uint32(y)
  3462  	// result: (FlagGT_UGT)
  3463  	for {
  3464  		y := v.AuxInt
  3465  		v_0 := v.Args[0]
  3466  		if v_0.Op != Op386MOVLconst {
  3467  			break
  3468  		}
  3469  		x := v_0.AuxInt
  3470  		if !(int32(x) > int32(y) && uint32(x) > uint32(y)) {
  3471  			break
  3472  		}
  3473  		v.reset(Op386FlagGT_UGT)
  3474  		return true
  3475  	}
  3476  	// match: (CMPLconst (SHRLconst _ [c]) [n])
  3477  	// cond: 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n)
  3478  	// result: (FlagLT_ULT)
  3479  	for {
  3480  		n := v.AuxInt
  3481  		v_0 := v.Args[0]
  3482  		if v_0.Op != Op386SHRLconst {
  3483  			break
  3484  		}
  3485  		c := v_0.AuxInt
  3486  		if !(0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n)) {
  3487  			break
  3488  		}
  3489  		v.reset(Op386FlagLT_ULT)
  3490  		return true
  3491  	}
  3492  	// match: (CMPLconst (ANDLconst _ [m]) [n])
  3493  	// cond: 0 <= int32(m) && int32(m) < int32(n)
  3494  	// result: (FlagLT_ULT)
  3495  	for {
  3496  		n := v.AuxInt
  3497  		v_0 := v.Args[0]
  3498  		if v_0.Op != Op386ANDLconst {
  3499  			break
  3500  		}
  3501  		m := v_0.AuxInt
  3502  		if !(0 <= int32(m) && int32(m) < int32(n)) {
  3503  			break
  3504  		}
  3505  		v.reset(Op386FlagLT_ULT)
  3506  		return true
  3507  	}
  3508  	// match: (CMPLconst l:(ANDL x y) [0])
  3509  	// cond: l.Uses==1
  3510  	// result: (TESTL x y)
  3511  	for {
  3512  		if v.AuxInt != 0 {
  3513  			break
  3514  		}
  3515  		l := v.Args[0]
  3516  		if l.Op != Op386ANDL {
  3517  			break
  3518  		}
  3519  		y := l.Args[1]
  3520  		x := l.Args[0]
  3521  		if !(l.Uses == 1) {
  3522  			break
  3523  		}
  3524  		v.reset(Op386TESTL)
  3525  		v.AddArg(x)
  3526  		v.AddArg(y)
  3527  		return true
  3528  	}
  3529  	// match: (CMPLconst l:(ANDLconst [c] x) [0])
  3530  	// cond: l.Uses==1
  3531  	// result: (TESTLconst [c] x)
  3532  	for {
  3533  		if v.AuxInt != 0 {
  3534  			break
  3535  		}
  3536  		l := v.Args[0]
  3537  		if l.Op != Op386ANDLconst {
  3538  			break
  3539  		}
  3540  		c := l.AuxInt
  3541  		x := l.Args[0]
  3542  		if !(l.Uses == 1) {
  3543  			break
  3544  		}
  3545  		v.reset(Op386TESTLconst)
  3546  		v.AuxInt = c
  3547  		v.AddArg(x)
  3548  		return true
  3549  	}
  3550  	// match: (CMPLconst x [0])
  3551  	// cond:
  3552  	// result: (TESTL x x)
  3553  	for {
  3554  		if v.AuxInt != 0 {
  3555  			break
  3556  		}
  3557  		x := v.Args[0]
  3558  		v.reset(Op386TESTL)
  3559  		v.AddArg(x)
  3560  		v.AddArg(x)
  3561  		return true
  3562  	}
  3563  	return false
  3564  }
  3565  func rewriteValue386_Op386CMPLconst_10(v *Value) bool {
  3566  	b := v.Block
  3567  	// match: (CMPLconst l:(MOVLload {sym} [off] ptr mem) [c])
  3568  	// cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l)
  3569  	// result: @l.Block (CMPLconstload {sym} [makeValAndOff(c,off)] ptr mem)
  3570  	for {
  3571  		c := v.AuxInt
  3572  		l := v.Args[0]
  3573  		if l.Op != Op386MOVLload {
  3574  			break
  3575  		}
  3576  		off := l.AuxInt
  3577  		sym := l.Aux
  3578  		mem := l.Args[1]
  3579  		ptr := l.Args[0]
  3580  		if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) {
  3581  			break
  3582  		}
  3583  		b = l.Block
  3584  		v0 := b.NewValue0(l.Pos, Op386CMPLconstload, types.TypeFlags)
  3585  		v.reset(OpCopy)
  3586  		v.AddArg(v0)
  3587  		v0.AuxInt = makeValAndOff(c, off)
  3588  		v0.Aux = sym
  3589  		v0.AddArg(ptr)
  3590  		v0.AddArg(mem)
  3591  		return true
  3592  	}
  3593  	return false
  3594  }
  3595  func rewriteValue386_Op386CMPLload_0(v *Value) bool {
  3596  	// match: (CMPLload {sym} [off] ptr (MOVLconst [c]) mem)
  3597  	// cond: validValAndOff(int64(int32(c)),off)
  3598  	// result: (CMPLconstload {sym} [makeValAndOff(int64(int32(c)),off)] ptr mem)
  3599  	for {
  3600  		off := v.AuxInt
  3601  		sym := v.Aux
  3602  		mem := v.Args[2]
  3603  		ptr := v.Args[0]
  3604  		v_1 := v.Args[1]
  3605  		if v_1.Op != Op386MOVLconst {
  3606  			break
  3607  		}
  3608  		c := v_1.AuxInt
  3609  		if !(validValAndOff(int64(int32(c)), off)) {
  3610  			break
  3611  		}
  3612  		v.reset(Op386CMPLconstload)
  3613  		v.AuxInt = makeValAndOff(int64(int32(c)), off)
  3614  		v.Aux = sym
  3615  		v.AddArg(ptr)
  3616  		v.AddArg(mem)
  3617  		return true
  3618  	}
  3619  	return false
  3620  }
  3621  func rewriteValue386_Op386CMPW_0(v *Value) bool {
  3622  	b := v.Block
  3623  	// match: (CMPW x (MOVLconst [c]))
  3624  	// cond:
  3625  	// result: (CMPWconst x [int64(int16(c))])
  3626  	for {
  3627  		_ = v.Args[1]
  3628  		x := v.Args[0]
  3629  		v_1 := v.Args[1]
  3630  		if v_1.Op != Op386MOVLconst {
  3631  			break
  3632  		}
  3633  		c := v_1.AuxInt
  3634  		v.reset(Op386CMPWconst)
  3635  		v.AuxInt = int64(int16(c))
  3636  		v.AddArg(x)
  3637  		return true
  3638  	}
  3639  	// match: (CMPW (MOVLconst [c]) x)
  3640  	// cond:
  3641  	// result: (InvertFlags (CMPWconst x [int64(int16(c))]))
  3642  	for {
  3643  		x := v.Args[1]
  3644  		v_0 := v.Args[0]
  3645  		if v_0.Op != Op386MOVLconst {
  3646  			break
  3647  		}
  3648  		c := v_0.AuxInt
  3649  		v.reset(Op386InvertFlags)
  3650  		v0 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags)
  3651  		v0.AuxInt = int64(int16(c))
  3652  		v0.AddArg(x)
  3653  		v.AddArg(v0)
  3654  		return true
  3655  	}
  3656  	// match: (CMPW l:(MOVWload {sym} [off] ptr mem) x)
  3657  	// cond: canMergeLoad(v, l) && clobber(l)
  3658  	// result: (CMPWload {sym} [off] ptr x mem)
  3659  	for {
  3660  		x := v.Args[1]
  3661  		l := v.Args[0]
  3662  		if l.Op != Op386MOVWload {
  3663  			break
  3664  		}
  3665  		off := l.AuxInt
  3666  		sym := l.Aux
  3667  		mem := l.Args[1]
  3668  		ptr := l.Args[0]
  3669  		if !(canMergeLoad(v, l) && clobber(l)) {
  3670  			break
  3671  		}
  3672  		v.reset(Op386CMPWload)
  3673  		v.AuxInt = off
  3674  		v.Aux = sym
  3675  		v.AddArg(ptr)
  3676  		v.AddArg(x)
  3677  		v.AddArg(mem)
  3678  		return true
  3679  	}
  3680  	// match: (CMPW x l:(MOVWload {sym} [off] ptr mem))
  3681  	// cond: canMergeLoad(v, l) && clobber(l)
  3682  	// result: (InvertFlags (CMPWload {sym} [off] ptr x mem))
  3683  	for {
  3684  		_ = v.Args[1]
  3685  		x := v.Args[0]
  3686  		l := v.Args[1]
  3687  		if l.Op != Op386MOVWload {
  3688  			break
  3689  		}
  3690  		off := l.AuxInt
  3691  		sym := l.Aux
  3692  		mem := l.Args[1]
  3693  		ptr := l.Args[0]
  3694  		if !(canMergeLoad(v, l) && clobber(l)) {
  3695  			break
  3696  		}
  3697  		v.reset(Op386InvertFlags)
  3698  		v0 := b.NewValue0(l.Pos, Op386CMPWload, types.TypeFlags)
  3699  		v0.AuxInt = off
  3700  		v0.Aux = sym
  3701  		v0.AddArg(ptr)
  3702  		v0.AddArg(x)
  3703  		v0.AddArg(mem)
  3704  		v.AddArg(v0)
  3705  		return true
  3706  	}
  3707  	return false
  3708  }
  3709  func rewriteValue386_Op386CMPWconst_0(v *Value) bool {
  3710  	b := v.Block
  3711  	// match: (CMPWconst (MOVLconst [x]) [y])
  3712  	// cond: int16(x)==int16(y)
  3713  	// result: (FlagEQ)
  3714  	for {
  3715  		y := v.AuxInt
  3716  		v_0 := v.Args[0]
  3717  		if v_0.Op != Op386MOVLconst {
  3718  			break
  3719  		}
  3720  		x := v_0.AuxInt
  3721  		if !(int16(x) == int16(y)) {
  3722  			break
  3723  		}
  3724  		v.reset(Op386FlagEQ)
  3725  		return true
  3726  	}
  3727  	// match: (CMPWconst (MOVLconst [x]) [y])
  3728  	// cond: int16(x)<int16(y) && uint16(x)<uint16(y)
  3729  	// result: (FlagLT_ULT)
  3730  	for {
  3731  		y := v.AuxInt
  3732  		v_0 := v.Args[0]
  3733  		if v_0.Op != Op386MOVLconst {
  3734  			break
  3735  		}
  3736  		x := v_0.AuxInt
  3737  		if !(int16(x) < int16(y) && uint16(x) < uint16(y)) {
  3738  			break
  3739  		}
  3740  		v.reset(Op386FlagLT_ULT)
  3741  		return true
  3742  	}
  3743  	// match: (CMPWconst (MOVLconst [x]) [y])
  3744  	// cond: int16(x)<int16(y) && uint16(x)>uint16(y)
  3745  	// result: (FlagLT_UGT)
  3746  	for {
  3747  		y := v.AuxInt
  3748  		v_0 := v.Args[0]
  3749  		if v_0.Op != Op386MOVLconst {
  3750  			break
  3751  		}
  3752  		x := v_0.AuxInt
  3753  		if !(int16(x) < int16(y) && uint16(x) > uint16(y)) {
  3754  			break
  3755  		}
  3756  		v.reset(Op386FlagLT_UGT)
  3757  		return true
  3758  	}
  3759  	// match: (CMPWconst (MOVLconst [x]) [y])
  3760  	// cond: int16(x)>int16(y) && uint16(x)<uint16(y)
  3761  	// result: (FlagGT_ULT)
  3762  	for {
  3763  		y := v.AuxInt
  3764  		v_0 := v.Args[0]
  3765  		if v_0.Op != Op386MOVLconst {
  3766  			break
  3767  		}
  3768  		x := v_0.AuxInt
  3769  		if !(int16(x) > int16(y) && uint16(x) < uint16(y)) {
  3770  			break
  3771  		}
  3772  		v.reset(Op386FlagGT_ULT)
  3773  		return true
  3774  	}
  3775  	// match: (CMPWconst (MOVLconst [x]) [y])
  3776  	// cond: int16(x)>int16(y) && uint16(x)>uint16(y)
  3777  	// result: (FlagGT_UGT)
  3778  	for {
  3779  		y := v.AuxInt
  3780  		v_0 := v.Args[0]
  3781  		if v_0.Op != Op386MOVLconst {
  3782  			break
  3783  		}
  3784  		x := v_0.AuxInt
  3785  		if !(int16(x) > int16(y) && uint16(x) > uint16(y)) {
  3786  			break
  3787  		}
  3788  		v.reset(Op386FlagGT_UGT)
  3789  		return true
  3790  	}
  3791  	// match: (CMPWconst (ANDLconst _ [m]) [n])
  3792  	// cond: 0 <= int16(m) && int16(m) < int16(n)
  3793  	// result: (FlagLT_ULT)
  3794  	for {
  3795  		n := v.AuxInt
  3796  		v_0 := v.Args[0]
  3797  		if v_0.Op != Op386ANDLconst {
  3798  			break
  3799  		}
  3800  		m := v_0.AuxInt
  3801  		if !(0 <= int16(m) && int16(m) < int16(n)) {
  3802  			break
  3803  		}
  3804  		v.reset(Op386FlagLT_ULT)
  3805  		return true
  3806  	}
  3807  	// match: (CMPWconst l:(ANDL x y) [0])
  3808  	// cond: l.Uses==1
  3809  	// result: (TESTW x y)
  3810  	for {
  3811  		if v.AuxInt != 0 {
  3812  			break
  3813  		}
  3814  		l := v.Args[0]
  3815  		if l.Op != Op386ANDL {
  3816  			break
  3817  		}
  3818  		y := l.Args[1]
  3819  		x := l.Args[0]
  3820  		if !(l.Uses == 1) {
  3821  			break
  3822  		}
  3823  		v.reset(Op386TESTW)
  3824  		v.AddArg(x)
  3825  		v.AddArg(y)
  3826  		return true
  3827  	}
  3828  	// match: (CMPWconst l:(ANDLconst [c] x) [0])
  3829  	// cond: l.Uses==1
  3830  	// result: (TESTWconst [int64(int16(c))] x)
  3831  	for {
  3832  		if v.AuxInt != 0 {
  3833  			break
  3834  		}
  3835  		l := v.Args[0]
  3836  		if l.Op != Op386ANDLconst {
  3837  			break
  3838  		}
  3839  		c := l.AuxInt
  3840  		x := l.Args[0]
  3841  		if !(l.Uses == 1) {
  3842  			break
  3843  		}
  3844  		v.reset(Op386TESTWconst)
  3845  		v.AuxInt = int64(int16(c))
  3846  		v.AddArg(x)
  3847  		return true
  3848  	}
  3849  	// match: (CMPWconst x [0])
  3850  	// cond:
  3851  	// result: (TESTW x x)
  3852  	for {
  3853  		if v.AuxInt != 0 {
  3854  			break
  3855  		}
  3856  		x := v.Args[0]
  3857  		v.reset(Op386TESTW)
  3858  		v.AddArg(x)
  3859  		v.AddArg(x)
  3860  		return true
  3861  	}
  3862  	// match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c])
  3863  	// cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l)
  3864  	// result: @l.Block (CMPWconstload {sym} [makeValAndOff(c,off)] ptr mem)
  3865  	for {
  3866  		c := v.AuxInt
  3867  		l := v.Args[0]
  3868  		if l.Op != Op386MOVWload {
  3869  			break
  3870  		}
  3871  		off := l.AuxInt
  3872  		sym := l.Aux
  3873  		mem := l.Args[1]
  3874  		ptr := l.Args[0]
  3875  		if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) {
  3876  			break
  3877  		}
  3878  		b = l.Block
  3879  		v0 := b.NewValue0(l.Pos, Op386CMPWconstload, types.TypeFlags)
  3880  		v.reset(OpCopy)
  3881  		v.AddArg(v0)
  3882  		v0.AuxInt = makeValAndOff(c, off)
  3883  		v0.Aux = sym
  3884  		v0.AddArg(ptr)
  3885  		v0.AddArg(mem)
  3886  		return true
  3887  	}
  3888  	return false
  3889  }
  3890  func rewriteValue386_Op386CMPWload_0(v *Value) bool {
  3891  	// match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem)
  3892  	// cond: validValAndOff(int64(int16(c)),off)
  3893  	// result: (CMPWconstload {sym} [makeValAndOff(int64(int16(c)),off)] ptr mem)
  3894  	for {
  3895  		off := v.AuxInt
  3896  		sym := v.Aux
  3897  		mem := v.Args[2]
  3898  		ptr := v.Args[0]
  3899  		v_1 := v.Args[1]
  3900  		if v_1.Op != Op386MOVLconst {
  3901  			break
  3902  		}
  3903  		c := v_1.AuxInt
  3904  		if !(validValAndOff(int64(int16(c)), off)) {
  3905  			break
  3906  		}
  3907  		v.reset(Op386CMPWconstload)
  3908  		v.AuxInt = makeValAndOff(int64(int16(c)), off)
  3909  		v.Aux = sym
  3910  		v.AddArg(ptr)
  3911  		v.AddArg(mem)
  3912  		return true
  3913  	}
  3914  	return false
  3915  }
  3916  func rewriteValue386_Op386DIVSD_0(v *Value) bool {
  3917  	b := v.Block
  3918  	config := b.Func.Config
  3919  	// match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem))
  3920  	// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
  3921  	// result: (DIVSDload x [off] {sym} ptr mem)
  3922  	for {
  3923  		_ = v.Args[1]
  3924  		x := v.Args[0]
  3925  		l := v.Args[1]
  3926  		if l.Op != Op386MOVSDload {
  3927  			break
  3928  		}
  3929  		off := l.AuxInt
  3930  		sym := l.Aux
  3931  		mem := l.Args[1]
  3932  		ptr := l.Args[0]
  3933  		if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
  3934  			break
  3935  		}
  3936  		v.reset(Op386DIVSDload)
  3937  		v.AuxInt = off
  3938  		v.Aux = sym
  3939  		v.AddArg(x)
  3940  		v.AddArg(ptr)
  3941  		v.AddArg(mem)
  3942  		return true
  3943  	}
  3944  	return false
  3945  }
  3946  func rewriteValue386_Op386DIVSDload_0(v *Value) bool {
  3947  	b := v.Block
  3948  	config := b.Func.Config
  3949  	// match: (DIVSDload [off1] {sym} val (ADDLconst [off2] base) mem)
  3950  	// cond: is32Bit(off1+off2)
  3951  	// result: (DIVSDload [off1+off2] {sym} val base mem)
  3952  	for {
  3953  		off1 := v.AuxInt
  3954  		sym := v.Aux
  3955  		mem := v.Args[2]
  3956  		val := v.Args[0]
  3957  		v_1 := v.Args[1]
  3958  		if v_1.Op != Op386ADDLconst {
  3959  			break
  3960  		}
  3961  		off2 := v_1.AuxInt
  3962  		base := v_1.Args[0]
  3963  		if !(is32Bit(off1 + off2)) {
  3964  			break
  3965  		}
  3966  		v.reset(Op386DIVSDload)
  3967  		v.AuxInt = off1 + off2
  3968  		v.Aux = sym
  3969  		v.AddArg(val)
  3970  		v.AddArg(base)
  3971  		v.AddArg(mem)
  3972  		return true
  3973  	}
  3974  	// match: (DIVSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
  3975  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  3976  	// result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  3977  	for {
  3978  		off1 := v.AuxInt
  3979  		sym1 := v.Aux
  3980  		mem := v.Args[2]
  3981  		val := v.Args[0]
  3982  		v_1 := v.Args[1]
  3983  		if v_1.Op != Op386LEAL {
  3984  			break
  3985  		}
  3986  		off2 := v_1.AuxInt
  3987  		sym2 := v_1.Aux
  3988  		base := v_1.Args[0]
  3989  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  3990  			break
  3991  		}
  3992  		v.reset(Op386DIVSDload)
  3993  		v.AuxInt = off1 + off2
  3994  		v.Aux = mergeSym(sym1, sym2)
  3995  		v.AddArg(val)
  3996  		v.AddArg(base)
  3997  		v.AddArg(mem)
  3998  		return true
  3999  	}
  4000  	return false
  4001  }
  4002  func rewriteValue386_Op386DIVSS_0(v *Value) bool {
  4003  	b := v.Block
  4004  	config := b.Func.Config
  4005  	// match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem))
  4006  	// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
  4007  	// result: (DIVSSload x [off] {sym} ptr mem)
  4008  	for {
  4009  		_ = v.Args[1]
  4010  		x := v.Args[0]
  4011  		l := v.Args[1]
  4012  		if l.Op != Op386MOVSSload {
  4013  			break
  4014  		}
  4015  		off := l.AuxInt
  4016  		sym := l.Aux
  4017  		mem := l.Args[1]
  4018  		ptr := l.Args[0]
  4019  		if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
  4020  			break
  4021  		}
  4022  		v.reset(Op386DIVSSload)
  4023  		v.AuxInt = off
  4024  		v.Aux = sym
  4025  		v.AddArg(x)
  4026  		v.AddArg(ptr)
  4027  		v.AddArg(mem)
  4028  		return true
  4029  	}
  4030  	return false
  4031  }
  4032  func rewriteValue386_Op386DIVSSload_0(v *Value) bool {
  4033  	b := v.Block
  4034  	config := b.Func.Config
  4035  	// match: (DIVSSload [off1] {sym} val (ADDLconst [off2] base) mem)
  4036  	// cond: is32Bit(off1+off2)
  4037  	// result: (DIVSSload [off1+off2] {sym} val base mem)
  4038  	for {
  4039  		off1 := v.AuxInt
  4040  		sym := v.Aux
  4041  		mem := v.Args[2]
  4042  		val := v.Args[0]
  4043  		v_1 := v.Args[1]
  4044  		if v_1.Op != Op386ADDLconst {
  4045  			break
  4046  		}
  4047  		off2 := v_1.AuxInt
  4048  		base := v_1.Args[0]
  4049  		if !(is32Bit(off1 + off2)) {
  4050  			break
  4051  		}
  4052  		v.reset(Op386DIVSSload)
  4053  		v.AuxInt = off1 + off2
  4054  		v.Aux = sym
  4055  		v.AddArg(val)
  4056  		v.AddArg(base)
  4057  		v.AddArg(mem)
  4058  		return true
  4059  	}
  4060  	// match: (DIVSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
  4061  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  4062  	// result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  4063  	for {
  4064  		off1 := v.AuxInt
  4065  		sym1 := v.Aux
  4066  		mem := v.Args[2]
  4067  		val := v.Args[0]
  4068  		v_1 := v.Args[1]
  4069  		if v_1.Op != Op386LEAL {
  4070  			break
  4071  		}
  4072  		off2 := v_1.AuxInt
  4073  		sym2 := v_1.Aux
  4074  		base := v_1.Args[0]
  4075  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  4076  			break
  4077  		}
  4078  		v.reset(Op386DIVSSload)
  4079  		v.AuxInt = off1 + off2
  4080  		v.Aux = mergeSym(sym1, sym2)
  4081  		v.AddArg(val)
  4082  		v.AddArg(base)
  4083  		v.AddArg(mem)
  4084  		return true
  4085  	}
  4086  	return false
  4087  }
  4088  func rewriteValue386_Op386LEAL_0(v *Value) bool {
  4089  	// match: (LEAL [c] {s} (ADDLconst [d] x))
  4090  	// cond: is32Bit(c+d)
  4091  	// result: (LEAL [c+d] {s} x)
  4092  	for {
  4093  		c := v.AuxInt
  4094  		s := v.Aux
  4095  		v_0 := v.Args[0]
  4096  		if v_0.Op != Op386ADDLconst {
  4097  			break
  4098  		}
  4099  		d := v_0.AuxInt
  4100  		x := v_0.Args[0]
  4101  		if !(is32Bit(c + d)) {
  4102  			break
  4103  		}
  4104  		v.reset(Op386LEAL)
  4105  		v.AuxInt = c + d
  4106  		v.Aux = s
  4107  		v.AddArg(x)
  4108  		return true
  4109  	}
  4110  	// match: (LEAL [c] {s} (ADDL x y))
  4111  	// cond: x.Op != OpSB && y.Op != OpSB
  4112  	// result: (LEAL1 [c] {s} x y)
  4113  	for {
  4114  		c := v.AuxInt
  4115  		s := v.Aux
  4116  		v_0 := v.Args[0]
  4117  		if v_0.Op != Op386ADDL {
  4118  			break
  4119  		}
  4120  		y := v_0.Args[1]
  4121  		x := v_0.Args[0]
  4122  		if !(x.Op != OpSB && y.Op != OpSB) {
  4123  			break
  4124  		}
  4125  		v.reset(Op386LEAL1)
  4126  		v.AuxInt = c
  4127  		v.Aux = s
  4128  		v.AddArg(x)
  4129  		v.AddArg(y)
  4130  		return true
  4131  	}
  4132  	// match: (LEAL [off1] {sym1} (LEAL [off2] {sym2} x))
  4133  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4134  	// result: (LEAL [off1+off2] {mergeSym(sym1,sym2)} x)
  4135  	for {
  4136  		off1 := v.AuxInt
  4137  		sym1 := v.Aux
  4138  		v_0 := v.Args[0]
  4139  		if v_0.Op != Op386LEAL {
  4140  			break
  4141  		}
  4142  		off2 := v_0.AuxInt
  4143  		sym2 := v_0.Aux
  4144  		x := v_0.Args[0]
  4145  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4146  			break
  4147  		}
  4148  		v.reset(Op386LEAL)
  4149  		v.AuxInt = off1 + off2
  4150  		v.Aux = mergeSym(sym1, sym2)
  4151  		v.AddArg(x)
  4152  		return true
  4153  	}
  4154  	// match: (LEAL [off1] {sym1} (LEAL1 [off2] {sym2} x y))
  4155  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4156  	// result: (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4157  	for {
  4158  		off1 := v.AuxInt
  4159  		sym1 := v.Aux
  4160  		v_0 := v.Args[0]
  4161  		if v_0.Op != Op386LEAL1 {
  4162  			break
  4163  		}
  4164  		off2 := v_0.AuxInt
  4165  		sym2 := v_0.Aux
  4166  		y := v_0.Args[1]
  4167  		x := v_0.Args[0]
  4168  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4169  			break
  4170  		}
  4171  		v.reset(Op386LEAL1)
  4172  		v.AuxInt = off1 + off2
  4173  		v.Aux = mergeSym(sym1, sym2)
  4174  		v.AddArg(x)
  4175  		v.AddArg(y)
  4176  		return true
  4177  	}
  4178  	// match: (LEAL [off1] {sym1} (LEAL2 [off2] {sym2} x y))
  4179  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4180  	// result: (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4181  	for {
  4182  		off1 := v.AuxInt
  4183  		sym1 := v.Aux
  4184  		v_0 := v.Args[0]
  4185  		if v_0.Op != Op386LEAL2 {
  4186  			break
  4187  		}
  4188  		off2 := v_0.AuxInt
  4189  		sym2 := v_0.Aux
  4190  		y := v_0.Args[1]
  4191  		x := v_0.Args[0]
  4192  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4193  			break
  4194  		}
  4195  		v.reset(Op386LEAL2)
  4196  		v.AuxInt = off1 + off2
  4197  		v.Aux = mergeSym(sym1, sym2)
  4198  		v.AddArg(x)
  4199  		v.AddArg(y)
  4200  		return true
  4201  	}
  4202  	// match: (LEAL [off1] {sym1} (LEAL4 [off2] {sym2} x y))
  4203  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4204  	// result: (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4205  	for {
  4206  		off1 := v.AuxInt
  4207  		sym1 := v.Aux
  4208  		v_0 := v.Args[0]
  4209  		if v_0.Op != Op386LEAL4 {
  4210  			break
  4211  		}
  4212  		off2 := v_0.AuxInt
  4213  		sym2 := v_0.Aux
  4214  		y := v_0.Args[1]
  4215  		x := v_0.Args[0]
  4216  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4217  			break
  4218  		}
  4219  		v.reset(Op386LEAL4)
  4220  		v.AuxInt = off1 + off2
  4221  		v.Aux = mergeSym(sym1, sym2)
  4222  		v.AddArg(x)
  4223  		v.AddArg(y)
  4224  		return true
  4225  	}
  4226  	// match: (LEAL [off1] {sym1} (LEAL8 [off2] {sym2} x y))
  4227  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4228  	// result: (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4229  	for {
  4230  		off1 := v.AuxInt
  4231  		sym1 := v.Aux
  4232  		v_0 := v.Args[0]
  4233  		if v_0.Op != Op386LEAL8 {
  4234  			break
  4235  		}
  4236  		off2 := v_0.AuxInt
  4237  		sym2 := v_0.Aux
  4238  		y := v_0.Args[1]
  4239  		x := v_0.Args[0]
  4240  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4241  			break
  4242  		}
  4243  		v.reset(Op386LEAL8)
  4244  		v.AuxInt = off1 + off2
  4245  		v.Aux = mergeSym(sym1, sym2)
  4246  		v.AddArg(x)
  4247  		v.AddArg(y)
  4248  		return true
  4249  	}
  4250  	return false
  4251  }
  4252  func rewriteValue386_Op386LEAL1_0(v *Value) bool {
  4253  	// match: (LEAL1 [c] {s} (ADDLconst [d] x) y)
  4254  	// cond: is32Bit(c+d) && x.Op != OpSB
  4255  	// result: (LEAL1 [c+d] {s} x y)
  4256  	for {
  4257  		c := v.AuxInt
  4258  		s := v.Aux
  4259  		y := v.Args[1]
  4260  		v_0 := v.Args[0]
  4261  		if v_0.Op != Op386ADDLconst {
  4262  			break
  4263  		}
  4264  		d := v_0.AuxInt
  4265  		x := v_0.Args[0]
  4266  		if !(is32Bit(c+d) && x.Op != OpSB) {
  4267  			break
  4268  		}
  4269  		v.reset(Op386LEAL1)
  4270  		v.AuxInt = c + d
  4271  		v.Aux = s
  4272  		v.AddArg(x)
  4273  		v.AddArg(y)
  4274  		return true
  4275  	}
  4276  	// match: (LEAL1 [c] {s} y (ADDLconst [d] x))
  4277  	// cond: is32Bit(c+d) && x.Op != OpSB
  4278  	// result: (LEAL1 [c+d] {s} x y)
  4279  	for {
  4280  		c := v.AuxInt
  4281  		s := v.Aux
  4282  		_ = v.Args[1]
  4283  		y := v.Args[0]
  4284  		v_1 := v.Args[1]
  4285  		if v_1.Op != Op386ADDLconst {
  4286  			break
  4287  		}
  4288  		d := v_1.AuxInt
  4289  		x := v_1.Args[0]
  4290  		if !(is32Bit(c+d) && x.Op != OpSB) {
  4291  			break
  4292  		}
  4293  		v.reset(Op386LEAL1)
  4294  		v.AuxInt = c + d
  4295  		v.Aux = s
  4296  		v.AddArg(x)
  4297  		v.AddArg(y)
  4298  		return true
  4299  	}
  4300  	// match: (LEAL1 [c] {s} x (SHLLconst [1] y))
  4301  	// cond:
  4302  	// result: (LEAL2 [c] {s} x y)
  4303  	for {
  4304  		c := v.AuxInt
  4305  		s := v.Aux
  4306  		_ = v.Args[1]
  4307  		x := v.Args[0]
  4308  		v_1 := v.Args[1]
  4309  		if v_1.Op != Op386SHLLconst {
  4310  			break
  4311  		}
  4312  		if v_1.AuxInt != 1 {
  4313  			break
  4314  		}
  4315  		y := v_1.Args[0]
  4316  		v.reset(Op386LEAL2)
  4317  		v.AuxInt = c
  4318  		v.Aux = s
  4319  		v.AddArg(x)
  4320  		v.AddArg(y)
  4321  		return true
  4322  	}
  4323  	// match: (LEAL1 [c] {s} (SHLLconst [1] y) x)
  4324  	// cond:
  4325  	// result: (LEAL2 [c] {s} x y)
  4326  	for {
  4327  		c := v.AuxInt
  4328  		s := v.Aux
  4329  		x := v.Args[1]
  4330  		v_0 := v.Args[0]
  4331  		if v_0.Op != Op386SHLLconst {
  4332  			break
  4333  		}
  4334  		if v_0.AuxInt != 1 {
  4335  			break
  4336  		}
  4337  		y := v_0.Args[0]
  4338  		v.reset(Op386LEAL2)
  4339  		v.AuxInt = c
  4340  		v.Aux = s
  4341  		v.AddArg(x)
  4342  		v.AddArg(y)
  4343  		return true
  4344  	}
  4345  	// match: (LEAL1 [c] {s} x (SHLLconst [2] y))
  4346  	// cond:
  4347  	// result: (LEAL4 [c] {s} x y)
  4348  	for {
  4349  		c := v.AuxInt
  4350  		s := v.Aux
  4351  		_ = v.Args[1]
  4352  		x := v.Args[0]
  4353  		v_1 := v.Args[1]
  4354  		if v_1.Op != Op386SHLLconst {
  4355  			break
  4356  		}
  4357  		if v_1.AuxInt != 2 {
  4358  			break
  4359  		}
  4360  		y := v_1.Args[0]
  4361  		v.reset(Op386LEAL4)
  4362  		v.AuxInt = c
  4363  		v.Aux = s
  4364  		v.AddArg(x)
  4365  		v.AddArg(y)
  4366  		return true
  4367  	}
  4368  	// match: (LEAL1 [c] {s} (SHLLconst [2] y) x)
  4369  	// cond:
  4370  	// result: (LEAL4 [c] {s} x y)
  4371  	for {
  4372  		c := v.AuxInt
  4373  		s := v.Aux
  4374  		x := v.Args[1]
  4375  		v_0 := v.Args[0]
  4376  		if v_0.Op != Op386SHLLconst {
  4377  			break
  4378  		}
  4379  		if v_0.AuxInt != 2 {
  4380  			break
  4381  		}
  4382  		y := v_0.Args[0]
  4383  		v.reset(Op386LEAL4)
  4384  		v.AuxInt = c
  4385  		v.Aux = s
  4386  		v.AddArg(x)
  4387  		v.AddArg(y)
  4388  		return true
  4389  	}
  4390  	// match: (LEAL1 [c] {s} x (SHLLconst [3] y))
  4391  	// cond:
  4392  	// result: (LEAL8 [c] {s} x y)
  4393  	for {
  4394  		c := v.AuxInt
  4395  		s := v.Aux
  4396  		_ = v.Args[1]
  4397  		x := v.Args[0]
  4398  		v_1 := v.Args[1]
  4399  		if v_1.Op != Op386SHLLconst {
  4400  			break
  4401  		}
  4402  		if v_1.AuxInt != 3 {
  4403  			break
  4404  		}
  4405  		y := v_1.Args[0]
  4406  		v.reset(Op386LEAL8)
  4407  		v.AuxInt = c
  4408  		v.Aux = s
  4409  		v.AddArg(x)
  4410  		v.AddArg(y)
  4411  		return true
  4412  	}
  4413  	// match: (LEAL1 [c] {s} (SHLLconst [3] y) x)
  4414  	// cond:
  4415  	// result: (LEAL8 [c] {s} x y)
  4416  	for {
  4417  		c := v.AuxInt
  4418  		s := v.Aux
  4419  		x := v.Args[1]
  4420  		v_0 := v.Args[0]
  4421  		if v_0.Op != Op386SHLLconst {
  4422  			break
  4423  		}
  4424  		if v_0.AuxInt != 3 {
  4425  			break
  4426  		}
  4427  		y := v_0.Args[0]
  4428  		v.reset(Op386LEAL8)
  4429  		v.AuxInt = c
  4430  		v.Aux = s
  4431  		v.AddArg(x)
  4432  		v.AddArg(y)
  4433  		return true
  4434  	}
  4435  	// match: (LEAL1 [off1] {sym1} (LEAL [off2] {sym2} x) y)
  4436  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
  4437  	// result: (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4438  	for {
  4439  		off1 := v.AuxInt
  4440  		sym1 := v.Aux
  4441  		y := v.Args[1]
  4442  		v_0 := v.Args[0]
  4443  		if v_0.Op != Op386LEAL {
  4444  			break
  4445  		}
  4446  		off2 := v_0.AuxInt
  4447  		sym2 := v_0.Aux
  4448  		x := v_0.Args[0]
  4449  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
  4450  			break
  4451  		}
  4452  		v.reset(Op386LEAL1)
  4453  		v.AuxInt = off1 + off2
  4454  		v.Aux = mergeSym(sym1, sym2)
  4455  		v.AddArg(x)
  4456  		v.AddArg(y)
  4457  		return true
  4458  	}
  4459  	// match: (LEAL1 [off1] {sym1} y (LEAL [off2] {sym2} x))
  4460  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
  4461  	// result: (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4462  	for {
  4463  		off1 := v.AuxInt
  4464  		sym1 := v.Aux
  4465  		_ = v.Args[1]
  4466  		y := v.Args[0]
  4467  		v_1 := v.Args[1]
  4468  		if v_1.Op != Op386LEAL {
  4469  			break
  4470  		}
  4471  		off2 := v_1.AuxInt
  4472  		sym2 := v_1.Aux
  4473  		x := v_1.Args[0]
  4474  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
  4475  			break
  4476  		}
  4477  		v.reset(Op386LEAL1)
  4478  		v.AuxInt = off1 + off2
  4479  		v.Aux = mergeSym(sym1, sym2)
  4480  		v.AddArg(x)
  4481  		v.AddArg(y)
  4482  		return true
  4483  	}
  4484  	return false
  4485  }
  4486  func rewriteValue386_Op386LEAL2_0(v *Value) bool {
  4487  	// match: (LEAL2 [c] {s} (ADDLconst [d] x) y)
  4488  	// cond: is32Bit(c+d) && x.Op != OpSB
  4489  	// result: (LEAL2 [c+d] {s} x y)
  4490  	for {
  4491  		c := v.AuxInt
  4492  		s := v.Aux
  4493  		y := v.Args[1]
  4494  		v_0 := v.Args[0]
  4495  		if v_0.Op != Op386ADDLconst {
  4496  			break
  4497  		}
  4498  		d := v_0.AuxInt
  4499  		x := v_0.Args[0]
  4500  		if !(is32Bit(c+d) && x.Op != OpSB) {
  4501  			break
  4502  		}
  4503  		v.reset(Op386LEAL2)
  4504  		v.AuxInt = c + d
  4505  		v.Aux = s
  4506  		v.AddArg(x)
  4507  		v.AddArg(y)
  4508  		return true
  4509  	}
  4510  	// match: (LEAL2 [c] {s} x (ADDLconst [d] y))
  4511  	// cond: is32Bit(c+2*d) && y.Op != OpSB
  4512  	// result: (LEAL2 [c+2*d] {s} x y)
  4513  	for {
  4514  		c := v.AuxInt
  4515  		s := v.Aux
  4516  		_ = v.Args[1]
  4517  		x := v.Args[0]
  4518  		v_1 := v.Args[1]
  4519  		if v_1.Op != Op386ADDLconst {
  4520  			break
  4521  		}
  4522  		d := v_1.AuxInt
  4523  		y := v_1.Args[0]
  4524  		if !(is32Bit(c+2*d) && y.Op != OpSB) {
  4525  			break
  4526  		}
  4527  		v.reset(Op386LEAL2)
  4528  		v.AuxInt = c + 2*d
  4529  		v.Aux = s
  4530  		v.AddArg(x)
  4531  		v.AddArg(y)
  4532  		return true
  4533  	}
  4534  	// match: (LEAL2 [c] {s} x (SHLLconst [1] y))
  4535  	// cond:
  4536  	// result: (LEAL4 [c] {s} x y)
  4537  	for {
  4538  		c := v.AuxInt
  4539  		s := v.Aux
  4540  		_ = v.Args[1]
  4541  		x := v.Args[0]
  4542  		v_1 := v.Args[1]
  4543  		if v_1.Op != Op386SHLLconst {
  4544  			break
  4545  		}
  4546  		if v_1.AuxInt != 1 {
  4547  			break
  4548  		}
  4549  		y := v_1.Args[0]
  4550  		v.reset(Op386LEAL4)
  4551  		v.AuxInt = c
  4552  		v.Aux = s
  4553  		v.AddArg(x)
  4554  		v.AddArg(y)
  4555  		return true
  4556  	}
  4557  	// match: (LEAL2 [c] {s} x (SHLLconst [2] y))
  4558  	// cond:
  4559  	// result: (LEAL8 [c] {s} x y)
  4560  	for {
  4561  		c := v.AuxInt
  4562  		s := v.Aux
  4563  		_ = v.Args[1]
  4564  		x := v.Args[0]
  4565  		v_1 := v.Args[1]
  4566  		if v_1.Op != Op386SHLLconst {
  4567  			break
  4568  		}
  4569  		if v_1.AuxInt != 2 {
  4570  			break
  4571  		}
  4572  		y := v_1.Args[0]
  4573  		v.reset(Op386LEAL8)
  4574  		v.AuxInt = c
  4575  		v.Aux = s
  4576  		v.AddArg(x)
  4577  		v.AddArg(y)
  4578  		return true
  4579  	}
  4580  	// match: (LEAL2 [off1] {sym1} (LEAL [off2] {sym2} x) y)
  4581  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
  4582  	// result: (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4583  	for {
  4584  		off1 := v.AuxInt
  4585  		sym1 := v.Aux
  4586  		y := v.Args[1]
  4587  		v_0 := v.Args[0]
  4588  		if v_0.Op != Op386LEAL {
  4589  			break
  4590  		}
  4591  		off2 := v_0.AuxInt
  4592  		sym2 := v_0.Aux
  4593  		x := v_0.Args[0]
  4594  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
  4595  			break
  4596  		}
  4597  		v.reset(Op386LEAL2)
  4598  		v.AuxInt = off1 + off2
  4599  		v.Aux = mergeSym(sym1, sym2)
  4600  		v.AddArg(x)
  4601  		v.AddArg(y)
  4602  		return true
  4603  	}
  4604  	return false
  4605  }
  4606  func rewriteValue386_Op386LEAL4_0(v *Value) bool {
  4607  	// match: (LEAL4 [c] {s} (ADDLconst [d] x) y)
  4608  	// cond: is32Bit(c+d) && x.Op != OpSB
  4609  	// result: (LEAL4 [c+d] {s} x y)
  4610  	for {
  4611  		c := v.AuxInt
  4612  		s := v.Aux
  4613  		y := v.Args[1]
  4614  		v_0 := v.Args[0]
  4615  		if v_0.Op != Op386ADDLconst {
  4616  			break
  4617  		}
  4618  		d := v_0.AuxInt
  4619  		x := v_0.Args[0]
  4620  		if !(is32Bit(c+d) && x.Op != OpSB) {
  4621  			break
  4622  		}
  4623  		v.reset(Op386LEAL4)
  4624  		v.AuxInt = c + d
  4625  		v.Aux = s
  4626  		v.AddArg(x)
  4627  		v.AddArg(y)
  4628  		return true
  4629  	}
  4630  	// match: (LEAL4 [c] {s} x (ADDLconst [d] y))
  4631  	// cond: is32Bit(c+4*d) && y.Op != OpSB
  4632  	// result: (LEAL4 [c+4*d] {s} x y)
  4633  	for {
  4634  		c := v.AuxInt
  4635  		s := v.Aux
  4636  		_ = v.Args[1]
  4637  		x := v.Args[0]
  4638  		v_1 := v.Args[1]
  4639  		if v_1.Op != Op386ADDLconst {
  4640  			break
  4641  		}
  4642  		d := v_1.AuxInt
  4643  		y := v_1.Args[0]
  4644  		if !(is32Bit(c+4*d) && y.Op != OpSB) {
  4645  			break
  4646  		}
  4647  		v.reset(Op386LEAL4)
  4648  		v.AuxInt = c + 4*d
  4649  		v.Aux = s
  4650  		v.AddArg(x)
  4651  		v.AddArg(y)
  4652  		return true
  4653  	}
  4654  	// match: (LEAL4 [c] {s} x (SHLLconst [1] y))
  4655  	// cond:
  4656  	// result: (LEAL8 [c] {s} x y)
  4657  	for {
  4658  		c := v.AuxInt
  4659  		s := v.Aux
  4660  		_ = v.Args[1]
  4661  		x := v.Args[0]
  4662  		v_1 := v.Args[1]
  4663  		if v_1.Op != Op386SHLLconst {
  4664  			break
  4665  		}
  4666  		if v_1.AuxInt != 1 {
  4667  			break
  4668  		}
  4669  		y := v_1.Args[0]
  4670  		v.reset(Op386LEAL8)
  4671  		v.AuxInt = c
  4672  		v.Aux = s
  4673  		v.AddArg(x)
  4674  		v.AddArg(y)
  4675  		return true
  4676  	}
  4677  	// match: (LEAL4 [off1] {sym1} (LEAL [off2] {sym2} x) y)
  4678  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
  4679  	// result: (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4680  	for {
  4681  		off1 := v.AuxInt
  4682  		sym1 := v.Aux
  4683  		y := v.Args[1]
  4684  		v_0 := v.Args[0]
  4685  		if v_0.Op != Op386LEAL {
  4686  			break
  4687  		}
  4688  		off2 := v_0.AuxInt
  4689  		sym2 := v_0.Aux
  4690  		x := v_0.Args[0]
  4691  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
  4692  			break
  4693  		}
  4694  		v.reset(Op386LEAL4)
  4695  		v.AuxInt = off1 + off2
  4696  		v.Aux = mergeSym(sym1, sym2)
  4697  		v.AddArg(x)
  4698  		v.AddArg(y)
  4699  		return true
  4700  	}
  4701  	return false
  4702  }
  4703  func rewriteValue386_Op386LEAL8_0(v *Value) bool {
  4704  	// match: (LEAL8 [c] {s} (ADDLconst [d] x) y)
  4705  	// cond: is32Bit(c+d) && x.Op != OpSB
  4706  	// result: (LEAL8 [c+d] {s} x y)
  4707  	for {
  4708  		c := v.AuxInt
  4709  		s := v.Aux
  4710  		y := v.Args[1]
  4711  		v_0 := v.Args[0]
  4712  		if v_0.Op != Op386ADDLconst {
  4713  			break
  4714  		}
  4715  		d := v_0.AuxInt
  4716  		x := v_0.Args[0]
  4717  		if !(is32Bit(c+d) && x.Op != OpSB) {
  4718  			break
  4719  		}
  4720  		v.reset(Op386LEAL8)
  4721  		v.AuxInt = c + d
  4722  		v.Aux = s
  4723  		v.AddArg(x)
  4724  		v.AddArg(y)
  4725  		return true
  4726  	}
  4727  	// match: (LEAL8 [c] {s} x (ADDLconst [d] y))
  4728  	// cond: is32Bit(c+8*d) && y.Op != OpSB
  4729  	// result: (LEAL8 [c+8*d] {s} x y)
  4730  	for {
  4731  		c := v.AuxInt
  4732  		s := v.Aux
  4733  		_ = v.Args[1]
  4734  		x := v.Args[0]
  4735  		v_1 := v.Args[1]
  4736  		if v_1.Op != Op386ADDLconst {
  4737  			break
  4738  		}
  4739  		d := v_1.AuxInt
  4740  		y := v_1.Args[0]
  4741  		if !(is32Bit(c+8*d) && y.Op != OpSB) {
  4742  			break
  4743  		}
  4744  		v.reset(Op386LEAL8)
  4745  		v.AuxInt = c + 8*d
  4746  		v.Aux = s
  4747  		v.AddArg(x)
  4748  		v.AddArg(y)
  4749  		return true
  4750  	}
  4751  	// match: (LEAL8 [off1] {sym1} (LEAL [off2] {sym2} x) y)
  4752  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
  4753  	// result: (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4754  	for {
  4755  		off1 := v.AuxInt
  4756  		sym1 := v.Aux
  4757  		y := v.Args[1]
  4758  		v_0 := v.Args[0]
  4759  		if v_0.Op != Op386LEAL {
  4760  			break
  4761  		}
  4762  		off2 := v_0.AuxInt
  4763  		sym2 := v_0.Aux
  4764  		x := v_0.Args[0]
  4765  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
  4766  			break
  4767  		}
  4768  		v.reset(Op386LEAL8)
  4769  		v.AuxInt = off1 + off2
  4770  		v.Aux = mergeSym(sym1, sym2)
  4771  		v.AddArg(x)
  4772  		v.AddArg(y)
  4773  		return true
  4774  	}
  4775  	return false
  4776  }
  4777  func rewriteValue386_Op386MOVBLSX_0(v *Value) bool {
  4778  	b := v.Block
  4779  	// match: (MOVBLSX x:(MOVBload [off] {sym} ptr mem))
  4780  	// cond: x.Uses == 1 && clobber(x)
  4781  	// result: @x.Block (MOVBLSXload <v.Type> [off] {sym} ptr mem)
  4782  	for {
  4783  		x := v.Args[0]
  4784  		if x.Op != Op386MOVBload {
  4785  			break
  4786  		}
  4787  		off := x.AuxInt
  4788  		sym := x.Aux
  4789  		mem := x.Args[1]
  4790  		ptr := x.Args[0]
  4791  		if !(x.Uses == 1 && clobber(x)) {
  4792  			break
  4793  		}
  4794  		b = x.Block
  4795  		v0 := b.NewValue0(x.Pos, Op386MOVBLSXload, v.Type)
  4796  		v.reset(OpCopy)
  4797  		v.AddArg(v0)
  4798  		v0.AuxInt = off
  4799  		v0.Aux = sym
  4800  		v0.AddArg(ptr)
  4801  		v0.AddArg(mem)
  4802  		return true
  4803  	}
  4804  	// match: (MOVBLSX (ANDLconst [c] x))
  4805  	// cond: c & 0x80 == 0
  4806  	// result: (ANDLconst [c & 0x7f] x)
  4807  	for {
  4808  		v_0 := v.Args[0]
  4809  		if v_0.Op != Op386ANDLconst {
  4810  			break
  4811  		}
  4812  		c := v_0.AuxInt
  4813  		x := v_0.Args[0]
  4814  		if !(c&0x80 == 0) {
  4815  			break
  4816  		}
  4817  		v.reset(Op386ANDLconst)
  4818  		v.AuxInt = c & 0x7f
  4819  		v.AddArg(x)
  4820  		return true
  4821  	}
  4822  	return false
  4823  }
  4824  func rewriteValue386_Op386MOVBLSXload_0(v *Value) bool {
  4825  	b := v.Block
  4826  	config := b.Func.Config
  4827  	// match: (MOVBLSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _))
  4828  	// cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
  4829  	// result: (MOVBLSX x)
  4830  	for {
  4831  		off := v.AuxInt
  4832  		sym := v.Aux
  4833  		_ = v.Args[1]
  4834  		ptr := v.Args[0]
  4835  		v_1 := v.Args[1]
  4836  		if v_1.Op != Op386MOVBstore {
  4837  			break
  4838  		}
  4839  		off2 := v_1.AuxInt
  4840  		sym2 := v_1.Aux
  4841  		_ = v_1.Args[2]
  4842  		ptr2 := v_1.Args[0]
  4843  		x := v_1.Args[1]
  4844  		if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
  4845  			break
  4846  		}
  4847  		v.reset(Op386MOVBLSX)
  4848  		v.AddArg(x)
  4849  		return true
  4850  	}
  4851  	// match: (MOVBLSXload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
  4852  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  4853  	// result: (MOVBLSXload [off1+off2] {mergeSym(sym1,sym2)} base mem)
  4854  	for {
  4855  		off1 := v.AuxInt
  4856  		sym1 := v.Aux
  4857  		mem := v.Args[1]
  4858  		v_0 := v.Args[0]
  4859  		if v_0.Op != Op386LEAL {
  4860  			break
  4861  		}
  4862  		off2 := v_0.AuxInt
  4863  		sym2 := v_0.Aux
  4864  		base := v_0.Args[0]
  4865  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  4866  			break
  4867  		}
  4868  		v.reset(Op386MOVBLSXload)
  4869  		v.AuxInt = off1 + off2
  4870  		v.Aux = mergeSym(sym1, sym2)
  4871  		v.AddArg(base)
  4872  		v.AddArg(mem)
  4873  		return true
  4874  	}
  4875  	return false
  4876  }
  4877  func rewriteValue386_Op386MOVBLZX_0(v *Value) bool {
  4878  	b := v.Block
  4879  	// match: (MOVBLZX x:(MOVBload [off] {sym} ptr mem))
  4880  	// cond: x.Uses == 1 && clobber(x)
  4881  	// result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
  4882  	for {
  4883  		x := v.Args[0]
  4884  		if x.Op != Op386MOVBload {
  4885  			break
  4886  		}
  4887  		off := x.AuxInt
  4888  		sym := x.Aux
  4889  		mem := x.Args[1]
  4890  		ptr := x.Args[0]
  4891  		if !(x.Uses == 1 && clobber(x)) {
  4892  			break
  4893  		}
  4894  		b = x.Block
  4895  		v0 := b.NewValue0(x.Pos, Op386MOVBload, v.Type)
  4896  		v.reset(OpCopy)
  4897  		v.AddArg(v0)
  4898  		v0.AuxInt = off
  4899  		v0.Aux = sym
  4900  		v0.AddArg(ptr)
  4901  		v0.AddArg(mem)
  4902  		return true
  4903  	}
  4904  	// match: (MOVBLZX x:(MOVBloadidx1 [off] {sym} ptr idx mem))
  4905  	// cond: x.Uses == 1 && clobber(x)
  4906  	// result: @x.Block (MOVBloadidx1 <v.Type> [off] {sym} ptr idx mem)
  4907  	for {
  4908  		x := v.Args[0]
  4909  		if x.Op != Op386MOVBloadidx1 {
  4910  			break
  4911  		}
  4912  		off := x.AuxInt
  4913  		sym := x.Aux
  4914  		mem := x.Args[2]
  4915  		ptr := x.Args[0]
  4916  		idx := x.Args[1]
  4917  		if !(x.Uses == 1 && clobber(x)) {
  4918  			break
  4919  		}
  4920  		b = x.Block
  4921  		v0 := b.NewValue0(v.Pos, Op386MOVBloadidx1, v.Type)
  4922  		v.reset(OpCopy)
  4923  		v.AddArg(v0)
  4924  		v0.AuxInt = off
  4925  		v0.Aux = sym
  4926  		v0.AddArg(ptr)
  4927  		v0.AddArg(idx)
  4928  		v0.AddArg(mem)
  4929  		return true
  4930  	}
  4931  	// match: (MOVBLZX (ANDLconst [c] x))
  4932  	// cond:
  4933  	// result: (ANDLconst [c & 0xff] x)
  4934  	for {
  4935  		v_0 := v.Args[0]
  4936  		if v_0.Op != Op386ANDLconst {
  4937  			break
  4938  		}
  4939  		c := v_0.AuxInt
  4940  		x := v_0.Args[0]
  4941  		v.reset(Op386ANDLconst)
  4942  		v.AuxInt = c & 0xff
  4943  		v.AddArg(x)
  4944  		return true
  4945  	}
  4946  	return false
  4947  }
  4948  func rewriteValue386_Op386MOVBload_0(v *Value) bool {
  4949  	b := v.Block
  4950  	config := b.Func.Config
  4951  	// match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _))
  4952  	// cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
  4953  	// result: (MOVBLZX x)
  4954  	for {
  4955  		off := v.AuxInt
  4956  		sym := v.Aux
  4957  		_ = v.Args[1]
  4958  		ptr := v.Args[0]
  4959  		v_1 := v.Args[1]
  4960  		if v_1.Op != Op386MOVBstore {
  4961  			break
  4962  		}
  4963  		off2 := v_1.AuxInt
  4964  		sym2 := v_1.Aux
  4965  		_ = v_1.Args[2]
  4966  		ptr2 := v_1.Args[0]
  4967  		x := v_1.Args[1]
  4968  		if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
  4969  			break
  4970  		}
  4971  		v.reset(Op386MOVBLZX)
  4972  		v.AddArg(x)
  4973  		return true
  4974  	}
  4975  	// match: (MOVBload [off1] {sym} (ADDLconst [off2] ptr) mem)
  4976  	// cond: is32Bit(off1+off2)
  4977  	// result: (MOVBload [off1+off2] {sym} ptr mem)
  4978  	for {
  4979  		off1 := v.AuxInt
  4980  		sym := v.Aux
  4981  		mem := v.Args[1]
  4982  		v_0 := v.Args[0]
  4983  		if v_0.Op != Op386ADDLconst {
  4984  			break
  4985  		}
  4986  		off2 := v_0.AuxInt
  4987  		ptr := v_0.Args[0]
  4988  		if !(is32Bit(off1 + off2)) {
  4989  			break
  4990  		}
  4991  		v.reset(Op386MOVBload)
  4992  		v.AuxInt = off1 + off2
  4993  		v.Aux = sym
  4994  		v.AddArg(ptr)
  4995  		v.AddArg(mem)
  4996  		return true
  4997  	}
  4998  	// match: (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
  4999  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  5000  	// result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem)
  5001  	for {
  5002  		off1 := v.AuxInt
  5003  		sym1 := v.Aux
  5004  		mem := v.Args[1]
  5005  		v_0 := v.Args[0]
  5006  		if v_0.Op != Op386LEAL {
  5007  			break
  5008  		}
  5009  		off2 := v_0.AuxInt
  5010  		sym2 := v_0.Aux
  5011  		base := v_0.Args[0]
  5012  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  5013  			break
  5014  		}
  5015  		v.reset(Op386MOVBload)
  5016  		v.AuxInt = off1 + off2
  5017  		v.Aux = mergeSym(sym1, sym2)
  5018  		v.AddArg(base)
  5019  		v.AddArg(mem)
  5020  		return true
  5021  	}
  5022  	// match: (MOVBload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem)
  5023  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  5024  	// result: (MOVBloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
  5025  	for {
  5026  		off1 := v.AuxInt
  5027  		sym1 := v.Aux
  5028  		mem := v.Args[1]
  5029  		v_0 := v.Args[0]
  5030  		if v_0.Op != Op386LEAL1 {
  5031  			break
  5032  		}
  5033  		off2 := v_0.AuxInt
  5034  		sym2 := v_0.Aux
  5035  		idx := v_0.Args[1]
  5036  		ptr := v_0.Args[0]
  5037  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  5038  			break
  5039  		}
  5040  		v.reset(Op386MOVBloadidx1)
  5041  		v.AuxInt = off1 + off2
  5042  		v.Aux = mergeSym(sym1, sym2)
  5043  		v.AddArg(ptr)
  5044  		v.AddArg(idx)
  5045  		v.AddArg(mem)
  5046  		return true
  5047  	}
  5048  	// match: (MOVBload [off] {sym} (ADDL ptr idx) mem)
  5049  	// cond: ptr.Op != OpSB
  5050  	// result: (MOVBloadidx1 [off] {sym} ptr idx mem)
  5051  	for {
  5052  		off := v.AuxInt
  5053  		sym := v.Aux
  5054  		mem := v.Args[1]
  5055  		v_0 := v.Args[0]
  5056  		if v_0.Op != Op386ADDL {
  5057  			break
  5058  		}
  5059  		idx := v_0.Args[1]
  5060  		ptr := v_0.Args[0]
  5061  		if !(ptr.Op != OpSB) {
  5062  			break
  5063  		}
  5064  		v.reset(Op386MOVBloadidx1)
  5065  		v.AuxInt = off
  5066  		v.Aux = sym
  5067  		v.AddArg(ptr)
  5068  		v.AddArg(idx)
  5069  		v.AddArg(mem)
  5070  		return true
  5071  	}
  5072  	// match: (MOVBload [off] {sym} (SB) _)
  5073  	// cond: symIsRO(sym)
  5074  	// result: (MOVLconst [int64(read8(sym, off))])
  5075  	for {
  5076  		off := v.AuxInt
  5077  		sym := v.Aux
  5078  		_ = v.Args[1]
  5079  		v_0 := v.Args[0]
  5080  		if v_0.Op != OpSB {
  5081  			break
  5082  		}
  5083  		if !(symIsRO(sym)) {
  5084  			break
  5085  		}
  5086  		v.reset(Op386MOVLconst)
  5087  		v.AuxInt = int64(read8(sym, off))
  5088  		return true
  5089  	}
  5090  	return false
  5091  }
  5092  func rewriteValue386_Op386MOVBloadidx1_0(v *Value) bool {
  5093  	// match: (MOVBloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem)
  5094  	// cond:
  5095  	// result: (MOVBloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  5096  	for {
  5097  		c := v.AuxInt
  5098  		sym := v.Aux
  5099  		mem := v.Args[2]
  5100  		v_0 := v.Args[0]
  5101  		if v_0.Op != Op386ADDLconst {
  5102  			break
  5103  		}
  5104  		d := v_0.AuxInt
  5105  		ptr := v_0.Args[0]
  5106  		idx := v.Args[1]
  5107  		v.reset(Op386MOVBloadidx1)
  5108  		v.AuxInt = int64(int32(c + d))
  5109  		v.Aux = sym
  5110  		v.AddArg(ptr)
  5111  		v.AddArg(idx)
  5112  		v.AddArg(mem)
  5113  		return true
  5114  	}
  5115  	// match: (MOVBloadidx1 [c] {sym} idx (ADDLconst [d] ptr) mem)
  5116  	// cond:
  5117  	// result: (MOVBloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  5118  	for {
  5119  		c := v.AuxInt
  5120  		sym := v.Aux
  5121  		mem := v.Args[2]
  5122  		idx := v.Args[0]
  5123  		v_1 := v.Args[1]
  5124  		if v_1.Op != Op386ADDLconst {
  5125  			break
  5126  		}
  5127  		d := v_1.AuxInt
  5128  		ptr := v_1.Args[0]
  5129  		v.reset(Op386MOVBloadidx1)
  5130  		v.AuxInt = int64(int32(c + d))
  5131  		v.Aux = sym
  5132  		v.AddArg(ptr)
  5133  		v.AddArg(idx)
  5134  		v.AddArg(mem)
  5135  		return true
  5136  	}
  5137  	// match: (MOVBloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem)
  5138  	// cond:
  5139  	// result: (MOVBloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  5140  	for {
  5141  		c := v.AuxInt
  5142  		sym := v.Aux
  5143  		mem := v.Args[2]
  5144  		ptr := v.Args[0]
  5145  		v_1 := v.Args[1]
  5146  		if v_1.Op != Op386ADDLconst {
  5147  			break
  5148  		}
  5149  		d := v_1.AuxInt
  5150  		idx := v_1.Args[0]
  5151  		v.reset(Op386MOVBloadidx1)
  5152  		v.AuxInt = int64(int32(c + d))
  5153  		v.Aux = sym
  5154  		v.AddArg(ptr)
  5155  		v.AddArg(idx)
  5156  		v.AddArg(mem)
  5157  		return true
  5158  	}
  5159  	// match: (MOVBloadidx1 [c] {sym} (ADDLconst [d] idx) ptr mem)
  5160  	// cond:
  5161  	// result: (MOVBloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  5162  	for {
  5163  		c := v.AuxInt
  5164  		sym := v.Aux
  5165  		mem := v.Args[2]
  5166  		v_0 := v.Args[0]
  5167  		if v_0.Op != Op386ADDLconst {
  5168  			break
  5169  		}
  5170  		d := v_0.AuxInt
  5171  		idx := v_0.Args[0]
  5172  		ptr := v.Args[1]
  5173  		v.reset(Op386MOVBloadidx1)
  5174  		v.AuxInt = int64(int32(c + d))
  5175  		v.Aux = sym
  5176  		v.AddArg(ptr)
  5177  		v.AddArg(idx)
  5178  		v.AddArg(mem)
  5179  		return true
  5180  	}
  5181  	return false
  5182  }
  5183  func rewriteValue386_Op386MOVBstore_0(v *Value) bool {
  5184  	b := v.Block
  5185  	config := b.Func.Config
  5186  	// match: (MOVBstore [off] {sym} ptr (MOVBLSX x) mem)
  5187  	// cond:
  5188  	// result: (MOVBstore [off] {sym} ptr x mem)
  5189  	for {
  5190  		off := v.AuxInt
  5191  		sym := v.Aux
  5192  		mem := v.Args[2]
  5193  		ptr := v.Args[0]
  5194  		v_1 := v.Args[1]
  5195  		if v_1.Op != Op386MOVBLSX {
  5196  			break
  5197  		}
  5198  		x := v_1.Args[0]
  5199  		v.reset(Op386MOVBstore)
  5200  		v.AuxInt = off
  5201  		v.Aux = sym
  5202  		v.AddArg(ptr)
  5203  		v.AddArg(x)
  5204  		v.AddArg(mem)
  5205  		return true
  5206  	}
  5207  	// match: (MOVBstore [off] {sym} ptr (MOVBLZX x) mem)
  5208  	// cond:
  5209  	// result: (MOVBstore [off] {sym} ptr x mem)
  5210  	for {
  5211  		off := v.AuxInt
  5212  		sym := v.Aux
  5213  		mem := v.Args[2]
  5214  		ptr := v.Args[0]
  5215  		v_1 := v.Args[1]
  5216  		if v_1.Op != Op386MOVBLZX {
  5217  			break
  5218  		}
  5219  		x := v_1.Args[0]
  5220  		v.reset(Op386MOVBstore)
  5221  		v.AuxInt = off
  5222  		v.Aux = sym
  5223  		v.AddArg(ptr)
  5224  		v.AddArg(x)
  5225  		v.AddArg(mem)
  5226  		return true
  5227  	}
  5228  	// match: (MOVBstore [off1] {sym} (ADDLconst [off2] ptr) val mem)
  5229  	// cond: is32Bit(off1+off2)
  5230  	// result: (MOVBstore [off1+off2] {sym} ptr val mem)
  5231  	for {
  5232  		off1 := v.AuxInt
  5233  		sym := v.Aux
  5234  		mem := v.Args[2]
  5235  		v_0 := v.Args[0]
  5236  		if v_0.Op != Op386ADDLconst {
  5237  			break
  5238  		}
  5239  		off2 := v_0.AuxInt
  5240  		ptr := v_0.Args[0]
  5241  		val := v.Args[1]
  5242  		if !(is32Bit(off1 + off2)) {
  5243  			break
  5244  		}
  5245  		v.reset(Op386MOVBstore)
  5246  		v.AuxInt = off1 + off2
  5247  		v.Aux = sym
  5248  		v.AddArg(ptr)
  5249  		v.AddArg(val)
  5250  		v.AddArg(mem)
  5251  		return true
  5252  	}
  5253  	// match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem)
  5254  	// cond: validOff(off)
  5255  	// result: (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem)
  5256  	for {
  5257  		off := v.AuxInt
  5258  		sym := v.Aux
  5259  		mem := v.Args[2]
  5260  		ptr := v.Args[0]
  5261  		v_1 := v.Args[1]
  5262  		if v_1.Op != Op386MOVLconst {
  5263  			break
  5264  		}
  5265  		c := v_1.AuxInt
  5266  		if !(validOff(off)) {
  5267  			break
  5268  		}
  5269  		v.reset(Op386MOVBstoreconst)
  5270  		v.AuxInt = makeValAndOff(int64(int8(c)), off)
  5271  		v.Aux = sym
  5272  		v.AddArg(ptr)
  5273  		v.AddArg(mem)
  5274  		return true
  5275  	}
  5276  	// match: (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
  5277  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  5278  	// result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  5279  	for {
  5280  		off1 := v.AuxInt
  5281  		sym1 := v.Aux
  5282  		mem := v.Args[2]
  5283  		v_0 := v.Args[0]
  5284  		if v_0.Op != Op386LEAL {
  5285  			break
  5286  		}
  5287  		off2 := v_0.AuxInt
  5288  		sym2 := v_0.Aux
  5289  		base := v_0.Args[0]
  5290  		val := v.Args[1]
  5291  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  5292  			break
  5293  		}
  5294  		v.reset(Op386MOVBstore)
  5295  		v.AuxInt = off1 + off2
  5296  		v.Aux = mergeSym(sym1, sym2)
  5297  		v.AddArg(base)
  5298  		v.AddArg(val)
  5299  		v.AddArg(mem)
  5300  		return true
  5301  	}
  5302  	// match: (MOVBstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem)
  5303  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  5304  	// result: (MOVBstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
  5305  	for {
  5306  		off1 := v.AuxInt
  5307  		sym1 := v.Aux
  5308  		mem := v.Args[2]
  5309  		v_0 := v.Args[0]
  5310  		if v_0.Op != Op386LEAL1 {
  5311  			break
  5312  		}
  5313  		off2 := v_0.AuxInt
  5314  		sym2 := v_0.Aux
  5315  		idx := v_0.Args[1]
  5316  		ptr := v_0.Args[0]
  5317  		val := v.Args[1]
  5318  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  5319  			break
  5320  		}
  5321  		v.reset(Op386MOVBstoreidx1)
  5322  		v.AuxInt = off1 + off2
  5323  		v.Aux = mergeSym(sym1, sym2)
  5324  		v.AddArg(ptr)
  5325  		v.AddArg(idx)
  5326  		v.AddArg(val)
  5327  		v.AddArg(mem)
  5328  		return true
  5329  	}
  5330  	// match: (MOVBstore [off] {sym} (ADDL ptr idx) val mem)
  5331  	// cond: ptr.Op != OpSB
  5332  	// result: (MOVBstoreidx1 [off] {sym} ptr idx val mem)
  5333  	for {
  5334  		off := v.AuxInt
  5335  		sym := v.Aux
  5336  		mem := v.Args[2]
  5337  		v_0 := v.Args[0]
  5338  		if v_0.Op != Op386ADDL {
  5339  			break
  5340  		}
  5341  		idx := v_0.Args[1]
  5342  		ptr := v_0.Args[0]
  5343  		val := v.Args[1]
  5344  		if !(ptr.Op != OpSB) {
  5345  			break
  5346  		}
  5347  		v.reset(Op386MOVBstoreidx1)
  5348  		v.AuxInt = off
  5349  		v.Aux = sym
  5350  		v.AddArg(ptr)
  5351  		v.AddArg(idx)
  5352  		v.AddArg(val)
  5353  		v.AddArg(mem)
  5354  		return true
  5355  	}
  5356  	// match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem))
  5357  	// cond: x.Uses == 1 && clobber(x)
  5358  	// result: (MOVWstore [i-1] {s} p w mem)
  5359  	for {
  5360  		i := v.AuxInt
  5361  		s := v.Aux
  5362  		_ = v.Args[2]
  5363  		p := v.Args[0]
  5364  		v_1 := v.Args[1]
  5365  		if v_1.Op != Op386SHRWconst {
  5366  			break
  5367  		}
  5368  		if v_1.AuxInt != 8 {
  5369  			break
  5370  		}
  5371  		w := v_1.Args[0]
  5372  		x := v.Args[2]
  5373  		if x.Op != Op386MOVBstore {
  5374  			break
  5375  		}
  5376  		if x.AuxInt != i-1 {
  5377  			break
  5378  		}
  5379  		if x.Aux != s {
  5380  			break
  5381  		}
  5382  		mem := x.Args[2]
  5383  		if p != x.Args[0] {
  5384  			break
  5385  		}
  5386  		if w != x.Args[1] {
  5387  			break
  5388  		}
  5389  		if !(x.Uses == 1 && clobber(x)) {
  5390  			break
  5391  		}
  5392  		v.reset(Op386MOVWstore)
  5393  		v.AuxInt = i - 1
  5394  		v.Aux = s
  5395  		v.AddArg(p)
  5396  		v.AddArg(w)
  5397  		v.AddArg(mem)
  5398  		return true
  5399  	}
  5400  	// match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem))
  5401  	// cond: x.Uses == 1 && clobber(x)
  5402  	// result: (MOVWstore [i-1] {s} p w mem)
  5403  	for {
  5404  		i := v.AuxInt
  5405  		s := v.Aux
  5406  		_ = v.Args[2]
  5407  		p := v.Args[0]
  5408  		v_1 := v.Args[1]
  5409  		if v_1.Op != Op386SHRLconst {
  5410  			break
  5411  		}
  5412  		if v_1.AuxInt != 8 {
  5413  			break
  5414  		}
  5415  		w := v_1.Args[0]
  5416  		x := v.Args[2]
  5417  		if x.Op != Op386MOVBstore {
  5418  			break
  5419  		}
  5420  		if x.AuxInt != i-1 {
  5421  			break
  5422  		}
  5423  		if x.Aux != s {
  5424  			break
  5425  		}
  5426  		mem := x.Args[2]
  5427  		if p != x.Args[0] {
  5428  			break
  5429  		}
  5430  		if w != x.Args[1] {
  5431  			break
  5432  		}
  5433  		if !(x.Uses == 1 && clobber(x)) {
  5434  			break
  5435  		}
  5436  		v.reset(Op386MOVWstore)
  5437  		v.AuxInt = i - 1
  5438  		v.Aux = s
  5439  		v.AddArg(p)
  5440  		v.AddArg(w)
  5441  		v.AddArg(mem)
  5442  		return true
  5443  	}
  5444  	// match: (MOVBstore [i] {s} p w x:(MOVBstore {s} [i+1] p (SHRWconst [8] w) mem))
  5445  	// cond: x.Uses == 1 && clobber(x)
  5446  	// result: (MOVWstore [i] {s} p w mem)
  5447  	for {
  5448  		i := v.AuxInt
  5449  		s := v.Aux
  5450  		_ = v.Args[2]
  5451  		p := v.Args[0]
  5452  		w := v.Args[1]
  5453  		x := v.Args[2]
  5454  		if x.Op != Op386MOVBstore {
  5455  			break
  5456  		}
  5457  		if x.AuxInt != i+1 {
  5458  			break
  5459  		}
  5460  		if x.Aux != s {
  5461  			break
  5462  		}
  5463  		mem := x.Args[2]
  5464  		if p != x.Args[0] {
  5465  			break
  5466  		}
  5467  		x_1 := x.Args[1]
  5468  		if x_1.Op != Op386SHRWconst {
  5469  			break
  5470  		}
  5471  		if x_1.AuxInt != 8 {
  5472  			break
  5473  		}
  5474  		if w != x_1.Args[0] {
  5475  			break
  5476  		}
  5477  		if !(x.Uses == 1 && clobber(x)) {
  5478  			break
  5479  		}
  5480  		v.reset(Op386MOVWstore)
  5481  		v.AuxInt = i
  5482  		v.Aux = s
  5483  		v.AddArg(p)
  5484  		v.AddArg(w)
  5485  		v.AddArg(mem)
  5486  		return true
  5487  	}
  5488  	return false
  5489  }
  5490  func rewriteValue386_Op386MOVBstore_10(v *Value) bool {
  5491  	// match: (MOVBstore [i] {s} p w x:(MOVBstore {s} [i+1] p (SHRLconst [8] w) mem))
  5492  	// cond: x.Uses == 1 && clobber(x)
  5493  	// result: (MOVWstore [i] {s} p w mem)
  5494  	for {
  5495  		i := v.AuxInt
  5496  		s := v.Aux
  5497  		_ = v.Args[2]
  5498  		p := v.Args[0]
  5499  		w := v.Args[1]
  5500  		x := v.Args[2]
  5501  		if x.Op != Op386MOVBstore {
  5502  			break
  5503  		}
  5504  		if x.AuxInt != i+1 {
  5505  			break
  5506  		}
  5507  		if x.Aux != s {
  5508  			break
  5509  		}
  5510  		mem := x.Args[2]
  5511  		if p != x.Args[0] {
  5512  			break
  5513  		}
  5514  		x_1 := x.Args[1]
  5515  		if x_1.Op != Op386SHRLconst {
  5516  			break
  5517  		}
  5518  		if x_1.AuxInt != 8 {
  5519  			break
  5520  		}
  5521  		if w != x_1.Args[0] {
  5522  			break
  5523  		}
  5524  		if !(x.Uses == 1 && clobber(x)) {
  5525  			break
  5526  		}
  5527  		v.reset(Op386MOVWstore)
  5528  		v.AuxInt = i
  5529  		v.Aux = s
  5530  		v.AddArg(p)
  5531  		v.AddArg(w)
  5532  		v.AddArg(mem)
  5533  		return true
  5534  	}
  5535  	// match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem))
  5536  	// cond: x.Uses == 1 && clobber(x)
  5537  	// result: (MOVWstore [i-1] {s} p w0 mem)
  5538  	for {
  5539  		i := v.AuxInt
  5540  		s := v.Aux
  5541  		_ = v.Args[2]
  5542  		p := v.Args[0]
  5543  		v_1 := v.Args[1]
  5544  		if v_1.Op != Op386SHRLconst {
  5545  			break
  5546  		}
  5547  		j := v_1.AuxInt
  5548  		w := v_1.Args[0]
  5549  		x := v.Args[2]
  5550  		if x.Op != Op386MOVBstore {
  5551  			break
  5552  		}
  5553  		if x.AuxInt != i-1 {
  5554  			break
  5555  		}
  5556  		if x.Aux != s {
  5557  			break
  5558  		}
  5559  		mem := x.Args[2]
  5560  		if p != x.Args[0] {
  5561  			break
  5562  		}
  5563  		w0 := x.Args[1]
  5564  		if w0.Op != Op386SHRLconst {
  5565  			break
  5566  		}
  5567  		if w0.AuxInt != j-8 {
  5568  			break
  5569  		}
  5570  		if w != w0.Args[0] {
  5571  			break
  5572  		}
  5573  		if !(x.Uses == 1 && clobber(x)) {
  5574  			break
  5575  		}
  5576  		v.reset(Op386MOVWstore)
  5577  		v.AuxInt = i - 1
  5578  		v.Aux = s
  5579  		v.AddArg(p)
  5580  		v.AddArg(w0)
  5581  		v.AddArg(mem)
  5582  		return true
  5583  	}
  5584  	return false
  5585  }
  5586  func rewriteValue386_Op386MOVBstoreconst_0(v *Value) bool {
  5587  	b := v.Block
  5588  	config := b.Func.Config
  5589  	// match: (MOVBstoreconst [sc] {s} (ADDLconst [off] ptr) mem)
  5590  	// cond: ValAndOff(sc).canAdd(off)
  5591  	// result: (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem)
  5592  	for {
  5593  		sc := v.AuxInt
  5594  		s := v.Aux
  5595  		mem := v.Args[1]
  5596  		v_0 := v.Args[0]
  5597  		if v_0.Op != Op386ADDLconst {
  5598  			break
  5599  		}
  5600  		off := v_0.AuxInt
  5601  		ptr := v_0.Args[0]
  5602  		if !(ValAndOff(sc).canAdd(off)) {
  5603  			break
  5604  		}
  5605  		v.reset(Op386MOVBstoreconst)
  5606  		v.AuxInt = ValAndOff(sc).add(off)
  5607  		v.Aux = s
  5608  		v.AddArg(ptr)
  5609  		v.AddArg(mem)
  5610  		return true
  5611  	}
  5612  	// match: (MOVBstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem)
  5613  	// cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  5614  	// result: (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem)
  5615  	for {
  5616  		sc := v.AuxInt
  5617  		sym1 := v.Aux
  5618  		mem := v.Args[1]
  5619  		v_0 := v.Args[0]
  5620  		if v_0.Op != Op386LEAL {
  5621  			break
  5622  		}
  5623  		off := v_0.AuxInt
  5624  		sym2 := v_0.Aux
  5625  		ptr := v_0.Args[0]
  5626  		if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  5627  			break
  5628  		}
  5629  		v.reset(Op386MOVBstoreconst)
  5630  		v.AuxInt = ValAndOff(sc).add(off)
  5631  		v.Aux = mergeSym(sym1, sym2)
  5632  		v.AddArg(ptr)
  5633  		v.AddArg(mem)
  5634  		return true
  5635  	}
  5636  	// match: (MOVBstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem)
  5637  	// cond: canMergeSym(sym1, sym2)
  5638  	// result: (MOVBstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem)
  5639  	for {
  5640  		x := v.AuxInt
  5641  		sym1 := v.Aux
  5642  		mem := v.Args[1]
  5643  		v_0 := v.Args[0]
  5644  		if v_0.Op != Op386LEAL1 {
  5645  			break
  5646  		}
  5647  		off := v_0.AuxInt
  5648  		sym2 := v_0.Aux
  5649  		idx := v_0.Args[1]
  5650  		ptr := v_0.Args[0]
  5651  		if !(canMergeSym(sym1, sym2)) {
  5652  			break
  5653  		}
  5654  		v.reset(Op386MOVBstoreconstidx1)
  5655  		v.AuxInt = ValAndOff(x).add(off)
  5656  		v.Aux = mergeSym(sym1, sym2)
  5657  		v.AddArg(ptr)
  5658  		v.AddArg(idx)
  5659  		v.AddArg(mem)
  5660  		return true
  5661  	}
  5662  	// match: (MOVBstoreconst [x] {sym} (ADDL ptr idx) mem)
  5663  	// cond:
  5664  	// result: (MOVBstoreconstidx1 [x] {sym} ptr idx mem)
  5665  	for {
  5666  		x := v.AuxInt
  5667  		sym := v.Aux
  5668  		mem := v.Args[1]
  5669  		v_0 := v.Args[0]
  5670  		if v_0.Op != Op386ADDL {
  5671  			break
  5672  		}
  5673  		idx := v_0.Args[1]
  5674  		ptr := v_0.Args[0]
  5675  		v.reset(Op386MOVBstoreconstidx1)
  5676  		v.AuxInt = x
  5677  		v.Aux = sym
  5678  		v.AddArg(ptr)
  5679  		v.AddArg(idx)
  5680  		v.AddArg(mem)
  5681  		return true
  5682  	}
  5683  	// match: (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem))
  5684  	// cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x)
  5685  	// result: (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem)
  5686  	for {
  5687  		c := v.AuxInt
  5688  		s := v.Aux
  5689  		_ = v.Args[1]
  5690  		p := v.Args[0]
  5691  		x := v.Args[1]
  5692  		if x.Op != Op386MOVBstoreconst {
  5693  			break
  5694  		}
  5695  		a := x.AuxInt
  5696  		if x.Aux != s {
  5697  			break
  5698  		}
  5699  		mem := x.Args[1]
  5700  		if p != x.Args[0] {
  5701  			break
  5702  		}
  5703  		if !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) {
  5704  			break
  5705  		}
  5706  		v.reset(Op386MOVWstoreconst)
  5707  		v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off())
  5708  		v.Aux = s
  5709  		v.AddArg(p)
  5710  		v.AddArg(mem)
  5711  		return true
  5712  	}
  5713  	// match: (MOVBstoreconst [a] {s} p x:(MOVBstoreconst [c] {s} p mem))
  5714  	// cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x)
  5715  	// result: (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem)
  5716  	for {
  5717  		a := v.AuxInt
  5718  		s := v.Aux
  5719  		_ = v.Args[1]
  5720  		p := v.Args[0]
  5721  		x := v.Args[1]
  5722  		if x.Op != Op386MOVBstoreconst {
  5723  			break
  5724  		}
  5725  		c := x.AuxInt
  5726  		if x.Aux != s {
  5727  			break
  5728  		}
  5729  		mem := x.Args[1]
  5730  		if p != x.Args[0] {
  5731  			break
  5732  		}
  5733  		if !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) {
  5734  			break
  5735  		}
  5736  		v.reset(Op386MOVWstoreconst)
  5737  		v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off())
  5738  		v.Aux = s
  5739  		v.AddArg(p)
  5740  		v.AddArg(mem)
  5741  		return true
  5742  	}
  5743  	return false
  5744  }
  5745  func rewriteValue386_Op386MOVBstoreconstidx1_0(v *Value) bool {
  5746  	// match: (MOVBstoreconstidx1 [x] {sym} (ADDLconst [c] ptr) idx mem)
  5747  	// cond:
  5748  	// result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem)
  5749  	for {
  5750  		x := v.AuxInt
  5751  		sym := v.Aux
  5752  		mem := v.Args[2]
  5753  		v_0 := v.Args[0]
  5754  		if v_0.Op != Op386ADDLconst {
  5755  			break
  5756  		}
  5757  		c := v_0.AuxInt
  5758  		ptr := v_0.Args[0]
  5759  		idx := v.Args[1]
  5760  		v.reset(Op386MOVBstoreconstidx1)
  5761  		v.AuxInt = ValAndOff(x).add(c)
  5762  		v.Aux = sym
  5763  		v.AddArg(ptr)
  5764  		v.AddArg(idx)
  5765  		v.AddArg(mem)
  5766  		return true
  5767  	}
  5768  	// match: (MOVBstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem)
  5769  	// cond:
  5770  	// result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem)
  5771  	for {
  5772  		x := v.AuxInt
  5773  		sym := v.Aux
  5774  		mem := v.Args[2]
  5775  		ptr := v.Args[0]
  5776  		v_1 := v.Args[1]
  5777  		if v_1.Op != Op386ADDLconst {
  5778  			break
  5779  		}
  5780  		c := v_1.AuxInt
  5781  		idx := v_1.Args[0]
  5782  		v.reset(Op386MOVBstoreconstidx1)
  5783  		v.AuxInt = ValAndOff(x).add(c)
  5784  		v.Aux = sym
  5785  		v.AddArg(ptr)
  5786  		v.AddArg(idx)
  5787  		v.AddArg(mem)
  5788  		return true
  5789  	}
  5790  	// match: (MOVBstoreconstidx1 [c] {s} p i x:(MOVBstoreconstidx1 [a] {s} p i mem))
  5791  	// cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x)
  5792  	// result: (MOVWstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p i mem)
  5793  	for {
  5794  		c := v.AuxInt
  5795  		s := v.Aux
  5796  		_ = v.Args[2]
  5797  		p := v.Args[0]
  5798  		i := v.Args[1]
  5799  		x := v.Args[2]
  5800  		if x.Op != Op386MOVBstoreconstidx1 {
  5801  			break
  5802  		}
  5803  		a := x.AuxInt
  5804  		if x.Aux != s {
  5805  			break
  5806  		}
  5807  		mem := x.Args[2]
  5808  		if p != x.Args[0] {
  5809  			break
  5810  		}
  5811  		if i != x.Args[1] {
  5812  			break
  5813  		}
  5814  		if !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) {
  5815  			break
  5816  		}
  5817  		v.reset(Op386MOVWstoreconstidx1)
  5818  		v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off())
  5819  		v.Aux = s
  5820  		v.AddArg(p)
  5821  		v.AddArg(i)
  5822  		v.AddArg(mem)
  5823  		return true
  5824  	}
  5825  	return false
  5826  }
  5827  func rewriteValue386_Op386MOVBstoreidx1_0(v *Value) bool {
  5828  	// match: (MOVBstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem)
  5829  	// cond:
  5830  	// result: (MOVBstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  5831  	for {
  5832  		c := v.AuxInt
  5833  		sym := v.Aux
  5834  		mem := v.Args[3]
  5835  		v_0 := v.Args[0]
  5836  		if v_0.Op != Op386ADDLconst {
  5837  			break
  5838  		}
  5839  		d := v_0.AuxInt
  5840  		ptr := v_0.Args[0]
  5841  		idx := v.Args[1]
  5842  		val := v.Args[2]
  5843  		v.reset(Op386MOVBstoreidx1)
  5844  		v.AuxInt = int64(int32(c + d))
  5845  		v.Aux = sym
  5846  		v.AddArg(ptr)
  5847  		v.AddArg(idx)
  5848  		v.AddArg(val)
  5849  		v.AddArg(mem)
  5850  		return true
  5851  	}
  5852  	// match: (MOVBstoreidx1 [c] {sym} idx (ADDLconst [d] ptr) val mem)
  5853  	// cond:
  5854  	// result: (MOVBstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  5855  	for {
  5856  		c := v.AuxInt
  5857  		sym := v.Aux
  5858  		mem := v.Args[3]
  5859  		idx := v.Args[0]
  5860  		v_1 := v.Args[1]
  5861  		if v_1.Op != Op386ADDLconst {
  5862  			break
  5863  		}
  5864  		d := v_1.AuxInt
  5865  		ptr := v_1.Args[0]
  5866  		val := v.Args[2]
  5867  		v.reset(Op386MOVBstoreidx1)
  5868  		v.AuxInt = int64(int32(c + d))
  5869  		v.Aux = sym
  5870  		v.AddArg(ptr)
  5871  		v.AddArg(idx)
  5872  		v.AddArg(val)
  5873  		v.AddArg(mem)
  5874  		return true
  5875  	}
  5876  	// match: (MOVBstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem)
  5877  	// cond:
  5878  	// result: (MOVBstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  5879  	for {
  5880  		c := v.AuxInt
  5881  		sym := v.Aux
  5882  		mem := v.Args[3]
  5883  		ptr := v.Args[0]
  5884  		v_1 := v.Args[1]
  5885  		if v_1.Op != Op386ADDLconst {
  5886  			break
  5887  		}
  5888  		d := v_1.AuxInt
  5889  		idx := v_1.Args[0]
  5890  		val := v.Args[2]
  5891  		v.reset(Op386MOVBstoreidx1)
  5892  		v.AuxInt = int64(int32(c + d))
  5893  		v.Aux = sym
  5894  		v.AddArg(ptr)
  5895  		v.AddArg(idx)
  5896  		v.AddArg(val)
  5897  		v.AddArg(mem)
  5898  		return true
  5899  	}
  5900  	// match: (MOVBstoreidx1 [c] {sym} (ADDLconst [d] idx) ptr val mem)
  5901  	// cond:
  5902  	// result: (MOVBstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  5903  	for {
  5904  		c := v.AuxInt
  5905  		sym := v.Aux
  5906  		mem := v.Args[3]
  5907  		v_0 := v.Args[0]
  5908  		if v_0.Op != Op386ADDLconst {
  5909  			break
  5910  		}
  5911  		d := v_0.AuxInt
  5912  		idx := v_0.Args[0]
  5913  		ptr := v.Args[1]
  5914  		val := v.Args[2]
  5915  		v.reset(Op386MOVBstoreidx1)
  5916  		v.AuxInt = int64(int32(c + d))
  5917  		v.Aux = sym
  5918  		v.AddArg(ptr)
  5919  		v.AddArg(idx)
  5920  		v.AddArg(val)
  5921  		v.AddArg(mem)
  5922  		return true
  5923  	}
  5924  	// match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem))
  5925  	// cond: x.Uses == 1 && clobber(x)
  5926  	// result: (MOVWstoreidx1 [i-1] {s} p idx w mem)
  5927  	for {
  5928  		i := v.AuxInt
  5929  		s := v.Aux
  5930  		_ = v.Args[3]
  5931  		p := v.Args[0]
  5932  		idx := v.Args[1]
  5933  		v_2 := v.Args[2]
  5934  		if v_2.Op != Op386SHRLconst {
  5935  			break
  5936  		}
  5937  		if v_2.AuxInt != 8 {
  5938  			break
  5939  		}
  5940  		w := v_2.Args[0]
  5941  		x := v.Args[3]
  5942  		if x.Op != Op386MOVBstoreidx1 {
  5943  			break
  5944  		}
  5945  		if x.AuxInt != i-1 {
  5946  			break
  5947  		}
  5948  		if x.Aux != s {
  5949  			break
  5950  		}
  5951  		mem := x.Args[3]
  5952  		if p != x.Args[0] {
  5953  			break
  5954  		}
  5955  		if idx != x.Args[1] {
  5956  			break
  5957  		}
  5958  		if w != x.Args[2] {
  5959  			break
  5960  		}
  5961  		if !(x.Uses == 1 && clobber(x)) {
  5962  			break
  5963  		}
  5964  		v.reset(Op386MOVWstoreidx1)
  5965  		v.AuxInt = i - 1
  5966  		v.Aux = s
  5967  		v.AddArg(p)
  5968  		v.AddArg(idx)
  5969  		v.AddArg(w)
  5970  		v.AddArg(mem)
  5971  		return true
  5972  	}
  5973  	// match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem))
  5974  	// cond: x.Uses == 1 && clobber(x)
  5975  	// result: (MOVWstoreidx1 [i-1] {s} p idx w mem)
  5976  	for {
  5977  		i := v.AuxInt
  5978  		s := v.Aux
  5979  		_ = v.Args[3]
  5980  		p := v.Args[0]
  5981  		idx := v.Args[1]
  5982  		v_2 := v.Args[2]
  5983  		if v_2.Op != Op386SHRLconst {
  5984  			break
  5985  		}
  5986  		if v_2.AuxInt != 8 {
  5987  			break
  5988  		}
  5989  		w := v_2.Args[0]
  5990  		x := v.Args[3]
  5991  		if x.Op != Op386MOVBstoreidx1 {
  5992  			break
  5993  		}
  5994  		if x.AuxInt != i-1 {
  5995  			break
  5996  		}
  5997  		if x.Aux != s {
  5998  			break
  5999  		}
  6000  		mem := x.Args[3]
  6001  		if idx != x.Args[0] {
  6002  			break
  6003  		}
  6004  		if p != x.Args[1] {
  6005  			break
  6006  		}
  6007  		if w != x.Args[2] {
  6008  			break
  6009  		}
  6010  		if !(x.Uses == 1 && clobber(x)) {
  6011  			break
  6012  		}
  6013  		v.reset(Op386MOVWstoreidx1)
  6014  		v.AuxInt = i - 1
  6015  		v.Aux = s
  6016  		v.AddArg(p)
  6017  		v.AddArg(idx)
  6018  		v.AddArg(w)
  6019  		v.AddArg(mem)
  6020  		return true
  6021  	}
  6022  	// match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem))
  6023  	// cond: x.Uses == 1 && clobber(x)
  6024  	// result: (MOVWstoreidx1 [i-1] {s} p idx w mem)
  6025  	for {
  6026  		i := v.AuxInt
  6027  		s := v.Aux
  6028  		_ = v.Args[3]
  6029  		idx := v.Args[0]
  6030  		p := v.Args[1]
  6031  		v_2 := v.Args[2]
  6032  		if v_2.Op != Op386SHRLconst {
  6033  			break
  6034  		}
  6035  		if v_2.AuxInt != 8 {
  6036  			break
  6037  		}
  6038  		w := v_2.Args[0]
  6039  		x := v.Args[3]
  6040  		if x.Op != Op386MOVBstoreidx1 {
  6041  			break
  6042  		}
  6043  		if x.AuxInt != i-1 {
  6044  			break
  6045  		}
  6046  		if x.Aux != s {
  6047  			break
  6048  		}
  6049  		mem := x.Args[3]
  6050  		if p != x.Args[0] {
  6051  			break
  6052  		}
  6053  		if idx != x.Args[1] {
  6054  			break
  6055  		}
  6056  		if w != x.Args[2] {
  6057  			break
  6058  		}
  6059  		if !(x.Uses == 1 && clobber(x)) {
  6060  			break
  6061  		}
  6062  		v.reset(Op386MOVWstoreidx1)
  6063  		v.AuxInt = i - 1
  6064  		v.Aux = s
  6065  		v.AddArg(p)
  6066  		v.AddArg(idx)
  6067  		v.AddArg(w)
  6068  		v.AddArg(mem)
  6069  		return true
  6070  	}
  6071  	// match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem))
  6072  	// cond: x.Uses == 1 && clobber(x)
  6073  	// result: (MOVWstoreidx1 [i-1] {s} p idx w mem)
  6074  	for {
  6075  		i := v.AuxInt
  6076  		s := v.Aux
  6077  		_ = v.Args[3]
  6078  		idx := v.Args[0]
  6079  		p := v.Args[1]
  6080  		v_2 := v.Args[2]
  6081  		if v_2.Op != Op386SHRLconst {
  6082  			break
  6083  		}
  6084  		if v_2.AuxInt != 8 {
  6085  			break
  6086  		}
  6087  		w := v_2.Args[0]
  6088  		x := v.Args[3]
  6089  		if x.Op != Op386MOVBstoreidx1 {
  6090  			break
  6091  		}
  6092  		if x.AuxInt != i-1 {
  6093  			break
  6094  		}
  6095  		if x.Aux != s {
  6096  			break
  6097  		}
  6098  		mem := x.Args[3]
  6099  		if idx != x.Args[0] {
  6100  			break
  6101  		}
  6102  		if p != x.Args[1] {
  6103  			break
  6104  		}
  6105  		if w != x.Args[2] {
  6106  			break
  6107  		}
  6108  		if !(x.Uses == 1 && clobber(x)) {
  6109  			break
  6110  		}
  6111  		v.reset(Op386MOVWstoreidx1)
  6112  		v.AuxInt = i - 1
  6113  		v.Aux = s
  6114  		v.AddArg(p)
  6115  		v.AddArg(idx)
  6116  		v.AddArg(w)
  6117  		v.AddArg(mem)
  6118  		return true
  6119  	}
  6120  	// match: (MOVBstoreidx1 [i] {s} p idx (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem))
  6121  	// cond: x.Uses == 1 && clobber(x)
  6122  	// result: (MOVWstoreidx1 [i-1] {s} p idx w mem)
  6123  	for {
  6124  		i := v.AuxInt
  6125  		s := v.Aux
  6126  		_ = v.Args[3]
  6127  		p := v.Args[0]
  6128  		idx := v.Args[1]
  6129  		v_2 := v.Args[2]
  6130  		if v_2.Op != Op386SHRWconst {
  6131  			break
  6132  		}
  6133  		if v_2.AuxInt != 8 {
  6134  			break
  6135  		}
  6136  		w := v_2.Args[0]
  6137  		x := v.Args[3]
  6138  		if x.Op != Op386MOVBstoreidx1 {
  6139  			break
  6140  		}
  6141  		if x.AuxInt != i-1 {
  6142  			break
  6143  		}
  6144  		if x.Aux != s {
  6145  			break
  6146  		}
  6147  		mem := x.Args[3]
  6148  		if p != x.Args[0] {
  6149  			break
  6150  		}
  6151  		if idx != x.Args[1] {
  6152  			break
  6153  		}
  6154  		if w != x.Args[2] {
  6155  			break
  6156  		}
  6157  		if !(x.Uses == 1 && clobber(x)) {
  6158  			break
  6159  		}
  6160  		v.reset(Op386MOVWstoreidx1)
  6161  		v.AuxInt = i - 1
  6162  		v.Aux = s
  6163  		v.AddArg(p)
  6164  		v.AddArg(idx)
  6165  		v.AddArg(w)
  6166  		v.AddArg(mem)
  6167  		return true
  6168  	}
  6169  	// match: (MOVBstoreidx1 [i] {s} p idx (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem))
  6170  	// cond: x.Uses == 1 && clobber(x)
  6171  	// result: (MOVWstoreidx1 [i-1] {s} p idx w mem)
  6172  	for {
  6173  		i := v.AuxInt
  6174  		s := v.Aux
  6175  		_ = v.Args[3]
  6176  		p := v.Args[0]
  6177  		idx := v.Args[1]
  6178  		v_2 := v.Args[2]
  6179  		if v_2.Op != Op386SHRWconst {
  6180  			break
  6181  		}
  6182  		if v_2.AuxInt != 8 {
  6183  			break
  6184  		}
  6185  		w := v_2.Args[0]
  6186  		x := v.Args[3]
  6187  		if x.Op != Op386MOVBstoreidx1 {
  6188  			break
  6189  		}
  6190  		if x.AuxInt != i-1 {
  6191  			break
  6192  		}
  6193  		if x.Aux != s {
  6194  			break
  6195  		}
  6196  		mem := x.Args[3]
  6197  		if idx != x.Args[0] {
  6198  			break
  6199  		}
  6200  		if p != x.Args[1] {
  6201  			break
  6202  		}
  6203  		if w != x.Args[2] {
  6204  			break
  6205  		}
  6206  		if !(x.Uses == 1 && clobber(x)) {
  6207  			break
  6208  		}
  6209  		v.reset(Op386MOVWstoreidx1)
  6210  		v.AuxInt = i - 1
  6211  		v.Aux = s
  6212  		v.AddArg(p)
  6213  		v.AddArg(idx)
  6214  		v.AddArg(w)
  6215  		v.AddArg(mem)
  6216  		return true
  6217  	}
  6218  	return false
  6219  }
  6220  func rewriteValue386_Op386MOVBstoreidx1_10(v *Value) bool {
  6221  	// match: (MOVBstoreidx1 [i] {s} idx p (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem))
  6222  	// cond: x.Uses == 1 && clobber(x)
  6223  	// result: (MOVWstoreidx1 [i-1] {s} p idx w mem)
  6224  	for {
  6225  		i := v.AuxInt
  6226  		s := v.Aux
  6227  		_ = v.Args[3]
  6228  		idx := v.Args[0]
  6229  		p := v.Args[1]
  6230  		v_2 := v.Args[2]
  6231  		if v_2.Op != Op386SHRWconst {
  6232  			break
  6233  		}
  6234  		if v_2.AuxInt != 8 {
  6235  			break
  6236  		}
  6237  		w := v_2.Args[0]
  6238  		x := v.Args[3]
  6239  		if x.Op != Op386MOVBstoreidx1 {
  6240  			break
  6241  		}
  6242  		if x.AuxInt != i-1 {
  6243  			break
  6244  		}
  6245  		if x.Aux != s {
  6246  			break
  6247  		}
  6248  		mem := x.Args[3]
  6249  		if p != x.Args[0] {
  6250  			break
  6251  		}
  6252  		if idx != x.Args[1] {
  6253  			break
  6254  		}
  6255  		if w != x.Args[2] {
  6256  			break
  6257  		}
  6258  		if !(x.Uses == 1 && clobber(x)) {
  6259  			break
  6260  		}
  6261  		v.reset(Op386MOVWstoreidx1)
  6262  		v.AuxInt = i - 1
  6263  		v.Aux = s
  6264  		v.AddArg(p)
  6265  		v.AddArg(idx)
  6266  		v.AddArg(w)
  6267  		v.AddArg(mem)
  6268  		return true
  6269  	}
  6270  	// match: (MOVBstoreidx1 [i] {s} idx p (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem))
  6271  	// cond: x.Uses == 1 && clobber(x)
  6272  	// result: (MOVWstoreidx1 [i-1] {s} p idx w mem)
  6273  	for {
  6274  		i := v.AuxInt
  6275  		s := v.Aux
  6276  		_ = v.Args[3]
  6277  		idx := v.Args[0]
  6278  		p := v.Args[1]
  6279  		v_2 := v.Args[2]
  6280  		if v_2.Op != Op386SHRWconst {
  6281  			break
  6282  		}
  6283  		if v_2.AuxInt != 8 {
  6284  			break
  6285  		}
  6286  		w := v_2.Args[0]
  6287  		x := v.Args[3]
  6288  		if x.Op != Op386MOVBstoreidx1 {
  6289  			break
  6290  		}
  6291  		if x.AuxInt != i-1 {
  6292  			break
  6293  		}
  6294  		if x.Aux != s {
  6295  			break
  6296  		}
  6297  		mem := x.Args[3]
  6298  		if idx != x.Args[0] {
  6299  			break
  6300  		}
  6301  		if p != x.Args[1] {
  6302  			break
  6303  		}
  6304  		if w != x.Args[2] {
  6305  			break
  6306  		}
  6307  		if !(x.Uses == 1 && clobber(x)) {
  6308  			break
  6309  		}
  6310  		v.reset(Op386MOVWstoreidx1)
  6311  		v.AuxInt = i - 1
  6312  		v.Aux = s
  6313  		v.AddArg(p)
  6314  		v.AddArg(idx)
  6315  		v.AddArg(w)
  6316  		v.AddArg(mem)
  6317  		return true
  6318  	}
  6319  	// match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRLconst [8] w) mem))
  6320  	// cond: x.Uses == 1 && clobber(x)
  6321  	// result: (MOVWstoreidx1 [i] {s} p idx w mem)
  6322  	for {
  6323  		i := v.AuxInt
  6324  		s := v.Aux
  6325  		_ = v.Args[3]
  6326  		p := v.Args[0]
  6327  		idx := v.Args[1]
  6328  		w := v.Args[2]
  6329  		x := v.Args[3]
  6330  		if x.Op != Op386MOVBstoreidx1 {
  6331  			break
  6332  		}
  6333  		if x.AuxInt != i+1 {
  6334  			break
  6335  		}
  6336  		if x.Aux != s {
  6337  			break
  6338  		}
  6339  		mem := x.Args[3]
  6340  		if p != x.Args[0] {
  6341  			break
  6342  		}
  6343  		if idx != x.Args[1] {
  6344  			break
  6345  		}
  6346  		x_2 := x.Args[2]
  6347  		if x_2.Op != Op386SHRLconst {
  6348  			break
  6349  		}
  6350  		if x_2.AuxInt != 8 {
  6351  			break
  6352  		}
  6353  		if w != x_2.Args[0] {
  6354  			break
  6355  		}
  6356  		if !(x.Uses == 1 && clobber(x)) {
  6357  			break
  6358  		}
  6359  		v.reset(Op386MOVWstoreidx1)
  6360  		v.AuxInt = i
  6361  		v.Aux = s
  6362  		v.AddArg(p)
  6363  		v.AddArg(idx)
  6364  		v.AddArg(w)
  6365  		v.AddArg(mem)
  6366  		return true
  6367  	}
  6368  	// match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRLconst [8] w) mem))
  6369  	// cond: x.Uses == 1 && clobber(x)
  6370  	// result: (MOVWstoreidx1 [i] {s} p idx w mem)
  6371  	for {
  6372  		i := v.AuxInt
  6373  		s := v.Aux
  6374  		_ = v.Args[3]
  6375  		p := v.Args[0]
  6376  		idx := v.Args[1]
  6377  		w := v.Args[2]
  6378  		x := v.Args[3]
  6379  		if x.Op != Op386MOVBstoreidx1 {
  6380  			break
  6381  		}
  6382  		if x.AuxInt != i+1 {
  6383  			break
  6384  		}
  6385  		if x.Aux != s {
  6386  			break
  6387  		}
  6388  		mem := x.Args[3]
  6389  		if idx != x.Args[0] {
  6390  			break
  6391  		}
  6392  		if p != x.Args[1] {
  6393  			break
  6394  		}
  6395  		x_2 := x.Args[2]
  6396  		if x_2.Op != Op386SHRLconst {
  6397  			break
  6398  		}
  6399  		if x_2.AuxInt != 8 {
  6400  			break
  6401  		}
  6402  		if w != x_2.Args[0] {
  6403  			break
  6404  		}
  6405  		if !(x.Uses == 1 && clobber(x)) {
  6406  			break
  6407  		}
  6408  		v.reset(Op386MOVWstoreidx1)
  6409  		v.AuxInt = i
  6410  		v.Aux = s
  6411  		v.AddArg(p)
  6412  		v.AddArg(idx)
  6413  		v.AddArg(w)
  6414  		v.AddArg(mem)
  6415  		return true
  6416  	}
  6417  	// match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRLconst [8] w) mem))
  6418  	// cond: x.Uses == 1 && clobber(x)
  6419  	// result: (MOVWstoreidx1 [i] {s} p idx w mem)
  6420  	for {
  6421  		i := v.AuxInt
  6422  		s := v.Aux
  6423  		_ = v.Args[3]
  6424  		idx := v.Args[0]
  6425  		p := v.Args[1]
  6426  		w := v.Args[2]
  6427  		x := v.Args[3]
  6428  		if x.Op != Op386MOVBstoreidx1 {
  6429  			break
  6430  		}
  6431  		if x.AuxInt != i+1 {
  6432  			break
  6433  		}
  6434  		if x.Aux != s {
  6435  			break
  6436  		}
  6437  		mem := x.Args[3]
  6438  		if p != x.Args[0] {
  6439  			break
  6440  		}
  6441  		if idx != x.Args[1] {
  6442  			break
  6443  		}
  6444  		x_2 := x.Args[2]
  6445  		if x_2.Op != Op386SHRLconst {
  6446  			break
  6447  		}
  6448  		if x_2.AuxInt != 8 {
  6449  			break
  6450  		}
  6451  		if w != x_2.Args[0] {
  6452  			break
  6453  		}
  6454  		if !(x.Uses == 1 && clobber(x)) {
  6455  			break
  6456  		}
  6457  		v.reset(Op386MOVWstoreidx1)
  6458  		v.AuxInt = i
  6459  		v.Aux = s
  6460  		v.AddArg(p)
  6461  		v.AddArg(idx)
  6462  		v.AddArg(w)
  6463  		v.AddArg(mem)
  6464  		return true
  6465  	}
  6466  	// match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRLconst [8] w) mem))
  6467  	// cond: x.Uses == 1 && clobber(x)
  6468  	// result: (MOVWstoreidx1 [i] {s} p idx w mem)
  6469  	for {
  6470  		i := v.AuxInt
  6471  		s := v.Aux
  6472  		_ = v.Args[3]
  6473  		idx := v.Args[0]
  6474  		p := v.Args[1]
  6475  		w := v.Args[2]
  6476  		x := v.Args[3]
  6477  		if x.Op != Op386MOVBstoreidx1 {
  6478  			break
  6479  		}
  6480  		if x.AuxInt != i+1 {
  6481  			break
  6482  		}
  6483  		if x.Aux != s {
  6484  			break
  6485  		}
  6486  		mem := x.Args[3]
  6487  		if idx != x.Args[0] {
  6488  			break
  6489  		}
  6490  		if p != x.Args[1] {
  6491  			break
  6492  		}
  6493  		x_2 := x.Args[2]
  6494  		if x_2.Op != Op386SHRLconst {
  6495  			break
  6496  		}
  6497  		if x_2.AuxInt != 8 {
  6498  			break
  6499  		}
  6500  		if w != x_2.Args[0] {
  6501  			break
  6502  		}
  6503  		if !(x.Uses == 1 && clobber(x)) {
  6504  			break
  6505  		}
  6506  		v.reset(Op386MOVWstoreidx1)
  6507  		v.AuxInt = i
  6508  		v.Aux = s
  6509  		v.AddArg(p)
  6510  		v.AddArg(idx)
  6511  		v.AddArg(w)
  6512  		v.AddArg(mem)
  6513  		return true
  6514  	}
  6515  	// match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRWconst [8] w) mem))
  6516  	// cond: x.Uses == 1 && clobber(x)
  6517  	// result: (MOVWstoreidx1 [i] {s} p idx w mem)
  6518  	for {
  6519  		i := v.AuxInt
  6520  		s := v.Aux
  6521  		_ = v.Args[3]
  6522  		p := v.Args[0]
  6523  		idx := v.Args[1]
  6524  		w := v.Args[2]
  6525  		x := v.Args[3]
  6526  		if x.Op != Op386MOVBstoreidx1 {
  6527  			break
  6528  		}
  6529  		if x.AuxInt != i+1 {
  6530  			break
  6531  		}
  6532  		if x.Aux != s {
  6533  			break
  6534  		}
  6535  		mem := x.Args[3]
  6536  		if p != x.Args[0] {
  6537  			break
  6538  		}
  6539  		if idx != x.Args[1] {
  6540  			break
  6541  		}
  6542  		x_2 := x.Args[2]
  6543  		if x_2.Op != Op386SHRWconst {
  6544  			break
  6545  		}
  6546  		if x_2.AuxInt != 8 {
  6547  			break
  6548  		}
  6549  		if w != x_2.Args[0] {
  6550  			break
  6551  		}
  6552  		if !(x.Uses == 1 && clobber(x)) {
  6553  			break
  6554  		}
  6555  		v.reset(Op386MOVWstoreidx1)
  6556  		v.AuxInt = i
  6557  		v.Aux = s
  6558  		v.AddArg(p)
  6559  		v.AddArg(idx)
  6560  		v.AddArg(w)
  6561  		v.AddArg(mem)
  6562  		return true
  6563  	}
  6564  	// match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRWconst [8] w) mem))
  6565  	// cond: x.Uses == 1 && clobber(x)
  6566  	// result: (MOVWstoreidx1 [i] {s} p idx w mem)
  6567  	for {
  6568  		i := v.AuxInt
  6569  		s := v.Aux
  6570  		_ = v.Args[3]
  6571  		p := v.Args[0]
  6572  		idx := v.Args[1]
  6573  		w := v.Args[2]
  6574  		x := v.Args[3]
  6575  		if x.Op != Op386MOVBstoreidx1 {
  6576  			break
  6577  		}
  6578  		if x.AuxInt != i+1 {
  6579  			break
  6580  		}
  6581  		if x.Aux != s {
  6582  			break
  6583  		}
  6584  		mem := x.Args[3]
  6585  		if idx != x.Args[0] {
  6586  			break
  6587  		}
  6588  		if p != x.Args[1] {
  6589  			break
  6590  		}
  6591  		x_2 := x.Args[2]
  6592  		if x_2.Op != Op386SHRWconst {
  6593  			break
  6594  		}
  6595  		if x_2.AuxInt != 8 {
  6596  			break
  6597  		}
  6598  		if w != x_2.Args[0] {
  6599  			break
  6600  		}
  6601  		if !(x.Uses == 1 && clobber(x)) {
  6602  			break
  6603  		}
  6604  		v.reset(Op386MOVWstoreidx1)
  6605  		v.AuxInt = i
  6606  		v.Aux = s
  6607  		v.AddArg(p)
  6608  		v.AddArg(idx)
  6609  		v.AddArg(w)
  6610  		v.AddArg(mem)
  6611  		return true
  6612  	}
  6613  	// match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRWconst [8] w) mem))
  6614  	// cond: x.Uses == 1 && clobber(x)
  6615  	// result: (MOVWstoreidx1 [i] {s} p idx w mem)
  6616  	for {
  6617  		i := v.AuxInt
  6618  		s := v.Aux
  6619  		_ = v.Args[3]
  6620  		idx := v.Args[0]
  6621  		p := v.Args[1]
  6622  		w := v.Args[2]
  6623  		x := v.Args[3]
  6624  		if x.Op != Op386MOVBstoreidx1 {
  6625  			break
  6626  		}
  6627  		if x.AuxInt != i+1 {
  6628  			break
  6629  		}
  6630  		if x.Aux != s {
  6631  			break
  6632  		}
  6633  		mem := x.Args[3]
  6634  		if p != x.Args[0] {
  6635  			break
  6636  		}
  6637  		if idx != x.Args[1] {
  6638  			break
  6639  		}
  6640  		x_2 := x.Args[2]
  6641  		if x_2.Op != Op386SHRWconst {
  6642  			break
  6643  		}
  6644  		if x_2.AuxInt != 8 {
  6645  			break
  6646  		}
  6647  		if w != x_2.Args[0] {
  6648  			break
  6649  		}
  6650  		if !(x.Uses == 1 && clobber(x)) {
  6651  			break
  6652  		}
  6653  		v.reset(Op386MOVWstoreidx1)
  6654  		v.AuxInt = i
  6655  		v.Aux = s
  6656  		v.AddArg(p)
  6657  		v.AddArg(idx)
  6658  		v.AddArg(w)
  6659  		v.AddArg(mem)
  6660  		return true
  6661  	}
  6662  	// match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRWconst [8] w) mem))
  6663  	// cond: x.Uses == 1 && clobber(x)
  6664  	// result: (MOVWstoreidx1 [i] {s} p idx w mem)
  6665  	for {
  6666  		i := v.AuxInt
  6667  		s := v.Aux
  6668  		_ = v.Args[3]
  6669  		idx := v.Args[0]
  6670  		p := v.Args[1]
  6671  		w := v.Args[2]
  6672  		x := v.Args[3]
  6673  		if x.Op != Op386MOVBstoreidx1 {
  6674  			break
  6675  		}
  6676  		if x.AuxInt != i+1 {
  6677  			break
  6678  		}
  6679  		if x.Aux != s {
  6680  			break
  6681  		}
  6682  		mem := x.Args[3]
  6683  		if idx != x.Args[0] {
  6684  			break
  6685  		}
  6686  		if p != x.Args[1] {
  6687  			break
  6688  		}
  6689  		x_2 := x.Args[2]
  6690  		if x_2.Op != Op386SHRWconst {
  6691  			break
  6692  		}
  6693  		if x_2.AuxInt != 8 {
  6694  			break
  6695  		}
  6696  		if w != x_2.Args[0] {
  6697  			break
  6698  		}
  6699  		if !(x.Uses == 1 && clobber(x)) {
  6700  			break
  6701  		}
  6702  		v.reset(Op386MOVWstoreidx1)
  6703  		v.AuxInt = i
  6704  		v.Aux = s
  6705  		v.AddArg(p)
  6706  		v.AddArg(idx)
  6707  		v.AddArg(w)
  6708  		v.AddArg(mem)
  6709  		return true
  6710  	}
  6711  	return false
  6712  }
  6713  func rewriteValue386_Op386MOVBstoreidx1_20(v *Value) bool {
  6714  	// match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem))
  6715  	// cond: x.Uses == 1 && clobber(x)
  6716  	// result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem)
  6717  	for {
  6718  		i := v.AuxInt
  6719  		s := v.Aux
  6720  		_ = v.Args[3]
  6721  		p := v.Args[0]
  6722  		idx := v.Args[1]
  6723  		v_2 := v.Args[2]
  6724  		if v_2.Op != Op386SHRLconst {
  6725  			break
  6726  		}
  6727  		j := v_2.AuxInt
  6728  		w := v_2.Args[0]
  6729  		x := v.Args[3]
  6730  		if x.Op != Op386MOVBstoreidx1 {
  6731  			break
  6732  		}
  6733  		if x.AuxInt != i-1 {
  6734  			break
  6735  		}
  6736  		if x.Aux != s {
  6737  			break
  6738  		}
  6739  		mem := x.Args[3]
  6740  		if p != x.Args[0] {
  6741  			break
  6742  		}
  6743  		if idx != x.Args[1] {
  6744  			break
  6745  		}
  6746  		w0 := x.Args[2]
  6747  		if w0.Op != Op386SHRLconst {
  6748  			break
  6749  		}
  6750  		if w0.AuxInt != j-8 {
  6751  			break
  6752  		}
  6753  		if w != w0.Args[0] {
  6754  			break
  6755  		}
  6756  		if !(x.Uses == 1 && clobber(x)) {
  6757  			break
  6758  		}
  6759  		v.reset(Op386MOVWstoreidx1)
  6760  		v.AuxInt = i - 1
  6761  		v.Aux = s
  6762  		v.AddArg(p)
  6763  		v.AddArg(idx)
  6764  		v.AddArg(w0)
  6765  		v.AddArg(mem)
  6766  		return true
  6767  	}
  6768  	// match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} idx p w0:(SHRLconst [j-8] w) mem))
  6769  	// cond: x.Uses == 1 && clobber(x)
  6770  	// result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem)
  6771  	for {
  6772  		i := v.AuxInt
  6773  		s := v.Aux
  6774  		_ = v.Args[3]
  6775  		p := v.Args[0]
  6776  		idx := v.Args[1]
  6777  		v_2 := v.Args[2]
  6778  		if v_2.Op != Op386SHRLconst {
  6779  			break
  6780  		}
  6781  		j := v_2.AuxInt
  6782  		w := v_2.Args[0]
  6783  		x := v.Args[3]
  6784  		if x.Op != Op386MOVBstoreidx1 {
  6785  			break
  6786  		}
  6787  		if x.AuxInt != i-1 {
  6788  			break
  6789  		}
  6790  		if x.Aux != s {
  6791  			break
  6792  		}
  6793  		mem := x.Args[3]
  6794  		if idx != x.Args[0] {
  6795  			break
  6796  		}
  6797  		if p != x.Args[1] {
  6798  			break
  6799  		}
  6800  		w0 := x.Args[2]
  6801  		if w0.Op != Op386SHRLconst {
  6802  			break
  6803  		}
  6804  		if w0.AuxInt != j-8 {
  6805  			break
  6806  		}
  6807  		if w != w0.Args[0] {
  6808  			break
  6809  		}
  6810  		if !(x.Uses == 1 && clobber(x)) {
  6811  			break
  6812  		}
  6813  		v.reset(Op386MOVWstoreidx1)
  6814  		v.AuxInt = i - 1
  6815  		v.Aux = s
  6816  		v.AddArg(p)
  6817  		v.AddArg(idx)
  6818  		v.AddArg(w0)
  6819  		v.AddArg(mem)
  6820  		return true
  6821  	}
  6822  	// match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem))
  6823  	// cond: x.Uses == 1 && clobber(x)
  6824  	// result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem)
  6825  	for {
  6826  		i := v.AuxInt
  6827  		s := v.Aux
  6828  		_ = v.Args[3]
  6829  		idx := v.Args[0]
  6830  		p := v.Args[1]
  6831  		v_2 := v.Args[2]
  6832  		if v_2.Op != Op386SHRLconst {
  6833  			break
  6834  		}
  6835  		j := v_2.AuxInt
  6836  		w := v_2.Args[0]
  6837  		x := v.Args[3]
  6838  		if x.Op != Op386MOVBstoreidx1 {
  6839  			break
  6840  		}
  6841  		if x.AuxInt != i-1 {
  6842  			break
  6843  		}
  6844  		if x.Aux != s {
  6845  			break
  6846  		}
  6847  		mem := x.Args[3]
  6848  		if p != x.Args[0] {
  6849  			break
  6850  		}
  6851  		if idx != x.Args[1] {
  6852  			break
  6853  		}
  6854  		w0 := x.Args[2]
  6855  		if w0.Op != Op386SHRLconst {
  6856  			break
  6857  		}
  6858  		if w0.AuxInt != j-8 {
  6859  			break
  6860  		}
  6861  		if w != w0.Args[0] {
  6862  			break
  6863  		}
  6864  		if !(x.Uses == 1 && clobber(x)) {
  6865  			break
  6866  		}
  6867  		v.reset(Op386MOVWstoreidx1)
  6868  		v.AuxInt = i - 1
  6869  		v.Aux = s
  6870  		v.AddArg(p)
  6871  		v.AddArg(idx)
  6872  		v.AddArg(w0)
  6873  		v.AddArg(mem)
  6874  		return true
  6875  	}
  6876  	// match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} idx p w0:(SHRLconst [j-8] w) mem))
  6877  	// cond: x.Uses == 1 && clobber(x)
  6878  	// result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem)
  6879  	for {
  6880  		i := v.AuxInt
  6881  		s := v.Aux
  6882  		_ = v.Args[3]
  6883  		idx := v.Args[0]
  6884  		p := v.Args[1]
  6885  		v_2 := v.Args[2]
  6886  		if v_2.Op != Op386SHRLconst {
  6887  			break
  6888  		}
  6889  		j := v_2.AuxInt
  6890  		w := v_2.Args[0]
  6891  		x := v.Args[3]
  6892  		if x.Op != Op386MOVBstoreidx1 {
  6893  			break
  6894  		}
  6895  		if x.AuxInt != i-1 {
  6896  			break
  6897  		}
  6898  		if x.Aux != s {
  6899  			break
  6900  		}
  6901  		mem := x.Args[3]
  6902  		if idx != x.Args[0] {
  6903  			break
  6904  		}
  6905  		if p != x.Args[1] {
  6906  			break
  6907  		}
  6908  		w0 := x.Args[2]
  6909  		if w0.Op != Op386SHRLconst {
  6910  			break
  6911  		}
  6912  		if w0.AuxInt != j-8 {
  6913  			break
  6914  		}
  6915  		if w != w0.Args[0] {
  6916  			break
  6917  		}
  6918  		if !(x.Uses == 1 && clobber(x)) {
  6919  			break
  6920  		}
  6921  		v.reset(Op386MOVWstoreidx1)
  6922  		v.AuxInt = i - 1
  6923  		v.Aux = s
  6924  		v.AddArg(p)
  6925  		v.AddArg(idx)
  6926  		v.AddArg(w0)
  6927  		v.AddArg(mem)
  6928  		return true
  6929  	}
  6930  	return false
  6931  }
  6932  func rewriteValue386_Op386MOVLload_0(v *Value) bool {
  6933  	b := v.Block
  6934  	config := b.Func.Config
  6935  	// match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _))
  6936  	// cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
  6937  	// result: x
  6938  	for {
  6939  		off := v.AuxInt
  6940  		sym := v.Aux
  6941  		_ = v.Args[1]
  6942  		ptr := v.Args[0]
  6943  		v_1 := v.Args[1]
  6944  		if v_1.Op != Op386MOVLstore {
  6945  			break
  6946  		}
  6947  		off2 := v_1.AuxInt
  6948  		sym2 := v_1.Aux
  6949  		_ = v_1.Args[2]
  6950  		ptr2 := v_1.Args[0]
  6951  		x := v_1.Args[1]
  6952  		if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
  6953  			break
  6954  		}
  6955  		v.reset(OpCopy)
  6956  		v.Type = x.Type
  6957  		v.AddArg(x)
  6958  		return true
  6959  	}
  6960  	// match: (MOVLload [off1] {sym} (ADDLconst [off2] ptr) mem)
  6961  	// cond: is32Bit(off1+off2)
  6962  	// result: (MOVLload [off1+off2] {sym} ptr mem)
  6963  	for {
  6964  		off1 := v.AuxInt
  6965  		sym := v.Aux
  6966  		mem := v.Args[1]
  6967  		v_0 := v.Args[0]
  6968  		if v_0.Op != Op386ADDLconst {
  6969  			break
  6970  		}
  6971  		off2 := v_0.AuxInt
  6972  		ptr := v_0.Args[0]
  6973  		if !(is32Bit(off1 + off2)) {
  6974  			break
  6975  		}
  6976  		v.reset(Op386MOVLload)
  6977  		v.AuxInt = off1 + off2
  6978  		v.Aux = sym
  6979  		v.AddArg(ptr)
  6980  		v.AddArg(mem)
  6981  		return true
  6982  	}
  6983  	// match: (MOVLload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
  6984  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  6985  	// result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem)
  6986  	for {
  6987  		off1 := v.AuxInt
  6988  		sym1 := v.Aux
  6989  		mem := v.Args[1]
  6990  		v_0 := v.Args[0]
  6991  		if v_0.Op != Op386LEAL {
  6992  			break
  6993  		}
  6994  		off2 := v_0.AuxInt
  6995  		sym2 := v_0.Aux
  6996  		base := v_0.Args[0]
  6997  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  6998  			break
  6999  		}
  7000  		v.reset(Op386MOVLload)
  7001  		v.AuxInt = off1 + off2
  7002  		v.Aux = mergeSym(sym1, sym2)
  7003  		v.AddArg(base)
  7004  		v.AddArg(mem)
  7005  		return true
  7006  	}
  7007  	// match: (MOVLload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem)
  7008  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  7009  	// result: (MOVLloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
  7010  	for {
  7011  		off1 := v.AuxInt
  7012  		sym1 := v.Aux
  7013  		mem := v.Args[1]
  7014  		v_0 := v.Args[0]
  7015  		if v_0.Op != Op386LEAL1 {
  7016  			break
  7017  		}
  7018  		off2 := v_0.AuxInt
  7019  		sym2 := v_0.Aux
  7020  		idx := v_0.Args[1]
  7021  		ptr := v_0.Args[0]
  7022  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  7023  			break
  7024  		}
  7025  		v.reset(Op386MOVLloadidx1)
  7026  		v.AuxInt = off1 + off2
  7027  		v.Aux = mergeSym(sym1, sym2)
  7028  		v.AddArg(ptr)
  7029  		v.AddArg(idx)
  7030  		v.AddArg(mem)
  7031  		return true
  7032  	}
  7033  	// match: (MOVLload [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) mem)
  7034  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  7035  	// result: (MOVLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
  7036  	for {
  7037  		off1 := v.AuxInt
  7038  		sym1 := v.Aux
  7039  		mem := v.Args[1]
  7040  		v_0 := v.Args[0]
  7041  		if v_0.Op != Op386LEAL4 {
  7042  			break
  7043  		}
  7044  		off2 := v_0.AuxInt
  7045  		sym2 := v_0.Aux
  7046  		idx := v_0.Args[1]
  7047  		ptr := v_0.Args[0]
  7048  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  7049  			break
  7050  		}
  7051  		v.reset(Op386MOVLloadidx4)
  7052  		v.AuxInt = off1 + off2
  7053  		v.Aux = mergeSym(sym1, sym2)
  7054  		v.AddArg(ptr)
  7055  		v.AddArg(idx)
  7056  		v.AddArg(mem)
  7057  		return true
  7058  	}
  7059  	// match: (MOVLload [off] {sym} (ADDL ptr idx) mem)
  7060  	// cond: ptr.Op != OpSB
  7061  	// result: (MOVLloadidx1 [off] {sym} ptr idx mem)
  7062  	for {
  7063  		off := v.AuxInt
  7064  		sym := v.Aux
  7065  		mem := v.Args[1]
  7066  		v_0 := v.Args[0]
  7067  		if v_0.Op != Op386ADDL {
  7068  			break
  7069  		}
  7070  		idx := v_0.Args[1]
  7071  		ptr := v_0.Args[0]
  7072  		if !(ptr.Op != OpSB) {
  7073  			break
  7074  		}
  7075  		v.reset(Op386MOVLloadidx1)
  7076  		v.AuxInt = off
  7077  		v.Aux = sym
  7078  		v.AddArg(ptr)
  7079  		v.AddArg(idx)
  7080  		v.AddArg(mem)
  7081  		return true
  7082  	}
  7083  	// match: (MOVLload [off] {sym} (SB) _)
  7084  	// cond: symIsRO(sym)
  7085  	// result: (MOVLconst [int64(int32(read32(sym, off, config.BigEndian)))])
  7086  	for {
  7087  		off := v.AuxInt
  7088  		sym := v.Aux
  7089  		_ = v.Args[1]
  7090  		v_0 := v.Args[0]
  7091  		if v_0.Op != OpSB {
  7092  			break
  7093  		}
  7094  		if !(symIsRO(sym)) {
  7095  			break
  7096  		}
  7097  		v.reset(Op386MOVLconst)
  7098  		v.AuxInt = int64(int32(read32(sym, off, config.BigEndian)))
  7099  		return true
  7100  	}
  7101  	return false
  7102  }
  7103  func rewriteValue386_Op386MOVLloadidx1_0(v *Value) bool {
  7104  	// match: (MOVLloadidx1 [c] {sym} ptr (SHLLconst [2] idx) mem)
  7105  	// cond:
  7106  	// result: (MOVLloadidx4 [c] {sym} ptr idx mem)
  7107  	for {
  7108  		c := v.AuxInt
  7109  		sym := v.Aux
  7110  		mem := v.Args[2]
  7111  		ptr := v.Args[0]
  7112  		v_1 := v.Args[1]
  7113  		if v_1.Op != Op386SHLLconst {
  7114  			break
  7115  		}
  7116  		if v_1.AuxInt != 2 {
  7117  			break
  7118  		}
  7119  		idx := v_1.Args[0]
  7120  		v.reset(Op386MOVLloadidx4)
  7121  		v.AuxInt = c
  7122  		v.Aux = sym
  7123  		v.AddArg(ptr)
  7124  		v.AddArg(idx)
  7125  		v.AddArg(mem)
  7126  		return true
  7127  	}
  7128  	// match: (MOVLloadidx1 [c] {sym} (SHLLconst [2] idx) ptr mem)
  7129  	// cond:
  7130  	// result: (MOVLloadidx4 [c] {sym} ptr idx mem)
  7131  	for {
  7132  		c := v.AuxInt
  7133  		sym := v.Aux
  7134  		mem := v.Args[2]
  7135  		v_0 := v.Args[0]
  7136  		if v_0.Op != Op386SHLLconst {
  7137  			break
  7138  		}
  7139  		if v_0.AuxInt != 2 {
  7140  			break
  7141  		}
  7142  		idx := v_0.Args[0]
  7143  		ptr := v.Args[1]
  7144  		v.reset(Op386MOVLloadidx4)
  7145  		v.AuxInt = c
  7146  		v.Aux = sym
  7147  		v.AddArg(ptr)
  7148  		v.AddArg(idx)
  7149  		v.AddArg(mem)
  7150  		return true
  7151  	}
  7152  	// match: (MOVLloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem)
  7153  	// cond:
  7154  	// result: (MOVLloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  7155  	for {
  7156  		c := v.AuxInt
  7157  		sym := v.Aux
  7158  		mem := v.Args[2]
  7159  		v_0 := v.Args[0]
  7160  		if v_0.Op != Op386ADDLconst {
  7161  			break
  7162  		}
  7163  		d := v_0.AuxInt
  7164  		ptr := v_0.Args[0]
  7165  		idx := v.Args[1]
  7166  		v.reset(Op386MOVLloadidx1)
  7167  		v.AuxInt = int64(int32(c + d))
  7168  		v.Aux = sym
  7169  		v.AddArg(ptr)
  7170  		v.AddArg(idx)
  7171  		v.AddArg(mem)
  7172  		return true
  7173  	}
  7174  	// match: (MOVLloadidx1 [c] {sym} idx (ADDLconst [d] ptr) mem)
  7175  	// cond:
  7176  	// result: (MOVLloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  7177  	for {
  7178  		c := v.AuxInt
  7179  		sym := v.Aux
  7180  		mem := v.Args[2]
  7181  		idx := v.Args[0]
  7182  		v_1 := v.Args[1]
  7183  		if v_1.Op != Op386ADDLconst {
  7184  			break
  7185  		}
  7186  		d := v_1.AuxInt
  7187  		ptr := v_1.Args[0]
  7188  		v.reset(Op386MOVLloadidx1)
  7189  		v.AuxInt = int64(int32(c + d))
  7190  		v.Aux = sym
  7191  		v.AddArg(ptr)
  7192  		v.AddArg(idx)
  7193  		v.AddArg(mem)
  7194  		return true
  7195  	}
  7196  	// match: (MOVLloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem)
  7197  	// cond:
  7198  	// result: (MOVLloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  7199  	for {
  7200  		c := v.AuxInt
  7201  		sym := v.Aux
  7202  		mem := v.Args[2]
  7203  		ptr := v.Args[0]
  7204  		v_1 := v.Args[1]
  7205  		if v_1.Op != Op386ADDLconst {
  7206  			break
  7207  		}
  7208  		d := v_1.AuxInt
  7209  		idx := v_1.Args[0]
  7210  		v.reset(Op386MOVLloadidx1)
  7211  		v.AuxInt = int64(int32(c + d))
  7212  		v.Aux = sym
  7213  		v.AddArg(ptr)
  7214  		v.AddArg(idx)
  7215  		v.AddArg(mem)
  7216  		return true
  7217  	}
  7218  	// match: (MOVLloadidx1 [c] {sym} (ADDLconst [d] idx) ptr mem)
  7219  	// cond:
  7220  	// result: (MOVLloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  7221  	for {
  7222  		c := v.AuxInt
  7223  		sym := v.Aux
  7224  		mem := v.Args[2]
  7225  		v_0 := v.Args[0]
  7226  		if v_0.Op != Op386ADDLconst {
  7227  			break
  7228  		}
  7229  		d := v_0.AuxInt
  7230  		idx := v_0.Args[0]
  7231  		ptr := v.Args[1]
  7232  		v.reset(Op386MOVLloadidx1)
  7233  		v.AuxInt = int64(int32(c + d))
  7234  		v.Aux = sym
  7235  		v.AddArg(ptr)
  7236  		v.AddArg(idx)
  7237  		v.AddArg(mem)
  7238  		return true
  7239  	}
  7240  	return false
  7241  }
  7242  func rewriteValue386_Op386MOVLloadidx4_0(v *Value) bool {
  7243  	// match: (MOVLloadidx4 [c] {sym} (ADDLconst [d] ptr) idx mem)
  7244  	// cond:
  7245  	// result: (MOVLloadidx4 [int64(int32(c+d))] {sym} ptr idx mem)
  7246  	for {
  7247  		c := v.AuxInt
  7248  		sym := v.Aux
  7249  		mem := v.Args[2]
  7250  		v_0 := v.Args[0]
  7251  		if v_0.Op != Op386ADDLconst {
  7252  			break
  7253  		}
  7254  		d := v_0.AuxInt
  7255  		ptr := v_0.Args[0]
  7256  		idx := v.Args[1]
  7257  		v.reset(Op386MOVLloadidx4)
  7258  		v.AuxInt = int64(int32(c + d))
  7259  		v.Aux = sym
  7260  		v.AddArg(ptr)
  7261  		v.AddArg(idx)
  7262  		v.AddArg(mem)
  7263  		return true
  7264  	}
  7265  	// match: (MOVLloadidx4 [c] {sym} ptr (ADDLconst [d] idx) mem)
  7266  	// cond:
  7267  	// result: (MOVLloadidx4 [int64(int32(c+4*d))] {sym} ptr idx mem)
  7268  	for {
  7269  		c := v.AuxInt
  7270  		sym := v.Aux
  7271  		mem := v.Args[2]
  7272  		ptr := v.Args[0]
  7273  		v_1 := v.Args[1]
  7274  		if v_1.Op != Op386ADDLconst {
  7275  			break
  7276  		}
  7277  		d := v_1.AuxInt
  7278  		idx := v_1.Args[0]
  7279  		v.reset(Op386MOVLloadidx4)
  7280  		v.AuxInt = int64(int32(c + 4*d))
  7281  		v.Aux = sym
  7282  		v.AddArg(ptr)
  7283  		v.AddArg(idx)
  7284  		v.AddArg(mem)
  7285  		return true
  7286  	}
  7287  	return false
  7288  }
  7289  func rewriteValue386_Op386MOVLstore_0(v *Value) bool {
  7290  	b := v.Block
  7291  	config := b.Func.Config
  7292  	// match: (MOVLstore [off1] {sym} (ADDLconst [off2] ptr) val mem)
  7293  	// cond: is32Bit(off1+off2)
  7294  	// result: (MOVLstore [off1+off2] {sym} ptr val mem)
  7295  	for {
  7296  		off1 := v.AuxInt
  7297  		sym := v.Aux
  7298  		mem := v.Args[2]
  7299  		v_0 := v.Args[0]
  7300  		if v_0.Op != Op386ADDLconst {
  7301  			break
  7302  		}
  7303  		off2 := v_0.AuxInt
  7304  		ptr := v_0.Args[0]
  7305  		val := v.Args[1]
  7306  		if !(is32Bit(off1 + off2)) {
  7307  			break
  7308  		}
  7309  		v.reset(Op386MOVLstore)
  7310  		v.AuxInt = off1 + off2
  7311  		v.Aux = sym
  7312  		v.AddArg(ptr)
  7313  		v.AddArg(val)
  7314  		v.AddArg(mem)
  7315  		return true
  7316  	}
  7317  	// match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem)
  7318  	// cond: validOff(off)
  7319  	// result: (MOVLstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem)
  7320  	for {
  7321  		off := v.AuxInt
  7322  		sym := v.Aux
  7323  		mem := v.Args[2]
  7324  		ptr := v.Args[0]
  7325  		v_1 := v.Args[1]
  7326  		if v_1.Op != Op386MOVLconst {
  7327  			break
  7328  		}
  7329  		c := v_1.AuxInt
  7330  		if !(validOff(off)) {
  7331  			break
  7332  		}
  7333  		v.reset(Op386MOVLstoreconst)
  7334  		v.AuxInt = makeValAndOff(int64(int32(c)), off)
  7335  		v.Aux = sym
  7336  		v.AddArg(ptr)
  7337  		v.AddArg(mem)
  7338  		return true
  7339  	}
  7340  	// match: (MOVLstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
  7341  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  7342  	// result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  7343  	for {
  7344  		off1 := v.AuxInt
  7345  		sym1 := v.Aux
  7346  		mem := v.Args[2]
  7347  		v_0 := v.Args[0]
  7348  		if v_0.Op != Op386LEAL {
  7349  			break
  7350  		}
  7351  		off2 := v_0.AuxInt
  7352  		sym2 := v_0.Aux
  7353  		base := v_0.Args[0]
  7354  		val := v.Args[1]
  7355  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  7356  			break
  7357  		}
  7358  		v.reset(Op386MOVLstore)
  7359  		v.AuxInt = off1 + off2
  7360  		v.Aux = mergeSym(sym1, sym2)
  7361  		v.AddArg(base)
  7362  		v.AddArg(val)
  7363  		v.AddArg(mem)
  7364  		return true
  7365  	}
  7366  	// match: (MOVLstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem)
  7367  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  7368  	// result: (MOVLstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
  7369  	for {
  7370  		off1 := v.AuxInt
  7371  		sym1 := v.Aux
  7372  		mem := v.Args[2]
  7373  		v_0 := v.Args[0]
  7374  		if v_0.Op != Op386LEAL1 {
  7375  			break
  7376  		}
  7377  		off2 := v_0.AuxInt
  7378  		sym2 := v_0.Aux
  7379  		idx := v_0.Args[1]
  7380  		ptr := v_0.Args[0]
  7381  		val := v.Args[1]
  7382  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  7383  			break
  7384  		}
  7385  		v.reset(Op386MOVLstoreidx1)
  7386  		v.AuxInt = off1 + off2
  7387  		v.Aux = mergeSym(sym1, sym2)
  7388  		v.AddArg(ptr)
  7389  		v.AddArg(idx)
  7390  		v.AddArg(val)
  7391  		v.AddArg(mem)
  7392  		return true
  7393  	}
  7394  	// match: (MOVLstore [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) val mem)
  7395  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  7396  	// result: (MOVLstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
  7397  	for {
  7398  		off1 := v.AuxInt
  7399  		sym1 := v.Aux
  7400  		mem := v.Args[2]
  7401  		v_0 := v.Args[0]
  7402  		if v_0.Op != Op386LEAL4 {
  7403  			break
  7404  		}
  7405  		off2 := v_0.AuxInt
  7406  		sym2 := v_0.Aux
  7407  		idx := v_0.Args[1]
  7408  		ptr := v_0.Args[0]
  7409  		val := v.Args[1]
  7410  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  7411  			break
  7412  		}
  7413  		v.reset(Op386MOVLstoreidx4)
  7414  		v.AuxInt = off1 + off2
  7415  		v.Aux = mergeSym(sym1, sym2)
  7416  		v.AddArg(ptr)
  7417  		v.AddArg(idx)
  7418  		v.AddArg(val)
  7419  		v.AddArg(mem)
  7420  		return true
  7421  	}
  7422  	// match: (MOVLstore [off] {sym} (ADDL ptr idx) val mem)
  7423  	// cond: ptr.Op != OpSB
  7424  	// result: (MOVLstoreidx1 [off] {sym} ptr idx val mem)
  7425  	for {
  7426  		off := v.AuxInt
  7427  		sym := v.Aux
  7428  		mem := v.Args[2]
  7429  		v_0 := v.Args[0]
  7430  		if v_0.Op != Op386ADDL {
  7431  			break
  7432  		}
  7433  		idx := v_0.Args[1]
  7434  		ptr := v_0.Args[0]
  7435  		val := v.Args[1]
  7436  		if !(ptr.Op != OpSB) {
  7437  			break
  7438  		}
  7439  		v.reset(Op386MOVLstoreidx1)
  7440  		v.AuxInt = off
  7441  		v.Aux = sym
  7442  		v.AddArg(ptr)
  7443  		v.AddArg(idx)
  7444  		v.AddArg(val)
  7445  		v.AddArg(mem)
  7446  		return true
  7447  	}
  7448  	// match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem)
  7449  	// cond: y.Uses==1 && clobber(y)
  7450  	// result: (ADDLmodify [off] {sym} ptr x mem)
  7451  	for {
  7452  		off := v.AuxInt
  7453  		sym := v.Aux
  7454  		mem := v.Args[2]
  7455  		ptr := v.Args[0]
  7456  		y := v.Args[1]
  7457  		if y.Op != Op386ADDLload {
  7458  			break
  7459  		}
  7460  		if y.AuxInt != off {
  7461  			break
  7462  		}
  7463  		if y.Aux != sym {
  7464  			break
  7465  		}
  7466  		_ = y.Args[2]
  7467  		x := y.Args[0]
  7468  		if ptr != y.Args[1] {
  7469  			break
  7470  		}
  7471  		if mem != y.Args[2] {
  7472  			break
  7473  		}
  7474  		if !(y.Uses == 1 && clobber(y)) {
  7475  			break
  7476  		}
  7477  		v.reset(Op386ADDLmodify)
  7478  		v.AuxInt = off
  7479  		v.Aux = sym
  7480  		v.AddArg(ptr)
  7481  		v.AddArg(x)
  7482  		v.AddArg(mem)
  7483  		return true
  7484  	}
  7485  	// match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem)
  7486  	// cond: y.Uses==1 && clobber(y)
  7487  	// result: (ANDLmodify [off] {sym} ptr x mem)
  7488  	for {
  7489  		off := v.AuxInt
  7490  		sym := v.Aux
  7491  		mem := v.Args[2]
  7492  		ptr := v.Args[0]
  7493  		y := v.Args[1]
  7494  		if y.Op != Op386ANDLload {
  7495  			break
  7496  		}
  7497  		if y.AuxInt != off {
  7498  			break
  7499  		}
  7500  		if y.Aux != sym {
  7501  			break
  7502  		}
  7503  		_ = y.Args[2]
  7504  		x := y.Args[0]
  7505  		if ptr != y.Args[1] {
  7506  			break
  7507  		}
  7508  		if mem != y.Args[2] {
  7509  			break
  7510  		}
  7511  		if !(y.Uses == 1 && clobber(y)) {
  7512  			break
  7513  		}
  7514  		v.reset(Op386ANDLmodify)
  7515  		v.AuxInt = off
  7516  		v.Aux = sym
  7517  		v.AddArg(ptr)
  7518  		v.AddArg(x)
  7519  		v.AddArg(mem)
  7520  		return true
  7521  	}
  7522  	// match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem)
  7523  	// cond: y.Uses==1 && clobber(y)
  7524  	// result: (ORLmodify [off] {sym} ptr x mem)
  7525  	for {
  7526  		off := v.AuxInt
  7527  		sym := v.Aux
  7528  		mem := v.Args[2]
  7529  		ptr := v.Args[0]
  7530  		y := v.Args[1]
  7531  		if y.Op != Op386ORLload {
  7532  			break
  7533  		}
  7534  		if y.AuxInt != off {
  7535  			break
  7536  		}
  7537  		if y.Aux != sym {
  7538  			break
  7539  		}
  7540  		_ = y.Args[2]
  7541  		x := y.Args[0]
  7542  		if ptr != y.Args[1] {
  7543  			break
  7544  		}
  7545  		if mem != y.Args[2] {
  7546  			break
  7547  		}
  7548  		if !(y.Uses == 1 && clobber(y)) {
  7549  			break
  7550  		}
  7551  		v.reset(Op386ORLmodify)
  7552  		v.AuxInt = off
  7553  		v.Aux = sym
  7554  		v.AddArg(ptr)
  7555  		v.AddArg(x)
  7556  		v.AddArg(mem)
  7557  		return true
  7558  	}
  7559  	// match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem)
  7560  	// cond: y.Uses==1 && clobber(y)
  7561  	// result: (XORLmodify [off] {sym} ptr x mem)
  7562  	for {
  7563  		off := v.AuxInt
  7564  		sym := v.Aux
  7565  		mem := v.Args[2]
  7566  		ptr := v.Args[0]
  7567  		y := v.Args[1]
  7568  		if y.Op != Op386XORLload {
  7569  			break
  7570  		}
  7571  		if y.AuxInt != off {
  7572  			break
  7573  		}
  7574  		if y.Aux != sym {
  7575  			break
  7576  		}
  7577  		_ = y.Args[2]
  7578  		x := y.Args[0]
  7579  		if ptr != y.Args[1] {
  7580  			break
  7581  		}
  7582  		if mem != y.Args[2] {
  7583  			break
  7584  		}
  7585  		if !(y.Uses == 1 && clobber(y)) {
  7586  			break
  7587  		}
  7588  		v.reset(Op386XORLmodify)
  7589  		v.AuxInt = off
  7590  		v.Aux = sym
  7591  		v.AddArg(ptr)
  7592  		v.AddArg(x)
  7593  		v.AddArg(mem)
  7594  		return true
  7595  	}
  7596  	return false
  7597  }
  7598  func rewriteValue386_Op386MOVLstore_10(v *Value) bool {
  7599  	// match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem)
  7600  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  7601  	// result: (ADDLmodify [off] {sym} ptr x mem)
  7602  	for {
  7603  		off := v.AuxInt
  7604  		sym := v.Aux
  7605  		mem := v.Args[2]
  7606  		ptr := v.Args[0]
  7607  		y := v.Args[1]
  7608  		if y.Op != Op386ADDL {
  7609  			break
  7610  		}
  7611  		x := y.Args[1]
  7612  		l := y.Args[0]
  7613  		if l.Op != Op386MOVLload {
  7614  			break
  7615  		}
  7616  		if l.AuxInt != off {
  7617  			break
  7618  		}
  7619  		if l.Aux != sym {
  7620  			break
  7621  		}
  7622  		_ = l.Args[1]
  7623  		if ptr != l.Args[0] {
  7624  			break
  7625  		}
  7626  		if mem != l.Args[1] {
  7627  			break
  7628  		}
  7629  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  7630  			break
  7631  		}
  7632  		v.reset(Op386ADDLmodify)
  7633  		v.AuxInt = off
  7634  		v.Aux = sym
  7635  		v.AddArg(ptr)
  7636  		v.AddArg(x)
  7637  		v.AddArg(mem)
  7638  		return true
  7639  	}
  7640  	// match: (MOVLstore {sym} [off] ptr y:(ADDL x l:(MOVLload [off] {sym} ptr mem)) mem)
  7641  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  7642  	// result: (ADDLmodify [off] {sym} ptr x mem)
  7643  	for {
  7644  		off := v.AuxInt
  7645  		sym := v.Aux
  7646  		mem := v.Args[2]
  7647  		ptr := v.Args[0]
  7648  		y := v.Args[1]
  7649  		if y.Op != Op386ADDL {
  7650  			break
  7651  		}
  7652  		_ = y.Args[1]
  7653  		x := y.Args[0]
  7654  		l := y.Args[1]
  7655  		if l.Op != Op386MOVLload {
  7656  			break
  7657  		}
  7658  		if l.AuxInt != off {
  7659  			break
  7660  		}
  7661  		if l.Aux != sym {
  7662  			break
  7663  		}
  7664  		_ = l.Args[1]
  7665  		if ptr != l.Args[0] {
  7666  			break
  7667  		}
  7668  		if mem != l.Args[1] {
  7669  			break
  7670  		}
  7671  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  7672  			break
  7673  		}
  7674  		v.reset(Op386ADDLmodify)
  7675  		v.AuxInt = off
  7676  		v.Aux = sym
  7677  		v.AddArg(ptr)
  7678  		v.AddArg(x)
  7679  		v.AddArg(mem)
  7680  		return true
  7681  	}
  7682  	// match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem)
  7683  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  7684  	// result: (SUBLmodify [off] {sym} ptr x mem)
  7685  	for {
  7686  		off := v.AuxInt
  7687  		sym := v.Aux
  7688  		mem := v.Args[2]
  7689  		ptr := v.Args[0]
  7690  		y := v.Args[1]
  7691  		if y.Op != Op386SUBL {
  7692  			break
  7693  		}
  7694  		x := y.Args[1]
  7695  		l := y.Args[0]
  7696  		if l.Op != Op386MOVLload {
  7697  			break
  7698  		}
  7699  		if l.AuxInt != off {
  7700  			break
  7701  		}
  7702  		if l.Aux != sym {
  7703  			break
  7704  		}
  7705  		_ = l.Args[1]
  7706  		if ptr != l.Args[0] {
  7707  			break
  7708  		}
  7709  		if mem != l.Args[1] {
  7710  			break
  7711  		}
  7712  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  7713  			break
  7714  		}
  7715  		v.reset(Op386SUBLmodify)
  7716  		v.AuxInt = off
  7717  		v.Aux = sym
  7718  		v.AddArg(ptr)
  7719  		v.AddArg(x)
  7720  		v.AddArg(mem)
  7721  		return true
  7722  	}
  7723  	// match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem)
  7724  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  7725  	// result: (ANDLmodify [off] {sym} ptr x mem)
  7726  	for {
  7727  		off := v.AuxInt
  7728  		sym := v.Aux
  7729  		mem := v.Args[2]
  7730  		ptr := v.Args[0]
  7731  		y := v.Args[1]
  7732  		if y.Op != Op386ANDL {
  7733  			break
  7734  		}
  7735  		x := y.Args[1]
  7736  		l := y.Args[0]
  7737  		if l.Op != Op386MOVLload {
  7738  			break
  7739  		}
  7740  		if l.AuxInt != off {
  7741  			break
  7742  		}
  7743  		if l.Aux != sym {
  7744  			break
  7745  		}
  7746  		_ = l.Args[1]
  7747  		if ptr != l.Args[0] {
  7748  			break
  7749  		}
  7750  		if mem != l.Args[1] {
  7751  			break
  7752  		}
  7753  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  7754  			break
  7755  		}
  7756  		v.reset(Op386ANDLmodify)
  7757  		v.AuxInt = off
  7758  		v.Aux = sym
  7759  		v.AddArg(ptr)
  7760  		v.AddArg(x)
  7761  		v.AddArg(mem)
  7762  		return true
  7763  	}
  7764  	// match: (MOVLstore {sym} [off] ptr y:(ANDL x l:(MOVLload [off] {sym} ptr mem)) mem)
  7765  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  7766  	// result: (ANDLmodify [off] {sym} ptr x mem)
  7767  	for {
  7768  		off := v.AuxInt
  7769  		sym := v.Aux
  7770  		mem := v.Args[2]
  7771  		ptr := v.Args[0]
  7772  		y := v.Args[1]
  7773  		if y.Op != Op386ANDL {
  7774  			break
  7775  		}
  7776  		_ = y.Args[1]
  7777  		x := y.Args[0]
  7778  		l := y.Args[1]
  7779  		if l.Op != Op386MOVLload {
  7780  			break
  7781  		}
  7782  		if l.AuxInt != off {
  7783  			break
  7784  		}
  7785  		if l.Aux != sym {
  7786  			break
  7787  		}
  7788  		_ = l.Args[1]
  7789  		if ptr != l.Args[0] {
  7790  			break
  7791  		}
  7792  		if mem != l.Args[1] {
  7793  			break
  7794  		}
  7795  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  7796  			break
  7797  		}
  7798  		v.reset(Op386ANDLmodify)
  7799  		v.AuxInt = off
  7800  		v.Aux = sym
  7801  		v.AddArg(ptr)
  7802  		v.AddArg(x)
  7803  		v.AddArg(mem)
  7804  		return true
  7805  	}
  7806  	// match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem)
  7807  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  7808  	// result: (ORLmodify [off] {sym} ptr x mem)
  7809  	for {
  7810  		off := v.AuxInt
  7811  		sym := v.Aux
  7812  		mem := v.Args[2]
  7813  		ptr := v.Args[0]
  7814  		y := v.Args[1]
  7815  		if y.Op != Op386ORL {
  7816  			break
  7817  		}
  7818  		x := y.Args[1]
  7819  		l := y.Args[0]
  7820  		if l.Op != Op386MOVLload {
  7821  			break
  7822  		}
  7823  		if l.AuxInt != off {
  7824  			break
  7825  		}
  7826  		if l.Aux != sym {
  7827  			break
  7828  		}
  7829  		_ = l.Args[1]
  7830  		if ptr != l.Args[0] {
  7831  			break
  7832  		}
  7833  		if mem != l.Args[1] {
  7834  			break
  7835  		}
  7836  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  7837  			break
  7838  		}
  7839  		v.reset(Op386ORLmodify)
  7840  		v.AuxInt = off
  7841  		v.Aux = sym
  7842  		v.AddArg(ptr)
  7843  		v.AddArg(x)
  7844  		v.AddArg(mem)
  7845  		return true
  7846  	}
  7847  	// match: (MOVLstore {sym} [off] ptr y:(ORL x l:(MOVLload [off] {sym} ptr mem)) mem)
  7848  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  7849  	// result: (ORLmodify [off] {sym} ptr x mem)
  7850  	for {
  7851  		off := v.AuxInt
  7852  		sym := v.Aux
  7853  		mem := v.Args[2]
  7854  		ptr := v.Args[0]
  7855  		y := v.Args[1]
  7856  		if y.Op != Op386ORL {
  7857  			break
  7858  		}
  7859  		_ = y.Args[1]
  7860  		x := y.Args[0]
  7861  		l := y.Args[1]
  7862  		if l.Op != Op386MOVLload {
  7863  			break
  7864  		}
  7865  		if l.AuxInt != off {
  7866  			break
  7867  		}
  7868  		if l.Aux != sym {
  7869  			break
  7870  		}
  7871  		_ = l.Args[1]
  7872  		if ptr != l.Args[0] {
  7873  			break
  7874  		}
  7875  		if mem != l.Args[1] {
  7876  			break
  7877  		}
  7878  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  7879  			break
  7880  		}
  7881  		v.reset(Op386ORLmodify)
  7882  		v.AuxInt = off
  7883  		v.Aux = sym
  7884  		v.AddArg(ptr)
  7885  		v.AddArg(x)
  7886  		v.AddArg(mem)
  7887  		return true
  7888  	}
  7889  	// match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem)
  7890  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  7891  	// result: (XORLmodify [off] {sym} ptr x mem)
  7892  	for {
  7893  		off := v.AuxInt
  7894  		sym := v.Aux
  7895  		mem := v.Args[2]
  7896  		ptr := v.Args[0]
  7897  		y := v.Args[1]
  7898  		if y.Op != Op386XORL {
  7899  			break
  7900  		}
  7901  		x := y.Args[1]
  7902  		l := y.Args[0]
  7903  		if l.Op != Op386MOVLload {
  7904  			break
  7905  		}
  7906  		if l.AuxInt != off {
  7907  			break
  7908  		}
  7909  		if l.Aux != sym {
  7910  			break
  7911  		}
  7912  		_ = l.Args[1]
  7913  		if ptr != l.Args[0] {
  7914  			break
  7915  		}
  7916  		if mem != l.Args[1] {
  7917  			break
  7918  		}
  7919  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  7920  			break
  7921  		}
  7922  		v.reset(Op386XORLmodify)
  7923  		v.AuxInt = off
  7924  		v.Aux = sym
  7925  		v.AddArg(ptr)
  7926  		v.AddArg(x)
  7927  		v.AddArg(mem)
  7928  		return true
  7929  	}
  7930  	// match: (MOVLstore {sym} [off] ptr y:(XORL x l:(MOVLload [off] {sym} ptr mem)) mem)
  7931  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  7932  	// result: (XORLmodify [off] {sym} ptr x mem)
  7933  	for {
  7934  		off := v.AuxInt
  7935  		sym := v.Aux
  7936  		mem := v.Args[2]
  7937  		ptr := v.Args[0]
  7938  		y := v.Args[1]
  7939  		if y.Op != Op386XORL {
  7940  			break
  7941  		}
  7942  		_ = y.Args[1]
  7943  		x := y.Args[0]
  7944  		l := y.Args[1]
  7945  		if l.Op != Op386MOVLload {
  7946  			break
  7947  		}
  7948  		if l.AuxInt != off {
  7949  			break
  7950  		}
  7951  		if l.Aux != sym {
  7952  			break
  7953  		}
  7954  		_ = l.Args[1]
  7955  		if ptr != l.Args[0] {
  7956  			break
  7957  		}
  7958  		if mem != l.Args[1] {
  7959  			break
  7960  		}
  7961  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  7962  			break
  7963  		}
  7964  		v.reset(Op386XORLmodify)
  7965  		v.AuxInt = off
  7966  		v.Aux = sym
  7967  		v.AddArg(ptr)
  7968  		v.AddArg(x)
  7969  		v.AddArg(mem)
  7970  		return true
  7971  	}
  7972  	// match: (MOVLstore {sym} [off] ptr y:(ADDLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem)
  7973  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off)
  7974  	// result: (ADDLconstmodify [makeValAndOff(c,off)] {sym} ptr mem)
  7975  	for {
  7976  		off := v.AuxInt
  7977  		sym := v.Aux
  7978  		mem := v.Args[2]
  7979  		ptr := v.Args[0]
  7980  		y := v.Args[1]
  7981  		if y.Op != Op386ADDLconst {
  7982  			break
  7983  		}
  7984  		c := y.AuxInt
  7985  		l := y.Args[0]
  7986  		if l.Op != Op386MOVLload {
  7987  			break
  7988  		}
  7989  		if l.AuxInt != off {
  7990  			break
  7991  		}
  7992  		if l.Aux != sym {
  7993  			break
  7994  		}
  7995  		_ = l.Args[1]
  7996  		if ptr != l.Args[0] {
  7997  			break
  7998  		}
  7999  		if mem != l.Args[1] {
  8000  			break
  8001  		}
  8002  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) {
  8003  			break
  8004  		}
  8005  		v.reset(Op386ADDLconstmodify)
  8006  		v.AuxInt = makeValAndOff(c, off)
  8007  		v.Aux = sym
  8008  		v.AddArg(ptr)
  8009  		v.AddArg(mem)
  8010  		return true
  8011  	}
  8012  	return false
  8013  }
  8014  func rewriteValue386_Op386MOVLstore_20(v *Value) bool {
  8015  	// match: (MOVLstore {sym} [off] ptr y:(ANDLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem)
  8016  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off)
  8017  	// result: (ANDLconstmodify [makeValAndOff(c,off)] {sym} ptr mem)
  8018  	for {
  8019  		off := v.AuxInt
  8020  		sym := v.Aux
  8021  		mem := v.Args[2]
  8022  		ptr := v.Args[0]
  8023  		y := v.Args[1]
  8024  		if y.Op != Op386ANDLconst {
  8025  			break
  8026  		}
  8027  		c := y.AuxInt
  8028  		l := y.Args[0]
  8029  		if l.Op != Op386MOVLload {
  8030  			break
  8031  		}
  8032  		if l.AuxInt != off {
  8033  			break
  8034  		}
  8035  		if l.Aux != sym {
  8036  			break
  8037  		}
  8038  		_ = l.Args[1]
  8039  		if ptr != l.Args[0] {
  8040  			break
  8041  		}
  8042  		if mem != l.Args[1] {
  8043  			break
  8044  		}
  8045  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) {
  8046  			break
  8047  		}
  8048  		v.reset(Op386ANDLconstmodify)
  8049  		v.AuxInt = makeValAndOff(c, off)
  8050  		v.Aux = sym
  8051  		v.AddArg(ptr)
  8052  		v.AddArg(mem)
  8053  		return true
  8054  	}
  8055  	// match: (MOVLstore {sym} [off] ptr y:(ORLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem)
  8056  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off)
  8057  	// result: (ORLconstmodify [makeValAndOff(c,off)] {sym} ptr mem)
  8058  	for {
  8059  		off := v.AuxInt
  8060  		sym := v.Aux
  8061  		mem := v.Args[2]
  8062  		ptr := v.Args[0]
  8063  		y := v.Args[1]
  8064  		if y.Op != Op386ORLconst {
  8065  			break
  8066  		}
  8067  		c := y.AuxInt
  8068  		l := y.Args[0]
  8069  		if l.Op != Op386MOVLload {
  8070  			break
  8071  		}
  8072  		if l.AuxInt != off {
  8073  			break
  8074  		}
  8075  		if l.Aux != sym {
  8076  			break
  8077  		}
  8078  		_ = l.Args[1]
  8079  		if ptr != l.Args[0] {
  8080  			break
  8081  		}
  8082  		if mem != l.Args[1] {
  8083  			break
  8084  		}
  8085  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) {
  8086  			break
  8087  		}
  8088  		v.reset(Op386ORLconstmodify)
  8089  		v.AuxInt = makeValAndOff(c, off)
  8090  		v.Aux = sym
  8091  		v.AddArg(ptr)
  8092  		v.AddArg(mem)
  8093  		return true
  8094  	}
  8095  	// match: (MOVLstore {sym} [off] ptr y:(XORLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem)
  8096  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off)
  8097  	// result: (XORLconstmodify [makeValAndOff(c,off)] {sym} ptr mem)
  8098  	for {
  8099  		off := v.AuxInt
  8100  		sym := v.Aux
  8101  		mem := v.Args[2]
  8102  		ptr := v.Args[0]
  8103  		y := v.Args[1]
  8104  		if y.Op != Op386XORLconst {
  8105  			break
  8106  		}
  8107  		c := y.AuxInt
  8108  		l := y.Args[0]
  8109  		if l.Op != Op386MOVLload {
  8110  			break
  8111  		}
  8112  		if l.AuxInt != off {
  8113  			break
  8114  		}
  8115  		if l.Aux != sym {
  8116  			break
  8117  		}
  8118  		_ = l.Args[1]
  8119  		if ptr != l.Args[0] {
  8120  			break
  8121  		}
  8122  		if mem != l.Args[1] {
  8123  			break
  8124  		}
  8125  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) {
  8126  			break
  8127  		}
  8128  		v.reset(Op386XORLconstmodify)
  8129  		v.AuxInt = makeValAndOff(c, off)
  8130  		v.Aux = sym
  8131  		v.AddArg(ptr)
  8132  		v.AddArg(mem)
  8133  		return true
  8134  	}
  8135  	return false
  8136  }
  8137  func rewriteValue386_Op386MOVLstoreconst_0(v *Value) bool {
  8138  	b := v.Block
  8139  	config := b.Func.Config
  8140  	// match: (MOVLstoreconst [sc] {s} (ADDLconst [off] ptr) mem)
  8141  	// cond: ValAndOff(sc).canAdd(off)
  8142  	// result: (MOVLstoreconst [ValAndOff(sc).add(off)] {s} ptr mem)
  8143  	for {
  8144  		sc := v.AuxInt
  8145  		s := v.Aux
  8146  		mem := v.Args[1]
  8147  		v_0 := v.Args[0]
  8148  		if v_0.Op != Op386ADDLconst {
  8149  			break
  8150  		}
  8151  		off := v_0.AuxInt
  8152  		ptr := v_0.Args[0]
  8153  		if !(ValAndOff(sc).canAdd(off)) {
  8154  			break
  8155  		}
  8156  		v.reset(Op386MOVLstoreconst)
  8157  		v.AuxInt = ValAndOff(sc).add(off)
  8158  		v.Aux = s
  8159  		v.AddArg(ptr)
  8160  		v.AddArg(mem)
  8161  		return true
  8162  	}
  8163  	// match: (MOVLstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem)
  8164  	// cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  8165  	// result: (MOVLstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem)
  8166  	for {
  8167  		sc := v.AuxInt
  8168  		sym1 := v.Aux
  8169  		mem := v.Args[1]
  8170  		v_0 := v.Args[0]
  8171  		if v_0.Op != Op386LEAL {
  8172  			break
  8173  		}
  8174  		off := v_0.AuxInt
  8175  		sym2 := v_0.Aux
  8176  		ptr := v_0.Args[0]
  8177  		if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  8178  			break
  8179  		}
  8180  		v.reset(Op386MOVLstoreconst)
  8181  		v.AuxInt = ValAndOff(sc).add(off)
  8182  		v.Aux = mergeSym(sym1, sym2)
  8183  		v.AddArg(ptr)
  8184  		v.AddArg(mem)
  8185  		return true
  8186  	}
  8187  	// match: (MOVLstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem)
  8188  	// cond: canMergeSym(sym1, sym2)
  8189  	// result: (MOVLstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem)
  8190  	for {
  8191  		x := v.AuxInt
  8192  		sym1 := v.Aux
  8193  		mem := v.Args[1]
  8194  		v_0 := v.Args[0]
  8195  		if v_0.Op != Op386LEAL1 {
  8196  			break
  8197  		}
  8198  		off := v_0.AuxInt
  8199  		sym2 := v_0.Aux
  8200  		idx := v_0.Args[1]
  8201  		ptr := v_0.Args[0]
  8202  		if !(canMergeSym(sym1, sym2)) {
  8203  			break
  8204  		}
  8205  		v.reset(Op386MOVLstoreconstidx1)
  8206  		v.AuxInt = ValAndOff(x).add(off)
  8207  		v.Aux = mergeSym(sym1, sym2)
  8208  		v.AddArg(ptr)
  8209  		v.AddArg(idx)
  8210  		v.AddArg(mem)
  8211  		return true
  8212  	}
  8213  	// match: (MOVLstoreconst [x] {sym1} (LEAL4 [off] {sym2} ptr idx) mem)
  8214  	// cond: canMergeSym(sym1, sym2)
  8215  	// result: (MOVLstoreconstidx4 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem)
  8216  	for {
  8217  		x := v.AuxInt
  8218  		sym1 := v.Aux
  8219  		mem := v.Args[1]
  8220  		v_0 := v.Args[0]
  8221  		if v_0.Op != Op386LEAL4 {
  8222  			break
  8223  		}
  8224  		off := v_0.AuxInt
  8225  		sym2 := v_0.Aux
  8226  		idx := v_0.Args[1]
  8227  		ptr := v_0.Args[0]
  8228  		if !(canMergeSym(sym1, sym2)) {
  8229  			break
  8230  		}
  8231  		v.reset(Op386MOVLstoreconstidx4)
  8232  		v.AuxInt = ValAndOff(x).add(off)
  8233  		v.Aux = mergeSym(sym1, sym2)
  8234  		v.AddArg(ptr)
  8235  		v.AddArg(idx)
  8236  		v.AddArg(mem)
  8237  		return true
  8238  	}
  8239  	// match: (MOVLstoreconst [x] {sym} (ADDL ptr idx) mem)
  8240  	// cond:
  8241  	// result: (MOVLstoreconstidx1 [x] {sym} ptr idx mem)
  8242  	for {
  8243  		x := v.AuxInt
  8244  		sym := v.Aux
  8245  		mem := v.Args[1]
  8246  		v_0 := v.Args[0]
  8247  		if v_0.Op != Op386ADDL {
  8248  			break
  8249  		}
  8250  		idx := v_0.Args[1]
  8251  		ptr := v_0.Args[0]
  8252  		v.reset(Op386MOVLstoreconstidx1)
  8253  		v.AuxInt = x
  8254  		v.Aux = sym
  8255  		v.AddArg(ptr)
  8256  		v.AddArg(idx)
  8257  		v.AddArg(mem)
  8258  		return true
  8259  	}
  8260  	return false
  8261  }
  8262  func rewriteValue386_Op386MOVLstoreconstidx1_0(v *Value) bool {
  8263  	// match: (MOVLstoreconstidx1 [c] {sym} ptr (SHLLconst [2] idx) mem)
  8264  	// cond:
  8265  	// result: (MOVLstoreconstidx4 [c] {sym} ptr idx mem)
  8266  	for {
  8267  		c := v.AuxInt
  8268  		sym := v.Aux
  8269  		mem := v.Args[2]
  8270  		ptr := v.Args[0]
  8271  		v_1 := v.Args[1]
  8272  		if v_1.Op != Op386SHLLconst {
  8273  			break
  8274  		}
  8275  		if v_1.AuxInt != 2 {
  8276  			break
  8277  		}
  8278  		idx := v_1.Args[0]
  8279  		v.reset(Op386MOVLstoreconstidx4)
  8280  		v.AuxInt = c
  8281  		v.Aux = sym
  8282  		v.AddArg(ptr)
  8283  		v.AddArg(idx)
  8284  		v.AddArg(mem)
  8285  		return true
  8286  	}
  8287  	// match: (MOVLstoreconstidx1 [x] {sym} (ADDLconst [c] ptr) idx mem)
  8288  	// cond:
  8289  	// result: (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem)
  8290  	for {
  8291  		x := v.AuxInt
  8292  		sym := v.Aux
  8293  		mem := v.Args[2]
  8294  		v_0 := v.Args[0]
  8295  		if v_0.Op != Op386ADDLconst {
  8296  			break
  8297  		}
  8298  		c := v_0.AuxInt
  8299  		ptr := v_0.Args[0]
  8300  		idx := v.Args[1]
  8301  		v.reset(Op386MOVLstoreconstidx1)
  8302  		v.AuxInt = ValAndOff(x).add(c)
  8303  		v.Aux = sym
  8304  		v.AddArg(ptr)
  8305  		v.AddArg(idx)
  8306  		v.AddArg(mem)
  8307  		return true
  8308  	}
  8309  	// match: (MOVLstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem)
  8310  	// cond:
  8311  	// result: (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem)
  8312  	for {
  8313  		x := v.AuxInt
  8314  		sym := v.Aux
  8315  		mem := v.Args[2]
  8316  		ptr := v.Args[0]
  8317  		v_1 := v.Args[1]
  8318  		if v_1.Op != Op386ADDLconst {
  8319  			break
  8320  		}
  8321  		c := v_1.AuxInt
  8322  		idx := v_1.Args[0]
  8323  		v.reset(Op386MOVLstoreconstidx1)
  8324  		v.AuxInt = ValAndOff(x).add(c)
  8325  		v.Aux = sym
  8326  		v.AddArg(ptr)
  8327  		v.AddArg(idx)
  8328  		v.AddArg(mem)
  8329  		return true
  8330  	}
  8331  	return false
  8332  }
  8333  func rewriteValue386_Op386MOVLstoreconstidx4_0(v *Value) bool {
  8334  	// match: (MOVLstoreconstidx4 [x] {sym} (ADDLconst [c] ptr) idx mem)
  8335  	// cond:
  8336  	// result: (MOVLstoreconstidx4 [ValAndOff(x).add(c)] {sym} ptr idx mem)
  8337  	for {
  8338  		x := v.AuxInt
  8339  		sym := v.Aux
  8340  		mem := v.Args[2]
  8341  		v_0 := v.Args[0]
  8342  		if v_0.Op != Op386ADDLconst {
  8343  			break
  8344  		}
  8345  		c := v_0.AuxInt
  8346  		ptr := v_0.Args[0]
  8347  		idx := v.Args[1]
  8348  		v.reset(Op386MOVLstoreconstidx4)
  8349  		v.AuxInt = ValAndOff(x).add(c)
  8350  		v.Aux = sym
  8351  		v.AddArg(ptr)
  8352  		v.AddArg(idx)
  8353  		v.AddArg(mem)
  8354  		return true
  8355  	}
  8356  	// match: (MOVLstoreconstidx4 [x] {sym} ptr (ADDLconst [c] idx) mem)
  8357  	// cond:
  8358  	// result: (MOVLstoreconstidx4 [ValAndOff(x).add(4*c)] {sym} ptr idx mem)
  8359  	for {
  8360  		x := v.AuxInt
  8361  		sym := v.Aux
  8362  		mem := v.Args[2]
  8363  		ptr := v.Args[0]
  8364  		v_1 := v.Args[1]
  8365  		if v_1.Op != Op386ADDLconst {
  8366  			break
  8367  		}
  8368  		c := v_1.AuxInt
  8369  		idx := v_1.Args[0]
  8370  		v.reset(Op386MOVLstoreconstidx4)
  8371  		v.AuxInt = ValAndOff(x).add(4 * c)
  8372  		v.Aux = sym
  8373  		v.AddArg(ptr)
  8374  		v.AddArg(idx)
  8375  		v.AddArg(mem)
  8376  		return true
  8377  	}
  8378  	return false
  8379  }
  8380  func rewriteValue386_Op386MOVLstoreidx1_0(v *Value) bool {
  8381  	// match: (MOVLstoreidx1 [c] {sym} ptr (SHLLconst [2] idx) val mem)
  8382  	// cond:
  8383  	// result: (MOVLstoreidx4 [c] {sym} ptr idx val mem)
  8384  	for {
  8385  		c := v.AuxInt
  8386  		sym := v.Aux
  8387  		mem := v.Args[3]
  8388  		ptr := v.Args[0]
  8389  		v_1 := v.Args[1]
  8390  		if v_1.Op != Op386SHLLconst {
  8391  			break
  8392  		}
  8393  		if v_1.AuxInt != 2 {
  8394  			break
  8395  		}
  8396  		idx := v_1.Args[0]
  8397  		val := v.Args[2]
  8398  		v.reset(Op386MOVLstoreidx4)
  8399  		v.AuxInt = c
  8400  		v.Aux = sym
  8401  		v.AddArg(ptr)
  8402  		v.AddArg(idx)
  8403  		v.AddArg(val)
  8404  		v.AddArg(mem)
  8405  		return true
  8406  	}
  8407  	// match: (MOVLstoreidx1 [c] {sym} (SHLLconst [2] idx) ptr val mem)
  8408  	// cond:
  8409  	// result: (MOVLstoreidx4 [c] {sym} ptr idx val mem)
  8410  	for {
  8411  		c := v.AuxInt
  8412  		sym := v.Aux
  8413  		mem := v.Args[3]
  8414  		v_0 := v.Args[0]
  8415  		if v_0.Op != Op386SHLLconst {
  8416  			break
  8417  		}
  8418  		if v_0.AuxInt != 2 {
  8419  			break
  8420  		}
  8421  		idx := v_0.Args[0]
  8422  		ptr := v.Args[1]
  8423  		val := v.Args[2]
  8424  		v.reset(Op386MOVLstoreidx4)
  8425  		v.AuxInt = c
  8426  		v.Aux = sym
  8427  		v.AddArg(ptr)
  8428  		v.AddArg(idx)
  8429  		v.AddArg(val)
  8430  		v.AddArg(mem)
  8431  		return true
  8432  	}
  8433  	// match: (MOVLstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem)
  8434  	// cond:
  8435  	// result: (MOVLstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  8436  	for {
  8437  		c := v.AuxInt
  8438  		sym := v.Aux
  8439  		mem := v.Args[3]
  8440  		v_0 := v.Args[0]
  8441  		if v_0.Op != Op386ADDLconst {
  8442  			break
  8443  		}
  8444  		d := v_0.AuxInt
  8445  		ptr := v_0.Args[0]
  8446  		idx := v.Args[1]
  8447  		val := v.Args[2]
  8448  		v.reset(Op386MOVLstoreidx1)
  8449  		v.AuxInt = int64(int32(c + d))
  8450  		v.Aux = sym
  8451  		v.AddArg(ptr)
  8452  		v.AddArg(idx)
  8453  		v.AddArg(val)
  8454  		v.AddArg(mem)
  8455  		return true
  8456  	}
  8457  	// match: (MOVLstoreidx1 [c] {sym} idx (ADDLconst [d] ptr) val mem)
  8458  	// cond:
  8459  	// result: (MOVLstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  8460  	for {
  8461  		c := v.AuxInt
  8462  		sym := v.Aux
  8463  		mem := v.Args[3]
  8464  		idx := v.Args[0]
  8465  		v_1 := v.Args[1]
  8466  		if v_1.Op != Op386ADDLconst {
  8467  			break
  8468  		}
  8469  		d := v_1.AuxInt
  8470  		ptr := v_1.Args[0]
  8471  		val := v.Args[2]
  8472  		v.reset(Op386MOVLstoreidx1)
  8473  		v.AuxInt = int64(int32(c + d))
  8474  		v.Aux = sym
  8475  		v.AddArg(ptr)
  8476  		v.AddArg(idx)
  8477  		v.AddArg(val)
  8478  		v.AddArg(mem)
  8479  		return true
  8480  	}
  8481  	// match: (MOVLstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem)
  8482  	// cond:
  8483  	// result: (MOVLstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  8484  	for {
  8485  		c := v.AuxInt
  8486  		sym := v.Aux
  8487  		mem := v.Args[3]
  8488  		ptr := v.Args[0]
  8489  		v_1 := v.Args[1]
  8490  		if v_1.Op != Op386ADDLconst {
  8491  			break
  8492  		}
  8493  		d := v_1.AuxInt
  8494  		idx := v_1.Args[0]
  8495  		val := v.Args[2]
  8496  		v.reset(Op386MOVLstoreidx1)
  8497  		v.AuxInt = int64(int32(c + d))
  8498  		v.Aux = sym
  8499  		v.AddArg(ptr)
  8500  		v.AddArg(idx)
  8501  		v.AddArg(val)
  8502  		v.AddArg(mem)
  8503  		return true
  8504  	}
  8505  	// match: (MOVLstoreidx1 [c] {sym} (ADDLconst [d] idx) ptr val mem)
  8506  	// cond:
  8507  	// result: (MOVLstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  8508  	for {
  8509  		c := v.AuxInt
  8510  		sym := v.Aux
  8511  		mem := v.Args[3]
  8512  		v_0 := v.Args[0]
  8513  		if v_0.Op != Op386ADDLconst {
  8514  			break
  8515  		}
  8516  		d := v_0.AuxInt
  8517  		idx := v_0.Args[0]
  8518  		ptr := v.Args[1]
  8519  		val := v.Args[2]
  8520  		v.reset(Op386MOVLstoreidx1)
  8521  		v.AuxInt = int64(int32(c + d))
  8522  		v.Aux = sym
  8523  		v.AddArg(ptr)
  8524  		v.AddArg(idx)
  8525  		v.AddArg(val)
  8526  		v.AddArg(mem)
  8527  		return true
  8528  	}
  8529  	return false
  8530  }
  8531  func rewriteValue386_Op386MOVLstoreidx4_0(v *Value) bool {
  8532  	// match: (MOVLstoreidx4 [c] {sym} (ADDLconst [d] ptr) idx val mem)
  8533  	// cond:
  8534  	// result: (MOVLstoreidx4 [int64(int32(c+d))] {sym} ptr idx val mem)
  8535  	for {
  8536  		c := v.AuxInt
  8537  		sym := v.Aux
  8538  		mem := v.Args[3]
  8539  		v_0 := v.Args[0]
  8540  		if v_0.Op != Op386ADDLconst {
  8541  			break
  8542  		}
  8543  		d := v_0.AuxInt
  8544  		ptr := v_0.Args[0]
  8545  		idx := v.Args[1]
  8546  		val := v.Args[2]
  8547  		v.reset(Op386MOVLstoreidx4)
  8548  		v.AuxInt = int64(int32(c + d))
  8549  		v.Aux = sym
  8550  		v.AddArg(ptr)
  8551  		v.AddArg(idx)
  8552  		v.AddArg(val)
  8553  		v.AddArg(mem)
  8554  		return true
  8555  	}
  8556  	// match: (MOVLstoreidx4 [c] {sym} ptr (ADDLconst [d] idx) val mem)
  8557  	// cond:
  8558  	// result: (MOVLstoreidx4 [int64(int32(c+4*d))] {sym} ptr idx val mem)
  8559  	for {
  8560  		c := v.AuxInt
  8561  		sym := v.Aux
  8562  		mem := v.Args[3]
  8563  		ptr := v.Args[0]
  8564  		v_1 := v.Args[1]
  8565  		if v_1.Op != Op386ADDLconst {
  8566  			break
  8567  		}
  8568  		d := v_1.AuxInt
  8569  		idx := v_1.Args[0]
  8570  		val := v.Args[2]
  8571  		v.reset(Op386MOVLstoreidx4)
  8572  		v.AuxInt = int64(int32(c + 4*d))
  8573  		v.Aux = sym
  8574  		v.AddArg(ptr)
  8575  		v.AddArg(idx)
  8576  		v.AddArg(val)
  8577  		v.AddArg(mem)
  8578  		return true
  8579  	}
  8580  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDLloadidx4 x [off] {sym} ptr idx mem) mem)
  8581  	// cond: y.Uses==1 && clobber(y)
  8582  	// result: (ADDLmodifyidx4 [off] {sym} ptr idx x mem)
  8583  	for {
  8584  		off := v.AuxInt
  8585  		sym := v.Aux
  8586  		mem := v.Args[3]
  8587  		ptr := v.Args[0]
  8588  		idx := v.Args[1]
  8589  		y := v.Args[2]
  8590  		if y.Op != Op386ADDLloadidx4 {
  8591  			break
  8592  		}
  8593  		if y.AuxInt != off {
  8594  			break
  8595  		}
  8596  		if y.Aux != sym {
  8597  			break
  8598  		}
  8599  		_ = y.Args[3]
  8600  		x := y.Args[0]
  8601  		if ptr != y.Args[1] {
  8602  			break
  8603  		}
  8604  		if idx != y.Args[2] {
  8605  			break
  8606  		}
  8607  		if mem != y.Args[3] {
  8608  			break
  8609  		}
  8610  		if !(y.Uses == 1 && clobber(y)) {
  8611  			break
  8612  		}
  8613  		v.reset(Op386ADDLmodifyidx4)
  8614  		v.AuxInt = off
  8615  		v.Aux = sym
  8616  		v.AddArg(ptr)
  8617  		v.AddArg(idx)
  8618  		v.AddArg(x)
  8619  		v.AddArg(mem)
  8620  		return true
  8621  	}
  8622  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDLloadidx4 x [off] {sym} ptr idx mem) mem)
  8623  	// cond: y.Uses==1 && clobber(y)
  8624  	// result: (ANDLmodifyidx4 [off] {sym} ptr idx x mem)
  8625  	for {
  8626  		off := v.AuxInt
  8627  		sym := v.Aux
  8628  		mem := v.Args[3]
  8629  		ptr := v.Args[0]
  8630  		idx := v.Args[1]
  8631  		y := v.Args[2]
  8632  		if y.Op != Op386ANDLloadidx4 {
  8633  			break
  8634  		}
  8635  		if y.AuxInt != off {
  8636  			break
  8637  		}
  8638  		if y.Aux != sym {
  8639  			break
  8640  		}
  8641  		_ = y.Args[3]
  8642  		x := y.Args[0]
  8643  		if ptr != y.Args[1] {
  8644  			break
  8645  		}
  8646  		if idx != y.Args[2] {
  8647  			break
  8648  		}
  8649  		if mem != y.Args[3] {
  8650  			break
  8651  		}
  8652  		if !(y.Uses == 1 && clobber(y)) {
  8653  			break
  8654  		}
  8655  		v.reset(Op386ANDLmodifyidx4)
  8656  		v.AuxInt = off
  8657  		v.Aux = sym
  8658  		v.AddArg(ptr)
  8659  		v.AddArg(idx)
  8660  		v.AddArg(x)
  8661  		v.AddArg(mem)
  8662  		return true
  8663  	}
  8664  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORLloadidx4 x [off] {sym} ptr idx mem) mem)
  8665  	// cond: y.Uses==1 && clobber(y)
  8666  	// result: (ORLmodifyidx4 [off] {sym} ptr idx x mem)
  8667  	for {
  8668  		off := v.AuxInt
  8669  		sym := v.Aux
  8670  		mem := v.Args[3]
  8671  		ptr := v.Args[0]
  8672  		idx := v.Args[1]
  8673  		y := v.Args[2]
  8674  		if y.Op != Op386ORLloadidx4 {
  8675  			break
  8676  		}
  8677  		if y.AuxInt != off {
  8678  			break
  8679  		}
  8680  		if y.Aux != sym {
  8681  			break
  8682  		}
  8683  		_ = y.Args[3]
  8684  		x := y.Args[0]
  8685  		if ptr != y.Args[1] {
  8686  			break
  8687  		}
  8688  		if idx != y.Args[2] {
  8689  			break
  8690  		}
  8691  		if mem != y.Args[3] {
  8692  			break
  8693  		}
  8694  		if !(y.Uses == 1 && clobber(y)) {
  8695  			break
  8696  		}
  8697  		v.reset(Op386ORLmodifyidx4)
  8698  		v.AuxInt = off
  8699  		v.Aux = sym
  8700  		v.AddArg(ptr)
  8701  		v.AddArg(idx)
  8702  		v.AddArg(x)
  8703  		v.AddArg(mem)
  8704  		return true
  8705  	}
  8706  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORLloadidx4 x [off] {sym} ptr idx mem) mem)
  8707  	// cond: y.Uses==1 && clobber(y)
  8708  	// result: (XORLmodifyidx4 [off] {sym} ptr idx x mem)
  8709  	for {
  8710  		off := v.AuxInt
  8711  		sym := v.Aux
  8712  		mem := v.Args[3]
  8713  		ptr := v.Args[0]
  8714  		idx := v.Args[1]
  8715  		y := v.Args[2]
  8716  		if y.Op != Op386XORLloadidx4 {
  8717  			break
  8718  		}
  8719  		if y.AuxInt != off {
  8720  			break
  8721  		}
  8722  		if y.Aux != sym {
  8723  			break
  8724  		}
  8725  		_ = y.Args[3]
  8726  		x := y.Args[0]
  8727  		if ptr != y.Args[1] {
  8728  			break
  8729  		}
  8730  		if idx != y.Args[2] {
  8731  			break
  8732  		}
  8733  		if mem != y.Args[3] {
  8734  			break
  8735  		}
  8736  		if !(y.Uses == 1 && clobber(y)) {
  8737  			break
  8738  		}
  8739  		v.reset(Op386XORLmodifyidx4)
  8740  		v.AuxInt = off
  8741  		v.Aux = sym
  8742  		v.AddArg(ptr)
  8743  		v.AddArg(idx)
  8744  		v.AddArg(x)
  8745  		v.AddArg(mem)
  8746  		return true
  8747  	}
  8748  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem)
  8749  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  8750  	// result: (ADDLmodifyidx4 [off] {sym} ptr idx x mem)
  8751  	for {
  8752  		off := v.AuxInt
  8753  		sym := v.Aux
  8754  		mem := v.Args[3]
  8755  		ptr := v.Args[0]
  8756  		idx := v.Args[1]
  8757  		y := v.Args[2]
  8758  		if y.Op != Op386ADDL {
  8759  			break
  8760  		}
  8761  		x := y.Args[1]
  8762  		l := y.Args[0]
  8763  		if l.Op != Op386MOVLloadidx4 {
  8764  			break
  8765  		}
  8766  		if l.AuxInt != off {
  8767  			break
  8768  		}
  8769  		if l.Aux != sym {
  8770  			break
  8771  		}
  8772  		_ = l.Args[2]
  8773  		if ptr != l.Args[0] {
  8774  			break
  8775  		}
  8776  		if idx != l.Args[1] {
  8777  			break
  8778  		}
  8779  		if mem != l.Args[2] {
  8780  			break
  8781  		}
  8782  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  8783  			break
  8784  		}
  8785  		v.reset(Op386ADDLmodifyidx4)
  8786  		v.AuxInt = off
  8787  		v.Aux = sym
  8788  		v.AddArg(ptr)
  8789  		v.AddArg(idx)
  8790  		v.AddArg(x)
  8791  		v.AddArg(mem)
  8792  		return true
  8793  	}
  8794  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
  8795  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  8796  	// result: (ADDLmodifyidx4 [off] {sym} ptr idx x mem)
  8797  	for {
  8798  		off := v.AuxInt
  8799  		sym := v.Aux
  8800  		mem := v.Args[3]
  8801  		ptr := v.Args[0]
  8802  		idx := v.Args[1]
  8803  		y := v.Args[2]
  8804  		if y.Op != Op386ADDL {
  8805  			break
  8806  		}
  8807  		_ = y.Args[1]
  8808  		x := y.Args[0]
  8809  		l := y.Args[1]
  8810  		if l.Op != Op386MOVLloadidx4 {
  8811  			break
  8812  		}
  8813  		if l.AuxInt != off {
  8814  			break
  8815  		}
  8816  		if l.Aux != sym {
  8817  			break
  8818  		}
  8819  		_ = l.Args[2]
  8820  		if ptr != l.Args[0] {
  8821  			break
  8822  		}
  8823  		if idx != l.Args[1] {
  8824  			break
  8825  		}
  8826  		if mem != l.Args[2] {
  8827  			break
  8828  		}
  8829  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  8830  			break
  8831  		}
  8832  		v.reset(Op386ADDLmodifyidx4)
  8833  		v.AuxInt = off
  8834  		v.Aux = sym
  8835  		v.AddArg(ptr)
  8836  		v.AddArg(idx)
  8837  		v.AddArg(x)
  8838  		v.AddArg(mem)
  8839  		return true
  8840  	}
  8841  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(SUBL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem)
  8842  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  8843  	// result: (SUBLmodifyidx4 [off] {sym} ptr idx x mem)
  8844  	for {
  8845  		off := v.AuxInt
  8846  		sym := v.Aux
  8847  		mem := v.Args[3]
  8848  		ptr := v.Args[0]
  8849  		idx := v.Args[1]
  8850  		y := v.Args[2]
  8851  		if y.Op != Op386SUBL {
  8852  			break
  8853  		}
  8854  		x := y.Args[1]
  8855  		l := y.Args[0]
  8856  		if l.Op != Op386MOVLloadidx4 {
  8857  			break
  8858  		}
  8859  		if l.AuxInt != off {
  8860  			break
  8861  		}
  8862  		if l.Aux != sym {
  8863  			break
  8864  		}
  8865  		_ = l.Args[2]
  8866  		if ptr != l.Args[0] {
  8867  			break
  8868  		}
  8869  		if idx != l.Args[1] {
  8870  			break
  8871  		}
  8872  		if mem != l.Args[2] {
  8873  			break
  8874  		}
  8875  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  8876  			break
  8877  		}
  8878  		v.reset(Op386SUBLmodifyidx4)
  8879  		v.AuxInt = off
  8880  		v.Aux = sym
  8881  		v.AddArg(ptr)
  8882  		v.AddArg(idx)
  8883  		v.AddArg(x)
  8884  		v.AddArg(mem)
  8885  		return true
  8886  	}
  8887  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem)
  8888  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  8889  	// result: (ANDLmodifyidx4 [off] {sym} ptr idx x mem)
  8890  	for {
  8891  		off := v.AuxInt
  8892  		sym := v.Aux
  8893  		mem := v.Args[3]
  8894  		ptr := v.Args[0]
  8895  		idx := v.Args[1]
  8896  		y := v.Args[2]
  8897  		if y.Op != Op386ANDL {
  8898  			break
  8899  		}
  8900  		x := y.Args[1]
  8901  		l := y.Args[0]
  8902  		if l.Op != Op386MOVLloadidx4 {
  8903  			break
  8904  		}
  8905  		if l.AuxInt != off {
  8906  			break
  8907  		}
  8908  		if l.Aux != sym {
  8909  			break
  8910  		}
  8911  		_ = l.Args[2]
  8912  		if ptr != l.Args[0] {
  8913  			break
  8914  		}
  8915  		if idx != l.Args[1] {
  8916  			break
  8917  		}
  8918  		if mem != l.Args[2] {
  8919  			break
  8920  		}
  8921  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  8922  			break
  8923  		}
  8924  		v.reset(Op386ANDLmodifyidx4)
  8925  		v.AuxInt = off
  8926  		v.Aux = sym
  8927  		v.AddArg(ptr)
  8928  		v.AddArg(idx)
  8929  		v.AddArg(x)
  8930  		v.AddArg(mem)
  8931  		return true
  8932  	}
  8933  	return false
  8934  }
  8935  func rewriteValue386_Op386MOVLstoreidx4_10(v *Value) bool {
  8936  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
  8937  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  8938  	// result: (ANDLmodifyidx4 [off] {sym} ptr idx x mem)
  8939  	for {
  8940  		off := v.AuxInt
  8941  		sym := v.Aux
  8942  		mem := v.Args[3]
  8943  		ptr := v.Args[0]
  8944  		idx := v.Args[1]
  8945  		y := v.Args[2]
  8946  		if y.Op != Op386ANDL {
  8947  			break
  8948  		}
  8949  		_ = y.Args[1]
  8950  		x := y.Args[0]
  8951  		l := y.Args[1]
  8952  		if l.Op != Op386MOVLloadidx4 {
  8953  			break
  8954  		}
  8955  		if l.AuxInt != off {
  8956  			break
  8957  		}
  8958  		if l.Aux != sym {
  8959  			break
  8960  		}
  8961  		_ = l.Args[2]
  8962  		if ptr != l.Args[0] {
  8963  			break
  8964  		}
  8965  		if idx != l.Args[1] {
  8966  			break
  8967  		}
  8968  		if mem != l.Args[2] {
  8969  			break
  8970  		}
  8971  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  8972  			break
  8973  		}
  8974  		v.reset(Op386ANDLmodifyidx4)
  8975  		v.AuxInt = off
  8976  		v.Aux = sym
  8977  		v.AddArg(ptr)
  8978  		v.AddArg(idx)
  8979  		v.AddArg(x)
  8980  		v.AddArg(mem)
  8981  		return true
  8982  	}
  8983  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem)
  8984  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  8985  	// result: (ORLmodifyidx4 [off] {sym} ptr idx x mem)
  8986  	for {
  8987  		off := v.AuxInt
  8988  		sym := v.Aux
  8989  		mem := v.Args[3]
  8990  		ptr := v.Args[0]
  8991  		idx := v.Args[1]
  8992  		y := v.Args[2]
  8993  		if y.Op != Op386ORL {
  8994  			break
  8995  		}
  8996  		x := y.Args[1]
  8997  		l := y.Args[0]
  8998  		if l.Op != Op386MOVLloadidx4 {
  8999  			break
  9000  		}
  9001  		if l.AuxInt != off {
  9002  			break
  9003  		}
  9004  		if l.Aux != sym {
  9005  			break
  9006  		}
  9007  		_ = l.Args[2]
  9008  		if ptr != l.Args[0] {
  9009  			break
  9010  		}
  9011  		if idx != l.Args[1] {
  9012  			break
  9013  		}
  9014  		if mem != l.Args[2] {
  9015  			break
  9016  		}
  9017  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  9018  			break
  9019  		}
  9020  		v.reset(Op386ORLmodifyidx4)
  9021  		v.AuxInt = off
  9022  		v.Aux = sym
  9023  		v.AddArg(ptr)
  9024  		v.AddArg(idx)
  9025  		v.AddArg(x)
  9026  		v.AddArg(mem)
  9027  		return true
  9028  	}
  9029  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
  9030  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  9031  	// result: (ORLmodifyidx4 [off] {sym} ptr idx x mem)
  9032  	for {
  9033  		off := v.AuxInt
  9034  		sym := v.Aux
  9035  		mem := v.Args[3]
  9036  		ptr := v.Args[0]
  9037  		idx := v.Args[1]
  9038  		y := v.Args[2]
  9039  		if y.Op != Op386ORL {
  9040  			break
  9041  		}
  9042  		_ = y.Args[1]
  9043  		x := y.Args[0]
  9044  		l := y.Args[1]
  9045  		if l.Op != Op386MOVLloadidx4 {
  9046  			break
  9047  		}
  9048  		if l.AuxInt != off {
  9049  			break
  9050  		}
  9051  		if l.Aux != sym {
  9052  			break
  9053  		}
  9054  		_ = l.Args[2]
  9055  		if ptr != l.Args[0] {
  9056  			break
  9057  		}
  9058  		if idx != l.Args[1] {
  9059  			break
  9060  		}
  9061  		if mem != l.Args[2] {
  9062  			break
  9063  		}
  9064  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  9065  			break
  9066  		}
  9067  		v.reset(Op386ORLmodifyidx4)
  9068  		v.AuxInt = off
  9069  		v.Aux = sym
  9070  		v.AddArg(ptr)
  9071  		v.AddArg(idx)
  9072  		v.AddArg(x)
  9073  		v.AddArg(mem)
  9074  		return true
  9075  	}
  9076  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem)
  9077  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  9078  	// result: (XORLmodifyidx4 [off] {sym} ptr idx x mem)
  9079  	for {
  9080  		off := v.AuxInt
  9081  		sym := v.Aux
  9082  		mem := v.Args[3]
  9083  		ptr := v.Args[0]
  9084  		idx := v.Args[1]
  9085  		y := v.Args[2]
  9086  		if y.Op != Op386XORL {
  9087  			break
  9088  		}
  9089  		x := y.Args[1]
  9090  		l := y.Args[0]
  9091  		if l.Op != Op386MOVLloadidx4 {
  9092  			break
  9093  		}
  9094  		if l.AuxInt != off {
  9095  			break
  9096  		}
  9097  		if l.Aux != sym {
  9098  			break
  9099  		}
  9100  		_ = l.Args[2]
  9101  		if ptr != l.Args[0] {
  9102  			break
  9103  		}
  9104  		if idx != l.Args[1] {
  9105  			break
  9106  		}
  9107  		if mem != l.Args[2] {
  9108  			break
  9109  		}
  9110  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  9111  			break
  9112  		}
  9113  		v.reset(Op386XORLmodifyidx4)
  9114  		v.AuxInt = off
  9115  		v.Aux = sym
  9116  		v.AddArg(ptr)
  9117  		v.AddArg(idx)
  9118  		v.AddArg(x)
  9119  		v.AddArg(mem)
  9120  		return true
  9121  	}
  9122  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
  9123  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  9124  	// result: (XORLmodifyidx4 [off] {sym} ptr idx x mem)
  9125  	for {
  9126  		off := v.AuxInt
  9127  		sym := v.Aux
  9128  		mem := v.Args[3]
  9129  		ptr := v.Args[0]
  9130  		idx := v.Args[1]
  9131  		y := v.Args[2]
  9132  		if y.Op != Op386XORL {
  9133  			break
  9134  		}
  9135  		_ = y.Args[1]
  9136  		x := y.Args[0]
  9137  		l := y.Args[1]
  9138  		if l.Op != Op386MOVLloadidx4 {
  9139  			break
  9140  		}
  9141  		if l.AuxInt != off {
  9142  			break
  9143  		}
  9144  		if l.Aux != sym {
  9145  			break
  9146  		}
  9147  		_ = l.Args[2]
  9148  		if ptr != l.Args[0] {
  9149  			break
  9150  		}
  9151  		if idx != l.Args[1] {
  9152  			break
  9153  		}
  9154  		if mem != l.Args[2] {
  9155  			break
  9156  		}
  9157  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  9158  			break
  9159  		}
  9160  		v.reset(Op386XORLmodifyidx4)
  9161  		v.AuxInt = off
  9162  		v.Aux = sym
  9163  		v.AddArg(ptr)
  9164  		v.AddArg(idx)
  9165  		v.AddArg(x)
  9166  		v.AddArg(mem)
  9167  		return true
  9168  	}
  9169  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
  9170  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off)
  9171  	// result: (ADDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem)
  9172  	for {
  9173  		off := v.AuxInt
  9174  		sym := v.Aux
  9175  		mem := v.Args[3]
  9176  		ptr := v.Args[0]
  9177  		idx := v.Args[1]
  9178  		y := v.Args[2]
  9179  		if y.Op != Op386ADDLconst {
  9180  			break
  9181  		}
  9182  		c := y.AuxInt
  9183  		l := y.Args[0]
  9184  		if l.Op != Op386MOVLloadidx4 {
  9185  			break
  9186  		}
  9187  		if l.AuxInt != off {
  9188  			break
  9189  		}
  9190  		if l.Aux != sym {
  9191  			break
  9192  		}
  9193  		_ = l.Args[2]
  9194  		if ptr != l.Args[0] {
  9195  			break
  9196  		}
  9197  		if idx != l.Args[1] {
  9198  			break
  9199  		}
  9200  		if mem != l.Args[2] {
  9201  			break
  9202  		}
  9203  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) {
  9204  			break
  9205  		}
  9206  		v.reset(Op386ADDLconstmodifyidx4)
  9207  		v.AuxInt = makeValAndOff(c, off)
  9208  		v.Aux = sym
  9209  		v.AddArg(ptr)
  9210  		v.AddArg(idx)
  9211  		v.AddArg(mem)
  9212  		return true
  9213  	}
  9214  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
  9215  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off)
  9216  	// result: (ANDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem)
  9217  	for {
  9218  		off := v.AuxInt
  9219  		sym := v.Aux
  9220  		mem := v.Args[3]
  9221  		ptr := v.Args[0]
  9222  		idx := v.Args[1]
  9223  		y := v.Args[2]
  9224  		if y.Op != Op386ANDLconst {
  9225  			break
  9226  		}
  9227  		c := y.AuxInt
  9228  		l := y.Args[0]
  9229  		if l.Op != Op386MOVLloadidx4 {
  9230  			break
  9231  		}
  9232  		if l.AuxInt != off {
  9233  			break
  9234  		}
  9235  		if l.Aux != sym {
  9236  			break
  9237  		}
  9238  		_ = l.Args[2]
  9239  		if ptr != l.Args[0] {
  9240  			break
  9241  		}
  9242  		if idx != l.Args[1] {
  9243  			break
  9244  		}
  9245  		if mem != l.Args[2] {
  9246  			break
  9247  		}
  9248  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) {
  9249  			break
  9250  		}
  9251  		v.reset(Op386ANDLconstmodifyidx4)
  9252  		v.AuxInt = makeValAndOff(c, off)
  9253  		v.Aux = sym
  9254  		v.AddArg(ptr)
  9255  		v.AddArg(idx)
  9256  		v.AddArg(mem)
  9257  		return true
  9258  	}
  9259  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
  9260  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off)
  9261  	// result: (ORLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem)
  9262  	for {
  9263  		off := v.AuxInt
  9264  		sym := v.Aux
  9265  		mem := v.Args[3]
  9266  		ptr := v.Args[0]
  9267  		idx := v.Args[1]
  9268  		y := v.Args[2]
  9269  		if y.Op != Op386ORLconst {
  9270  			break
  9271  		}
  9272  		c := y.AuxInt
  9273  		l := y.Args[0]
  9274  		if l.Op != Op386MOVLloadidx4 {
  9275  			break
  9276  		}
  9277  		if l.AuxInt != off {
  9278  			break
  9279  		}
  9280  		if l.Aux != sym {
  9281  			break
  9282  		}
  9283  		_ = l.Args[2]
  9284  		if ptr != l.Args[0] {
  9285  			break
  9286  		}
  9287  		if idx != l.Args[1] {
  9288  			break
  9289  		}
  9290  		if mem != l.Args[2] {
  9291  			break
  9292  		}
  9293  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) {
  9294  			break
  9295  		}
  9296  		v.reset(Op386ORLconstmodifyidx4)
  9297  		v.AuxInt = makeValAndOff(c, off)
  9298  		v.Aux = sym
  9299  		v.AddArg(ptr)
  9300  		v.AddArg(idx)
  9301  		v.AddArg(mem)
  9302  		return true
  9303  	}
  9304  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
  9305  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off)
  9306  	// result: (XORLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem)
  9307  	for {
  9308  		off := v.AuxInt
  9309  		sym := v.Aux
  9310  		mem := v.Args[3]
  9311  		ptr := v.Args[0]
  9312  		idx := v.Args[1]
  9313  		y := v.Args[2]
  9314  		if y.Op != Op386XORLconst {
  9315  			break
  9316  		}
  9317  		c := y.AuxInt
  9318  		l := y.Args[0]
  9319  		if l.Op != Op386MOVLloadidx4 {
  9320  			break
  9321  		}
  9322  		if l.AuxInt != off {
  9323  			break
  9324  		}
  9325  		if l.Aux != sym {
  9326  			break
  9327  		}
  9328  		_ = l.Args[2]
  9329  		if ptr != l.Args[0] {
  9330  			break
  9331  		}
  9332  		if idx != l.Args[1] {
  9333  			break
  9334  		}
  9335  		if mem != l.Args[2] {
  9336  			break
  9337  		}
  9338  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) {
  9339  			break
  9340  		}
  9341  		v.reset(Op386XORLconstmodifyidx4)
  9342  		v.AuxInt = makeValAndOff(c, off)
  9343  		v.Aux = sym
  9344  		v.AddArg(ptr)
  9345  		v.AddArg(idx)
  9346  		v.AddArg(mem)
  9347  		return true
  9348  	}
  9349  	return false
  9350  }
  9351  func rewriteValue386_Op386MOVSDconst_0(v *Value) bool {
  9352  	b := v.Block
  9353  	config := b.Func.Config
  9354  	typ := &b.Func.Config.Types
  9355  	// match: (MOVSDconst [c])
  9356  	// cond: config.ctxt.Flag_shared
  9357  	// result: (MOVSDconst2 (MOVSDconst1 [c]))
  9358  	for {
  9359  		c := v.AuxInt
  9360  		if !(config.ctxt.Flag_shared) {
  9361  			break
  9362  		}
  9363  		v.reset(Op386MOVSDconst2)
  9364  		v0 := b.NewValue0(v.Pos, Op386MOVSDconst1, typ.UInt32)
  9365  		v0.AuxInt = c
  9366  		v.AddArg(v0)
  9367  		return true
  9368  	}
  9369  	return false
  9370  }
  9371  func rewriteValue386_Op386MOVSDload_0(v *Value) bool {
  9372  	b := v.Block
  9373  	config := b.Func.Config
  9374  	// match: (MOVSDload [off1] {sym} (ADDLconst [off2] ptr) mem)
  9375  	// cond: is32Bit(off1+off2)
  9376  	// result: (MOVSDload [off1+off2] {sym} ptr mem)
  9377  	for {
  9378  		off1 := v.AuxInt
  9379  		sym := v.Aux
  9380  		mem := v.Args[1]
  9381  		v_0 := v.Args[0]
  9382  		if v_0.Op != Op386ADDLconst {
  9383  			break
  9384  		}
  9385  		off2 := v_0.AuxInt
  9386  		ptr := v_0.Args[0]
  9387  		if !(is32Bit(off1 + off2)) {
  9388  			break
  9389  		}
  9390  		v.reset(Op386MOVSDload)
  9391  		v.AuxInt = off1 + off2
  9392  		v.Aux = sym
  9393  		v.AddArg(ptr)
  9394  		v.AddArg(mem)
  9395  		return true
  9396  	}
  9397  	// match: (MOVSDload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
  9398  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  9399  	// result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem)
  9400  	for {
  9401  		off1 := v.AuxInt
  9402  		sym1 := v.Aux
  9403  		mem := v.Args[1]
  9404  		v_0 := v.Args[0]
  9405  		if v_0.Op != Op386LEAL {
  9406  			break
  9407  		}
  9408  		off2 := v_0.AuxInt
  9409  		sym2 := v_0.Aux
  9410  		base := v_0.Args[0]
  9411  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  9412  			break
  9413  		}
  9414  		v.reset(Op386MOVSDload)
  9415  		v.AuxInt = off1 + off2
  9416  		v.Aux = mergeSym(sym1, sym2)
  9417  		v.AddArg(base)
  9418  		v.AddArg(mem)
  9419  		return true
  9420  	}
  9421  	// match: (MOVSDload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem)
  9422  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  9423  	// result: (MOVSDloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
  9424  	for {
  9425  		off1 := v.AuxInt
  9426  		sym1 := v.Aux
  9427  		mem := v.Args[1]
  9428  		v_0 := v.Args[0]
  9429  		if v_0.Op != Op386LEAL1 {
  9430  			break
  9431  		}
  9432  		off2 := v_0.AuxInt
  9433  		sym2 := v_0.Aux
  9434  		idx := v_0.Args[1]
  9435  		ptr := v_0.Args[0]
  9436  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  9437  			break
  9438  		}
  9439  		v.reset(Op386MOVSDloadidx1)
  9440  		v.AuxInt = off1 + off2
  9441  		v.Aux = mergeSym(sym1, sym2)
  9442  		v.AddArg(ptr)
  9443  		v.AddArg(idx)
  9444  		v.AddArg(mem)
  9445  		return true
  9446  	}
  9447  	// match: (MOVSDload [off1] {sym1} (LEAL8 [off2] {sym2} ptr idx) mem)
  9448  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  9449  	// result: (MOVSDloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
  9450  	for {
  9451  		off1 := v.AuxInt
  9452  		sym1 := v.Aux
  9453  		mem := v.Args[1]
  9454  		v_0 := v.Args[0]
  9455  		if v_0.Op != Op386LEAL8 {
  9456  			break
  9457  		}
  9458  		off2 := v_0.AuxInt
  9459  		sym2 := v_0.Aux
  9460  		idx := v_0.Args[1]
  9461  		ptr := v_0.Args[0]
  9462  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  9463  			break
  9464  		}
  9465  		v.reset(Op386MOVSDloadidx8)
  9466  		v.AuxInt = off1 + off2
  9467  		v.Aux = mergeSym(sym1, sym2)
  9468  		v.AddArg(ptr)
  9469  		v.AddArg(idx)
  9470  		v.AddArg(mem)
  9471  		return true
  9472  	}
  9473  	// match: (MOVSDload [off] {sym} (ADDL ptr idx) mem)
  9474  	// cond: ptr.Op != OpSB
  9475  	// result: (MOVSDloadidx1 [off] {sym} ptr idx mem)
  9476  	for {
  9477  		off := v.AuxInt
  9478  		sym := v.Aux
  9479  		mem := v.Args[1]
  9480  		v_0 := v.Args[0]
  9481  		if v_0.Op != Op386ADDL {
  9482  			break
  9483  		}
  9484  		idx := v_0.Args[1]
  9485  		ptr := v_0.Args[0]
  9486  		if !(ptr.Op != OpSB) {
  9487  			break
  9488  		}
  9489  		v.reset(Op386MOVSDloadidx1)
  9490  		v.AuxInt = off
  9491  		v.Aux = sym
  9492  		v.AddArg(ptr)
  9493  		v.AddArg(idx)
  9494  		v.AddArg(mem)
  9495  		return true
  9496  	}
  9497  	return false
  9498  }
  9499  func rewriteValue386_Op386MOVSDloadidx1_0(v *Value) bool {
  9500  	// match: (MOVSDloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem)
  9501  	// cond:
  9502  	// result: (MOVSDloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  9503  	for {
  9504  		c := v.AuxInt
  9505  		sym := v.Aux
  9506  		mem := v.Args[2]
  9507  		v_0 := v.Args[0]
  9508  		if v_0.Op != Op386ADDLconst {
  9509  			break
  9510  		}
  9511  		d := v_0.AuxInt
  9512  		ptr := v_0.Args[0]
  9513  		idx := v.Args[1]
  9514  		v.reset(Op386MOVSDloadidx1)
  9515  		v.AuxInt = int64(int32(c + d))
  9516  		v.Aux = sym
  9517  		v.AddArg(ptr)
  9518  		v.AddArg(idx)
  9519  		v.AddArg(mem)
  9520  		return true
  9521  	}
  9522  	// match: (MOVSDloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem)
  9523  	// cond:
  9524  	// result: (MOVSDloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  9525  	for {
  9526  		c := v.AuxInt
  9527  		sym := v.Aux
  9528  		mem := v.Args[2]
  9529  		ptr := v.Args[0]
  9530  		v_1 := v.Args[1]
  9531  		if v_1.Op != Op386ADDLconst {
  9532  			break
  9533  		}
  9534  		d := v_1.AuxInt
  9535  		idx := v_1.Args[0]
  9536  		v.reset(Op386MOVSDloadidx1)
  9537  		v.AuxInt = int64(int32(c + d))
  9538  		v.Aux = sym
  9539  		v.AddArg(ptr)
  9540  		v.AddArg(idx)
  9541  		v.AddArg(mem)
  9542  		return true
  9543  	}
  9544  	return false
  9545  }
  9546  func rewriteValue386_Op386MOVSDloadidx8_0(v *Value) bool {
  9547  	// match: (MOVSDloadidx8 [c] {sym} (ADDLconst [d] ptr) idx mem)
  9548  	// cond:
  9549  	// result: (MOVSDloadidx8 [int64(int32(c+d))] {sym} ptr idx mem)
  9550  	for {
  9551  		c := v.AuxInt
  9552  		sym := v.Aux
  9553  		mem := v.Args[2]
  9554  		v_0 := v.Args[0]
  9555  		if v_0.Op != Op386ADDLconst {
  9556  			break
  9557  		}
  9558  		d := v_0.AuxInt
  9559  		ptr := v_0.Args[0]
  9560  		idx := v.Args[1]
  9561  		v.reset(Op386MOVSDloadidx8)
  9562  		v.AuxInt = int64(int32(c + d))
  9563  		v.Aux = sym
  9564  		v.AddArg(ptr)
  9565  		v.AddArg(idx)
  9566  		v.AddArg(mem)
  9567  		return true
  9568  	}
  9569  	// match: (MOVSDloadidx8 [c] {sym} ptr (ADDLconst [d] idx) mem)
  9570  	// cond:
  9571  	// result: (MOVSDloadidx8 [int64(int32(c+8*d))] {sym} ptr idx mem)
  9572  	for {
  9573  		c := v.AuxInt
  9574  		sym := v.Aux
  9575  		mem := v.Args[2]
  9576  		ptr := v.Args[0]
  9577  		v_1 := v.Args[1]
  9578  		if v_1.Op != Op386ADDLconst {
  9579  			break
  9580  		}
  9581  		d := v_1.AuxInt
  9582  		idx := v_1.Args[0]
  9583  		v.reset(Op386MOVSDloadidx8)
  9584  		v.AuxInt = int64(int32(c + 8*d))
  9585  		v.Aux = sym
  9586  		v.AddArg(ptr)
  9587  		v.AddArg(idx)
  9588  		v.AddArg(mem)
  9589  		return true
  9590  	}
  9591  	return false
  9592  }
  9593  func rewriteValue386_Op386MOVSDstore_0(v *Value) bool {
  9594  	b := v.Block
  9595  	config := b.Func.Config
  9596  	// match: (MOVSDstore [off1] {sym} (ADDLconst [off2] ptr) val mem)
  9597  	// cond: is32Bit(off1+off2)
  9598  	// result: (MOVSDstore [off1+off2] {sym} ptr val mem)
  9599  	for {
  9600  		off1 := v.AuxInt
  9601  		sym := v.Aux
  9602  		mem := v.Args[2]
  9603  		v_0 := v.Args[0]
  9604  		if v_0.Op != Op386ADDLconst {
  9605  			break
  9606  		}
  9607  		off2 := v_0.AuxInt
  9608  		ptr := v_0.Args[0]
  9609  		val := v.Args[1]
  9610  		if !(is32Bit(off1 + off2)) {
  9611  			break
  9612  		}
  9613  		v.reset(Op386MOVSDstore)
  9614  		v.AuxInt = off1 + off2
  9615  		v.Aux = sym
  9616  		v.AddArg(ptr)
  9617  		v.AddArg(val)
  9618  		v.AddArg(mem)
  9619  		return true
  9620  	}
  9621  	// match: (MOVSDstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
  9622  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  9623  	// result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  9624  	for {
  9625  		off1 := v.AuxInt
  9626  		sym1 := v.Aux
  9627  		mem := v.Args[2]
  9628  		v_0 := v.Args[0]
  9629  		if v_0.Op != Op386LEAL {
  9630  			break
  9631  		}
  9632  		off2 := v_0.AuxInt
  9633  		sym2 := v_0.Aux
  9634  		base := v_0.Args[0]
  9635  		val := v.Args[1]
  9636  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  9637  			break
  9638  		}
  9639  		v.reset(Op386MOVSDstore)
  9640  		v.AuxInt = off1 + off2
  9641  		v.Aux = mergeSym(sym1, sym2)
  9642  		v.AddArg(base)
  9643  		v.AddArg(val)
  9644  		v.AddArg(mem)
  9645  		return true
  9646  	}
  9647  	// match: (MOVSDstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem)
  9648  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  9649  	// result: (MOVSDstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
  9650  	for {
  9651  		off1 := v.AuxInt
  9652  		sym1 := v.Aux
  9653  		mem := v.Args[2]
  9654  		v_0 := v.Args[0]
  9655  		if v_0.Op != Op386LEAL1 {
  9656  			break
  9657  		}
  9658  		off2 := v_0.AuxInt
  9659  		sym2 := v_0.Aux
  9660  		idx := v_0.Args[1]
  9661  		ptr := v_0.Args[0]
  9662  		val := v.Args[1]
  9663  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  9664  			break
  9665  		}
  9666  		v.reset(Op386MOVSDstoreidx1)
  9667  		v.AuxInt = off1 + off2
  9668  		v.Aux = mergeSym(sym1, sym2)
  9669  		v.AddArg(ptr)
  9670  		v.AddArg(idx)
  9671  		v.AddArg(val)
  9672  		v.AddArg(mem)
  9673  		return true
  9674  	}
  9675  	// match: (MOVSDstore [off1] {sym1} (LEAL8 [off2] {sym2} ptr idx) val mem)
  9676  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  9677  	// result: (MOVSDstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
  9678  	for {
  9679  		off1 := v.AuxInt
  9680  		sym1 := v.Aux
  9681  		mem := v.Args[2]
  9682  		v_0 := v.Args[0]
  9683  		if v_0.Op != Op386LEAL8 {
  9684  			break
  9685  		}
  9686  		off2 := v_0.AuxInt
  9687  		sym2 := v_0.Aux
  9688  		idx := v_0.Args[1]
  9689  		ptr := v_0.Args[0]
  9690  		val := v.Args[1]
  9691  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  9692  			break
  9693  		}
  9694  		v.reset(Op386MOVSDstoreidx8)
  9695  		v.AuxInt = off1 + off2
  9696  		v.Aux = mergeSym(sym1, sym2)
  9697  		v.AddArg(ptr)
  9698  		v.AddArg(idx)
  9699  		v.AddArg(val)
  9700  		v.AddArg(mem)
  9701  		return true
  9702  	}
  9703  	// match: (MOVSDstore [off] {sym} (ADDL ptr idx) val mem)
  9704  	// cond: ptr.Op != OpSB
  9705  	// result: (MOVSDstoreidx1 [off] {sym} ptr idx val mem)
  9706  	for {
  9707  		off := v.AuxInt
  9708  		sym := v.Aux
  9709  		mem := v.Args[2]
  9710  		v_0 := v.Args[0]
  9711  		if v_0.Op != Op386ADDL {
  9712  			break
  9713  		}
  9714  		idx := v_0.Args[1]
  9715  		ptr := v_0.Args[0]
  9716  		val := v.Args[1]
  9717  		if !(ptr.Op != OpSB) {
  9718  			break
  9719  		}
  9720  		v.reset(Op386MOVSDstoreidx1)
  9721  		v.AuxInt = off
  9722  		v.Aux = sym
  9723  		v.AddArg(ptr)
  9724  		v.AddArg(idx)
  9725  		v.AddArg(val)
  9726  		v.AddArg(mem)
  9727  		return true
  9728  	}
  9729  	return false
  9730  }
  9731  func rewriteValue386_Op386MOVSDstoreidx1_0(v *Value) bool {
  9732  	// match: (MOVSDstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem)
  9733  	// cond:
  9734  	// result: (MOVSDstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  9735  	for {
  9736  		c := v.AuxInt
  9737  		sym := v.Aux
  9738  		mem := v.Args[3]
  9739  		v_0 := v.Args[0]
  9740  		if v_0.Op != Op386ADDLconst {
  9741  			break
  9742  		}
  9743  		d := v_0.AuxInt
  9744  		ptr := v_0.Args[0]
  9745  		idx := v.Args[1]
  9746  		val := v.Args[2]
  9747  		v.reset(Op386MOVSDstoreidx1)
  9748  		v.AuxInt = int64(int32(c + d))
  9749  		v.Aux = sym
  9750  		v.AddArg(ptr)
  9751  		v.AddArg(idx)
  9752  		v.AddArg(val)
  9753  		v.AddArg(mem)
  9754  		return true
  9755  	}
  9756  	// match: (MOVSDstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem)
  9757  	// cond:
  9758  	// result: (MOVSDstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  9759  	for {
  9760  		c := v.AuxInt
  9761  		sym := v.Aux
  9762  		mem := v.Args[3]
  9763  		ptr := v.Args[0]
  9764  		v_1 := v.Args[1]
  9765  		if v_1.Op != Op386ADDLconst {
  9766  			break
  9767  		}
  9768  		d := v_1.AuxInt
  9769  		idx := v_1.Args[0]
  9770  		val := v.Args[2]
  9771  		v.reset(Op386MOVSDstoreidx1)
  9772  		v.AuxInt = int64(int32(c + d))
  9773  		v.Aux = sym
  9774  		v.AddArg(ptr)
  9775  		v.AddArg(idx)
  9776  		v.AddArg(val)
  9777  		v.AddArg(mem)
  9778  		return true
  9779  	}
  9780  	return false
  9781  }
  9782  func rewriteValue386_Op386MOVSDstoreidx8_0(v *Value) bool {
  9783  	// match: (MOVSDstoreidx8 [c] {sym} (ADDLconst [d] ptr) idx val mem)
  9784  	// cond:
  9785  	// result: (MOVSDstoreidx8 [int64(int32(c+d))] {sym} ptr idx val mem)
  9786  	for {
  9787  		c := v.AuxInt
  9788  		sym := v.Aux
  9789  		mem := v.Args[3]
  9790  		v_0 := v.Args[0]
  9791  		if v_0.Op != Op386ADDLconst {
  9792  			break
  9793  		}
  9794  		d := v_0.AuxInt
  9795  		ptr := v_0.Args[0]
  9796  		idx := v.Args[1]
  9797  		val := v.Args[2]
  9798  		v.reset(Op386MOVSDstoreidx8)
  9799  		v.AuxInt = int64(int32(c + d))
  9800  		v.Aux = sym
  9801  		v.AddArg(ptr)
  9802  		v.AddArg(idx)
  9803  		v.AddArg(val)
  9804  		v.AddArg(mem)
  9805  		return true
  9806  	}
  9807  	// match: (MOVSDstoreidx8 [c] {sym} ptr (ADDLconst [d] idx) val mem)
  9808  	// cond:
  9809  	// result: (MOVSDstoreidx8 [int64(int32(c+8*d))] {sym} ptr idx val mem)
  9810  	for {
  9811  		c := v.AuxInt
  9812  		sym := v.Aux
  9813  		mem := v.Args[3]
  9814  		ptr := v.Args[0]
  9815  		v_1 := v.Args[1]
  9816  		if v_1.Op != Op386ADDLconst {
  9817  			break
  9818  		}
  9819  		d := v_1.AuxInt
  9820  		idx := v_1.Args[0]
  9821  		val := v.Args[2]
  9822  		v.reset(Op386MOVSDstoreidx8)
  9823  		v.AuxInt = int64(int32(c + 8*d))
  9824  		v.Aux = sym
  9825  		v.AddArg(ptr)
  9826  		v.AddArg(idx)
  9827  		v.AddArg(val)
  9828  		v.AddArg(mem)
  9829  		return true
  9830  	}
  9831  	return false
  9832  }
  9833  func rewriteValue386_Op386MOVSSconst_0(v *Value) bool {
  9834  	b := v.Block
  9835  	config := b.Func.Config
  9836  	typ := &b.Func.Config.Types
  9837  	// match: (MOVSSconst [c])
  9838  	// cond: config.ctxt.Flag_shared
  9839  	// result: (MOVSSconst2 (MOVSSconst1 [c]))
  9840  	for {
  9841  		c := v.AuxInt
  9842  		if !(config.ctxt.Flag_shared) {
  9843  			break
  9844  		}
  9845  		v.reset(Op386MOVSSconst2)
  9846  		v0 := b.NewValue0(v.Pos, Op386MOVSSconst1, typ.UInt32)
  9847  		v0.AuxInt = c
  9848  		v.AddArg(v0)
  9849  		return true
  9850  	}
  9851  	return false
  9852  }
  9853  func rewriteValue386_Op386MOVSSload_0(v *Value) bool {
  9854  	b := v.Block
  9855  	config := b.Func.Config
  9856  	// match: (MOVSSload [off1] {sym} (ADDLconst [off2] ptr) mem)
  9857  	// cond: is32Bit(off1+off2)
  9858  	// result: (MOVSSload [off1+off2] {sym} ptr mem)
  9859  	for {
  9860  		off1 := v.AuxInt
  9861  		sym := v.Aux
  9862  		mem := v.Args[1]
  9863  		v_0 := v.Args[0]
  9864  		if v_0.Op != Op386ADDLconst {
  9865  			break
  9866  		}
  9867  		off2 := v_0.AuxInt
  9868  		ptr := v_0.Args[0]
  9869  		if !(is32Bit(off1 + off2)) {
  9870  			break
  9871  		}
  9872  		v.reset(Op386MOVSSload)
  9873  		v.AuxInt = off1 + off2
  9874  		v.Aux = sym
  9875  		v.AddArg(ptr)
  9876  		v.AddArg(mem)
  9877  		return true
  9878  	}
  9879  	// match: (MOVSSload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
  9880  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  9881  	// result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem)
  9882  	for {
  9883  		off1 := v.AuxInt
  9884  		sym1 := v.Aux
  9885  		mem := v.Args[1]
  9886  		v_0 := v.Args[0]
  9887  		if v_0.Op != Op386LEAL {
  9888  			break
  9889  		}
  9890  		off2 := v_0.AuxInt
  9891  		sym2 := v_0.Aux
  9892  		base := v_0.Args[0]
  9893  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  9894  			break
  9895  		}
  9896  		v.reset(Op386MOVSSload)
  9897  		v.AuxInt = off1 + off2
  9898  		v.Aux = mergeSym(sym1, sym2)
  9899  		v.AddArg(base)
  9900  		v.AddArg(mem)
  9901  		return true
  9902  	}
  9903  	// match: (MOVSSload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem)
  9904  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  9905  	// result: (MOVSSloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
  9906  	for {
  9907  		off1 := v.AuxInt
  9908  		sym1 := v.Aux
  9909  		mem := v.Args[1]
  9910  		v_0 := v.Args[0]
  9911  		if v_0.Op != Op386LEAL1 {
  9912  			break
  9913  		}
  9914  		off2 := v_0.AuxInt
  9915  		sym2 := v_0.Aux
  9916  		idx := v_0.Args[1]
  9917  		ptr := v_0.Args[0]
  9918  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  9919  			break
  9920  		}
  9921  		v.reset(Op386MOVSSloadidx1)
  9922  		v.AuxInt = off1 + off2
  9923  		v.Aux = mergeSym(sym1, sym2)
  9924  		v.AddArg(ptr)
  9925  		v.AddArg(idx)
  9926  		v.AddArg(mem)
  9927  		return true
  9928  	}
  9929  	// match: (MOVSSload [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) mem)
  9930  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  9931  	// result: (MOVSSloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
  9932  	for {
  9933  		off1 := v.AuxInt
  9934  		sym1 := v.Aux
  9935  		mem := v.Args[1]
  9936  		v_0 := v.Args[0]
  9937  		if v_0.Op != Op386LEAL4 {
  9938  			break
  9939  		}
  9940  		off2 := v_0.AuxInt
  9941  		sym2 := v_0.Aux
  9942  		idx := v_0.Args[1]
  9943  		ptr := v_0.Args[0]
  9944  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  9945  			break
  9946  		}
  9947  		v.reset(Op386MOVSSloadidx4)
  9948  		v.AuxInt = off1 + off2
  9949  		v.Aux = mergeSym(sym1, sym2)
  9950  		v.AddArg(ptr)
  9951  		v.AddArg(idx)
  9952  		v.AddArg(mem)
  9953  		return true
  9954  	}
  9955  	// match: (MOVSSload [off] {sym} (ADDL ptr idx) mem)
  9956  	// cond: ptr.Op != OpSB
  9957  	// result: (MOVSSloadidx1 [off] {sym} ptr idx mem)
  9958  	for {
  9959  		off := v.AuxInt
  9960  		sym := v.Aux
  9961  		mem := v.Args[1]
  9962  		v_0 := v.Args[0]
  9963  		if v_0.Op != Op386ADDL {
  9964  			break
  9965  		}
  9966  		idx := v_0.Args[1]
  9967  		ptr := v_0.Args[0]
  9968  		if !(ptr.Op != OpSB) {
  9969  			break
  9970  		}
  9971  		v.reset(Op386MOVSSloadidx1)
  9972  		v.AuxInt = off
  9973  		v.Aux = sym
  9974  		v.AddArg(ptr)
  9975  		v.AddArg(idx)
  9976  		v.AddArg(mem)
  9977  		return true
  9978  	}
  9979  	return false
  9980  }
  9981  func rewriteValue386_Op386MOVSSloadidx1_0(v *Value) bool {
  9982  	// match: (MOVSSloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem)
  9983  	// cond:
  9984  	// result: (MOVSSloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  9985  	for {
  9986  		c := v.AuxInt
  9987  		sym := v.Aux
  9988  		mem := v.Args[2]
  9989  		v_0 := v.Args[0]
  9990  		if v_0.Op != Op386ADDLconst {
  9991  			break
  9992  		}
  9993  		d := v_0.AuxInt
  9994  		ptr := v_0.Args[0]
  9995  		idx := v.Args[1]
  9996  		v.reset(Op386MOVSSloadidx1)
  9997  		v.AuxInt = int64(int32(c + d))
  9998  		v.Aux = sym
  9999  		v.AddArg(ptr)
 10000  		v.AddArg(idx)
 10001  		v.AddArg(mem)
 10002  		return true
 10003  	}
 10004  	// match: (MOVSSloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem)
 10005  	// cond:
 10006  	// result: (MOVSSloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
 10007  	for {
 10008  		c := v.AuxInt
 10009  		sym := v.Aux
 10010  		mem := v.Args[2]
 10011  		ptr := v.Args[0]
 10012  		v_1 := v.Args[1]
 10013  		if v_1.Op != Op386ADDLconst {
 10014  			break
 10015  		}
 10016  		d := v_1.AuxInt
 10017  		idx := v_1.Args[0]
 10018  		v.reset(Op386MOVSSloadidx1)
 10019  		v.AuxInt = int64(int32(c + d))
 10020  		v.Aux = sym
 10021  		v.AddArg(ptr)
 10022  		v.AddArg(idx)
 10023  		v.AddArg(mem)
 10024  		return true
 10025  	}
 10026  	return false
 10027  }
 10028  func rewriteValue386_Op386MOVSSloadidx4_0(v *Value) bool {
 10029  	// match: (MOVSSloadidx4 [c] {sym} (ADDLconst [d] ptr) idx mem)
 10030  	// cond:
 10031  	// result: (MOVSSloadidx4 [int64(int32(c+d))] {sym} ptr idx mem)
 10032  	for {
 10033  		c := v.AuxInt
 10034  		sym := v.Aux
 10035  		mem := v.Args[2]
 10036  		v_0 := v.Args[0]
 10037  		if v_0.Op != Op386ADDLconst {
 10038  			break
 10039  		}
 10040  		d := v_0.AuxInt
 10041  		ptr := v_0.Args[0]
 10042  		idx := v.Args[1]
 10043  		v.reset(Op386MOVSSloadidx4)
 10044  		v.AuxInt = int64(int32(c + d))
 10045  		v.Aux = sym
 10046  		v.AddArg(ptr)
 10047  		v.AddArg(idx)
 10048  		v.AddArg(mem)
 10049  		return true
 10050  	}
 10051  	// match: (MOVSSloadidx4 [c] {sym} ptr (ADDLconst [d] idx) mem)
 10052  	// cond:
 10053  	// result: (MOVSSloadidx4 [int64(int32(c+4*d))] {sym} ptr idx mem)
 10054  	for {
 10055  		c := v.AuxInt
 10056  		sym := v.Aux
 10057  		mem := v.Args[2]
 10058  		ptr := v.Args[0]
 10059  		v_1 := v.Args[1]
 10060  		if v_1.Op != Op386ADDLconst {
 10061  			break
 10062  		}
 10063  		d := v_1.AuxInt
 10064  		idx := v_1.Args[0]
 10065  		v.reset(Op386MOVSSloadidx4)
 10066  		v.AuxInt = int64(int32(c + 4*d))
 10067  		v.Aux = sym
 10068  		v.AddArg(ptr)
 10069  		v.AddArg(idx)
 10070  		v.AddArg(mem)
 10071  		return true
 10072  	}
 10073  	return false
 10074  }
 10075  func rewriteValue386_Op386MOVSSstore_0(v *Value) bool {
 10076  	b := v.Block
 10077  	config := b.Func.Config
 10078  	// match: (MOVSSstore [off1] {sym} (ADDLconst [off2] ptr) val mem)
 10079  	// cond: is32Bit(off1+off2)
 10080  	// result: (MOVSSstore [off1+off2] {sym} ptr val mem)
 10081  	for {
 10082  		off1 := v.AuxInt
 10083  		sym := v.Aux
 10084  		mem := v.Args[2]
 10085  		v_0 := v.Args[0]
 10086  		if v_0.Op != Op386ADDLconst {
 10087  			break
 10088  		}
 10089  		off2 := v_0.AuxInt
 10090  		ptr := v_0.Args[0]
 10091  		val := v.Args[1]
 10092  		if !(is32Bit(off1 + off2)) {
 10093  			break
 10094  		}
 10095  		v.reset(Op386MOVSSstore)
 10096  		v.AuxInt = off1 + off2
 10097  		v.Aux = sym
 10098  		v.AddArg(ptr)
 10099  		v.AddArg(val)
 10100  		v.AddArg(mem)
 10101  		return true
 10102  	}
 10103  	// match: (MOVSSstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
 10104  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
 10105  	// result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
 10106  	for {
 10107  		off1 := v.AuxInt
 10108  		sym1 := v.Aux
 10109  		mem := v.Args[2]
 10110  		v_0 := v.Args[0]
 10111  		if v_0.Op != Op386LEAL {
 10112  			break
 10113  		}
 10114  		off2 := v_0.AuxInt
 10115  		sym2 := v_0.Aux
 10116  		base := v_0.Args[0]
 10117  		val := v.Args[1]
 10118  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
 10119  			break
 10120  		}
 10121  		v.reset(Op386MOVSSstore)
 10122  		v.AuxInt = off1 + off2
 10123  		v.Aux = mergeSym(sym1, sym2)
 10124  		v.AddArg(base)
 10125  		v.AddArg(val)
 10126  		v.AddArg(mem)
 10127  		return true
 10128  	}
 10129  	// match: (MOVSSstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem)
 10130  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10131  	// result: (MOVSSstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
 10132  	for {
 10133  		off1 := v.AuxInt
 10134  		sym1 := v.Aux
 10135  		mem := v.Args[2]
 10136  		v_0 := v.Args[0]
 10137  		if v_0.Op != Op386LEAL1 {
 10138  			break
 10139  		}
 10140  		off2 := v_0.AuxInt
 10141  		sym2 := v_0.Aux
 10142  		idx := v_0.Args[1]
 10143  		ptr := v_0.Args[0]
 10144  		val := v.Args[1]
 10145  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10146  			break
 10147  		}
 10148  		v.reset(Op386MOVSSstoreidx1)
 10149  		v.AuxInt = off1 + off2
 10150  		v.Aux = mergeSym(sym1, sym2)
 10151  		v.AddArg(ptr)
 10152  		v.AddArg(idx)
 10153  		v.AddArg(val)
 10154  		v.AddArg(mem)
 10155  		return true
 10156  	}
 10157  	// match: (MOVSSstore [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) val mem)
 10158  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10159  	// result: (MOVSSstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
 10160  	for {
 10161  		off1 := v.AuxInt
 10162  		sym1 := v.Aux
 10163  		mem := v.Args[2]
 10164  		v_0 := v.Args[0]
 10165  		if v_0.Op != Op386LEAL4 {
 10166  			break
 10167  		}
 10168  		off2 := v_0.AuxInt
 10169  		sym2 := v_0.Aux
 10170  		idx := v_0.Args[1]
 10171  		ptr := v_0.Args[0]
 10172  		val := v.Args[1]
 10173  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10174  			break
 10175  		}
 10176  		v.reset(Op386MOVSSstoreidx4)
 10177  		v.AuxInt = off1 + off2
 10178  		v.Aux = mergeSym(sym1, sym2)
 10179  		v.AddArg(ptr)
 10180  		v.AddArg(idx)
 10181  		v.AddArg(val)
 10182  		v.AddArg(mem)
 10183  		return true
 10184  	}
 10185  	// match: (MOVSSstore [off] {sym} (ADDL ptr idx) val mem)
 10186  	// cond: ptr.Op != OpSB
 10187  	// result: (MOVSSstoreidx1 [off] {sym} ptr idx val mem)
 10188  	for {
 10189  		off := v.AuxInt
 10190  		sym := v.Aux
 10191  		mem := v.Args[2]
 10192  		v_0 := v.Args[0]
 10193  		if v_0.Op != Op386ADDL {
 10194  			break
 10195  		}
 10196  		idx := v_0.Args[1]
 10197  		ptr := v_0.Args[0]
 10198  		val := v.Args[1]
 10199  		if !(ptr.Op != OpSB) {
 10200  			break
 10201  		}
 10202  		v.reset(Op386MOVSSstoreidx1)
 10203  		v.AuxInt = off
 10204  		v.Aux = sym
 10205  		v.AddArg(ptr)
 10206  		v.AddArg(idx)
 10207  		v.AddArg(val)
 10208  		v.AddArg(mem)
 10209  		return true
 10210  	}
 10211  	return false
 10212  }
 10213  func rewriteValue386_Op386MOVSSstoreidx1_0(v *Value) bool {
 10214  	// match: (MOVSSstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem)
 10215  	// cond:
 10216  	// result: (MOVSSstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
 10217  	for {
 10218  		c := v.AuxInt
 10219  		sym := v.Aux
 10220  		mem := v.Args[3]
 10221  		v_0 := v.Args[0]
 10222  		if v_0.Op != Op386ADDLconst {
 10223  			break
 10224  		}
 10225  		d := v_0.AuxInt
 10226  		ptr := v_0.Args[0]
 10227  		idx := v.Args[1]
 10228  		val := v.Args[2]
 10229  		v.reset(Op386MOVSSstoreidx1)
 10230  		v.AuxInt = int64(int32(c + d))
 10231  		v.Aux = sym
 10232  		v.AddArg(ptr)
 10233  		v.AddArg(idx)
 10234  		v.AddArg(val)
 10235  		v.AddArg(mem)
 10236  		return true
 10237  	}
 10238  	// match: (MOVSSstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem)
 10239  	// cond:
 10240  	// result: (MOVSSstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
 10241  	for {
 10242  		c := v.AuxInt
 10243  		sym := v.Aux
 10244  		mem := v.Args[3]
 10245  		ptr := v.Args[0]
 10246  		v_1 := v.Args[1]
 10247  		if v_1.Op != Op386ADDLconst {
 10248  			break
 10249  		}
 10250  		d := v_1.AuxInt
 10251  		idx := v_1.Args[0]
 10252  		val := v.Args[2]
 10253  		v.reset(Op386MOVSSstoreidx1)
 10254  		v.AuxInt = int64(int32(c + d))
 10255  		v.Aux = sym
 10256  		v.AddArg(ptr)
 10257  		v.AddArg(idx)
 10258  		v.AddArg(val)
 10259  		v.AddArg(mem)
 10260  		return true
 10261  	}
 10262  	return false
 10263  }
 10264  func rewriteValue386_Op386MOVSSstoreidx4_0(v *Value) bool {
 10265  	// match: (MOVSSstoreidx4 [c] {sym} (ADDLconst [d] ptr) idx val mem)
 10266  	// cond:
 10267  	// result: (MOVSSstoreidx4 [int64(int32(c+d))] {sym} ptr idx val mem)
 10268  	for {
 10269  		c := v.AuxInt
 10270  		sym := v.Aux
 10271  		mem := v.Args[3]
 10272  		v_0 := v.Args[0]
 10273  		if v_0.Op != Op386ADDLconst {
 10274  			break
 10275  		}
 10276  		d := v_0.AuxInt
 10277  		ptr := v_0.Args[0]
 10278  		idx := v.Args[1]
 10279  		val := v.Args[2]
 10280  		v.reset(Op386MOVSSstoreidx4)
 10281  		v.AuxInt = int64(int32(c + d))
 10282  		v.Aux = sym
 10283  		v.AddArg(ptr)
 10284  		v.AddArg(idx)
 10285  		v.AddArg(val)
 10286  		v.AddArg(mem)
 10287  		return true
 10288  	}
 10289  	// match: (MOVSSstoreidx4 [c] {sym} ptr (ADDLconst [d] idx) val mem)
 10290  	// cond:
 10291  	// result: (MOVSSstoreidx4 [int64(int32(c+4*d))] {sym} ptr idx val mem)
 10292  	for {
 10293  		c := v.AuxInt
 10294  		sym := v.Aux
 10295  		mem := v.Args[3]
 10296  		ptr := v.Args[0]
 10297  		v_1 := v.Args[1]
 10298  		if v_1.Op != Op386ADDLconst {
 10299  			break
 10300  		}
 10301  		d := v_1.AuxInt
 10302  		idx := v_1.Args[0]
 10303  		val := v.Args[2]
 10304  		v.reset(Op386MOVSSstoreidx4)
 10305  		v.AuxInt = int64(int32(c + 4*d))
 10306  		v.Aux = sym
 10307  		v.AddArg(ptr)
 10308  		v.AddArg(idx)
 10309  		v.AddArg(val)
 10310  		v.AddArg(mem)
 10311  		return true
 10312  	}
 10313  	return false
 10314  }
 10315  func rewriteValue386_Op386MOVWLSX_0(v *Value) bool {
 10316  	b := v.Block
 10317  	// match: (MOVWLSX x:(MOVWload [off] {sym} ptr mem))
 10318  	// cond: x.Uses == 1 && clobber(x)
 10319  	// result: @x.Block (MOVWLSXload <v.Type> [off] {sym} ptr mem)
 10320  	for {
 10321  		x := v.Args[0]
 10322  		if x.Op != Op386MOVWload {
 10323  			break
 10324  		}
 10325  		off := x.AuxInt
 10326  		sym := x.Aux
 10327  		mem := x.Args[1]
 10328  		ptr := x.Args[0]
 10329  		if !(x.Uses == 1 && clobber(x)) {
 10330  			break
 10331  		}
 10332  		b = x.Block
 10333  		v0 := b.NewValue0(x.Pos, Op386MOVWLSXload, v.Type)
 10334  		v.reset(OpCopy)
 10335  		v.AddArg(v0)
 10336  		v0.AuxInt = off
 10337  		v0.Aux = sym
 10338  		v0.AddArg(ptr)
 10339  		v0.AddArg(mem)
 10340  		return true
 10341  	}
 10342  	// match: (MOVWLSX (ANDLconst [c] x))
 10343  	// cond: c & 0x8000 == 0
 10344  	// result: (ANDLconst [c & 0x7fff] x)
 10345  	for {
 10346  		v_0 := v.Args[0]
 10347  		if v_0.Op != Op386ANDLconst {
 10348  			break
 10349  		}
 10350  		c := v_0.AuxInt
 10351  		x := v_0.Args[0]
 10352  		if !(c&0x8000 == 0) {
 10353  			break
 10354  		}
 10355  		v.reset(Op386ANDLconst)
 10356  		v.AuxInt = c & 0x7fff
 10357  		v.AddArg(x)
 10358  		return true
 10359  	}
 10360  	return false
 10361  }
 10362  func rewriteValue386_Op386MOVWLSXload_0(v *Value) bool {
 10363  	b := v.Block
 10364  	config := b.Func.Config
 10365  	// match: (MOVWLSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _))
 10366  	// cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
 10367  	// result: (MOVWLSX x)
 10368  	for {
 10369  		off := v.AuxInt
 10370  		sym := v.Aux
 10371  		_ = v.Args[1]
 10372  		ptr := v.Args[0]
 10373  		v_1 := v.Args[1]
 10374  		if v_1.Op != Op386MOVWstore {
 10375  			break
 10376  		}
 10377  		off2 := v_1.AuxInt
 10378  		sym2 := v_1.Aux
 10379  		_ = v_1.Args[2]
 10380  		ptr2 := v_1.Args[0]
 10381  		x := v_1.Args[1]
 10382  		if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
 10383  			break
 10384  		}
 10385  		v.reset(Op386MOVWLSX)
 10386  		v.AddArg(x)
 10387  		return true
 10388  	}
 10389  	// match: (MOVWLSXload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
 10390  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
 10391  	// result: (MOVWLSXload [off1+off2] {mergeSym(sym1,sym2)} base mem)
 10392  	for {
 10393  		off1 := v.AuxInt
 10394  		sym1 := v.Aux
 10395  		mem := v.Args[1]
 10396  		v_0 := v.Args[0]
 10397  		if v_0.Op != Op386LEAL {
 10398  			break
 10399  		}
 10400  		off2 := v_0.AuxInt
 10401  		sym2 := v_0.Aux
 10402  		base := v_0.Args[0]
 10403  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
 10404  			break
 10405  		}
 10406  		v.reset(Op386MOVWLSXload)
 10407  		v.AuxInt = off1 + off2
 10408  		v.Aux = mergeSym(sym1, sym2)
 10409  		v.AddArg(base)
 10410  		v.AddArg(mem)
 10411  		return true
 10412  	}
 10413  	return false
 10414  }
 10415  func rewriteValue386_Op386MOVWLZX_0(v *Value) bool {
 10416  	b := v.Block
 10417  	// match: (MOVWLZX x:(MOVWload [off] {sym} ptr mem))
 10418  	// cond: x.Uses == 1 && clobber(x)
 10419  	// result: @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
 10420  	for {
 10421  		x := v.Args[0]
 10422  		if x.Op != Op386MOVWload {
 10423  			break
 10424  		}
 10425  		off := x.AuxInt
 10426  		sym := x.Aux
 10427  		mem := x.Args[1]
 10428  		ptr := x.Args[0]
 10429  		if !(x.Uses == 1 && clobber(x)) {
 10430  			break
 10431  		}
 10432  		b = x.Block
 10433  		v0 := b.NewValue0(x.Pos, Op386MOVWload, v.Type)
 10434  		v.reset(OpCopy)
 10435  		v.AddArg(v0)
 10436  		v0.AuxInt = off
 10437  		v0.Aux = sym
 10438  		v0.AddArg(ptr)
 10439  		v0.AddArg(mem)
 10440  		return true
 10441  	}
 10442  	// match: (MOVWLZX x:(MOVWloadidx1 [off] {sym} ptr idx mem))
 10443  	// cond: x.Uses == 1 && clobber(x)
 10444  	// result: @x.Block (MOVWloadidx1 <v.Type> [off] {sym} ptr idx mem)
 10445  	for {
 10446  		x := v.Args[0]
 10447  		if x.Op != Op386MOVWloadidx1 {
 10448  			break
 10449  		}
 10450  		off := x.AuxInt
 10451  		sym := x.Aux
 10452  		mem := x.Args[2]
 10453  		ptr := x.Args[0]
 10454  		idx := x.Args[1]
 10455  		if !(x.Uses == 1 && clobber(x)) {
 10456  			break
 10457  		}
 10458  		b = x.Block
 10459  		v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type)
 10460  		v.reset(OpCopy)
 10461  		v.AddArg(v0)
 10462  		v0.AuxInt = off
 10463  		v0.Aux = sym
 10464  		v0.AddArg(ptr)
 10465  		v0.AddArg(idx)
 10466  		v0.AddArg(mem)
 10467  		return true
 10468  	}
 10469  	// match: (MOVWLZX x:(MOVWloadidx2 [off] {sym} ptr idx mem))
 10470  	// cond: x.Uses == 1 && clobber(x)
 10471  	// result: @x.Block (MOVWloadidx2 <v.Type> [off] {sym} ptr idx mem)
 10472  	for {
 10473  		x := v.Args[0]
 10474  		if x.Op != Op386MOVWloadidx2 {
 10475  			break
 10476  		}
 10477  		off := x.AuxInt
 10478  		sym := x.Aux
 10479  		mem := x.Args[2]
 10480  		ptr := x.Args[0]
 10481  		idx := x.Args[1]
 10482  		if !(x.Uses == 1 && clobber(x)) {
 10483  			break
 10484  		}
 10485  		b = x.Block
 10486  		v0 := b.NewValue0(v.Pos, Op386MOVWloadidx2, v.Type)
 10487  		v.reset(OpCopy)
 10488  		v.AddArg(v0)
 10489  		v0.AuxInt = off
 10490  		v0.Aux = sym
 10491  		v0.AddArg(ptr)
 10492  		v0.AddArg(idx)
 10493  		v0.AddArg(mem)
 10494  		return true
 10495  	}
 10496  	// match: (MOVWLZX (ANDLconst [c] x))
 10497  	// cond:
 10498  	// result: (ANDLconst [c & 0xffff] x)
 10499  	for {
 10500  		v_0 := v.Args[0]
 10501  		if v_0.Op != Op386ANDLconst {
 10502  			break
 10503  		}
 10504  		c := v_0.AuxInt
 10505  		x := v_0.Args[0]
 10506  		v.reset(Op386ANDLconst)
 10507  		v.AuxInt = c & 0xffff
 10508  		v.AddArg(x)
 10509  		return true
 10510  	}
 10511  	return false
 10512  }
 10513  func rewriteValue386_Op386MOVWload_0(v *Value) bool {
 10514  	b := v.Block
 10515  	config := b.Func.Config
 10516  	// match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _))
 10517  	// cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
 10518  	// result: (MOVWLZX x)
 10519  	for {
 10520  		off := v.AuxInt
 10521  		sym := v.Aux
 10522  		_ = v.Args[1]
 10523  		ptr := v.Args[0]
 10524  		v_1 := v.Args[1]
 10525  		if v_1.Op != Op386MOVWstore {
 10526  			break
 10527  		}
 10528  		off2 := v_1.AuxInt
 10529  		sym2 := v_1.Aux
 10530  		_ = v_1.Args[2]
 10531  		ptr2 := v_1.Args[0]
 10532  		x := v_1.Args[1]
 10533  		if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
 10534  			break
 10535  		}
 10536  		v.reset(Op386MOVWLZX)
 10537  		v.AddArg(x)
 10538  		return true
 10539  	}
 10540  	// match: (MOVWload [off1] {sym} (ADDLconst [off2] ptr) mem)
 10541  	// cond: is32Bit(off1+off2)
 10542  	// result: (MOVWload [off1+off2] {sym} ptr mem)
 10543  	for {
 10544  		off1 := v.AuxInt
 10545  		sym := v.Aux
 10546  		mem := v.Args[1]
 10547  		v_0 := v.Args[0]
 10548  		if v_0.Op != Op386ADDLconst {
 10549  			break
 10550  		}
 10551  		off2 := v_0.AuxInt
 10552  		ptr := v_0.Args[0]
 10553  		if !(is32Bit(off1 + off2)) {
 10554  			break
 10555  		}
 10556  		v.reset(Op386MOVWload)
 10557  		v.AuxInt = off1 + off2
 10558  		v.Aux = sym
 10559  		v.AddArg(ptr)
 10560  		v.AddArg(mem)
 10561  		return true
 10562  	}
 10563  	// match: (MOVWload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
 10564  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
 10565  	// result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem)
 10566  	for {
 10567  		off1 := v.AuxInt
 10568  		sym1 := v.Aux
 10569  		mem := v.Args[1]
 10570  		v_0 := v.Args[0]
 10571  		if v_0.Op != Op386LEAL {
 10572  			break
 10573  		}
 10574  		off2 := v_0.AuxInt
 10575  		sym2 := v_0.Aux
 10576  		base := v_0.Args[0]
 10577  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
 10578  			break
 10579  		}
 10580  		v.reset(Op386MOVWload)
 10581  		v.AuxInt = off1 + off2
 10582  		v.Aux = mergeSym(sym1, sym2)
 10583  		v.AddArg(base)
 10584  		v.AddArg(mem)
 10585  		return true
 10586  	}
 10587  	// match: (MOVWload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem)
 10588  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10589  	// result: (MOVWloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
 10590  	for {
 10591  		off1 := v.AuxInt
 10592  		sym1 := v.Aux
 10593  		mem := v.Args[1]
 10594  		v_0 := v.Args[0]
 10595  		if v_0.Op != Op386LEAL1 {
 10596  			break
 10597  		}
 10598  		off2 := v_0.AuxInt
 10599  		sym2 := v_0.Aux
 10600  		idx := v_0.Args[1]
 10601  		ptr := v_0.Args[0]
 10602  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10603  			break
 10604  		}
 10605  		v.reset(Op386MOVWloadidx1)
 10606  		v.AuxInt = off1 + off2
 10607  		v.Aux = mergeSym(sym1, sym2)
 10608  		v.AddArg(ptr)
 10609  		v.AddArg(idx)
 10610  		v.AddArg(mem)
 10611  		return true
 10612  	}
 10613  	// match: (MOVWload [off1] {sym1} (LEAL2 [off2] {sym2} ptr idx) mem)
 10614  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10615  	// result: (MOVWloadidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
 10616  	for {
 10617  		off1 := v.AuxInt
 10618  		sym1 := v.Aux
 10619  		mem := v.Args[1]
 10620  		v_0 := v.Args[0]
 10621  		if v_0.Op != Op386LEAL2 {
 10622  			break
 10623  		}
 10624  		off2 := v_0.AuxInt
 10625  		sym2 := v_0.Aux
 10626  		idx := v_0.Args[1]
 10627  		ptr := v_0.Args[0]
 10628  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10629  			break
 10630  		}
 10631  		v.reset(Op386MOVWloadidx2)
 10632  		v.AuxInt = off1 + off2
 10633  		v.Aux = mergeSym(sym1, sym2)
 10634  		v.AddArg(ptr)
 10635  		v.AddArg(idx)
 10636  		v.AddArg(mem)
 10637  		return true
 10638  	}
 10639  	// match: (MOVWload [off] {sym} (ADDL ptr idx) mem)
 10640  	// cond: ptr.Op != OpSB
 10641  	// result: (MOVWloadidx1 [off] {sym} ptr idx mem)
 10642  	for {
 10643  		off := v.AuxInt
 10644  		sym := v.Aux
 10645  		mem := v.Args[1]
 10646  		v_0 := v.Args[0]
 10647  		if v_0.Op != Op386ADDL {
 10648  			break
 10649  		}
 10650  		idx := v_0.Args[1]
 10651  		ptr := v_0.Args[0]
 10652  		if !(ptr.Op != OpSB) {
 10653  			break
 10654  		}
 10655  		v.reset(Op386MOVWloadidx1)
 10656  		v.AuxInt = off
 10657  		v.Aux = sym
 10658  		v.AddArg(ptr)
 10659  		v.AddArg(idx)
 10660  		v.AddArg(mem)
 10661  		return true
 10662  	}
 10663  	// match: (MOVWload [off] {sym} (SB) _)
 10664  	// cond: symIsRO(sym)
 10665  	// result: (MOVLconst [int64(read16(sym, off, config.BigEndian))])
 10666  	for {
 10667  		off := v.AuxInt
 10668  		sym := v.Aux
 10669  		_ = v.Args[1]
 10670  		v_0 := v.Args[0]
 10671  		if v_0.Op != OpSB {
 10672  			break
 10673  		}
 10674  		if !(symIsRO(sym)) {
 10675  			break
 10676  		}
 10677  		v.reset(Op386MOVLconst)
 10678  		v.AuxInt = int64(read16(sym, off, config.BigEndian))
 10679  		return true
 10680  	}
 10681  	return false
 10682  }
 10683  func rewriteValue386_Op386MOVWloadidx1_0(v *Value) bool {
 10684  	// match: (MOVWloadidx1 [c] {sym} ptr (SHLLconst [1] idx) mem)
 10685  	// cond:
 10686  	// result: (MOVWloadidx2 [c] {sym} ptr idx mem)
 10687  	for {
 10688  		c := v.AuxInt
 10689  		sym := v.Aux
 10690  		mem := v.Args[2]
 10691  		ptr := v.Args[0]
 10692  		v_1 := v.Args[1]
 10693  		if v_1.Op != Op386SHLLconst {
 10694  			break
 10695  		}
 10696  		if v_1.AuxInt != 1 {
 10697  			break
 10698  		}
 10699  		idx := v_1.Args[0]
 10700  		v.reset(Op386MOVWloadidx2)
 10701  		v.AuxInt = c
 10702  		v.Aux = sym
 10703  		v.AddArg(ptr)
 10704  		v.AddArg(idx)
 10705  		v.AddArg(mem)
 10706  		return true
 10707  	}
 10708  	// match: (MOVWloadidx1 [c] {sym} (SHLLconst [1] idx) ptr mem)
 10709  	// cond:
 10710  	// result: (MOVWloadidx2 [c] {sym} ptr idx mem)
 10711  	for {
 10712  		c := v.AuxInt
 10713  		sym := v.Aux
 10714  		mem := v.Args[2]
 10715  		v_0 := v.Args[0]
 10716  		if v_0.Op != Op386SHLLconst {
 10717  			break
 10718  		}
 10719  		if v_0.AuxInt != 1 {
 10720  			break
 10721  		}
 10722  		idx := v_0.Args[0]
 10723  		ptr := v.Args[1]
 10724  		v.reset(Op386MOVWloadidx2)
 10725  		v.AuxInt = c
 10726  		v.Aux = sym
 10727  		v.AddArg(ptr)
 10728  		v.AddArg(idx)
 10729  		v.AddArg(mem)
 10730  		return true
 10731  	}
 10732  	// match: (MOVWloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem)
 10733  	// cond:
 10734  	// result: (MOVWloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
 10735  	for {
 10736  		c := v.AuxInt
 10737  		sym := v.Aux
 10738  		mem := v.Args[2]
 10739  		v_0 := v.Args[0]
 10740  		if v_0.Op != Op386ADDLconst {
 10741  			break
 10742  		}
 10743  		d := v_0.AuxInt
 10744  		ptr := v_0.Args[0]
 10745  		idx := v.Args[1]
 10746  		v.reset(Op386MOVWloadidx1)
 10747  		v.AuxInt = int64(int32(c + d))
 10748  		v.Aux = sym
 10749  		v.AddArg(ptr)
 10750  		v.AddArg(idx)
 10751  		v.AddArg(mem)
 10752  		return true
 10753  	}
 10754  	// match: (MOVWloadidx1 [c] {sym} idx (ADDLconst [d] ptr) mem)
 10755  	// cond:
 10756  	// result: (MOVWloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
 10757  	for {
 10758  		c := v.AuxInt
 10759  		sym := v.Aux
 10760  		mem := v.Args[2]
 10761  		idx := v.Args[0]
 10762  		v_1 := v.Args[1]
 10763  		if v_1.Op != Op386ADDLconst {
 10764  			break
 10765  		}
 10766  		d := v_1.AuxInt
 10767  		ptr := v_1.Args[0]
 10768  		v.reset(Op386MOVWloadidx1)
 10769  		v.AuxInt = int64(int32(c + d))
 10770  		v.Aux = sym
 10771  		v.AddArg(ptr)
 10772  		v.AddArg(idx)
 10773  		v.AddArg(mem)
 10774  		return true
 10775  	}
 10776  	// match: (MOVWloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem)
 10777  	// cond:
 10778  	// result: (MOVWloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
 10779  	for {
 10780  		c := v.AuxInt
 10781  		sym := v.Aux
 10782  		mem := v.Args[2]
 10783  		ptr := v.Args[0]
 10784  		v_1 := v.Args[1]
 10785  		if v_1.Op != Op386ADDLconst {
 10786  			break
 10787  		}
 10788  		d := v_1.AuxInt
 10789  		idx := v_1.Args[0]
 10790  		v.reset(Op386MOVWloadidx1)
 10791  		v.AuxInt = int64(int32(c + d))
 10792  		v.Aux = sym
 10793  		v.AddArg(ptr)
 10794  		v.AddArg(idx)
 10795  		v.AddArg(mem)
 10796  		return true
 10797  	}
 10798  	// match: (MOVWloadidx1 [c] {sym} (ADDLconst [d] idx) ptr mem)
 10799  	// cond:
 10800  	// result: (MOVWloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
 10801  	for {
 10802  		c := v.AuxInt
 10803  		sym := v.Aux
 10804  		mem := v.Args[2]
 10805  		v_0 := v.Args[0]
 10806  		if v_0.Op != Op386ADDLconst {
 10807  			break
 10808  		}
 10809  		d := v_0.AuxInt
 10810  		idx := v_0.Args[0]
 10811  		ptr := v.Args[1]
 10812  		v.reset(Op386MOVWloadidx1)
 10813  		v.AuxInt = int64(int32(c + d))
 10814  		v.Aux = sym
 10815  		v.AddArg(ptr)
 10816  		v.AddArg(idx)
 10817  		v.AddArg(mem)
 10818  		return true
 10819  	}
 10820  	return false
 10821  }
 10822  func rewriteValue386_Op386MOVWloadidx2_0(v *Value) bool {
 10823  	// match: (MOVWloadidx2 [c] {sym} (ADDLconst [d] ptr) idx mem)
 10824  	// cond:
 10825  	// result: (MOVWloadidx2 [int64(int32(c+d))] {sym} ptr idx mem)
 10826  	for {
 10827  		c := v.AuxInt
 10828  		sym := v.Aux
 10829  		mem := v.Args[2]
 10830  		v_0 := v.Args[0]
 10831  		if v_0.Op != Op386ADDLconst {
 10832  			break
 10833  		}
 10834  		d := v_0.AuxInt
 10835  		ptr := v_0.Args[0]
 10836  		idx := v.Args[1]
 10837  		v.reset(Op386MOVWloadidx2)
 10838  		v.AuxInt = int64(int32(c + d))
 10839  		v.Aux = sym
 10840  		v.AddArg(ptr)
 10841  		v.AddArg(idx)
 10842  		v.AddArg(mem)
 10843  		return true
 10844  	}
 10845  	// match: (MOVWloadidx2 [c] {sym} ptr (ADDLconst [d] idx) mem)
 10846  	// cond:
 10847  	// result: (MOVWloadidx2 [int64(int32(c+2*d))] {sym} ptr idx mem)
 10848  	for {
 10849  		c := v.AuxInt
 10850  		sym := v.Aux
 10851  		mem := v.Args[2]
 10852  		ptr := v.Args[0]
 10853  		v_1 := v.Args[1]
 10854  		if v_1.Op != Op386ADDLconst {
 10855  			break
 10856  		}
 10857  		d := v_1.AuxInt
 10858  		idx := v_1.Args[0]
 10859  		v.reset(Op386MOVWloadidx2)
 10860  		v.AuxInt = int64(int32(c + 2*d))
 10861  		v.Aux = sym
 10862  		v.AddArg(ptr)
 10863  		v.AddArg(idx)
 10864  		v.AddArg(mem)
 10865  		return true
 10866  	}
 10867  	return false
 10868  }
 10869  func rewriteValue386_Op386MOVWstore_0(v *Value) bool {
 10870  	b := v.Block
 10871  	config := b.Func.Config
 10872  	// match: (MOVWstore [off] {sym} ptr (MOVWLSX x) mem)
 10873  	// cond:
 10874  	// result: (MOVWstore [off] {sym} ptr x mem)
 10875  	for {
 10876  		off := v.AuxInt
 10877  		sym := v.Aux
 10878  		mem := v.Args[2]
 10879  		ptr := v.Args[0]
 10880  		v_1 := v.Args[1]
 10881  		if v_1.Op != Op386MOVWLSX {
 10882  			break
 10883  		}
 10884  		x := v_1.Args[0]
 10885  		v.reset(Op386MOVWstore)
 10886  		v.AuxInt = off
 10887  		v.Aux = sym
 10888  		v.AddArg(ptr)
 10889  		v.AddArg(x)
 10890  		v.AddArg(mem)
 10891  		return true
 10892  	}
 10893  	// match: (MOVWstore [off] {sym} ptr (MOVWLZX x) mem)
 10894  	// cond:
 10895  	// result: (MOVWstore [off] {sym} ptr x mem)
 10896  	for {
 10897  		off := v.AuxInt
 10898  		sym := v.Aux
 10899  		mem := v.Args[2]
 10900  		ptr := v.Args[0]
 10901  		v_1 := v.Args[1]
 10902  		if v_1.Op != Op386MOVWLZX {
 10903  			break
 10904  		}
 10905  		x := v_1.Args[0]
 10906  		v.reset(Op386MOVWstore)
 10907  		v.AuxInt = off
 10908  		v.Aux = sym
 10909  		v.AddArg(ptr)
 10910  		v.AddArg(x)
 10911  		v.AddArg(mem)
 10912  		return true
 10913  	}
 10914  	// match: (MOVWstore [off1] {sym} (ADDLconst [off2] ptr) val mem)
 10915  	// cond: is32Bit(off1+off2)
 10916  	// result: (MOVWstore [off1+off2] {sym} ptr val mem)
 10917  	for {
 10918  		off1 := v.AuxInt
 10919  		sym := v.Aux
 10920  		mem := v.Args[2]
 10921  		v_0 := v.Args[0]
 10922  		if v_0.Op != Op386ADDLconst {
 10923  			break
 10924  		}
 10925  		off2 := v_0.AuxInt
 10926  		ptr := v_0.Args[0]
 10927  		val := v.Args[1]
 10928  		if !(is32Bit(off1 + off2)) {
 10929  			break
 10930  		}
 10931  		v.reset(Op386MOVWstore)
 10932  		v.AuxInt = off1 + off2
 10933  		v.Aux = sym
 10934  		v.AddArg(ptr)
 10935  		v.AddArg(val)
 10936  		v.AddArg(mem)
 10937  		return true
 10938  	}
 10939  	// match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem)
 10940  	// cond: validOff(off)
 10941  	// result: (MOVWstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem)
 10942  	for {
 10943  		off := v.AuxInt
 10944  		sym := v.Aux
 10945  		mem := v.Args[2]
 10946  		ptr := v.Args[0]
 10947  		v_1 := v.Args[1]
 10948  		if v_1.Op != Op386MOVLconst {
 10949  			break
 10950  		}
 10951  		c := v_1.AuxInt
 10952  		if !(validOff(off)) {
 10953  			break
 10954  		}
 10955  		v.reset(Op386MOVWstoreconst)
 10956  		v.AuxInt = makeValAndOff(int64(int16(c)), off)
 10957  		v.Aux = sym
 10958  		v.AddArg(ptr)
 10959  		v.AddArg(mem)
 10960  		return true
 10961  	}
 10962  	// match: (MOVWstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
 10963  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
 10964  	// result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
 10965  	for {
 10966  		off1 := v.AuxInt
 10967  		sym1 := v.Aux
 10968  		mem := v.Args[2]
 10969  		v_0 := v.Args[0]
 10970  		if v_0.Op != Op386LEAL {
 10971  			break
 10972  		}
 10973  		off2 := v_0.AuxInt
 10974  		sym2 := v_0.Aux
 10975  		base := v_0.Args[0]
 10976  		val := v.Args[1]
 10977  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
 10978  			break
 10979  		}
 10980  		v.reset(Op386MOVWstore)
 10981  		v.AuxInt = off1 + off2
 10982  		v.Aux = mergeSym(sym1, sym2)
 10983  		v.AddArg(base)
 10984  		v.AddArg(val)
 10985  		v.AddArg(mem)
 10986  		return true
 10987  	}
 10988  	// match: (MOVWstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem)
 10989  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10990  	// result: (MOVWstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
 10991  	for {
 10992  		off1 := v.AuxInt
 10993  		sym1 := v.Aux
 10994  		mem := v.Args[2]
 10995  		v_0 := v.Args[0]
 10996  		if v_0.Op != Op386LEAL1 {
 10997  			break
 10998  		}
 10999  		off2 := v_0.AuxInt
 11000  		sym2 := v_0.Aux
 11001  		idx := v_0.Args[1]
 11002  		ptr := v_0.Args[0]
 11003  		val := v.Args[1]
 11004  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 11005  			break
 11006  		}
 11007  		v.reset(Op386MOVWstoreidx1)
 11008  		v.AuxInt = off1 + off2
 11009  		v.Aux = mergeSym(sym1, sym2)
 11010  		v.AddArg(ptr)
 11011  		v.AddArg(idx)
 11012  		v.AddArg(val)
 11013  		v.AddArg(mem)
 11014  		return true
 11015  	}
 11016  	// match: (MOVWstore [off1] {sym1} (LEAL2 [off2] {sym2} ptr idx) val mem)
 11017  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 11018  	// result: (MOVWstoreidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
 11019  	for {
 11020  		off1 := v.AuxInt
 11021  		sym1 := v.Aux
 11022  		mem := v.Args[2]
 11023  		v_0 := v.Args[0]
 11024  		if v_0.Op != Op386LEAL2 {
 11025  			break
 11026  		}
 11027  		off2 := v_0.AuxInt
 11028  		sym2 := v_0.Aux
 11029  		idx := v_0.Args[1]
 11030  		ptr := v_0.Args[0]
 11031  		val := v.Args[1]
 11032  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 11033  			break
 11034  		}
 11035  		v.reset(Op386MOVWstoreidx2)
 11036  		v.AuxInt = off1 + off2
 11037  		v.Aux = mergeSym(sym1, sym2)
 11038  		v.AddArg(ptr)
 11039  		v.AddArg(idx)
 11040  		v.AddArg(val)
 11041  		v.AddArg(mem)
 11042  		return true
 11043  	}
 11044  	// match: (MOVWstore [off] {sym} (ADDL ptr idx) val mem)
 11045  	// cond: ptr.Op != OpSB
 11046  	// result: (MOVWstoreidx1 [off] {sym} ptr idx val mem)
 11047  	for {
 11048  		off := v.AuxInt
 11049  		sym := v.Aux
 11050  		mem := v.Args[2]
 11051  		v_0 := v.Args[0]
 11052  		if v_0.Op != Op386ADDL {
 11053  			break
 11054  		}
 11055  		idx := v_0.Args[1]
 11056  		ptr := v_0.Args[0]
 11057  		val := v.Args[1]
 11058  		if !(ptr.Op != OpSB) {
 11059  			break
 11060  		}
 11061  		v.reset(Op386MOVWstoreidx1)
 11062  		v.AuxInt = off
 11063  		v.Aux = sym
 11064  		v.AddArg(ptr)
 11065  		v.AddArg(idx)
 11066  		v.AddArg(val)
 11067  		v.AddArg(mem)
 11068  		return true
 11069  	}
 11070  	// match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem))
 11071  	// cond: x.Uses == 1 && clobber(x)
 11072  	// result: (MOVLstore [i-2] {s} p w mem)
 11073  	for {
 11074  		i := v.AuxInt
 11075  		s := v.Aux
 11076  		_ = v.Args[2]
 11077  		p := v.Args[0]
 11078  		v_1 := v.Args[1]
 11079  		if v_1.Op != Op386SHRLconst {
 11080  			break
 11081  		}
 11082  		if v_1.AuxInt != 16 {
 11083  			break
 11084  		}
 11085  		w := v_1.Args[0]
 11086  		x := v.Args[2]
 11087  		if x.Op != Op386MOVWstore {
 11088  			break
 11089  		}
 11090  		if x.AuxInt != i-2 {
 11091  			break
 11092  		}
 11093  		if x.Aux != s {
 11094  			break
 11095  		}
 11096  		mem := x.Args[2]
 11097  		if p != x.Args[0] {
 11098  			break
 11099  		}
 11100  		if w != x.Args[1] {
 11101  			break
 11102  		}
 11103  		if !(x.Uses == 1 && clobber(x)) {
 11104  			break
 11105  		}
 11106  		v.reset(Op386MOVLstore)
 11107  		v.AuxInt = i - 2
 11108  		v.Aux = s
 11109  		v.AddArg(p)
 11110  		v.AddArg(w)
 11111  		v.AddArg(mem)
 11112  		return true
 11113  	}
 11114  	// match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem))
 11115  	// cond: x.Uses == 1 && clobber(x)
 11116  	// result: (MOVLstore [i-2] {s} p w0 mem)
 11117  	for {
 11118  		i := v.AuxInt
 11119  		s := v.Aux
 11120  		_ = v.Args[2]
 11121  		p := v.Args[0]
 11122  		v_1 := v.Args[1]
 11123  		if v_1.Op != Op386SHRLconst {
 11124  			break
 11125  		}
 11126  		j := v_1.AuxInt
 11127  		w := v_1.Args[0]
 11128  		x := v.Args[2]
 11129  		if x.Op != Op386MOVWstore {
 11130  			break
 11131  		}
 11132  		if x.AuxInt != i-2 {
 11133  			break
 11134  		}
 11135  		if x.Aux != s {
 11136  			break
 11137  		}
 11138  		mem := x.Args[2]
 11139  		if p != x.Args[0] {
 11140  			break
 11141  		}
 11142  		w0 := x.Args[1]
 11143  		if w0.Op != Op386SHRLconst {
 11144  			break
 11145  		}
 11146  		if w0.AuxInt != j-16 {
 11147  			break
 11148  		}
 11149  		if w != w0.Args[0] {
 11150  			break
 11151  		}
 11152  		if !(x.Uses == 1 && clobber(x)) {
 11153  			break
 11154  		}
 11155  		v.reset(Op386MOVLstore)
 11156  		v.AuxInt = i - 2
 11157  		v.Aux = s
 11158  		v.AddArg(p)
 11159  		v.AddArg(w0)
 11160  		v.AddArg(mem)
 11161  		return true
 11162  	}
 11163  	return false
 11164  }
 11165  func rewriteValue386_Op386MOVWstoreconst_0(v *Value) bool {
 11166  	b := v.Block
 11167  	config := b.Func.Config
 11168  	// match: (MOVWstoreconst [sc] {s} (ADDLconst [off] ptr) mem)
 11169  	// cond: ValAndOff(sc).canAdd(off)
 11170  	// result: (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem)
 11171  	for {
 11172  		sc := v.AuxInt
 11173  		s := v.Aux
 11174  		mem := v.Args[1]
 11175  		v_0 := v.Args[0]
 11176  		if v_0.Op != Op386ADDLconst {
 11177  			break
 11178  		}
 11179  		off := v_0.AuxInt
 11180  		ptr := v_0.Args[0]
 11181  		if !(ValAndOff(sc).canAdd(off)) {
 11182  			break
 11183  		}
 11184  		v.reset(Op386MOVWstoreconst)
 11185  		v.AuxInt = ValAndOff(sc).add(off)
 11186  		v.Aux = s
 11187  		v.AddArg(ptr)
 11188  		v.AddArg(mem)
 11189  		return true
 11190  	}
 11191  	// match: (MOVWstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem)
 11192  	// cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
 11193  	// result: (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem)
 11194  	for {
 11195  		sc := v.AuxInt
 11196  		sym1 := v.Aux
 11197  		mem := v.Args[1]
 11198  		v_0 := v.Args[0]
 11199  		if v_0.Op != Op386LEAL {
 11200  			break
 11201  		}
 11202  		off := v_0.AuxInt
 11203  		sym2 := v_0.Aux
 11204  		ptr := v_0.Args[0]
 11205  		if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
 11206  			break
 11207  		}
 11208  		v.reset(Op386MOVWstoreconst)
 11209  		v.AuxInt = ValAndOff(sc).add(off)
 11210  		v.Aux = mergeSym(sym1, sym2)
 11211  		v.AddArg(ptr)
 11212  		v.AddArg(mem)
 11213  		return true
 11214  	}
 11215  	// match: (MOVWstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem)
 11216  	// cond: canMergeSym(sym1, sym2)
 11217  	// result: (MOVWstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem)
 11218  	for {
 11219  		x := v.AuxInt
 11220  		sym1 := v.Aux
 11221  		mem := v.Args[1]
 11222  		v_0 := v.Args[0]
 11223  		if v_0.Op != Op386LEAL1 {
 11224  			break
 11225  		}
 11226  		off := v_0.AuxInt
 11227  		sym2 := v_0.Aux
 11228  		idx := v_0.Args[1]
 11229  		ptr := v_0.Args[0]
 11230  		if !(canMergeSym(sym1, sym2)) {
 11231  			break
 11232  		}
 11233  		v.reset(Op386MOVWstoreconstidx1)
 11234  		v.AuxInt = ValAndOff(x).add(off)
 11235  		v.Aux = mergeSym(sym1, sym2)
 11236  		v.AddArg(ptr)
 11237  		v.AddArg(idx)
 11238  		v.AddArg(mem)
 11239  		return true
 11240  	}
 11241  	// match: (MOVWstoreconst [x] {sym1} (LEAL2 [off] {sym2} ptr idx) mem)
 11242  	// cond: canMergeSym(sym1, sym2)
 11243  	// result: (MOVWstoreconstidx2 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem)
 11244  	for {
 11245  		x := v.AuxInt
 11246  		sym1 := v.Aux
 11247  		mem := v.Args[1]
 11248  		v_0 := v.Args[0]
 11249  		if v_0.Op != Op386LEAL2 {
 11250  			break
 11251  		}
 11252  		off := v_0.AuxInt
 11253  		sym2 := v_0.Aux
 11254  		idx := v_0.Args[1]
 11255  		ptr := v_0.Args[0]
 11256  		if !(canMergeSym(sym1, sym2)) {
 11257  			break
 11258  		}
 11259  		v.reset(Op386MOVWstoreconstidx2)
 11260  		v.AuxInt = ValAndOff(x).add(off)
 11261  		v.Aux = mergeSym(sym1, sym2)
 11262  		v.AddArg(ptr)
 11263  		v.AddArg(idx)
 11264  		v.AddArg(mem)
 11265  		return true
 11266  	}
 11267  	// match: (MOVWstoreconst [x] {sym} (ADDL ptr idx) mem)
 11268  	// cond:
 11269  	// result: (MOVWstoreconstidx1 [x] {sym} ptr idx mem)
 11270  	for {
 11271  		x := v.AuxInt
 11272  		sym := v.Aux
 11273  		mem := v.Args[1]
 11274  		v_0 := v.Args[0]
 11275  		if v_0.Op != Op386ADDL {
 11276  			break
 11277  		}
 11278  		idx := v_0.Args[1]
 11279  		ptr := v_0.Args[0]
 11280  		v.reset(Op386MOVWstoreconstidx1)
 11281  		v.AuxInt = x
 11282  		v.Aux = sym
 11283  		v.AddArg(ptr)
 11284  		v.AddArg(idx)
 11285  		v.AddArg(mem)
 11286  		return true
 11287  	}
 11288  	// match: (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem))
 11289  	// cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x)
 11290  	// result: (MOVLstoreconst [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p mem)
 11291  	for {
 11292  		c := v.AuxInt
 11293  		s := v.Aux
 11294  		_ = v.Args[1]
 11295  		p := v.Args[0]
 11296  		x := v.Args[1]
 11297  		if x.Op != Op386MOVWstoreconst {
 11298  			break
 11299  		}
 11300  		a := x.AuxInt
 11301  		if x.Aux != s {
 11302  			break
 11303  		}
 11304  		mem := x.Args[1]
 11305  		if p != x.Args[0] {
 11306  			break
 11307  		}
 11308  		if !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) {
 11309  			break
 11310  		}
 11311  		v.reset(Op386MOVLstoreconst)
 11312  		v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off())
 11313  		v.Aux = s
 11314  		v.AddArg(p)
 11315  		v.AddArg(mem)
 11316  		return true
 11317  	}
 11318  	// match: (MOVWstoreconst [a] {s} p x:(MOVWstoreconst [c] {s} p mem))
 11319  	// cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x)
 11320  	// result: (MOVLstoreconst [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p mem)
 11321  	for {
 11322  		a := v.AuxInt
 11323  		s := v.Aux
 11324  		_ = v.Args[1]
 11325  		p := v.Args[0]
 11326  		x := v.Args[1]
 11327  		if x.Op != Op386MOVWstoreconst {
 11328  			break
 11329  		}
 11330  		c := x.AuxInt
 11331  		if x.Aux != s {
 11332  			break
 11333  		}
 11334  		mem := x.Args[1]
 11335  		if p != x.Args[0] {
 11336  			break
 11337  		}
 11338  		if !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) {
 11339  			break
 11340  		}
 11341  		v.reset(Op386MOVLstoreconst)
 11342  		v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off())
 11343  		v.Aux = s
 11344  		v.AddArg(p)
 11345  		v.AddArg(mem)
 11346  		return true
 11347  	}
 11348  	return false
 11349  }
 11350  func rewriteValue386_Op386MOVWstoreconstidx1_0(v *Value) bool {
 11351  	// match: (MOVWstoreconstidx1 [c] {sym} ptr (SHLLconst [1] idx) mem)
 11352  	// cond:
 11353  	// result: (MOVWstoreconstidx2 [c] {sym} ptr idx mem)
 11354  	for {
 11355  		c := v.AuxInt
 11356  		sym := v.Aux
 11357  		mem := v.Args[2]
 11358  		ptr := v.Args[0]
 11359  		v_1 := v.Args[1]
 11360  		if v_1.Op != Op386SHLLconst {
 11361  			break
 11362  		}
 11363  		if v_1.AuxInt != 1 {
 11364  			break
 11365  		}
 11366  		idx := v_1.Args[0]
 11367  		v.reset(Op386MOVWstoreconstidx2)
 11368  		v.AuxInt = c
 11369  		v.Aux = sym
 11370  		v.AddArg(ptr)
 11371  		v.AddArg(idx)
 11372  		v.AddArg(mem)
 11373  		return true
 11374  	}
 11375  	// match: (MOVWstoreconstidx1 [x] {sym} (ADDLconst [c] ptr) idx mem)
 11376  	// cond:
 11377  	// result: (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem)
 11378  	for {
 11379  		x := v.AuxInt
 11380  		sym := v.Aux
 11381  		mem := v.Args[2]
 11382  		v_0 := v.Args[0]
 11383  		if v_0.Op != Op386ADDLconst {
 11384  			break
 11385  		}
 11386  		c := v_0.AuxInt
 11387  		ptr := v_0.Args[0]
 11388  		idx := v.Args[1]
 11389  		v.reset(Op386MOVWstoreconstidx1)
 11390  		v.AuxInt = ValAndOff(x).add(c)
 11391  		v.Aux = sym
 11392  		v.AddArg(ptr)
 11393  		v.AddArg(idx)
 11394  		v.AddArg(mem)
 11395  		return true
 11396  	}
 11397  	// match: (MOVWstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem)
 11398  	// cond:
 11399  	// result: (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem)
 11400  	for {
 11401  		x := v.AuxInt
 11402  		sym := v.Aux
 11403  		mem := v.Args[2]
 11404  		ptr := v.Args[0]
 11405  		v_1 := v.Args[1]
 11406  		if v_1.Op != Op386ADDLconst {
 11407  			break
 11408  		}
 11409  		c := v_1.AuxInt
 11410  		idx := v_1.Args[0]
 11411  		v.reset(Op386MOVWstoreconstidx1)
 11412  		v.AuxInt = ValAndOff(x).add(c)
 11413  		v.Aux = sym
 11414  		v.AddArg(ptr)
 11415  		v.AddArg(idx)
 11416  		v.AddArg(mem)
 11417  		return true
 11418  	}
 11419  	// match: (MOVWstoreconstidx1 [c] {s} p i x:(MOVWstoreconstidx1 [a] {s} p i mem))
 11420  	// cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x)
 11421  	// result: (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p i mem)
 11422  	for {
 11423  		c := v.AuxInt
 11424  		s := v.Aux
 11425  		_ = v.Args[2]
 11426  		p := v.Args[0]
 11427  		i := v.Args[1]
 11428  		x := v.Args[2]
 11429  		if x.Op != Op386MOVWstoreconstidx1 {
 11430  			break
 11431  		}
 11432  		a := x.AuxInt
 11433  		if x.Aux != s {
 11434  			break
 11435  		}
 11436  		mem := x.Args[2]
 11437  		if p != x.Args[0] {
 11438  			break
 11439  		}
 11440  		if i != x.Args[1] {
 11441  			break
 11442  		}
 11443  		if !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) {
 11444  			break
 11445  		}
 11446  		v.reset(Op386MOVLstoreconstidx1)
 11447  		v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off())
 11448  		v.Aux = s
 11449  		v.AddArg(p)
 11450  		v.AddArg(i)
 11451  		v.AddArg(mem)
 11452  		return true
 11453  	}
 11454  	return false
 11455  }
 11456  func rewriteValue386_Op386MOVWstoreconstidx2_0(v *Value) bool {
 11457  	b := v.Block
 11458  	// match: (MOVWstoreconstidx2 [x] {sym} (ADDLconst [c] ptr) idx mem)
 11459  	// cond:
 11460  	// result: (MOVWstoreconstidx2 [ValAndOff(x).add(c)] {sym} ptr idx mem)
 11461  	for {
 11462  		x := v.AuxInt
 11463  		sym := v.Aux
 11464  		mem := v.Args[2]
 11465  		v_0 := v.Args[0]
 11466  		if v_0.Op != Op386ADDLconst {
 11467  			break
 11468  		}
 11469  		c := v_0.AuxInt
 11470  		ptr := v_0.Args[0]
 11471  		idx := v.Args[1]
 11472  		v.reset(Op386MOVWstoreconstidx2)
 11473  		v.AuxInt = ValAndOff(x).add(c)
 11474  		v.Aux = sym
 11475  		v.AddArg(ptr)
 11476  		v.AddArg(idx)
 11477  		v.AddArg(mem)
 11478  		return true
 11479  	}
 11480  	// match: (MOVWstoreconstidx2 [x] {sym} ptr (ADDLconst [c] idx) mem)
 11481  	// cond:
 11482  	// result: (MOVWstoreconstidx2 [ValAndOff(x).add(2*c)] {sym} ptr idx mem)
 11483  	for {
 11484  		x := v.AuxInt
 11485  		sym := v.Aux
 11486  		mem := v.Args[2]
 11487  		ptr := v.Args[0]
 11488  		v_1 := v.Args[1]
 11489  		if v_1.Op != Op386ADDLconst {
 11490  			break
 11491  		}
 11492  		c := v_1.AuxInt
 11493  		idx := v_1.Args[0]
 11494  		v.reset(Op386MOVWstoreconstidx2)
 11495  		v.AuxInt = ValAndOff(x).add(2 * c)
 11496  		v.Aux = sym
 11497  		v.AddArg(ptr)
 11498  		v.AddArg(idx)
 11499  		v.AddArg(mem)
 11500  		return true
 11501  	}
 11502  	// match: (MOVWstoreconstidx2 [c] {s} p i x:(MOVWstoreconstidx2 [a] {s} p i mem))
 11503  	// cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x)
 11504  	// result: (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p (SHLLconst <i.Type> [1] i) mem)
 11505  	for {
 11506  		c := v.AuxInt
 11507  		s := v.Aux
 11508  		_ = v.Args[2]
 11509  		p := v.Args[0]
 11510  		i := v.Args[1]
 11511  		x := v.Args[2]
 11512  		if x.Op != Op386MOVWstoreconstidx2 {
 11513  			break
 11514  		}
 11515  		a := x.AuxInt
 11516  		if x.Aux != s {
 11517  			break
 11518  		}
 11519  		mem := x.Args[2]
 11520  		if p != x.Args[0] {
 11521  			break
 11522  		}
 11523  		if i != x.Args[1] {
 11524  			break
 11525  		}
 11526  		if !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) {
 11527  			break
 11528  		}
 11529  		v.reset(Op386MOVLstoreconstidx1)
 11530  		v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off())
 11531  		v.Aux = s
 11532  		v.AddArg(p)
 11533  		v0 := b.NewValue0(v.Pos, Op386SHLLconst, i.Type)
 11534  		v0.AuxInt = 1
 11535  		v0.AddArg(i)
 11536  		v.AddArg(v0)
 11537  		v.AddArg(mem)
 11538  		return true
 11539  	}
 11540  	return false
 11541  }
 11542  func rewriteValue386_Op386MOVWstoreidx1_0(v *Value) bool {
 11543  	// match: (MOVWstoreidx1 [c] {sym} ptr (SHLLconst [1] idx) val mem)
 11544  	// cond:
 11545  	// result: (MOVWstoreidx2 [c] {sym} ptr idx val mem)
 11546  	for {
 11547  		c := v.AuxInt
 11548  		sym := v.Aux
 11549  		mem := v.Args[3]
 11550  		ptr := v.Args[0]
 11551  		v_1 := v.Args[1]
 11552  		if v_1.Op != Op386SHLLconst {
 11553  			break
 11554  		}
 11555  		if v_1.AuxInt != 1 {
 11556  			break
 11557  		}
 11558  		idx := v_1.Args[0]
 11559  		val := v.Args[2]
 11560  		v.reset(Op386MOVWstoreidx2)
 11561  		v.AuxInt = c
 11562  		v.Aux = sym
 11563  		v.AddArg(ptr)
 11564  		v.AddArg(idx)
 11565  		v.AddArg(val)
 11566  		v.AddArg(mem)
 11567  		return true
 11568  	}
 11569  	// match: (MOVWstoreidx1 [c] {sym} (SHLLconst [1] idx) ptr val mem)
 11570  	// cond:
 11571  	// result: (MOVWstoreidx2 [c] {sym} ptr idx val mem)
 11572  	for {
 11573  		c := v.AuxInt
 11574  		sym := v.Aux
 11575  		mem := v.Args[3]
 11576  		v_0 := v.Args[0]
 11577  		if v_0.Op != Op386SHLLconst {
 11578  			break
 11579  		}
 11580  		if v_0.AuxInt != 1 {
 11581  			break
 11582  		}
 11583  		idx := v_0.Args[0]
 11584  		ptr := v.Args[1]
 11585  		val := v.Args[2]
 11586  		v.reset(Op386MOVWstoreidx2)
 11587  		v.AuxInt = c
 11588  		v.Aux = sym
 11589  		v.AddArg(ptr)
 11590  		v.AddArg(idx)
 11591  		v.AddArg(val)
 11592  		v.AddArg(mem)
 11593  		return true
 11594  	}
 11595  	// match: (MOVWstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem)
 11596  	// cond:
 11597  	// result: (MOVWstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
 11598  	for {
 11599  		c := v.AuxInt
 11600  		sym := v.Aux
 11601  		mem := v.Args[3]
 11602  		v_0 := v.Args[0]
 11603  		if v_0.Op != Op386ADDLconst {
 11604  			break
 11605  		}
 11606  		d := v_0.AuxInt
 11607  		ptr := v_0.Args[0]
 11608  		idx := v.Args[1]
 11609  		val := v.Args[2]
 11610  		v.reset(Op386MOVWstoreidx1)
 11611  		v.AuxInt = int64(int32(c + d))
 11612  		v.Aux = sym
 11613  		v.AddArg(ptr)
 11614  		v.AddArg(idx)
 11615  		v.AddArg(val)
 11616  		v.AddArg(mem)
 11617  		return true
 11618  	}
 11619  	// match: (MOVWstoreidx1 [c] {sym} idx (ADDLconst [d] ptr) val mem)
 11620  	// cond:
 11621  	// result: (MOVWstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
 11622  	for {
 11623  		c := v.AuxInt
 11624  		sym := v.Aux
 11625  		mem := v.Args[3]
 11626  		idx := v.Args[0]
 11627  		v_1 := v.Args[1]
 11628  		if v_1.Op != Op386ADDLconst {
 11629  			break
 11630  		}
 11631  		d := v_1.AuxInt
 11632  		ptr := v_1.Args[0]
 11633  		val := v.Args[2]
 11634  		v.reset(Op386MOVWstoreidx1)
 11635  		v.AuxInt = int64(int32(c + d))
 11636  		v.Aux = sym
 11637  		v.AddArg(ptr)
 11638  		v.AddArg(idx)
 11639  		v.AddArg(val)
 11640  		v.AddArg(mem)
 11641  		return true
 11642  	}
 11643  	// match: (MOVWstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem)
 11644  	// cond:
 11645  	// result: (MOVWstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
 11646  	for {
 11647  		c := v.AuxInt
 11648  		sym := v.Aux
 11649  		mem := v.Args[3]
 11650  		ptr := v.Args[0]
 11651  		v_1 := v.Args[1]
 11652  		if v_1.Op != Op386ADDLconst {
 11653  			break
 11654  		}
 11655  		d := v_1.AuxInt
 11656  		idx := v_1.Args[0]
 11657  		val := v.Args[2]
 11658  		v.reset(Op386MOVWstoreidx1)
 11659  		v.AuxInt = int64(int32(c + d))
 11660  		v.Aux = sym
 11661  		v.AddArg(ptr)
 11662  		v.AddArg(idx)
 11663  		v.AddArg(val)
 11664  		v.AddArg(mem)
 11665  		return true
 11666  	}
 11667  	// match: (MOVWstoreidx1 [c] {sym} (ADDLconst [d] idx) ptr val mem)
 11668  	// cond:
 11669  	// result: (MOVWstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
 11670  	for {
 11671  		c := v.AuxInt
 11672  		sym := v.Aux
 11673  		mem := v.Args[3]
 11674  		v_0 := v.Args[0]
 11675  		if v_0.Op != Op386ADDLconst {
 11676  			break
 11677  		}
 11678  		d := v_0.AuxInt
 11679  		idx := v_0.Args[0]
 11680  		ptr := v.Args[1]
 11681  		val := v.Args[2]
 11682  		v.reset(Op386MOVWstoreidx1)
 11683  		v.AuxInt = int64(int32(c + d))
 11684  		v.Aux = sym
 11685  		v.AddArg(ptr)
 11686  		v.AddArg(idx)
 11687  		v.AddArg(val)
 11688  		v.AddArg(mem)
 11689  		return true
 11690  	}
 11691  	// match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem))
 11692  	// cond: x.Uses == 1 && clobber(x)
 11693  	// result: (MOVLstoreidx1 [i-2] {s} p idx w mem)
 11694  	for {
 11695  		i := v.AuxInt
 11696  		s := v.Aux
 11697  		_ = v.Args[3]
 11698  		p := v.Args[0]
 11699  		idx := v.Args[1]
 11700  		v_2 := v.Args[2]
 11701  		if v_2.Op != Op386SHRLconst {
 11702  			break
 11703  		}
 11704  		if v_2.AuxInt != 16 {
 11705  			break
 11706  		}
 11707  		w := v_2.Args[0]
 11708  		x := v.Args[3]
 11709  		if x.Op != Op386MOVWstoreidx1 {
 11710  			break
 11711  		}
 11712  		if x.AuxInt != i-2 {
 11713  			break
 11714  		}
 11715  		if x.Aux != s {
 11716  			break
 11717  		}
 11718  		mem := x.Args[3]
 11719  		if p != x.Args[0] {
 11720  			break
 11721  		}
 11722  		if idx != x.Args[1] {
 11723  			break
 11724  		}
 11725  		if w != x.Args[2] {
 11726  			break
 11727  		}
 11728  		if !(x.Uses == 1 && clobber(x)) {
 11729  			break
 11730  		}
 11731  		v.reset(Op386MOVLstoreidx1)
 11732  		v.AuxInt = i - 2
 11733  		v.Aux = s
 11734  		v.AddArg(p)
 11735  		v.AddArg(idx)
 11736  		v.AddArg(w)
 11737  		v.AddArg(mem)
 11738  		return true
 11739  	}
 11740  	// match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} idx p w mem))
 11741  	// cond: x.Uses == 1 && clobber(x)
 11742  	// result: (MOVLstoreidx1 [i-2] {s} p idx w mem)
 11743  	for {
 11744  		i := v.AuxInt
 11745  		s := v.Aux
 11746  		_ = v.Args[3]
 11747  		p := v.Args[0]
 11748  		idx := v.Args[1]
 11749  		v_2 := v.Args[2]
 11750  		if v_2.Op != Op386SHRLconst {
 11751  			break
 11752  		}
 11753  		if v_2.AuxInt != 16 {
 11754  			break
 11755  		}
 11756  		w := v_2.Args[0]
 11757  		x := v.Args[3]
 11758  		if x.Op != Op386MOVWstoreidx1 {
 11759  			break
 11760  		}
 11761  		if x.AuxInt != i-2 {
 11762  			break
 11763  		}
 11764  		if x.Aux != s {
 11765  			break
 11766  		}
 11767  		mem := x.Args[3]
 11768  		if idx != x.Args[0] {
 11769  			break
 11770  		}
 11771  		if p != x.Args[1] {
 11772  			break
 11773  		}
 11774  		if w != x.Args[2] {
 11775  			break
 11776  		}
 11777  		if !(x.Uses == 1 && clobber(x)) {
 11778  			break
 11779  		}
 11780  		v.reset(Op386MOVLstoreidx1)
 11781  		v.AuxInt = i - 2
 11782  		v.Aux = s
 11783  		v.AddArg(p)
 11784  		v.AddArg(idx)
 11785  		v.AddArg(w)
 11786  		v.AddArg(mem)
 11787  		return true
 11788  	}
 11789  	// match: (MOVWstoreidx1 [i] {s} idx p (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem))
 11790  	// cond: x.Uses == 1 && clobber(x)
 11791  	// result: (MOVLstoreidx1 [i-2] {s} p idx w mem)
 11792  	for {
 11793  		i := v.AuxInt
 11794  		s := v.Aux
 11795  		_ = v.Args[3]
 11796  		idx := v.Args[0]
 11797  		p := v.Args[1]
 11798  		v_2 := v.Args[2]
 11799  		if v_2.Op != Op386SHRLconst {
 11800  			break
 11801  		}
 11802  		if v_2.AuxInt != 16 {
 11803  			break
 11804  		}
 11805  		w := v_2.Args[0]
 11806  		x := v.Args[3]
 11807  		if x.Op != Op386MOVWstoreidx1 {
 11808  			break
 11809  		}
 11810  		if x.AuxInt != i-2 {
 11811  			break
 11812  		}
 11813  		if x.Aux != s {
 11814  			break
 11815  		}
 11816  		mem := x.Args[3]
 11817  		if p != x.Args[0] {
 11818  			break
 11819  		}
 11820  		if idx != x.Args[1] {
 11821  			break
 11822  		}
 11823  		if w != x.Args[2] {
 11824  			break
 11825  		}
 11826  		if !(x.Uses == 1 && clobber(x)) {
 11827  			break
 11828  		}
 11829  		v.reset(Op386MOVLstoreidx1)
 11830  		v.AuxInt = i - 2
 11831  		v.Aux = s
 11832  		v.AddArg(p)
 11833  		v.AddArg(idx)
 11834  		v.AddArg(w)
 11835  		v.AddArg(mem)
 11836  		return true
 11837  	}
 11838  	// match: (MOVWstoreidx1 [i] {s} idx p (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} idx p w mem))
 11839  	// cond: x.Uses == 1 && clobber(x)
 11840  	// result: (MOVLstoreidx1 [i-2] {s} p idx w mem)
 11841  	for {
 11842  		i := v.AuxInt
 11843  		s := v.Aux
 11844  		_ = v.Args[3]
 11845  		idx := v.Args[0]
 11846  		p := v.Args[1]
 11847  		v_2 := v.Args[2]
 11848  		if v_2.Op != Op386SHRLconst {
 11849  			break
 11850  		}
 11851  		if v_2.AuxInt != 16 {
 11852  			break
 11853  		}
 11854  		w := v_2.Args[0]
 11855  		x := v.Args[3]
 11856  		if x.Op != Op386MOVWstoreidx1 {
 11857  			break
 11858  		}
 11859  		if x.AuxInt != i-2 {
 11860  			break
 11861  		}
 11862  		if x.Aux != s {
 11863  			break
 11864  		}
 11865  		mem := x.Args[3]
 11866  		if idx != x.Args[0] {
 11867  			break
 11868  		}
 11869  		if p != x.Args[1] {
 11870  			break
 11871  		}
 11872  		if w != x.Args[2] {
 11873  			break
 11874  		}
 11875  		if !(x.Uses == 1 && clobber(x)) {
 11876  			break
 11877  		}
 11878  		v.reset(Op386MOVLstoreidx1)
 11879  		v.AuxInt = i - 2
 11880  		v.Aux = s
 11881  		v.AddArg(p)
 11882  		v.AddArg(idx)
 11883  		v.AddArg(w)
 11884  		v.AddArg(mem)
 11885  		return true
 11886  	}
 11887  	return false
 11888  }
 11889  func rewriteValue386_Op386MOVWstoreidx1_10(v *Value) bool {
 11890  	// match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem))
 11891  	// cond: x.Uses == 1 && clobber(x)
 11892  	// result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem)
 11893  	for {
 11894  		i := v.AuxInt
 11895  		s := v.Aux
 11896  		_ = v.Args[3]
 11897  		p := v.Args[0]
 11898  		idx := v.Args[1]
 11899  		v_2 := v.Args[2]
 11900  		if v_2.Op != Op386SHRLconst {
 11901  			break
 11902  		}
 11903  		j := v_2.AuxInt
 11904  		w := v_2.Args[0]
 11905  		x := v.Args[3]
 11906  		if x.Op != Op386MOVWstoreidx1 {
 11907  			break
 11908  		}
 11909  		if x.AuxInt != i-2 {
 11910  			break
 11911  		}
 11912  		if x.Aux != s {
 11913  			break
 11914  		}
 11915  		mem := x.Args[3]
 11916  		if p != x.Args[0] {
 11917  			break
 11918  		}
 11919  		if idx != x.Args[1] {
 11920  			break
 11921  		}
 11922  		w0 := x.Args[2]
 11923  		if w0.Op != Op386SHRLconst {
 11924  			break
 11925  		}
 11926  		if w0.AuxInt != j-16 {
 11927  			break
 11928  		}
 11929  		if w != w0.Args[0] {
 11930  			break
 11931  		}
 11932  		if !(x.Uses == 1 && clobber(x)) {
 11933  			break
 11934  		}
 11935  		v.reset(Op386MOVLstoreidx1)
 11936  		v.AuxInt = i - 2
 11937  		v.Aux = s
 11938  		v.AddArg(p)
 11939  		v.AddArg(idx)
 11940  		v.AddArg(w0)
 11941  		v.AddArg(mem)
 11942  		return true
 11943  	}
 11944  	// match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} idx p w0:(SHRLconst [j-16] w) mem))
 11945  	// cond: x.Uses == 1 && clobber(x)
 11946  	// result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem)
 11947  	for {
 11948  		i := v.AuxInt
 11949  		s := v.Aux
 11950  		_ = v.Args[3]
 11951  		p := v.Args[0]
 11952  		idx := v.Args[1]
 11953  		v_2 := v.Args[2]
 11954  		if v_2.Op != Op386SHRLconst {
 11955  			break
 11956  		}
 11957  		j := v_2.AuxInt
 11958  		w := v_2.Args[0]
 11959  		x := v.Args[3]
 11960  		if x.Op != Op386MOVWstoreidx1 {
 11961  			break
 11962  		}
 11963  		if x.AuxInt != i-2 {
 11964  			break
 11965  		}
 11966  		if x.Aux != s {
 11967  			break
 11968  		}
 11969  		mem := x.Args[3]
 11970  		if idx != x.Args[0] {
 11971  			break
 11972  		}
 11973  		if p != x.Args[1] {
 11974  			break
 11975  		}
 11976  		w0 := x.Args[2]
 11977  		if w0.Op != Op386SHRLconst {
 11978  			break
 11979  		}
 11980  		if w0.AuxInt != j-16 {
 11981  			break
 11982  		}
 11983  		if w != w0.Args[0] {
 11984  			break
 11985  		}
 11986  		if !(x.Uses == 1 && clobber(x)) {
 11987  			break
 11988  		}
 11989  		v.reset(Op386MOVLstoreidx1)
 11990  		v.AuxInt = i - 2
 11991  		v.Aux = s
 11992  		v.AddArg(p)
 11993  		v.AddArg(idx)
 11994  		v.AddArg(w0)
 11995  		v.AddArg(mem)
 11996  		return true
 11997  	}
 11998  	// match: (MOVWstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem))
 11999  	// cond: x.Uses == 1 && clobber(x)
 12000  	// result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem)
 12001  	for {
 12002  		i := v.AuxInt
 12003  		s := v.Aux
 12004  		_ = v.Args[3]
 12005  		idx := v.Args[0]
 12006  		p := v.Args[1]
 12007  		v_2 := v.Args[2]
 12008  		if v_2.Op != Op386SHRLconst {
 12009  			break
 12010  		}
 12011  		j := v_2.AuxInt
 12012  		w := v_2.Args[0]
 12013  		x := v.Args[3]
 12014  		if x.Op != Op386MOVWstoreidx1 {
 12015  			break
 12016  		}
 12017  		if x.AuxInt != i-2 {
 12018  			break
 12019  		}
 12020  		if x.Aux != s {
 12021  			break
 12022  		}
 12023  		mem := x.Args[3]
 12024  		if p != x.Args[0] {
 12025  			break
 12026  		}
 12027  		if idx != x.Args[1] {
 12028  			break
 12029  		}
 12030  		w0 := x.Args[2]
 12031  		if w0.Op != Op386SHRLconst {
 12032  			break
 12033  		}
 12034  		if w0.AuxInt != j-16 {
 12035  			break
 12036  		}
 12037  		if w != w0.Args[0] {
 12038  			break
 12039  		}
 12040  		if !(x.Uses == 1 && clobber(x)) {
 12041  			break
 12042  		}
 12043  		v.reset(Op386MOVLstoreidx1)
 12044  		v.AuxInt = i - 2
 12045  		v.Aux = s
 12046  		v.AddArg(p)
 12047  		v.AddArg(idx)
 12048  		v.AddArg(w0)
 12049  		v.AddArg(mem)
 12050  		return true
 12051  	}
 12052  	// match: (MOVWstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} idx p w0:(SHRLconst [j-16] w) mem))
 12053  	// cond: x.Uses == 1 && clobber(x)
 12054  	// result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem)
 12055  	for {
 12056  		i := v.AuxInt
 12057  		s := v.Aux
 12058  		_ = v.Args[3]
 12059  		idx := v.Args[0]
 12060  		p := v.Args[1]
 12061  		v_2 := v.Args[2]
 12062  		if v_2.Op != Op386SHRLconst {
 12063  			break
 12064  		}
 12065  		j := v_2.AuxInt
 12066  		w := v_2.Args[0]
 12067  		x := v.Args[3]
 12068  		if x.Op != Op386MOVWstoreidx1 {
 12069  			break
 12070  		}
 12071  		if x.AuxInt != i-2 {
 12072  			break
 12073  		}
 12074  		if x.Aux != s {
 12075  			break
 12076  		}
 12077  		mem := x.Args[3]
 12078  		if idx != x.Args[0] {
 12079  			break
 12080  		}
 12081  		if p != x.Args[1] {
 12082  			break
 12083  		}
 12084  		w0 := x.Args[2]
 12085  		if w0.Op != Op386SHRLconst {
 12086  			break
 12087  		}
 12088  		if w0.AuxInt != j-16 {
 12089  			break
 12090  		}
 12091  		if w != w0.Args[0] {
 12092  			break
 12093  		}
 12094  		if !(x.Uses == 1 && clobber(x)) {
 12095  			break
 12096  		}
 12097  		v.reset(Op386MOVLstoreidx1)
 12098  		v.AuxInt = i - 2
 12099  		v.Aux = s
 12100  		v.AddArg(p)
 12101  		v.AddArg(idx)
 12102  		v.AddArg(w0)
 12103  		v.AddArg(mem)
 12104  		return true
 12105  	}
 12106  	return false
 12107  }
 12108  func rewriteValue386_Op386MOVWstoreidx2_0(v *Value) bool {
 12109  	b := v.Block
 12110  	// match: (MOVWstoreidx2 [c] {sym} (ADDLconst [d] ptr) idx val mem)
 12111  	// cond:
 12112  	// result: (MOVWstoreidx2 [int64(int32(c+d))] {sym} ptr idx val mem)
 12113  	for {
 12114  		c := v.AuxInt
 12115  		sym := v.Aux
 12116  		mem := v.Args[3]
 12117  		v_0 := v.Args[0]
 12118  		if v_0.Op != Op386ADDLconst {
 12119  			break
 12120  		}
 12121  		d := v_0.AuxInt
 12122  		ptr := v_0.Args[0]
 12123  		idx := v.Args[1]
 12124  		val := v.Args[2]
 12125  		v.reset(Op386MOVWstoreidx2)
 12126  		v.AuxInt = int64(int32(c + d))
 12127  		v.Aux = sym
 12128  		v.AddArg(ptr)
 12129  		v.AddArg(idx)
 12130  		v.AddArg(val)
 12131  		v.AddArg(mem)
 12132  		return true
 12133  	}
 12134  	// match: (MOVWstoreidx2 [c] {sym} ptr (ADDLconst [d] idx) val mem)
 12135  	// cond:
 12136  	// result: (MOVWstoreidx2 [int64(int32(c+2*d))] {sym} ptr idx val mem)
 12137  	for {
 12138  		c := v.AuxInt
 12139  		sym := v.Aux
 12140  		mem := v.Args[3]
 12141  		ptr := v.Args[0]
 12142  		v_1 := v.Args[1]
 12143  		if v_1.Op != Op386ADDLconst {
 12144  			break
 12145  		}
 12146  		d := v_1.AuxInt
 12147  		idx := v_1.Args[0]
 12148  		val := v.Args[2]
 12149  		v.reset(Op386MOVWstoreidx2)
 12150  		v.AuxInt = int64(int32(c + 2*d))
 12151  		v.Aux = sym
 12152  		v.AddArg(ptr)
 12153  		v.AddArg(idx)
 12154  		v.AddArg(val)
 12155  		v.AddArg(mem)
 12156  		return true
 12157  	}
 12158  	// match: (MOVWstoreidx2 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx2 [i-2] {s} p idx w mem))
 12159  	// cond: x.Uses == 1 && clobber(x)
 12160  	// result: (MOVLstoreidx1 [i-2] {s} p (SHLLconst <idx.Type> [1] idx) w mem)
 12161  	for {
 12162  		i := v.AuxInt
 12163  		s := v.Aux
 12164  		_ = v.Args[3]
 12165  		p := v.Args[0]
 12166  		idx := v.Args[1]
 12167  		v_2 := v.Args[2]
 12168  		if v_2.Op != Op386SHRLconst {
 12169  			break
 12170  		}
 12171  		if v_2.AuxInt != 16 {
 12172  			break
 12173  		}
 12174  		w := v_2.Args[0]
 12175  		x := v.Args[3]
 12176  		if x.Op != Op386MOVWstoreidx2 {
 12177  			break
 12178  		}
 12179  		if x.AuxInt != i-2 {
 12180  			break
 12181  		}
 12182  		if x.Aux != s {
 12183  			break
 12184  		}
 12185  		mem := x.Args[3]
 12186  		if p != x.Args[0] {
 12187  			break
 12188  		}
 12189  		if idx != x.Args[1] {
 12190  			break
 12191  		}
 12192  		if w != x.Args[2] {
 12193  			break
 12194  		}
 12195  		if !(x.Uses == 1 && clobber(x)) {
 12196  			break
 12197  		}
 12198  		v.reset(Op386MOVLstoreidx1)
 12199  		v.AuxInt = i - 2
 12200  		v.Aux = s
 12201  		v.AddArg(p)
 12202  		v0 := b.NewValue0(v.Pos, Op386SHLLconst, idx.Type)
 12203  		v0.AuxInt = 1
 12204  		v0.AddArg(idx)
 12205  		v.AddArg(v0)
 12206  		v.AddArg(w)
 12207  		v.AddArg(mem)
 12208  		return true
 12209  	}
 12210  	// match: (MOVWstoreidx2 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx2 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem))
 12211  	// cond: x.Uses == 1 && clobber(x)
 12212  	// result: (MOVLstoreidx1 [i-2] {s} p (SHLLconst <idx.Type> [1] idx) w0 mem)
 12213  	for {
 12214  		i := v.AuxInt
 12215  		s := v.Aux
 12216  		_ = v.Args[3]
 12217  		p := v.Args[0]
 12218  		idx := v.Args[1]
 12219  		v_2 := v.Args[2]
 12220  		if v_2.Op != Op386SHRLconst {
 12221  			break
 12222  		}
 12223  		j := v_2.AuxInt
 12224  		w := v_2.Args[0]
 12225  		x := v.Args[3]
 12226  		if x.Op != Op386MOVWstoreidx2 {
 12227  			break
 12228  		}
 12229  		if x.AuxInt != i-2 {
 12230  			break
 12231  		}
 12232  		if x.Aux != s {
 12233  			break
 12234  		}
 12235  		mem := x.Args[3]
 12236  		if p != x.Args[0] {
 12237  			break
 12238  		}
 12239  		if idx != x.Args[1] {
 12240  			break
 12241  		}
 12242  		w0 := x.Args[2]
 12243  		if w0.Op != Op386SHRLconst {
 12244  			break
 12245  		}
 12246  		if w0.AuxInt != j-16 {
 12247  			break
 12248  		}
 12249  		if w != w0.Args[0] {
 12250  			break
 12251  		}
 12252  		if !(x.Uses == 1 && clobber(x)) {
 12253  			break
 12254  		}
 12255  		v.reset(Op386MOVLstoreidx1)
 12256  		v.AuxInt = i - 2
 12257  		v.Aux = s
 12258  		v.AddArg(p)
 12259  		v0 := b.NewValue0(v.Pos, Op386SHLLconst, idx.Type)
 12260  		v0.AuxInt = 1
 12261  		v0.AddArg(idx)
 12262  		v.AddArg(v0)
 12263  		v.AddArg(w0)
 12264  		v.AddArg(mem)
 12265  		return true
 12266  	}
 12267  	return false
 12268  }
 12269  func rewriteValue386_Op386MULL_0(v *Value) bool {
 12270  	// match: (MULL x (MOVLconst [c]))
 12271  	// cond:
 12272  	// result: (MULLconst [c] x)
 12273  	for {
 12274  		_ = v.Args[1]
 12275  		x := v.Args[0]
 12276  		v_1 := v.Args[1]
 12277  		if v_1.Op != Op386MOVLconst {
 12278  			break
 12279  		}
 12280  		c := v_1.AuxInt
 12281  		v.reset(Op386MULLconst)
 12282  		v.AuxInt = c
 12283  		v.AddArg(x)
 12284  		return true
 12285  	}
 12286  	// match: (MULL (MOVLconst [c]) x)
 12287  	// cond:
 12288  	// result: (MULLconst [c] x)
 12289  	for {
 12290  		x := v.Args[1]
 12291  		v_0 := v.Args[0]
 12292  		if v_0.Op != Op386MOVLconst {
 12293  			break
 12294  		}
 12295  		c := v_0.AuxInt
 12296  		v.reset(Op386MULLconst)
 12297  		v.AuxInt = c
 12298  		v.AddArg(x)
 12299  		return true
 12300  	}
 12301  	// match: (MULL x l:(MOVLload [off] {sym} ptr mem))
 12302  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
 12303  	// result: (MULLload x [off] {sym} ptr mem)
 12304  	for {
 12305  		_ = v.Args[1]
 12306  		x := v.Args[0]
 12307  		l := v.Args[1]
 12308  		if l.Op != Op386MOVLload {
 12309  			break
 12310  		}
 12311  		off := l.AuxInt
 12312  		sym := l.Aux
 12313  		mem := l.Args[1]
 12314  		ptr := l.Args[0]
 12315  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
 12316  			break
 12317  		}
 12318  		v.reset(Op386MULLload)
 12319  		v.AuxInt = off
 12320  		v.Aux = sym
 12321  		v.AddArg(x)
 12322  		v.AddArg(ptr)
 12323  		v.AddArg(mem)
 12324  		return true
 12325  	}
 12326  	// match: (MULL l:(MOVLload [off] {sym} ptr mem) x)
 12327  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
 12328  	// result: (MULLload x [off] {sym} ptr mem)
 12329  	for {
 12330  		x := v.Args[1]
 12331  		l := v.Args[0]
 12332  		if l.Op != Op386MOVLload {
 12333  			break
 12334  		}
 12335  		off := l.AuxInt
 12336  		sym := l.Aux
 12337  		mem := l.Args[1]
 12338  		ptr := l.Args[0]
 12339  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
 12340  			break
 12341  		}
 12342  		v.reset(Op386MULLload)
 12343  		v.AuxInt = off
 12344  		v.Aux = sym
 12345  		v.AddArg(x)
 12346  		v.AddArg(ptr)
 12347  		v.AddArg(mem)
 12348  		return true
 12349  	}
 12350  	// match: (MULL x l:(MOVLloadidx4 [off] {sym} ptr idx mem))
 12351  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
 12352  	// result: (MULLloadidx4 x [off] {sym} ptr idx mem)
 12353  	for {
 12354  		_ = v.Args[1]
 12355  		x := v.Args[0]
 12356  		l := v.Args[1]
 12357  		if l.Op != Op386MOVLloadidx4 {
 12358  			break
 12359  		}
 12360  		off := l.AuxInt
 12361  		sym := l.Aux
 12362  		mem := l.Args[2]
 12363  		ptr := l.Args[0]
 12364  		idx := l.Args[1]
 12365  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
 12366  			break
 12367  		}
 12368  		v.reset(Op386MULLloadidx4)
 12369  		v.AuxInt = off
 12370  		v.Aux = sym
 12371  		v.AddArg(x)
 12372  		v.AddArg(ptr)
 12373  		v.AddArg(idx)
 12374  		v.AddArg(mem)
 12375  		return true
 12376  	}
 12377  	// match: (MULL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x)
 12378  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
 12379  	// result: (MULLloadidx4 x [off] {sym} ptr idx mem)
 12380  	for {
 12381  		x := v.Args[1]
 12382  		l := v.Args[0]
 12383  		if l.Op != Op386MOVLloadidx4 {
 12384  			break
 12385  		}
 12386  		off := l.AuxInt
 12387  		sym := l.Aux
 12388  		mem := l.Args[2]
 12389  		ptr := l.Args[0]
 12390  		idx := l.Args[1]
 12391  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
 12392  			break
 12393  		}
 12394  		v.reset(Op386MULLloadidx4)
 12395  		v.AuxInt = off
 12396  		v.Aux = sym
 12397  		v.AddArg(x)
 12398  		v.AddArg(ptr)
 12399  		v.AddArg(idx)
 12400  		v.AddArg(mem)
 12401  		return true
 12402  	}
 12403  	return false
 12404  }
 12405  func rewriteValue386_Op386MULLconst_0(v *Value) bool {
 12406  	b := v.Block
 12407  	// match: (MULLconst [c] (MULLconst [d] x))
 12408  	// cond:
 12409  	// result: (MULLconst [int64(int32(c * d))] x)
 12410  	for {
 12411  		c := v.AuxInt
 12412  		v_0 := v.Args[0]
 12413  		if v_0.Op != Op386MULLconst {
 12414  			break
 12415  		}
 12416  		d := v_0.AuxInt
 12417  		x := v_0.Args[0]
 12418  		v.reset(Op386MULLconst)
 12419  		v.AuxInt = int64(int32(c * d))
 12420  		v.AddArg(x)
 12421  		return true
 12422  	}
 12423  	// match: (MULLconst [-9] x)
 12424  	// cond:
 12425  	// result: (NEGL (LEAL8 <v.Type> x x))
 12426  	for {
 12427  		if v.AuxInt != -9 {
 12428  			break
 12429  		}
 12430  		x := v.Args[0]
 12431  		v.reset(Op386NEGL)
 12432  		v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
 12433  		v0.AddArg(x)
 12434  		v0.AddArg(x)
 12435  		v.AddArg(v0)
 12436  		return true
 12437  	}
 12438  	// match: (MULLconst [-5] x)
 12439  	// cond:
 12440  	// result: (NEGL (LEAL4 <v.Type> x x))
 12441  	for {
 12442  		if v.AuxInt != -5 {
 12443  			break
 12444  		}
 12445  		x := v.Args[0]
 12446  		v.reset(Op386NEGL)
 12447  		v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
 12448  		v0.AddArg(x)
 12449  		v0.AddArg(x)
 12450  		v.AddArg(v0)
 12451  		return true
 12452  	}
 12453  	// match: (MULLconst [-3] x)
 12454  	// cond:
 12455  	// result: (NEGL (LEAL2 <v.Type> x x))
 12456  	for {
 12457  		if v.AuxInt != -3 {
 12458  			break
 12459  		}
 12460  		x := v.Args[0]
 12461  		v.reset(Op386NEGL)
 12462  		v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
 12463  		v0.AddArg(x)
 12464  		v0.AddArg(x)
 12465  		v.AddArg(v0)
 12466  		return true
 12467  	}
 12468  	// match: (MULLconst [-1] x)
 12469  	// cond:
 12470  	// result: (NEGL x)
 12471  	for {
 12472  		if v.AuxInt != -1 {
 12473  			break
 12474  		}
 12475  		x := v.Args[0]
 12476  		v.reset(Op386NEGL)
 12477  		v.AddArg(x)
 12478  		return true
 12479  	}
 12480  	// match: (MULLconst [0] _)
 12481  	// cond:
 12482  	// result: (MOVLconst [0])
 12483  	for {
 12484  		if v.AuxInt != 0 {
 12485  			break
 12486  		}
 12487  		v.reset(Op386MOVLconst)
 12488  		v.AuxInt = 0
 12489  		return true
 12490  	}
 12491  	// match: (MULLconst [1] x)
 12492  	// cond:
 12493  	// result: x
 12494  	for {
 12495  		if v.AuxInt != 1 {
 12496  			break
 12497  		}
 12498  		x := v.Args[0]
 12499  		v.reset(OpCopy)
 12500  		v.Type = x.Type
 12501  		v.AddArg(x)
 12502  		return true
 12503  	}
 12504  	// match: (MULLconst [3] x)
 12505  	// cond:
 12506  	// result: (LEAL2 x x)
 12507  	for {
 12508  		if v.AuxInt != 3 {
 12509  			break
 12510  		}
 12511  		x := v.Args[0]
 12512  		v.reset(Op386LEAL2)
 12513  		v.AddArg(x)
 12514  		v.AddArg(x)
 12515  		return true
 12516  	}
 12517  	// match: (MULLconst [5] x)
 12518  	// cond:
 12519  	// result: (LEAL4 x x)
 12520  	for {
 12521  		if v.AuxInt != 5 {
 12522  			break
 12523  		}
 12524  		x := v.Args[0]
 12525  		v.reset(Op386LEAL4)
 12526  		v.AddArg(x)
 12527  		v.AddArg(x)
 12528  		return true
 12529  	}
 12530  	// match: (MULLconst [7] x)
 12531  	// cond:
 12532  	// result: (LEAL2 x (LEAL2 <v.Type> x x))
 12533  	for {
 12534  		if v.AuxInt != 7 {
 12535  			break
 12536  		}
 12537  		x := v.Args[0]
 12538  		v.reset(Op386LEAL2)
 12539  		v.AddArg(x)
 12540  		v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
 12541  		v0.AddArg(x)
 12542  		v0.AddArg(x)
 12543  		v.AddArg(v0)
 12544  		return true
 12545  	}
 12546  	return false
 12547  }
 12548  func rewriteValue386_Op386MULLconst_10(v *Value) bool {
 12549  	b := v.Block
 12550  	// match: (MULLconst [9] x)
 12551  	// cond:
 12552  	// result: (LEAL8 x x)
 12553  	for {
 12554  		if v.AuxInt != 9 {
 12555  			break
 12556  		}
 12557  		x := v.Args[0]
 12558  		v.reset(Op386LEAL8)
 12559  		v.AddArg(x)
 12560  		v.AddArg(x)
 12561  		return true
 12562  	}
 12563  	// match: (MULLconst [11] x)
 12564  	// cond:
 12565  	// result: (LEAL2 x (LEAL4 <v.Type> x x))
 12566  	for {
 12567  		if v.AuxInt != 11 {
 12568  			break
 12569  		}
 12570  		x := v.Args[0]
 12571  		v.reset(Op386LEAL2)
 12572  		v.AddArg(x)
 12573  		v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
 12574  		v0.AddArg(x)
 12575  		v0.AddArg(x)
 12576  		v.AddArg(v0)
 12577  		return true
 12578  	}
 12579  	// match: (MULLconst [13] x)
 12580  	// cond:
 12581  	// result: (LEAL4 x (LEAL2 <v.Type> x x))
 12582  	for {
 12583  		if v.AuxInt != 13 {
 12584  			break
 12585  		}
 12586  		x := v.Args[0]
 12587  		v.reset(Op386LEAL4)
 12588  		v.AddArg(x)
 12589  		v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
 12590  		v0.AddArg(x)
 12591  		v0.AddArg(x)
 12592  		v.AddArg(v0)
 12593  		return true
 12594  	}
 12595  	// match: (MULLconst [19] x)
 12596  	// cond:
 12597  	// result: (LEAL2 x (LEAL8 <v.Type> x x))
 12598  	for {
 12599  		if v.AuxInt != 19 {
 12600  			break
 12601  		}
 12602  		x := v.Args[0]
 12603  		v.reset(Op386LEAL2)
 12604  		v.AddArg(x)
 12605  		v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
 12606  		v0.AddArg(x)
 12607  		v0.AddArg(x)
 12608  		v.AddArg(v0)
 12609  		return true
 12610  	}
 12611  	// match: (MULLconst [21] x)
 12612  	// cond:
 12613  	// result: (LEAL4 x (LEAL4 <v.Type> x x))
 12614  	for {
 12615  		if v.AuxInt != 21 {
 12616  			break
 12617  		}
 12618  		x := v.Args[0]
 12619  		v.reset(Op386LEAL4)
 12620  		v.AddArg(x)
 12621  		v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
 12622  		v0.AddArg(x)
 12623  		v0.AddArg(x)
 12624  		v.AddArg(v0)
 12625  		return true
 12626  	}
 12627  	// match: (MULLconst [25] x)
 12628  	// cond:
 12629  	// result: (LEAL8 x (LEAL2 <v.Type> x x))
 12630  	for {
 12631  		if v.AuxInt != 25 {
 12632  			break
 12633  		}
 12634  		x := v.Args[0]
 12635  		v.reset(Op386LEAL8)
 12636  		v.AddArg(x)
 12637  		v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
 12638  		v0.AddArg(x)
 12639  		v0.AddArg(x)
 12640  		v.AddArg(v0)
 12641  		return true
 12642  	}
 12643  	// match: (MULLconst [27] x)
 12644  	// cond:
 12645  	// result: (LEAL8 (LEAL2 <v.Type> x x) (LEAL2 <v.Type> x x))
 12646  	for {
 12647  		if v.AuxInt != 27 {
 12648  			break
 12649  		}
 12650  		x := v.Args[0]
 12651  		v.reset(Op386LEAL8)
 12652  		v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
 12653  		v0.AddArg(x)
 12654  		v0.AddArg(x)
 12655  		v.AddArg(v0)
 12656  		v1 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
 12657  		v1.AddArg(x)
 12658  		v1.AddArg(x)
 12659  		v.AddArg(v1)
 12660  		return true
 12661  	}
 12662  	// match: (MULLconst [37] x)
 12663  	// cond:
 12664  	// result: (LEAL4 x (LEAL8 <v.Type> x x))
 12665  	for {
 12666  		if v.AuxInt != 37 {
 12667  			break
 12668  		}
 12669  		x := v.Args[0]
 12670  		v.reset(Op386LEAL4)
 12671  		v.AddArg(x)
 12672  		v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
 12673  		v0.AddArg(x)
 12674  		v0.AddArg(x)
 12675  		v.AddArg(v0)
 12676  		return true
 12677  	}
 12678  	// match: (MULLconst [41] x)
 12679  	// cond:
 12680  	// result: (LEAL8 x (LEAL4 <v.Type> x x))
 12681  	for {
 12682  		if v.AuxInt != 41 {
 12683  			break
 12684  		}
 12685  		x := v.Args[0]
 12686  		v.reset(Op386LEAL8)
 12687  		v.AddArg(x)
 12688  		v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
 12689  		v0.AddArg(x)
 12690  		v0.AddArg(x)
 12691  		v.AddArg(v0)
 12692  		return true
 12693  	}
 12694  	// match: (MULLconst [45] x)
 12695  	// cond:
 12696  	// result: (LEAL8 (LEAL4 <v.Type> x x) (LEAL4 <v.Type> x x))
 12697  	for {
 12698  		if v.AuxInt != 45 {
 12699  			break
 12700  		}
 12701  		x := v.Args[0]
 12702  		v.reset(Op386LEAL8)
 12703  		v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
 12704  		v0.AddArg(x)
 12705  		v0.AddArg(x)
 12706  		v.AddArg(v0)
 12707  		v1 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
 12708  		v1.AddArg(x)
 12709  		v1.AddArg(x)
 12710  		v.AddArg(v1)
 12711  		return true
 12712  	}
 12713  	return false
 12714  }
 12715  func rewriteValue386_Op386MULLconst_20(v *Value) bool {
 12716  	b := v.Block
 12717  	// match: (MULLconst [73] x)
 12718  	// cond:
 12719  	// result: (LEAL8 x (LEAL8 <v.Type> x x))
 12720  	for {
 12721  		if v.AuxInt != 73 {
 12722  			break
 12723  		}
 12724  		x := v.Args[0]
 12725  		v.reset(Op386LEAL8)
 12726  		v.AddArg(x)
 12727  		v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
 12728  		v0.AddArg(x)
 12729  		v0.AddArg(x)
 12730  		v.AddArg(v0)
 12731  		return true
 12732  	}
 12733  	// match: (MULLconst [81] x)
 12734  	// cond:
 12735  	// result: (LEAL8 (LEAL8 <v.Type> x x) (LEAL8 <v.Type> x x))
 12736  	for {
 12737  		if v.AuxInt != 81 {
 12738  			break
 12739  		}
 12740  		x := v.Args[0]
 12741  		v.reset(Op386LEAL8)
 12742  		v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
 12743  		v0.AddArg(x)
 12744  		v0.AddArg(x)
 12745  		v.AddArg(v0)
 12746  		v1 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
 12747  		v1.AddArg(x)
 12748  		v1.AddArg(x)
 12749  		v.AddArg(v1)
 12750  		return true
 12751  	}
 12752  	// match: (MULLconst [c] x)
 12753  	// cond: isPowerOfTwo(c+1) && c >= 15
 12754  	// result: (SUBL (SHLLconst <v.Type> [log2(c+1)] x) x)
 12755  	for {
 12756  		c := v.AuxInt
 12757  		x := v.Args[0]
 12758  		if !(isPowerOfTwo(c+1) && c >= 15) {
 12759  			break
 12760  		}
 12761  		v.reset(Op386SUBL)
 12762  		v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type)
 12763  		v0.AuxInt = log2(c + 1)
 12764  		v0.AddArg(x)
 12765  		v.AddArg(v0)
 12766  		v.AddArg(x)
 12767  		return true
 12768  	}
 12769  	// match: (MULLconst [c] x)
 12770  	// cond: isPowerOfTwo(c-1) && c >= 17
 12771  	// result: (LEAL1 (SHLLconst <v.Type> [log2(c-1)] x) x)
 12772  	for {
 12773  		c := v.AuxInt
 12774  		x := v.Args[0]
 12775  		if !(isPowerOfTwo(c-1) && c >= 17) {
 12776  			break
 12777  		}
 12778  		v.reset(Op386LEAL1)
 12779  		v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type)
 12780  		v0.AuxInt = log2(c - 1)
 12781  		v0.AddArg(x)
 12782  		v.AddArg(v0)
 12783  		v.AddArg(x)
 12784  		return true
 12785  	}
 12786  	// match: (MULLconst [c] x)
 12787  	// cond: isPowerOfTwo(c-2) && c >= 34
 12788  	// result: (LEAL2 (SHLLconst <v.Type> [log2(c-2)] x) x)
 12789  	for {
 12790  		c := v.AuxInt
 12791  		x := v.Args[0]
 12792  		if !(isPowerOfTwo(c-2) && c >= 34) {
 12793  			break
 12794  		}
 12795  		v.reset(Op386LEAL2)
 12796  		v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type)
 12797  		v0.AuxInt = log2(c - 2)
 12798  		v0.AddArg(x)
 12799  		v.AddArg(v0)
 12800  		v.AddArg(x)
 12801  		return true
 12802  	}
 12803  	// match: (MULLconst [c] x)
 12804  	// cond: isPowerOfTwo(c-4) && c >= 68
 12805  	// result: (LEAL4 (SHLLconst <v.Type> [log2(c-4)] x) x)
 12806  	for {
 12807  		c := v.AuxInt
 12808  		x := v.Args[0]
 12809  		if !(isPowerOfTwo(c-4) && c >= 68) {
 12810  			break
 12811  		}
 12812  		v.reset(Op386LEAL4)
 12813  		v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type)
 12814  		v0.AuxInt = log2(c - 4)
 12815  		v0.AddArg(x)
 12816  		v.AddArg(v0)
 12817  		v.AddArg(x)
 12818  		return true
 12819  	}
 12820  	// match: (MULLconst [c] x)
 12821  	// cond: isPowerOfTwo(c-8) && c >= 136
 12822  	// result: (LEAL8 (SHLLconst <v.Type> [log2(c-8)] x) x)
 12823  	for {
 12824  		c := v.AuxInt
 12825  		x := v.Args[0]
 12826  		if !(isPowerOfTwo(c-8) && c >= 136) {
 12827  			break
 12828  		}
 12829  		v.reset(Op386LEAL8)
 12830  		v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type)
 12831  		v0.AuxInt = log2(c - 8)
 12832  		v0.AddArg(x)
 12833  		v.AddArg(v0)
 12834  		v.AddArg(x)
 12835  		return true
 12836  	}
 12837  	// match: (MULLconst [c] x)
 12838  	// cond: c%3 == 0 && isPowerOfTwo(c/3)
 12839  	// result: (SHLLconst [log2(c/3)] (LEAL2 <v.Type> x x))
 12840  	for {
 12841  		c := v.AuxInt
 12842  		x := v.Args[0]
 12843  		if !(c%3 == 0 && isPowerOfTwo(c/3)) {
 12844  			break
 12845  		}
 12846  		v.reset(Op386SHLLconst)
 12847  		v.AuxInt = log2(c / 3)
 12848  		v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
 12849  		v0.AddArg(x)
 12850  		v0.AddArg(x)
 12851  		v.AddArg(v0)
 12852  		return true
 12853  	}
 12854  	// match: (MULLconst [c] x)
 12855  	// cond: c%5 == 0 && isPowerOfTwo(c/5)
 12856  	// result: (SHLLconst [log2(c/5)] (LEAL4 <v.Type> x x))
 12857  	for {
 12858  		c := v.AuxInt
 12859  		x := v.Args[0]
 12860  		if !(c%5 == 0 && isPowerOfTwo(c/5)) {
 12861  			break
 12862  		}
 12863  		v.reset(Op386SHLLconst)
 12864  		v.AuxInt = log2(c / 5)
 12865  		v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
 12866  		v0.AddArg(x)
 12867  		v0.AddArg(x)
 12868  		v.AddArg(v0)
 12869  		return true
 12870  	}
 12871  	// match: (MULLconst [c] x)
 12872  	// cond: c%9 == 0 && isPowerOfTwo(c/9)
 12873  	// result: (SHLLconst [log2(c/9)] (LEAL8 <v.Type> x x))
 12874  	for {
 12875  		c := v.AuxInt
 12876  		x := v.Args[0]
 12877  		if !(c%9 == 0 && isPowerOfTwo(c/9)) {
 12878  			break
 12879  		}
 12880  		v.reset(Op386SHLLconst)
 12881  		v.AuxInt = log2(c / 9)
 12882  		v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
 12883  		v0.AddArg(x)
 12884  		v0.AddArg(x)
 12885  		v.AddArg(v0)
 12886  		return true
 12887  	}
 12888  	return false
 12889  }
 12890  func rewriteValue386_Op386MULLconst_30(v *Value) bool {
 12891  	// match: (MULLconst [c] (MOVLconst [d]))
 12892  	// cond:
 12893  	// result: (MOVLconst [int64(int32(c*d))])
 12894  	for {
 12895  		c := v.AuxInt
 12896  		v_0 := v.Args[0]
 12897  		if v_0.Op != Op386MOVLconst {
 12898  			break
 12899  		}
 12900  		d := v_0.AuxInt
 12901  		v.reset(Op386MOVLconst)
 12902  		v.AuxInt = int64(int32(c * d))
 12903  		return true
 12904  	}
 12905  	return false
 12906  }
 12907  func rewriteValue386_Op386MULLload_0(v *Value) bool {
 12908  	b := v.Block
 12909  	config := b.Func.Config
 12910  	// match: (MULLload [off1] {sym} val (ADDLconst [off2] base) mem)
 12911  	// cond: is32Bit(off1+off2)
 12912  	// result: (MULLload [off1+off2] {sym} val base mem)
 12913  	for {
 12914  		off1 := v.AuxInt
 12915  		sym := v.Aux
 12916  		mem := v.Args[2]
 12917  		val := v.Args[0]
 12918  		v_1 := v.Args[1]
 12919  		if v_1.Op != Op386ADDLconst {
 12920  			break
 12921  		}
 12922  		off2 := v_1.AuxInt
 12923  		base := v_1.Args[0]
 12924  		if !(is32Bit(off1 + off2)) {
 12925  			break
 12926  		}
 12927  		v.reset(Op386MULLload)
 12928  		v.AuxInt = off1 + off2
 12929  		v.Aux = sym
 12930  		v.AddArg(val)
 12931  		v.AddArg(base)
 12932  		v.AddArg(mem)
 12933  		return true
 12934  	}
 12935  	// match: (MULLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
 12936  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
 12937  	// result: (MULLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
 12938  	for {
 12939  		off1 := v.AuxInt
 12940  		sym1 := v.Aux
 12941  		mem := v.Args[2]
 12942  		val := v.Args[0]
 12943  		v_1 := v.Args[1]
 12944  		if v_1.Op != Op386LEAL {
 12945  			break
 12946  		}
 12947  		off2 := v_1.AuxInt
 12948  		sym2 := v_1.Aux
 12949  		base := v_1.Args[0]
 12950  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
 12951  			break
 12952  		}
 12953  		v.reset(Op386MULLload)
 12954  		v.AuxInt = off1 + off2
 12955  		v.Aux = mergeSym(sym1, sym2)
 12956  		v.AddArg(val)
 12957  		v.AddArg(base)
 12958  		v.AddArg(mem)
 12959  		return true
 12960  	}
 12961  	// match: (MULLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem)
 12962  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 12963  	// result: (MULLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem)
 12964  	for {
 12965  		off1 := v.AuxInt
 12966  		sym1 := v.Aux
 12967  		mem := v.Args[2]
 12968  		val := v.Args[0]
 12969  		v_1 := v.Args[1]
 12970  		if v_1.Op != Op386LEAL4 {
 12971  			break
 12972  		}
 12973  		off2 := v_1.AuxInt
 12974  		sym2 := v_1.Aux
 12975  		idx := v_1.Args[1]
 12976  		ptr := v_1.Args[0]
 12977  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 12978  			break
 12979  		}
 12980  		v.reset(Op386MULLloadidx4)
 12981  		v.AuxInt = off1 + off2
 12982  		v.Aux = mergeSym(sym1, sym2)
 12983  		v.AddArg(val)
 12984  		v.AddArg(ptr)
 12985  		v.AddArg(idx)
 12986  		v.AddArg(mem)
 12987  		return true
 12988  	}
 12989  	return false
 12990  }
 12991  func rewriteValue386_Op386MULLloadidx4_0(v *Value) bool {
 12992  	b := v.Block
 12993  	config := b.Func.Config
 12994  	// match: (MULLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem)
 12995  	// cond: is32Bit(off1+off2)
 12996  	// result: (MULLloadidx4 [off1+off2] {sym} val base idx mem)
 12997  	for {
 12998  		off1 := v.AuxInt
 12999  		sym := v.Aux
 13000  		mem := v.Args[3]
 13001  		val := v.Args[0]
 13002  		v_1 := v.Args[1]
 13003  		if v_1.Op != Op386ADDLconst {
 13004  			break
 13005  		}
 13006  		off2 := v_1.AuxInt
 13007  		base := v_1.Args[0]
 13008  		idx := v.Args[2]
 13009  		if !(is32Bit(off1 + off2)) {
 13010  			break
 13011  		}
 13012  		v.reset(Op386MULLloadidx4)
 13013  		v.AuxInt = off1 + off2
 13014  		v.Aux = sym
 13015  		v.AddArg(val)
 13016  		v.AddArg(base)
 13017  		v.AddArg(idx)
 13018  		v.AddArg(mem)
 13019  		return true
 13020  	}
 13021  	// match: (MULLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem)
 13022  	// cond: is32Bit(off1+off2*4)
 13023  	// result: (MULLloadidx4 [off1+off2*4] {sym} val base idx mem)
 13024  	for {
 13025  		off1 := v.AuxInt
 13026  		sym := v.Aux
 13027  		mem := v.Args[3]
 13028  		val := v.Args[0]
 13029  		base := v.Args[1]
 13030  		v_2 := v.Args[2]
 13031  		if v_2.Op != Op386ADDLconst {
 13032  			break
 13033  		}
 13034  		off2 := v_2.AuxInt
 13035  		idx := v_2.Args[0]
 13036  		if !(is32Bit(off1 + off2*4)) {
 13037  			break
 13038  		}
 13039  		v.reset(Op386MULLloadidx4)
 13040  		v.AuxInt = off1 + off2*4
 13041  		v.Aux = sym
 13042  		v.AddArg(val)
 13043  		v.AddArg(base)
 13044  		v.AddArg(idx)
 13045  		v.AddArg(mem)
 13046  		return true
 13047  	}
 13048  	// match: (MULLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem)
 13049  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
 13050  	// result: (MULLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem)
 13051  	for {
 13052  		off1 := v.AuxInt
 13053  		sym1 := v.Aux
 13054  		mem := v.Args[3]
 13055  		val := v.Args[0]
 13056  		v_1 := v.Args[1]
 13057  		if v_1.Op != Op386LEAL {
 13058  			break
 13059  		}
 13060  		off2 := v_1.AuxInt
 13061  		sym2 := v_1.Aux
 13062  		base := v_1.Args[0]
 13063  		idx := v.Args[2]
 13064  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
 13065  			break
 13066  		}
 13067  		v.reset(Op386MULLloadidx4)
 13068  		v.AuxInt = off1 + off2
 13069  		v.Aux = mergeSym(sym1, sym2)
 13070  		v.AddArg(val)
 13071  		v.AddArg(base)
 13072  		v.AddArg(idx)
 13073  		v.AddArg(mem)
 13074  		return true
 13075  	}
 13076  	return false
 13077  }
 13078  func rewriteValue386_Op386MULSD_0(v *Value) bool {
 13079  	b := v.Block
 13080  	config := b.Func.Config
 13081  	// match: (MULSD x l:(MOVSDload [off] {sym} ptr mem))
 13082  	// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
 13083  	// result: (MULSDload x [off] {sym} ptr mem)
 13084  	for {
 13085  		_ = v.Args[1]
 13086  		x := v.Args[0]
 13087  		l := v.Args[1]
 13088  		if l.Op != Op386MOVSDload {
 13089  			break
 13090  		}
 13091  		off := l.AuxInt
 13092  		sym := l.Aux
 13093  		mem := l.Args[1]
 13094  		ptr := l.Args[0]
 13095  		if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
 13096  			break
 13097  		}
 13098  		v.reset(Op386MULSDload)
 13099  		v.AuxInt = off
 13100  		v.Aux = sym
 13101  		v.AddArg(x)
 13102  		v.AddArg(ptr)
 13103  		v.AddArg(mem)
 13104  		return true
 13105  	}
 13106  	// match: (MULSD l:(MOVSDload [off] {sym} ptr mem) x)
 13107  	// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
 13108  	// result: (MULSDload x [off] {sym} ptr mem)
 13109  	for {
 13110  		x := v.Args[1]
 13111  		l := v.Args[0]
 13112  		if l.Op != Op386MOVSDload {
 13113  			break
 13114  		}
 13115  		off := l.AuxInt
 13116  		sym := l.Aux
 13117  		mem := l.Args[1]
 13118  		ptr := l.Args[0]
 13119  		if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
 13120  			break
 13121  		}
 13122  		v.reset(Op386MULSDload)
 13123  		v.AuxInt = off
 13124  		v.Aux = sym
 13125  		v.AddArg(x)
 13126  		v.AddArg(ptr)
 13127  		v.AddArg(mem)
 13128  		return true
 13129  	}
 13130  	return false
 13131  }
 13132  func rewriteValue386_Op386MULSDload_0(v *Value) bool {
 13133  	b := v.Block
 13134  	config := b.Func.Config
 13135  	// match: (MULSDload [off1] {sym} val (ADDLconst [off2] base) mem)
 13136  	// cond: is32Bit(off1+off2)
 13137  	// result: (MULSDload [off1+off2] {sym} val base mem)
 13138  	for {
 13139  		off1 := v.AuxInt
 13140  		sym := v.Aux
 13141  		mem := v.Args[2]
 13142  		val := v.Args[0]
 13143  		v_1 := v.Args[1]
 13144  		if v_1.Op != Op386ADDLconst {
 13145  			break
 13146  		}
 13147  		off2 := v_1.AuxInt
 13148  		base := v_1.Args[0]
 13149  		if !(is32Bit(off1 + off2)) {
 13150  			break
 13151  		}
 13152  		v.reset(Op386MULSDload)
 13153  		v.AuxInt = off1 + off2
 13154  		v.Aux = sym
 13155  		v.AddArg(val)
 13156  		v.AddArg(base)
 13157  		v.AddArg(mem)
 13158  		return true
 13159  	}
 13160  	// match: (MULSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
 13161  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
 13162  	// result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
 13163  	for {
 13164  		off1 := v.AuxInt
 13165  		sym1 := v.Aux
 13166  		mem := v.Args[2]
 13167  		val := v.Args[0]
 13168  		v_1 := v.Args[1]
 13169  		if v_1.Op != Op386LEAL {
 13170  			break
 13171  		}
 13172  		off2 := v_1.AuxInt
 13173  		sym2 := v_1.Aux
 13174  		base := v_1.Args[0]
 13175  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
 13176  			break
 13177  		}
 13178  		v.reset(Op386MULSDload)
 13179  		v.AuxInt = off1 + off2
 13180  		v.Aux = mergeSym(sym1, sym2)
 13181  		v.AddArg(val)
 13182  		v.AddArg(base)
 13183  		v.AddArg(mem)
 13184  		return true
 13185  	}
 13186  	return false
 13187  }
 13188  func rewriteValue386_Op386MULSS_0(v *Value) bool {
 13189  	b := v.Block
 13190  	config := b.Func.Config
 13191  	// match: (MULSS x l:(MOVSSload [off] {sym} ptr mem))
 13192  	// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
 13193  	// result: (MULSSload x [off] {sym} ptr mem)
 13194  	for {
 13195  		_ = v.Args[1]
 13196  		x := v.Args[0]
 13197  		l := v.Args[1]
 13198  		if l.Op != Op386MOVSSload {
 13199  			break
 13200  		}
 13201  		off := l.AuxInt
 13202  		sym := l.Aux
 13203  		mem := l.Args[1]
 13204  		ptr := l.Args[0]
 13205  		if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
 13206  			break
 13207  		}
 13208  		v.reset(Op386MULSSload)
 13209  		v.AuxInt = off
 13210  		v.Aux = sym
 13211  		v.AddArg(x)
 13212  		v.AddArg(ptr)
 13213  		v.AddArg(mem)
 13214  		return true
 13215  	}
 13216  	// match: (MULSS l:(MOVSSload [off] {sym} ptr mem) x)
 13217  	// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
 13218  	// result: (MULSSload x [off] {sym} ptr mem)
 13219  	for {
 13220  		x := v.Args[1]
 13221  		l := v.Args[0]
 13222  		if l.Op != Op386MOVSSload {
 13223  			break
 13224  		}
 13225  		off := l.AuxInt
 13226  		sym := l.Aux
 13227  		mem := l.Args[1]
 13228  		ptr := l.Args[0]
 13229  		if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
 13230  			break
 13231  		}
 13232  		v.reset(Op386MULSSload)
 13233  		v.AuxInt = off
 13234  		v.Aux = sym
 13235  		v.AddArg(x)
 13236  		v.AddArg(ptr)
 13237  		v.AddArg(mem)
 13238  		return true
 13239  	}
 13240  	return false
 13241  }
 13242  func rewriteValue386_Op386MULSSload_0(v *Value) bool {
 13243  	b := v.Block
 13244  	config := b.Func.Config
 13245  	// match: (MULSSload [off1] {sym} val (ADDLconst [off2] base) mem)
 13246  	// cond: is32Bit(off1+off2)
 13247  	// result: (MULSSload [off1+off2] {sym} val base mem)
 13248  	for {
 13249  		off1 := v.AuxInt
 13250  		sym := v.Aux
 13251  		mem := v.Args[2]
 13252  		val := v.Args[0]
 13253  		v_1 := v.Args[1]
 13254  		if v_1.Op != Op386ADDLconst {
 13255  			break
 13256  		}
 13257  		off2 := v_1.AuxInt
 13258  		base := v_1.Args[0]
 13259  		if !(is32Bit(off1 + off2)) {
 13260  			break
 13261  		}
 13262  		v.reset(Op386MULSSload)
 13263  		v.AuxInt = off1 + off2
 13264  		v.Aux = sym
 13265  		v.AddArg(val)
 13266  		v.AddArg(base)
 13267  		v.AddArg(mem)
 13268  		return true
 13269  	}
 13270  	// match: (MULSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
 13271  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
 13272  	// result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
 13273  	for {
 13274  		off1 := v.AuxInt
 13275  		sym1 := v.Aux
 13276  		mem := v.Args[2]
 13277  		val := v.Args[0]
 13278  		v_1 := v.Args[1]
 13279  		if v_1.Op != Op386LEAL {
 13280  			break
 13281  		}
 13282  		off2 := v_1.AuxInt
 13283  		sym2 := v_1.Aux
 13284  		base := v_1.Args[0]
 13285  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
 13286  			break
 13287  		}
 13288  		v.reset(Op386MULSSload)
 13289  		v.AuxInt = off1 + off2
 13290  		v.Aux = mergeSym(sym1, sym2)
 13291  		v.AddArg(val)
 13292  		v.AddArg(base)
 13293  		v.AddArg(mem)
 13294  		return true
 13295  	}
 13296  	return false
 13297  }
 13298  func rewriteValue386_Op386NEGL_0(v *Value) bool {
 13299  	// match: (NEGL (MOVLconst [c]))
 13300  	// cond:
 13301  	// result: (MOVLconst [int64(int32(-c))])
 13302  	for {
 13303  		v_0 := v.Args[0]
 13304  		if v_0.Op != Op386MOVLconst {
 13305  			break
 13306  		}
 13307  		c := v_0.AuxInt
 13308  		v.reset(Op386MOVLconst)
 13309  		v.AuxInt = int64(int32(-c))
 13310  		return true
 13311  	}
 13312  	return false
 13313  }
 13314  func rewriteValue386_Op386NOTL_0(v *Value) bool {
 13315  	// match: (NOTL (MOVLconst [c]))
 13316  	// cond:
 13317  	// result: (MOVLconst [^c])
 13318  	for {
 13319  		v_0 := v.Args[0]
 13320  		if v_0.Op != Op386MOVLconst {
 13321  			break
 13322  		}
 13323  		c := v_0.AuxInt
 13324  		v.reset(Op386MOVLconst)
 13325  		v.AuxInt = ^c
 13326  		return true
 13327  	}
 13328  	return false
 13329  }
 13330  func rewriteValue386_Op386ORL_0(v *Value) bool {
 13331  	// match: (ORL x (MOVLconst [c]))
 13332  	// cond:
 13333  	// result: (ORLconst [c] x)
 13334  	for {
 13335  		_ = v.Args[1]
 13336  		x := v.Args[0]
 13337  		v_1 := v.Args[1]
 13338  		if v_1.Op != Op386MOVLconst {
 13339  			break
 13340  		}
 13341  		c := v_1.AuxInt
 13342  		v.reset(Op386ORLconst)
 13343  		v.AuxInt = c
 13344  		v.AddArg(x)
 13345  		return true
 13346  	}
 13347  	// match: (ORL (MOVLconst [c]) x)
 13348  	// cond:
 13349  	// result: (ORLconst [c] x)
 13350  	for {
 13351  		x := v.Args[1]
 13352  		v_0 := v.Args[0]
 13353  		if v_0.Op != Op386MOVLconst {
 13354  			break
 13355  		}
 13356  		c := v_0.AuxInt
 13357  		v.reset(Op386ORLconst)
 13358  		v.AuxInt = c
 13359  		v.AddArg(x)
 13360  		return true
 13361  	}
 13362  	// match: (ORL (SHLLconst [c] x) (SHRLconst [d] x))
 13363  	// cond: d == 32-c
 13364  	// result: (ROLLconst [c] x)
 13365  	for {
 13366  		_ = v.Args[1]
 13367  		v_0 := v.Args[0]
 13368  		if v_0.Op != Op386SHLLconst {
 13369  			break
 13370  		}
 13371  		c := v_0.AuxInt
 13372  		x := v_0.Args[0]
 13373  		v_1 := v.Args[1]
 13374  		if v_1.Op != Op386SHRLconst {
 13375  			break
 13376  		}
 13377  		d := v_1.AuxInt
 13378  		if x != v_1.Args[0] {
 13379  			break
 13380  		}
 13381  		if !(d == 32-c) {
 13382  			break
 13383  		}
 13384  		v.reset(Op386ROLLconst)
 13385  		v.AuxInt = c
 13386  		v.AddArg(x)
 13387  		return true
 13388  	}
 13389  	// match: (ORL (SHRLconst [d] x) (SHLLconst [c] x))
 13390  	// cond: d == 32-c
 13391  	// result: (ROLLconst [c] x)
 13392  	for {
 13393  		_ = v.Args[1]
 13394  		v_0 := v.Args[0]
 13395  		if v_0.Op != Op386SHRLconst {
 13396  			break
 13397  		}
 13398  		d := v_0.AuxInt
 13399  		x := v_0.Args[0]
 13400  		v_1 := v.Args[1]
 13401  		if v_1.Op != Op386SHLLconst {
 13402  			break
 13403  		}
 13404  		c := v_1.AuxInt
 13405  		if x != v_1.Args[0] {
 13406  			break
 13407  		}
 13408  		if !(d == 32-c) {
 13409  			break
 13410  		}
 13411  		v.reset(Op386ROLLconst)
 13412  		v.AuxInt = c
 13413  		v.AddArg(x)
 13414  		return true
 13415  	}
 13416  	// match: (ORL <t> (SHLLconst x [c]) (SHRWconst x [d]))
 13417  	// cond: c < 16 && d == 16-c && t.Size() == 2
 13418  	// result: (ROLWconst x [c])
 13419  	for {
 13420  		t := v.Type
 13421  		_ = v.Args[1]
 13422  		v_0 := v.Args[0]
 13423  		if v_0.Op != Op386SHLLconst {
 13424  			break
 13425  		}
 13426  		c := v_0.AuxInt
 13427  		x := v_0.Args[0]
 13428  		v_1 := v.Args[1]
 13429  		if v_1.Op != Op386SHRWconst {
 13430  			break
 13431  		}
 13432  		d := v_1.AuxInt
 13433  		if x != v_1.Args[0] {
 13434  			break
 13435  		}
 13436  		if !(c < 16 && d == 16-c && t.Size() == 2) {