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Source file src/cmd/compile/internal/ssa/rewrite386.go

Documentation: cmd/compile/internal/ssa

     1  // Code generated from gen/386.rules; DO NOT EDIT.
     2  // generated with: cd gen; go run *.go
     3  
     4  package ssa
     5  
     6  import "fmt"
     7  import "math"
     8  import "cmd/internal/obj"
     9  import "cmd/internal/objabi"
    10  import "cmd/compile/internal/types"
    11  
    12  var _ = fmt.Println   // in case not otherwise used
    13  var _ = math.MinInt8  // in case not otherwise used
    14  var _ = obj.ANOP      // in case not otherwise used
    15  var _ = objabi.GOROOT // in case not otherwise used
    16  var _ = types.TypeMem // in case not otherwise used
    17  
    18  func rewriteValue386(v *Value) bool {
    19  	switch v.Op {
    20  	case Op386ADCL:
    21  		return rewriteValue386_Op386ADCL_0(v)
    22  	case Op386ADDL:
    23  		return rewriteValue386_Op386ADDL_0(v) || rewriteValue386_Op386ADDL_10(v) || rewriteValue386_Op386ADDL_20(v)
    24  	case Op386ADDLcarry:
    25  		return rewriteValue386_Op386ADDLcarry_0(v)
    26  	case Op386ADDLconst:
    27  		return rewriteValue386_Op386ADDLconst_0(v)
    28  	case Op386ADDLconstmodify:
    29  		return rewriteValue386_Op386ADDLconstmodify_0(v)
    30  	case Op386ADDLconstmodifyidx4:
    31  		return rewriteValue386_Op386ADDLconstmodifyidx4_0(v)
    32  	case Op386ADDLload:
    33  		return rewriteValue386_Op386ADDLload_0(v)
    34  	case Op386ADDLloadidx4:
    35  		return rewriteValue386_Op386ADDLloadidx4_0(v)
    36  	case Op386ADDLmodify:
    37  		return rewriteValue386_Op386ADDLmodify_0(v)
    38  	case Op386ADDLmodifyidx4:
    39  		return rewriteValue386_Op386ADDLmodifyidx4_0(v)
    40  	case Op386ADDSD:
    41  		return rewriteValue386_Op386ADDSD_0(v)
    42  	case Op386ADDSDload:
    43  		return rewriteValue386_Op386ADDSDload_0(v)
    44  	case Op386ADDSS:
    45  		return rewriteValue386_Op386ADDSS_0(v)
    46  	case Op386ADDSSload:
    47  		return rewriteValue386_Op386ADDSSload_0(v)
    48  	case Op386ANDL:
    49  		return rewriteValue386_Op386ANDL_0(v)
    50  	case Op386ANDLconst:
    51  		return rewriteValue386_Op386ANDLconst_0(v)
    52  	case Op386ANDLconstmodify:
    53  		return rewriteValue386_Op386ANDLconstmodify_0(v)
    54  	case Op386ANDLconstmodifyidx4:
    55  		return rewriteValue386_Op386ANDLconstmodifyidx4_0(v)
    56  	case Op386ANDLload:
    57  		return rewriteValue386_Op386ANDLload_0(v)
    58  	case Op386ANDLloadidx4:
    59  		return rewriteValue386_Op386ANDLloadidx4_0(v)
    60  	case Op386ANDLmodify:
    61  		return rewriteValue386_Op386ANDLmodify_0(v)
    62  	case Op386ANDLmodifyidx4:
    63  		return rewriteValue386_Op386ANDLmodifyidx4_0(v)
    64  	case Op386CMPB:
    65  		return rewriteValue386_Op386CMPB_0(v)
    66  	case Op386CMPBconst:
    67  		return rewriteValue386_Op386CMPBconst_0(v)
    68  	case Op386CMPBload:
    69  		return rewriteValue386_Op386CMPBload_0(v)
    70  	case Op386CMPL:
    71  		return rewriteValue386_Op386CMPL_0(v)
    72  	case Op386CMPLconst:
    73  		return rewriteValue386_Op386CMPLconst_0(v) || rewriteValue386_Op386CMPLconst_10(v)
    74  	case Op386CMPLload:
    75  		return rewriteValue386_Op386CMPLload_0(v)
    76  	case Op386CMPW:
    77  		return rewriteValue386_Op386CMPW_0(v)
    78  	case Op386CMPWconst:
    79  		return rewriteValue386_Op386CMPWconst_0(v)
    80  	case Op386CMPWload:
    81  		return rewriteValue386_Op386CMPWload_0(v)
    82  	case Op386DIVSD:
    83  		return rewriteValue386_Op386DIVSD_0(v)
    84  	case Op386DIVSDload:
    85  		return rewriteValue386_Op386DIVSDload_0(v)
    86  	case Op386DIVSS:
    87  		return rewriteValue386_Op386DIVSS_0(v)
    88  	case Op386DIVSSload:
    89  		return rewriteValue386_Op386DIVSSload_0(v)
    90  	case Op386LEAL:
    91  		return rewriteValue386_Op386LEAL_0(v)
    92  	case Op386LEAL1:
    93  		return rewriteValue386_Op386LEAL1_0(v)
    94  	case Op386LEAL2:
    95  		return rewriteValue386_Op386LEAL2_0(v)
    96  	case Op386LEAL4:
    97  		return rewriteValue386_Op386LEAL4_0(v)
    98  	case Op386LEAL8:
    99  		return rewriteValue386_Op386LEAL8_0(v)
   100  	case Op386MOVBLSX:
   101  		return rewriteValue386_Op386MOVBLSX_0(v)
   102  	case Op386MOVBLSXload:
   103  		return rewriteValue386_Op386MOVBLSXload_0(v)
   104  	case Op386MOVBLZX:
   105  		return rewriteValue386_Op386MOVBLZX_0(v)
   106  	case Op386MOVBload:
   107  		return rewriteValue386_Op386MOVBload_0(v)
   108  	case Op386MOVBloadidx1:
   109  		return rewriteValue386_Op386MOVBloadidx1_0(v)
   110  	case Op386MOVBstore:
   111  		return rewriteValue386_Op386MOVBstore_0(v) || rewriteValue386_Op386MOVBstore_10(v)
   112  	case Op386MOVBstoreconst:
   113  		return rewriteValue386_Op386MOVBstoreconst_0(v)
   114  	case Op386MOVBstoreconstidx1:
   115  		return rewriteValue386_Op386MOVBstoreconstidx1_0(v)
   116  	case Op386MOVBstoreidx1:
   117  		return rewriteValue386_Op386MOVBstoreidx1_0(v) || rewriteValue386_Op386MOVBstoreidx1_10(v) || rewriteValue386_Op386MOVBstoreidx1_20(v)
   118  	case Op386MOVLload:
   119  		return rewriteValue386_Op386MOVLload_0(v)
   120  	case Op386MOVLloadidx1:
   121  		return rewriteValue386_Op386MOVLloadidx1_0(v)
   122  	case Op386MOVLloadidx4:
   123  		return rewriteValue386_Op386MOVLloadidx4_0(v)
   124  	case Op386MOVLstore:
   125  		return rewriteValue386_Op386MOVLstore_0(v) || rewriteValue386_Op386MOVLstore_10(v) || rewriteValue386_Op386MOVLstore_20(v)
   126  	case Op386MOVLstoreconst:
   127  		return rewriteValue386_Op386MOVLstoreconst_0(v)
   128  	case Op386MOVLstoreconstidx1:
   129  		return rewriteValue386_Op386MOVLstoreconstidx1_0(v)
   130  	case Op386MOVLstoreconstidx4:
   131  		return rewriteValue386_Op386MOVLstoreconstidx4_0(v)
   132  	case Op386MOVLstoreidx1:
   133  		return rewriteValue386_Op386MOVLstoreidx1_0(v)
   134  	case Op386MOVLstoreidx4:
   135  		return rewriteValue386_Op386MOVLstoreidx4_0(v) || rewriteValue386_Op386MOVLstoreidx4_10(v)
   136  	case Op386MOVSDconst:
   137  		return rewriteValue386_Op386MOVSDconst_0(v)
   138  	case Op386MOVSDload:
   139  		return rewriteValue386_Op386MOVSDload_0(v)
   140  	case Op386MOVSDloadidx1:
   141  		return rewriteValue386_Op386MOVSDloadidx1_0(v)
   142  	case Op386MOVSDloadidx8:
   143  		return rewriteValue386_Op386MOVSDloadidx8_0(v)
   144  	case Op386MOVSDstore:
   145  		return rewriteValue386_Op386MOVSDstore_0(v)
   146  	case Op386MOVSDstoreidx1:
   147  		return rewriteValue386_Op386MOVSDstoreidx1_0(v)
   148  	case Op386MOVSDstoreidx8:
   149  		return rewriteValue386_Op386MOVSDstoreidx8_0(v)
   150  	case Op386MOVSSconst:
   151  		return rewriteValue386_Op386MOVSSconst_0(v)
   152  	case Op386MOVSSload:
   153  		return rewriteValue386_Op386MOVSSload_0(v)
   154  	case Op386MOVSSloadidx1:
   155  		return rewriteValue386_Op386MOVSSloadidx1_0(v)
   156  	case Op386MOVSSloadidx4:
   157  		return rewriteValue386_Op386MOVSSloadidx4_0(v)
   158  	case Op386MOVSSstore:
   159  		return rewriteValue386_Op386MOVSSstore_0(v)
   160  	case Op386MOVSSstoreidx1:
   161  		return rewriteValue386_Op386MOVSSstoreidx1_0(v)
   162  	case Op386MOVSSstoreidx4:
   163  		return rewriteValue386_Op386MOVSSstoreidx4_0(v)
   164  	case Op386MOVWLSX:
   165  		return rewriteValue386_Op386MOVWLSX_0(v)
   166  	case Op386MOVWLSXload:
   167  		return rewriteValue386_Op386MOVWLSXload_0(v)
   168  	case Op386MOVWLZX:
   169  		return rewriteValue386_Op386MOVWLZX_0(v)
   170  	case Op386MOVWload:
   171  		return rewriteValue386_Op386MOVWload_0(v)
   172  	case Op386MOVWloadidx1:
   173  		return rewriteValue386_Op386MOVWloadidx1_0(v)
   174  	case Op386MOVWloadidx2:
   175  		return rewriteValue386_Op386MOVWloadidx2_0(v)
   176  	case Op386MOVWstore:
   177  		return rewriteValue386_Op386MOVWstore_0(v)
   178  	case Op386MOVWstoreconst:
   179  		return rewriteValue386_Op386MOVWstoreconst_0(v)
   180  	case Op386MOVWstoreconstidx1:
   181  		return rewriteValue386_Op386MOVWstoreconstidx1_0(v)
   182  	case Op386MOVWstoreconstidx2:
   183  		return rewriteValue386_Op386MOVWstoreconstidx2_0(v)
   184  	case Op386MOVWstoreidx1:
   185  		return rewriteValue386_Op386MOVWstoreidx1_0(v) || rewriteValue386_Op386MOVWstoreidx1_10(v)
   186  	case Op386MOVWstoreidx2:
   187  		return rewriteValue386_Op386MOVWstoreidx2_0(v)
   188  	case Op386MULL:
   189  		return rewriteValue386_Op386MULL_0(v)
   190  	case Op386MULLconst:
   191  		return rewriteValue386_Op386MULLconst_0(v) || rewriteValue386_Op386MULLconst_10(v) || rewriteValue386_Op386MULLconst_20(v) || rewriteValue386_Op386MULLconst_30(v)
   192  	case Op386MULLload:
   193  		return rewriteValue386_Op386MULLload_0(v)
   194  	case Op386MULLloadidx4:
   195  		return rewriteValue386_Op386MULLloadidx4_0(v)
   196  	case Op386MULSD:
   197  		return rewriteValue386_Op386MULSD_0(v)
   198  	case Op386MULSDload:
   199  		return rewriteValue386_Op386MULSDload_0(v)
   200  	case Op386MULSS:
   201  		return rewriteValue386_Op386MULSS_0(v)
   202  	case Op386MULSSload:
   203  		return rewriteValue386_Op386MULSSload_0(v)
   204  	case Op386NEGL:
   205  		return rewriteValue386_Op386NEGL_0(v)
   206  	case Op386NOTL:
   207  		return rewriteValue386_Op386NOTL_0(v)
   208  	case Op386ORL:
   209  		return rewriteValue386_Op386ORL_0(v) || rewriteValue386_Op386ORL_10(v) || rewriteValue386_Op386ORL_20(v) || rewriteValue386_Op386ORL_30(v) || rewriteValue386_Op386ORL_40(v) || rewriteValue386_Op386ORL_50(v)
   210  	case Op386ORLconst:
   211  		return rewriteValue386_Op386ORLconst_0(v)
   212  	case Op386ORLconstmodify:
   213  		return rewriteValue386_Op386ORLconstmodify_0(v)
   214  	case Op386ORLconstmodifyidx4:
   215  		return rewriteValue386_Op386ORLconstmodifyidx4_0(v)
   216  	case Op386ORLload:
   217  		return rewriteValue386_Op386ORLload_0(v)
   218  	case Op386ORLloadidx4:
   219  		return rewriteValue386_Op386ORLloadidx4_0(v)
   220  	case Op386ORLmodify:
   221  		return rewriteValue386_Op386ORLmodify_0(v)
   222  	case Op386ORLmodifyidx4:
   223  		return rewriteValue386_Op386ORLmodifyidx4_0(v)
   224  	case Op386ROLBconst:
   225  		return rewriteValue386_Op386ROLBconst_0(v)
   226  	case Op386ROLLconst:
   227  		return rewriteValue386_Op386ROLLconst_0(v)
   228  	case Op386ROLWconst:
   229  		return rewriteValue386_Op386ROLWconst_0(v)
   230  	case Op386SARB:
   231  		return rewriteValue386_Op386SARB_0(v)
   232  	case Op386SARBconst:
   233  		return rewriteValue386_Op386SARBconst_0(v)
   234  	case Op386SARL:
   235  		return rewriteValue386_Op386SARL_0(v)
   236  	case Op386SARLconst:
   237  		return rewriteValue386_Op386SARLconst_0(v)
   238  	case Op386SARW:
   239  		return rewriteValue386_Op386SARW_0(v)
   240  	case Op386SARWconst:
   241  		return rewriteValue386_Op386SARWconst_0(v)
   242  	case Op386SBBL:
   243  		return rewriteValue386_Op386SBBL_0(v)
   244  	case Op386SBBLcarrymask:
   245  		return rewriteValue386_Op386SBBLcarrymask_0(v)
   246  	case Op386SETA:
   247  		return rewriteValue386_Op386SETA_0(v)
   248  	case Op386SETAE:
   249  		return rewriteValue386_Op386SETAE_0(v)
   250  	case Op386SETB:
   251  		return rewriteValue386_Op386SETB_0(v)
   252  	case Op386SETBE:
   253  		return rewriteValue386_Op386SETBE_0(v)
   254  	case Op386SETEQ:
   255  		return rewriteValue386_Op386SETEQ_0(v)
   256  	case Op386SETG:
   257  		return rewriteValue386_Op386SETG_0(v)
   258  	case Op386SETGE:
   259  		return rewriteValue386_Op386SETGE_0(v)
   260  	case Op386SETL:
   261  		return rewriteValue386_Op386SETL_0(v)
   262  	case Op386SETLE:
   263  		return rewriteValue386_Op386SETLE_0(v)
   264  	case Op386SETNE:
   265  		return rewriteValue386_Op386SETNE_0(v)
   266  	case Op386SHLL:
   267  		return rewriteValue386_Op386SHLL_0(v)
   268  	case Op386SHLLconst:
   269  		return rewriteValue386_Op386SHLLconst_0(v)
   270  	case Op386SHRB:
   271  		return rewriteValue386_Op386SHRB_0(v)
   272  	case Op386SHRBconst:
   273  		return rewriteValue386_Op386SHRBconst_0(v)
   274  	case Op386SHRL:
   275  		return rewriteValue386_Op386SHRL_0(v)
   276  	case Op386SHRLconst:
   277  		return rewriteValue386_Op386SHRLconst_0(v)
   278  	case Op386SHRW:
   279  		return rewriteValue386_Op386SHRW_0(v)
   280  	case Op386SHRWconst:
   281  		return rewriteValue386_Op386SHRWconst_0(v)
   282  	case Op386SUBL:
   283  		return rewriteValue386_Op386SUBL_0(v)
   284  	case Op386SUBLcarry:
   285  		return rewriteValue386_Op386SUBLcarry_0(v)
   286  	case Op386SUBLconst:
   287  		return rewriteValue386_Op386SUBLconst_0(v)
   288  	case Op386SUBLload:
   289  		return rewriteValue386_Op386SUBLload_0(v)
   290  	case Op386SUBLloadidx4:
   291  		return rewriteValue386_Op386SUBLloadidx4_0(v)
   292  	case Op386SUBLmodify:
   293  		return rewriteValue386_Op386SUBLmodify_0(v)
   294  	case Op386SUBLmodifyidx4:
   295  		return rewriteValue386_Op386SUBLmodifyidx4_0(v)
   296  	case Op386SUBSD:
   297  		return rewriteValue386_Op386SUBSD_0(v)
   298  	case Op386SUBSDload:
   299  		return rewriteValue386_Op386SUBSDload_0(v)
   300  	case Op386SUBSS:
   301  		return rewriteValue386_Op386SUBSS_0(v)
   302  	case Op386SUBSSload:
   303  		return rewriteValue386_Op386SUBSSload_0(v)
   304  	case Op386XORL:
   305  		return rewriteValue386_Op386XORL_0(v) || rewriteValue386_Op386XORL_10(v)
   306  	case Op386XORLconst:
   307  		return rewriteValue386_Op386XORLconst_0(v)
   308  	case Op386XORLconstmodify:
   309  		return rewriteValue386_Op386XORLconstmodify_0(v)
   310  	case Op386XORLconstmodifyidx4:
   311  		return rewriteValue386_Op386XORLconstmodifyidx4_0(v)
   312  	case Op386XORLload:
   313  		return rewriteValue386_Op386XORLload_0(v)
   314  	case Op386XORLloadidx4:
   315  		return rewriteValue386_Op386XORLloadidx4_0(v)
   316  	case Op386XORLmodify:
   317  		return rewriteValue386_Op386XORLmodify_0(v)
   318  	case Op386XORLmodifyidx4:
   319  		return rewriteValue386_Op386XORLmodifyidx4_0(v)
   320  	case OpAdd16:
   321  		return rewriteValue386_OpAdd16_0(v)
   322  	case OpAdd32:
   323  		return rewriteValue386_OpAdd32_0(v)
   324  	case OpAdd32F:
   325  		return rewriteValue386_OpAdd32F_0(v)
   326  	case OpAdd32carry:
   327  		return rewriteValue386_OpAdd32carry_0(v)
   328  	case OpAdd32withcarry:
   329  		return rewriteValue386_OpAdd32withcarry_0(v)
   330  	case OpAdd64F:
   331  		return rewriteValue386_OpAdd64F_0(v)
   332  	case OpAdd8:
   333  		return rewriteValue386_OpAdd8_0(v)
   334  	case OpAddPtr:
   335  		return rewriteValue386_OpAddPtr_0(v)
   336  	case OpAddr:
   337  		return rewriteValue386_OpAddr_0(v)
   338  	case OpAnd16:
   339  		return rewriteValue386_OpAnd16_0(v)
   340  	case OpAnd32:
   341  		return rewriteValue386_OpAnd32_0(v)
   342  	case OpAnd8:
   343  		return rewriteValue386_OpAnd8_0(v)
   344  	case OpAndB:
   345  		return rewriteValue386_OpAndB_0(v)
   346  	case OpAvg32u:
   347  		return rewriteValue386_OpAvg32u_0(v)
   348  	case OpBswap32:
   349  		return rewriteValue386_OpBswap32_0(v)
   350  	case OpClosureCall:
   351  		return rewriteValue386_OpClosureCall_0(v)
   352  	case OpCom16:
   353  		return rewriteValue386_OpCom16_0(v)
   354  	case OpCom32:
   355  		return rewriteValue386_OpCom32_0(v)
   356  	case OpCom8:
   357  		return rewriteValue386_OpCom8_0(v)
   358  	case OpConst16:
   359  		return rewriteValue386_OpConst16_0(v)
   360  	case OpConst32:
   361  		return rewriteValue386_OpConst32_0(v)
   362  	case OpConst32F:
   363  		return rewriteValue386_OpConst32F_0(v)
   364  	case OpConst64F:
   365  		return rewriteValue386_OpConst64F_0(v)
   366  	case OpConst8:
   367  		return rewriteValue386_OpConst8_0(v)
   368  	case OpConstBool:
   369  		return rewriteValue386_OpConstBool_0(v)
   370  	case OpConstNil:
   371  		return rewriteValue386_OpConstNil_0(v)
   372  	case OpCvt32Fto32:
   373  		return rewriteValue386_OpCvt32Fto32_0(v)
   374  	case OpCvt32Fto64F:
   375  		return rewriteValue386_OpCvt32Fto64F_0(v)
   376  	case OpCvt32to32F:
   377  		return rewriteValue386_OpCvt32to32F_0(v)
   378  	case OpCvt32to64F:
   379  		return rewriteValue386_OpCvt32to64F_0(v)
   380  	case OpCvt64Fto32:
   381  		return rewriteValue386_OpCvt64Fto32_0(v)
   382  	case OpCvt64Fto32F:
   383  		return rewriteValue386_OpCvt64Fto32F_0(v)
   384  	case OpDiv16:
   385  		return rewriteValue386_OpDiv16_0(v)
   386  	case OpDiv16u:
   387  		return rewriteValue386_OpDiv16u_0(v)
   388  	case OpDiv32:
   389  		return rewriteValue386_OpDiv32_0(v)
   390  	case OpDiv32F:
   391  		return rewriteValue386_OpDiv32F_0(v)
   392  	case OpDiv32u:
   393  		return rewriteValue386_OpDiv32u_0(v)
   394  	case OpDiv64F:
   395  		return rewriteValue386_OpDiv64F_0(v)
   396  	case OpDiv8:
   397  		return rewriteValue386_OpDiv8_0(v)
   398  	case OpDiv8u:
   399  		return rewriteValue386_OpDiv8u_0(v)
   400  	case OpEq16:
   401  		return rewriteValue386_OpEq16_0(v)
   402  	case OpEq32:
   403  		return rewriteValue386_OpEq32_0(v)
   404  	case OpEq32F:
   405  		return rewriteValue386_OpEq32F_0(v)
   406  	case OpEq64F:
   407  		return rewriteValue386_OpEq64F_0(v)
   408  	case OpEq8:
   409  		return rewriteValue386_OpEq8_0(v)
   410  	case OpEqB:
   411  		return rewriteValue386_OpEqB_0(v)
   412  	case OpEqPtr:
   413  		return rewriteValue386_OpEqPtr_0(v)
   414  	case OpGeq16:
   415  		return rewriteValue386_OpGeq16_0(v)
   416  	case OpGeq16U:
   417  		return rewriteValue386_OpGeq16U_0(v)
   418  	case OpGeq32:
   419  		return rewriteValue386_OpGeq32_0(v)
   420  	case OpGeq32F:
   421  		return rewriteValue386_OpGeq32F_0(v)
   422  	case OpGeq32U:
   423  		return rewriteValue386_OpGeq32U_0(v)
   424  	case OpGeq64F:
   425  		return rewriteValue386_OpGeq64F_0(v)
   426  	case OpGeq8:
   427  		return rewriteValue386_OpGeq8_0(v)
   428  	case OpGeq8U:
   429  		return rewriteValue386_OpGeq8U_0(v)
   430  	case OpGetCallerPC:
   431  		return rewriteValue386_OpGetCallerPC_0(v)
   432  	case OpGetCallerSP:
   433  		return rewriteValue386_OpGetCallerSP_0(v)
   434  	case OpGetClosurePtr:
   435  		return rewriteValue386_OpGetClosurePtr_0(v)
   436  	case OpGetG:
   437  		return rewriteValue386_OpGetG_0(v)
   438  	case OpGreater16:
   439  		return rewriteValue386_OpGreater16_0(v)
   440  	case OpGreater16U:
   441  		return rewriteValue386_OpGreater16U_0(v)
   442  	case OpGreater32:
   443  		return rewriteValue386_OpGreater32_0(v)
   444  	case OpGreater32F:
   445  		return rewriteValue386_OpGreater32F_0(v)
   446  	case OpGreater32U:
   447  		return rewriteValue386_OpGreater32U_0(v)
   448  	case OpGreater64F:
   449  		return rewriteValue386_OpGreater64F_0(v)
   450  	case OpGreater8:
   451  		return rewriteValue386_OpGreater8_0(v)
   452  	case OpGreater8U:
   453  		return rewriteValue386_OpGreater8U_0(v)
   454  	case OpHmul32:
   455  		return rewriteValue386_OpHmul32_0(v)
   456  	case OpHmul32u:
   457  		return rewriteValue386_OpHmul32u_0(v)
   458  	case OpInterCall:
   459  		return rewriteValue386_OpInterCall_0(v)
   460  	case OpIsInBounds:
   461  		return rewriteValue386_OpIsInBounds_0(v)
   462  	case OpIsNonNil:
   463  		return rewriteValue386_OpIsNonNil_0(v)
   464  	case OpIsSliceInBounds:
   465  		return rewriteValue386_OpIsSliceInBounds_0(v)
   466  	case OpLeq16:
   467  		return rewriteValue386_OpLeq16_0(v)
   468  	case OpLeq16U:
   469  		return rewriteValue386_OpLeq16U_0(v)
   470  	case OpLeq32:
   471  		return rewriteValue386_OpLeq32_0(v)
   472  	case OpLeq32F:
   473  		return rewriteValue386_OpLeq32F_0(v)
   474  	case OpLeq32U:
   475  		return rewriteValue386_OpLeq32U_0(v)
   476  	case OpLeq64F:
   477  		return rewriteValue386_OpLeq64F_0(v)
   478  	case OpLeq8:
   479  		return rewriteValue386_OpLeq8_0(v)
   480  	case OpLeq8U:
   481  		return rewriteValue386_OpLeq8U_0(v)
   482  	case OpLess16:
   483  		return rewriteValue386_OpLess16_0(v)
   484  	case OpLess16U:
   485  		return rewriteValue386_OpLess16U_0(v)
   486  	case OpLess32:
   487  		return rewriteValue386_OpLess32_0(v)
   488  	case OpLess32F:
   489  		return rewriteValue386_OpLess32F_0(v)
   490  	case OpLess32U:
   491  		return rewriteValue386_OpLess32U_0(v)
   492  	case OpLess64F:
   493  		return rewriteValue386_OpLess64F_0(v)
   494  	case OpLess8:
   495  		return rewriteValue386_OpLess8_0(v)
   496  	case OpLess8U:
   497  		return rewriteValue386_OpLess8U_0(v)
   498  	case OpLoad:
   499  		return rewriteValue386_OpLoad_0(v)
   500  	case OpLocalAddr:
   501  		return rewriteValue386_OpLocalAddr_0(v)
   502  	case OpLsh16x16:
   503  		return rewriteValue386_OpLsh16x16_0(v)
   504  	case OpLsh16x32:
   505  		return rewriteValue386_OpLsh16x32_0(v)
   506  	case OpLsh16x64:
   507  		return rewriteValue386_OpLsh16x64_0(v)
   508  	case OpLsh16x8:
   509  		return rewriteValue386_OpLsh16x8_0(v)
   510  	case OpLsh32x16:
   511  		return rewriteValue386_OpLsh32x16_0(v)
   512  	case OpLsh32x32:
   513  		return rewriteValue386_OpLsh32x32_0(v)
   514  	case OpLsh32x64:
   515  		return rewriteValue386_OpLsh32x64_0(v)
   516  	case OpLsh32x8:
   517  		return rewriteValue386_OpLsh32x8_0(v)
   518  	case OpLsh8x16:
   519  		return rewriteValue386_OpLsh8x16_0(v)
   520  	case OpLsh8x32:
   521  		return rewriteValue386_OpLsh8x32_0(v)
   522  	case OpLsh8x64:
   523  		return rewriteValue386_OpLsh8x64_0(v)
   524  	case OpLsh8x8:
   525  		return rewriteValue386_OpLsh8x8_0(v)
   526  	case OpMod16:
   527  		return rewriteValue386_OpMod16_0(v)
   528  	case OpMod16u:
   529  		return rewriteValue386_OpMod16u_0(v)
   530  	case OpMod32:
   531  		return rewriteValue386_OpMod32_0(v)
   532  	case OpMod32u:
   533  		return rewriteValue386_OpMod32u_0(v)
   534  	case OpMod8:
   535  		return rewriteValue386_OpMod8_0(v)
   536  	case OpMod8u:
   537  		return rewriteValue386_OpMod8u_0(v)
   538  	case OpMove:
   539  		return rewriteValue386_OpMove_0(v) || rewriteValue386_OpMove_10(v)
   540  	case OpMul16:
   541  		return rewriteValue386_OpMul16_0(v)
   542  	case OpMul32:
   543  		return rewriteValue386_OpMul32_0(v)
   544  	case OpMul32F:
   545  		return rewriteValue386_OpMul32F_0(v)
   546  	case OpMul32uhilo:
   547  		return rewriteValue386_OpMul32uhilo_0(v)
   548  	case OpMul64F:
   549  		return rewriteValue386_OpMul64F_0(v)
   550  	case OpMul8:
   551  		return rewriteValue386_OpMul8_0(v)
   552  	case OpNeg16:
   553  		return rewriteValue386_OpNeg16_0(v)
   554  	case OpNeg32:
   555  		return rewriteValue386_OpNeg32_0(v)
   556  	case OpNeg32F:
   557  		return rewriteValue386_OpNeg32F_0(v)
   558  	case OpNeg64F:
   559  		return rewriteValue386_OpNeg64F_0(v)
   560  	case OpNeg8:
   561  		return rewriteValue386_OpNeg8_0(v)
   562  	case OpNeq16:
   563  		return rewriteValue386_OpNeq16_0(v)
   564  	case OpNeq32:
   565  		return rewriteValue386_OpNeq32_0(v)
   566  	case OpNeq32F:
   567  		return rewriteValue386_OpNeq32F_0(v)
   568  	case OpNeq64F:
   569  		return rewriteValue386_OpNeq64F_0(v)
   570  	case OpNeq8:
   571  		return rewriteValue386_OpNeq8_0(v)
   572  	case OpNeqB:
   573  		return rewriteValue386_OpNeqB_0(v)
   574  	case OpNeqPtr:
   575  		return rewriteValue386_OpNeqPtr_0(v)
   576  	case OpNilCheck:
   577  		return rewriteValue386_OpNilCheck_0(v)
   578  	case OpNot:
   579  		return rewriteValue386_OpNot_0(v)
   580  	case OpOffPtr:
   581  		return rewriteValue386_OpOffPtr_0(v)
   582  	case OpOr16:
   583  		return rewriteValue386_OpOr16_0(v)
   584  	case OpOr32:
   585  		return rewriteValue386_OpOr32_0(v)
   586  	case OpOr8:
   587  		return rewriteValue386_OpOr8_0(v)
   588  	case OpOrB:
   589  		return rewriteValue386_OpOrB_0(v)
   590  	case OpRound32F:
   591  		return rewriteValue386_OpRound32F_0(v)
   592  	case OpRound64F:
   593  		return rewriteValue386_OpRound64F_0(v)
   594  	case OpRsh16Ux16:
   595  		return rewriteValue386_OpRsh16Ux16_0(v)
   596  	case OpRsh16Ux32:
   597  		return rewriteValue386_OpRsh16Ux32_0(v)
   598  	case OpRsh16Ux64:
   599  		return rewriteValue386_OpRsh16Ux64_0(v)
   600  	case OpRsh16Ux8:
   601  		return rewriteValue386_OpRsh16Ux8_0(v)
   602  	case OpRsh16x16:
   603  		return rewriteValue386_OpRsh16x16_0(v)
   604  	case OpRsh16x32:
   605  		return rewriteValue386_OpRsh16x32_0(v)
   606  	case OpRsh16x64:
   607  		return rewriteValue386_OpRsh16x64_0(v)
   608  	case OpRsh16x8:
   609  		return rewriteValue386_OpRsh16x8_0(v)
   610  	case OpRsh32Ux16:
   611  		return rewriteValue386_OpRsh32Ux16_0(v)
   612  	case OpRsh32Ux32:
   613  		return rewriteValue386_OpRsh32Ux32_0(v)
   614  	case OpRsh32Ux64:
   615  		return rewriteValue386_OpRsh32Ux64_0(v)
   616  	case OpRsh32Ux8:
   617  		return rewriteValue386_OpRsh32Ux8_0(v)
   618  	case OpRsh32x16:
   619  		return rewriteValue386_OpRsh32x16_0(v)
   620  	case OpRsh32x32:
   621  		return rewriteValue386_OpRsh32x32_0(v)
   622  	case OpRsh32x64:
   623  		return rewriteValue386_OpRsh32x64_0(v)
   624  	case OpRsh32x8:
   625  		return rewriteValue386_OpRsh32x8_0(v)
   626  	case OpRsh8Ux16:
   627  		return rewriteValue386_OpRsh8Ux16_0(v)
   628  	case OpRsh8Ux32:
   629  		return rewriteValue386_OpRsh8Ux32_0(v)
   630  	case OpRsh8Ux64:
   631  		return rewriteValue386_OpRsh8Ux64_0(v)
   632  	case OpRsh8Ux8:
   633  		return rewriteValue386_OpRsh8Ux8_0(v)
   634  	case OpRsh8x16:
   635  		return rewriteValue386_OpRsh8x16_0(v)
   636  	case OpRsh8x32:
   637  		return rewriteValue386_OpRsh8x32_0(v)
   638  	case OpRsh8x64:
   639  		return rewriteValue386_OpRsh8x64_0(v)
   640  	case OpRsh8x8:
   641  		return rewriteValue386_OpRsh8x8_0(v)
   642  	case OpSelect0:
   643  		return rewriteValue386_OpSelect0_0(v)
   644  	case OpSelect1:
   645  		return rewriteValue386_OpSelect1_0(v)
   646  	case OpSignExt16to32:
   647  		return rewriteValue386_OpSignExt16to32_0(v)
   648  	case OpSignExt8to16:
   649  		return rewriteValue386_OpSignExt8to16_0(v)
   650  	case OpSignExt8to32:
   651  		return rewriteValue386_OpSignExt8to32_0(v)
   652  	case OpSignmask:
   653  		return rewriteValue386_OpSignmask_0(v)
   654  	case OpSlicemask:
   655  		return rewriteValue386_OpSlicemask_0(v)
   656  	case OpSqrt:
   657  		return rewriteValue386_OpSqrt_0(v)
   658  	case OpStaticCall:
   659  		return rewriteValue386_OpStaticCall_0(v)
   660  	case OpStore:
   661  		return rewriteValue386_OpStore_0(v)
   662  	case OpSub16:
   663  		return rewriteValue386_OpSub16_0(v)
   664  	case OpSub32:
   665  		return rewriteValue386_OpSub32_0(v)
   666  	case OpSub32F:
   667  		return rewriteValue386_OpSub32F_0(v)
   668  	case OpSub32carry:
   669  		return rewriteValue386_OpSub32carry_0(v)
   670  	case OpSub32withcarry:
   671  		return rewriteValue386_OpSub32withcarry_0(v)
   672  	case OpSub64F:
   673  		return rewriteValue386_OpSub64F_0(v)
   674  	case OpSub8:
   675  		return rewriteValue386_OpSub8_0(v)
   676  	case OpSubPtr:
   677  		return rewriteValue386_OpSubPtr_0(v)
   678  	case OpTrunc16to8:
   679  		return rewriteValue386_OpTrunc16to8_0(v)
   680  	case OpTrunc32to16:
   681  		return rewriteValue386_OpTrunc32to16_0(v)
   682  	case OpTrunc32to8:
   683  		return rewriteValue386_OpTrunc32to8_0(v)
   684  	case OpWB:
   685  		return rewriteValue386_OpWB_0(v)
   686  	case OpXor16:
   687  		return rewriteValue386_OpXor16_0(v)
   688  	case OpXor32:
   689  		return rewriteValue386_OpXor32_0(v)
   690  	case OpXor8:
   691  		return rewriteValue386_OpXor8_0(v)
   692  	case OpZero:
   693  		return rewriteValue386_OpZero_0(v) || rewriteValue386_OpZero_10(v)
   694  	case OpZeroExt16to32:
   695  		return rewriteValue386_OpZeroExt16to32_0(v)
   696  	case OpZeroExt8to16:
   697  		return rewriteValue386_OpZeroExt8to16_0(v)
   698  	case OpZeroExt8to32:
   699  		return rewriteValue386_OpZeroExt8to32_0(v)
   700  	case OpZeromask:
   701  		return rewriteValue386_OpZeromask_0(v)
   702  	}
   703  	return false
   704  }
   705  func rewriteValue386_Op386ADCL_0(v *Value) bool {
   706  	// match: (ADCL x (MOVLconst [c]) f)
   707  	// cond:
   708  	// result: (ADCLconst [c] x f)
   709  	for {
   710  		_ = v.Args[2]
   711  		x := v.Args[0]
   712  		v_1 := v.Args[1]
   713  		if v_1.Op != Op386MOVLconst {
   714  			break
   715  		}
   716  		c := v_1.AuxInt
   717  		f := v.Args[2]
   718  		v.reset(Op386ADCLconst)
   719  		v.AuxInt = c
   720  		v.AddArg(x)
   721  		v.AddArg(f)
   722  		return true
   723  	}
   724  	// match: (ADCL (MOVLconst [c]) x f)
   725  	// cond:
   726  	// result: (ADCLconst [c] x f)
   727  	for {
   728  		_ = v.Args[2]
   729  		v_0 := v.Args[0]
   730  		if v_0.Op != Op386MOVLconst {
   731  			break
   732  		}
   733  		c := v_0.AuxInt
   734  		x := v.Args[1]
   735  		f := v.Args[2]
   736  		v.reset(Op386ADCLconst)
   737  		v.AuxInt = c
   738  		v.AddArg(x)
   739  		v.AddArg(f)
   740  		return true
   741  	}
   742  	// match: (ADCL (MOVLconst [c]) x f)
   743  	// cond:
   744  	// result: (ADCLconst [c] x f)
   745  	for {
   746  		_ = v.Args[2]
   747  		v_0 := v.Args[0]
   748  		if v_0.Op != Op386MOVLconst {
   749  			break
   750  		}
   751  		c := v_0.AuxInt
   752  		x := v.Args[1]
   753  		f := v.Args[2]
   754  		v.reset(Op386ADCLconst)
   755  		v.AuxInt = c
   756  		v.AddArg(x)
   757  		v.AddArg(f)
   758  		return true
   759  	}
   760  	// match: (ADCL x (MOVLconst [c]) f)
   761  	// cond:
   762  	// result: (ADCLconst [c] x f)
   763  	for {
   764  		_ = v.Args[2]
   765  		x := v.Args[0]
   766  		v_1 := v.Args[1]
   767  		if v_1.Op != Op386MOVLconst {
   768  			break
   769  		}
   770  		c := v_1.AuxInt
   771  		f := v.Args[2]
   772  		v.reset(Op386ADCLconst)
   773  		v.AuxInt = c
   774  		v.AddArg(x)
   775  		v.AddArg(f)
   776  		return true
   777  	}
   778  	return false
   779  }
   780  func rewriteValue386_Op386ADDL_0(v *Value) bool {
   781  	// match: (ADDL x (MOVLconst [c]))
   782  	// cond:
   783  	// result: (ADDLconst [c] x)
   784  	for {
   785  		_ = v.Args[1]
   786  		x := v.Args[0]
   787  		v_1 := v.Args[1]
   788  		if v_1.Op != Op386MOVLconst {
   789  			break
   790  		}
   791  		c := v_1.AuxInt
   792  		v.reset(Op386ADDLconst)
   793  		v.AuxInt = c
   794  		v.AddArg(x)
   795  		return true
   796  	}
   797  	// match: (ADDL (MOVLconst [c]) x)
   798  	// cond:
   799  	// result: (ADDLconst [c] x)
   800  	for {
   801  		_ = v.Args[1]
   802  		v_0 := v.Args[0]
   803  		if v_0.Op != Op386MOVLconst {
   804  			break
   805  		}
   806  		c := v_0.AuxInt
   807  		x := v.Args[1]
   808  		v.reset(Op386ADDLconst)
   809  		v.AuxInt = c
   810  		v.AddArg(x)
   811  		return true
   812  	}
   813  	// match: (ADDL (SHLLconst [c] x) (SHRLconst [d] x))
   814  	// cond: d == 32-c
   815  	// result: (ROLLconst [c] x)
   816  	for {
   817  		_ = v.Args[1]
   818  		v_0 := v.Args[0]
   819  		if v_0.Op != Op386SHLLconst {
   820  			break
   821  		}
   822  		c := v_0.AuxInt
   823  		x := v_0.Args[0]
   824  		v_1 := v.Args[1]
   825  		if v_1.Op != Op386SHRLconst {
   826  			break
   827  		}
   828  		d := v_1.AuxInt
   829  		if x != v_1.Args[0] {
   830  			break
   831  		}
   832  		if !(d == 32-c) {
   833  			break
   834  		}
   835  		v.reset(Op386ROLLconst)
   836  		v.AuxInt = c
   837  		v.AddArg(x)
   838  		return true
   839  	}
   840  	// match: (ADDL (SHRLconst [d] x) (SHLLconst [c] x))
   841  	// cond: d == 32-c
   842  	// result: (ROLLconst [c] x)
   843  	for {
   844  		_ = v.Args[1]
   845  		v_0 := v.Args[0]
   846  		if v_0.Op != Op386SHRLconst {
   847  			break
   848  		}
   849  		d := v_0.AuxInt
   850  		x := v_0.Args[0]
   851  		v_1 := v.Args[1]
   852  		if v_1.Op != Op386SHLLconst {
   853  			break
   854  		}
   855  		c := v_1.AuxInt
   856  		if x != v_1.Args[0] {
   857  			break
   858  		}
   859  		if !(d == 32-c) {
   860  			break
   861  		}
   862  		v.reset(Op386ROLLconst)
   863  		v.AuxInt = c
   864  		v.AddArg(x)
   865  		return true
   866  	}
   867  	// match: (ADDL <t> (SHLLconst x [c]) (SHRWconst x [d]))
   868  	// cond: c < 16 && d == 16-c && t.Size() == 2
   869  	// result: (ROLWconst x [c])
   870  	for {
   871  		t := v.Type
   872  		_ = v.Args[1]
   873  		v_0 := v.Args[0]
   874  		if v_0.Op != Op386SHLLconst {
   875  			break
   876  		}
   877  		c := v_0.AuxInt
   878  		x := v_0.Args[0]
   879  		v_1 := v.Args[1]
   880  		if v_1.Op != Op386SHRWconst {
   881  			break
   882  		}
   883  		d := v_1.AuxInt
   884  		if x != v_1.Args[0] {
   885  			break
   886  		}
   887  		if !(c < 16 && d == 16-c && t.Size() == 2) {
   888  			break
   889  		}
   890  		v.reset(Op386ROLWconst)
   891  		v.AuxInt = c
   892  		v.AddArg(x)
   893  		return true
   894  	}
   895  	// match: (ADDL <t> (SHRWconst x [d]) (SHLLconst x [c]))
   896  	// cond: c < 16 && d == 16-c && t.Size() == 2
   897  	// result: (ROLWconst x [c])
   898  	for {
   899  		t := v.Type
   900  		_ = v.Args[1]
   901  		v_0 := v.Args[0]
   902  		if v_0.Op != Op386SHRWconst {
   903  			break
   904  		}
   905  		d := v_0.AuxInt
   906  		x := v_0.Args[0]
   907  		v_1 := v.Args[1]
   908  		if v_1.Op != Op386SHLLconst {
   909  			break
   910  		}
   911  		c := v_1.AuxInt
   912  		if x != v_1.Args[0] {
   913  			break
   914  		}
   915  		if !(c < 16 && d == 16-c && t.Size() == 2) {
   916  			break
   917  		}
   918  		v.reset(Op386ROLWconst)
   919  		v.AuxInt = c
   920  		v.AddArg(x)
   921  		return true
   922  	}
   923  	// match: (ADDL <t> (SHLLconst x [c]) (SHRBconst x [d]))
   924  	// cond: c < 8 && d == 8-c && t.Size() == 1
   925  	// result: (ROLBconst x [c])
   926  	for {
   927  		t := v.Type
   928  		_ = v.Args[1]
   929  		v_0 := v.Args[0]
   930  		if v_0.Op != Op386SHLLconst {
   931  			break
   932  		}
   933  		c := v_0.AuxInt
   934  		x := v_0.Args[0]
   935  		v_1 := v.Args[1]
   936  		if v_1.Op != Op386SHRBconst {
   937  			break
   938  		}
   939  		d := v_1.AuxInt
   940  		if x != v_1.Args[0] {
   941  			break
   942  		}
   943  		if !(c < 8 && d == 8-c && t.Size() == 1) {
   944  			break
   945  		}
   946  		v.reset(Op386ROLBconst)
   947  		v.AuxInt = c
   948  		v.AddArg(x)
   949  		return true
   950  	}
   951  	// match: (ADDL <t> (SHRBconst x [d]) (SHLLconst x [c]))
   952  	// cond: c < 8 && d == 8-c && t.Size() == 1
   953  	// result: (ROLBconst x [c])
   954  	for {
   955  		t := v.Type
   956  		_ = v.Args[1]
   957  		v_0 := v.Args[0]
   958  		if v_0.Op != Op386SHRBconst {
   959  			break
   960  		}
   961  		d := v_0.AuxInt
   962  		x := v_0.Args[0]
   963  		v_1 := v.Args[1]
   964  		if v_1.Op != Op386SHLLconst {
   965  			break
   966  		}
   967  		c := v_1.AuxInt
   968  		if x != v_1.Args[0] {
   969  			break
   970  		}
   971  		if !(c < 8 && d == 8-c && t.Size() == 1) {
   972  			break
   973  		}
   974  		v.reset(Op386ROLBconst)
   975  		v.AuxInt = c
   976  		v.AddArg(x)
   977  		return true
   978  	}
   979  	// match: (ADDL x (SHLLconst [3] y))
   980  	// cond:
   981  	// result: (LEAL8 x y)
   982  	for {
   983  		_ = v.Args[1]
   984  		x := v.Args[0]
   985  		v_1 := v.Args[1]
   986  		if v_1.Op != Op386SHLLconst {
   987  			break
   988  		}
   989  		if v_1.AuxInt != 3 {
   990  			break
   991  		}
   992  		y := v_1.Args[0]
   993  		v.reset(Op386LEAL8)
   994  		v.AddArg(x)
   995  		v.AddArg(y)
   996  		return true
   997  	}
   998  	// match: (ADDL (SHLLconst [3] y) x)
   999  	// cond:
  1000  	// result: (LEAL8 x y)
  1001  	for {
  1002  		_ = v.Args[1]
  1003  		v_0 := v.Args[0]
  1004  		if v_0.Op != Op386SHLLconst {
  1005  			break
  1006  		}
  1007  		if v_0.AuxInt != 3 {
  1008  			break
  1009  		}
  1010  		y := v_0.Args[0]
  1011  		x := v.Args[1]
  1012  		v.reset(Op386LEAL8)
  1013  		v.AddArg(x)
  1014  		v.AddArg(y)
  1015  		return true
  1016  	}
  1017  	return false
  1018  }
  1019  func rewriteValue386_Op386ADDL_10(v *Value) bool {
  1020  	// match: (ADDL x (SHLLconst [2] y))
  1021  	// cond:
  1022  	// result: (LEAL4 x y)
  1023  	for {
  1024  		_ = v.Args[1]
  1025  		x := v.Args[0]
  1026  		v_1 := v.Args[1]
  1027  		if v_1.Op != Op386SHLLconst {
  1028  			break
  1029  		}
  1030  		if v_1.AuxInt != 2 {
  1031  			break
  1032  		}
  1033  		y := v_1.Args[0]
  1034  		v.reset(Op386LEAL4)
  1035  		v.AddArg(x)
  1036  		v.AddArg(y)
  1037  		return true
  1038  	}
  1039  	// match: (ADDL (SHLLconst [2] y) x)
  1040  	// cond:
  1041  	// result: (LEAL4 x y)
  1042  	for {
  1043  		_ = v.Args[1]
  1044  		v_0 := v.Args[0]
  1045  		if v_0.Op != Op386SHLLconst {
  1046  			break
  1047  		}
  1048  		if v_0.AuxInt != 2 {
  1049  			break
  1050  		}
  1051  		y := v_0.Args[0]
  1052  		x := v.Args[1]
  1053  		v.reset(Op386LEAL4)
  1054  		v.AddArg(x)
  1055  		v.AddArg(y)
  1056  		return true
  1057  	}
  1058  	// match: (ADDL x (SHLLconst [1] y))
  1059  	// cond:
  1060  	// result: (LEAL2 x y)
  1061  	for {
  1062  		_ = v.Args[1]
  1063  		x := v.Args[0]
  1064  		v_1 := v.Args[1]
  1065  		if v_1.Op != Op386SHLLconst {
  1066  			break
  1067  		}
  1068  		if v_1.AuxInt != 1 {
  1069  			break
  1070  		}
  1071  		y := v_1.Args[0]
  1072  		v.reset(Op386LEAL2)
  1073  		v.AddArg(x)
  1074  		v.AddArg(y)
  1075  		return true
  1076  	}
  1077  	// match: (ADDL (SHLLconst [1] y) x)
  1078  	// cond:
  1079  	// result: (LEAL2 x y)
  1080  	for {
  1081  		_ = v.Args[1]
  1082  		v_0 := v.Args[0]
  1083  		if v_0.Op != Op386SHLLconst {
  1084  			break
  1085  		}
  1086  		if v_0.AuxInt != 1 {
  1087  			break
  1088  		}
  1089  		y := v_0.Args[0]
  1090  		x := v.Args[1]
  1091  		v.reset(Op386LEAL2)
  1092  		v.AddArg(x)
  1093  		v.AddArg(y)
  1094  		return true
  1095  	}
  1096  	// match: (ADDL x (ADDL y y))
  1097  	// cond:
  1098  	// result: (LEAL2 x y)
  1099  	for {
  1100  		_ = v.Args[1]
  1101  		x := v.Args[0]
  1102  		v_1 := v.Args[1]
  1103  		if v_1.Op != Op386ADDL {
  1104  			break
  1105  		}
  1106  		_ = v_1.Args[1]
  1107  		y := v_1.Args[0]
  1108  		if y != v_1.Args[1] {
  1109  			break
  1110  		}
  1111  		v.reset(Op386LEAL2)
  1112  		v.AddArg(x)
  1113  		v.AddArg(y)
  1114  		return true
  1115  	}
  1116  	// match: (ADDL (ADDL y y) x)
  1117  	// cond:
  1118  	// result: (LEAL2 x y)
  1119  	for {
  1120  		_ = v.Args[1]
  1121  		v_0 := v.Args[0]
  1122  		if v_0.Op != Op386ADDL {
  1123  			break
  1124  		}
  1125  		_ = v_0.Args[1]
  1126  		y := v_0.Args[0]
  1127  		if y != v_0.Args[1] {
  1128  			break
  1129  		}
  1130  		x := v.Args[1]
  1131  		v.reset(Op386LEAL2)
  1132  		v.AddArg(x)
  1133  		v.AddArg(y)
  1134  		return true
  1135  	}
  1136  	// match: (ADDL x (ADDL x y))
  1137  	// cond:
  1138  	// result: (LEAL2 y x)
  1139  	for {
  1140  		_ = v.Args[1]
  1141  		x := v.Args[0]
  1142  		v_1 := v.Args[1]
  1143  		if v_1.Op != Op386ADDL {
  1144  			break
  1145  		}
  1146  		_ = v_1.Args[1]
  1147  		if x != v_1.Args[0] {
  1148  			break
  1149  		}
  1150  		y := v_1.Args[1]
  1151  		v.reset(Op386LEAL2)
  1152  		v.AddArg(y)
  1153  		v.AddArg(x)
  1154  		return true
  1155  	}
  1156  	// match: (ADDL x (ADDL y x))
  1157  	// cond:
  1158  	// result: (LEAL2 y x)
  1159  	for {
  1160  		_ = v.Args[1]
  1161  		x := v.Args[0]
  1162  		v_1 := v.Args[1]
  1163  		if v_1.Op != Op386ADDL {
  1164  			break
  1165  		}
  1166  		_ = v_1.Args[1]
  1167  		y := v_1.Args[0]
  1168  		if x != v_1.Args[1] {
  1169  			break
  1170  		}
  1171  		v.reset(Op386LEAL2)
  1172  		v.AddArg(y)
  1173  		v.AddArg(x)
  1174  		return true
  1175  	}
  1176  	// match: (ADDL (ADDL x y) x)
  1177  	// cond:
  1178  	// result: (LEAL2 y x)
  1179  	for {
  1180  		_ = v.Args[1]
  1181  		v_0 := v.Args[0]
  1182  		if v_0.Op != Op386ADDL {
  1183  			break
  1184  		}
  1185  		_ = v_0.Args[1]
  1186  		x := v_0.Args[0]
  1187  		y := v_0.Args[1]
  1188  		if x != v.Args[1] {
  1189  			break
  1190  		}
  1191  		v.reset(Op386LEAL2)
  1192  		v.AddArg(y)
  1193  		v.AddArg(x)
  1194  		return true
  1195  	}
  1196  	// match: (ADDL (ADDL y x) x)
  1197  	// cond:
  1198  	// result: (LEAL2 y x)
  1199  	for {
  1200  		_ = v.Args[1]
  1201  		v_0 := v.Args[0]
  1202  		if v_0.Op != Op386ADDL {
  1203  			break
  1204  		}
  1205  		_ = v_0.Args[1]
  1206  		y := v_0.Args[0]
  1207  		x := v_0.Args[1]
  1208  		if x != v.Args[1] {
  1209  			break
  1210  		}
  1211  		v.reset(Op386LEAL2)
  1212  		v.AddArg(y)
  1213  		v.AddArg(x)
  1214  		return true
  1215  	}
  1216  	return false
  1217  }
  1218  func rewriteValue386_Op386ADDL_20(v *Value) bool {
  1219  	// match: (ADDL (ADDLconst [c] x) y)
  1220  	// cond:
  1221  	// result: (LEAL1 [c] x y)
  1222  	for {
  1223  		_ = v.Args[1]
  1224  		v_0 := v.Args[0]
  1225  		if v_0.Op != Op386ADDLconst {
  1226  			break
  1227  		}
  1228  		c := v_0.AuxInt
  1229  		x := v_0.Args[0]
  1230  		y := v.Args[1]
  1231  		v.reset(Op386LEAL1)
  1232  		v.AuxInt = c
  1233  		v.AddArg(x)
  1234  		v.AddArg(y)
  1235  		return true
  1236  	}
  1237  	// match: (ADDL y (ADDLconst [c] x))
  1238  	// cond:
  1239  	// result: (LEAL1 [c] x y)
  1240  	for {
  1241  		_ = v.Args[1]
  1242  		y := v.Args[0]
  1243  		v_1 := v.Args[1]
  1244  		if v_1.Op != Op386ADDLconst {
  1245  			break
  1246  		}
  1247  		c := v_1.AuxInt
  1248  		x := v_1.Args[0]
  1249  		v.reset(Op386LEAL1)
  1250  		v.AuxInt = c
  1251  		v.AddArg(x)
  1252  		v.AddArg(y)
  1253  		return true
  1254  	}
  1255  	// match: (ADDL x (LEAL [c] {s} y))
  1256  	// cond: x.Op != OpSB && y.Op != OpSB
  1257  	// result: (LEAL1 [c] {s} x y)
  1258  	for {
  1259  		_ = v.Args[1]
  1260  		x := v.Args[0]
  1261  		v_1 := v.Args[1]
  1262  		if v_1.Op != Op386LEAL {
  1263  			break
  1264  		}
  1265  		c := v_1.AuxInt
  1266  		s := v_1.Aux
  1267  		y := v_1.Args[0]
  1268  		if !(x.Op != OpSB && y.Op != OpSB) {
  1269  			break
  1270  		}
  1271  		v.reset(Op386LEAL1)
  1272  		v.AuxInt = c
  1273  		v.Aux = s
  1274  		v.AddArg(x)
  1275  		v.AddArg(y)
  1276  		return true
  1277  	}
  1278  	// match: (ADDL (LEAL [c] {s} y) x)
  1279  	// cond: x.Op != OpSB && y.Op != OpSB
  1280  	// result: (LEAL1 [c] {s} x y)
  1281  	for {
  1282  		_ = v.Args[1]
  1283  		v_0 := v.Args[0]
  1284  		if v_0.Op != Op386LEAL {
  1285  			break
  1286  		}
  1287  		c := v_0.AuxInt
  1288  		s := v_0.Aux
  1289  		y := v_0.Args[0]
  1290  		x := v.Args[1]
  1291  		if !(x.Op != OpSB && y.Op != OpSB) {
  1292  			break
  1293  		}
  1294  		v.reset(Op386LEAL1)
  1295  		v.AuxInt = c
  1296  		v.Aux = s
  1297  		v.AddArg(x)
  1298  		v.AddArg(y)
  1299  		return true
  1300  	}
  1301  	// match: (ADDL x l:(MOVLload [off] {sym} ptr mem))
  1302  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  1303  	// result: (ADDLload x [off] {sym} ptr mem)
  1304  	for {
  1305  		_ = v.Args[1]
  1306  		x := v.Args[0]
  1307  		l := v.Args[1]
  1308  		if l.Op != Op386MOVLload {
  1309  			break
  1310  		}
  1311  		off := l.AuxInt
  1312  		sym := l.Aux
  1313  		_ = l.Args[1]
  1314  		ptr := l.Args[0]
  1315  		mem := l.Args[1]
  1316  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  1317  			break
  1318  		}
  1319  		v.reset(Op386ADDLload)
  1320  		v.AuxInt = off
  1321  		v.Aux = sym
  1322  		v.AddArg(x)
  1323  		v.AddArg(ptr)
  1324  		v.AddArg(mem)
  1325  		return true
  1326  	}
  1327  	// match: (ADDL l:(MOVLload [off] {sym} ptr mem) x)
  1328  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  1329  	// result: (ADDLload x [off] {sym} ptr mem)
  1330  	for {
  1331  		_ = v.Args[1]
  1332  		l := v.Args[0]
  1333  		if l.Op != Op386MOVLload {
  1334  			break
  1335  		}
  1336  		off := l.AuxInt
  1337  		sym := l.Aux
  1338  		_ = l.Args[1]
  1339  		ptr := l.Args[0]
  1340  		mem := l.Args[1]
  1341  		x := v.Args[1]
  1342  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  1343  			break
  1344  		}
  1345  		v.reset(Op386ADDLload)
  1346  		v.AuxInt = off
  1347  		v.Aux = sym
  1348  		v.AddArg(x)
  1349  		v.AddArg(ptr)
  1350  		v.AddArg(mem)
  1351  		return true
  1352  	}
  1353  	// match: (ADDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem))
  1354  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  1355  	// result: (ADDLloadidx4 x [off] {sym} ptr idx mem)
  1356  	for {
  1357  		_ = v.Args[1]
  1358  		x := v.Args[0]
  1359  		l := v.Args[1]
  1360  		if l.Op != Op386MOVLloadidx4 {
  1361  			break
  1362  		}
  1363  		off := l.AuxInt
  1364  		sym := l.Aux
  1365  		_ = l.Args[2]
  1366  		ptr := l.Args[0]
  1367  		idx := l.Args[1]
  1368  		mem := l.Args[2]
  1369  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  1370  			break
  1371  		}
  1372  		v.reset(Op386ADDLloadidx4)
  1373  		v.AuxInt = off
  1374  		v.Aux = sym
  1375  		v.AddArg(x)
  1376  		v.AddArg(ptr)
  1377  		v.AddArg(idx)
  1378  		v.AddArg(mem)
  1379  		return true
  1380  	}
  1381  	// match: (ADDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x)
  1382  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  1383  	// result: (ADDLloadidx4 x [off] {sym} ptr idx mem)
  1384  	for {
  1385  		_ = v.Args[1]
  1386  		l := v.Args[0]
  1387  		if l.Op != Op386MOVLloadidx4 {
  1388  			break
  1389  		}
  1390  		off := l.AuxInt
  1391  		sym := l.Aux
  1392  		_ = l.Args[2]
  1393  		ptr := l.Args[0]
  1394  		idx := l.Args[1]
  1395  		mem := l.Args[2]
  1396  		x := v.Args[1]
  1397  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  1398  			break
  1399  		}
  1400  		v.reset(Op386ADDLloadidx4)
  1401  		v.AuxInt = off
  1402  		v.Aux = sym
  1403  		v.AddArg(x)
  1404  		v.AddArg(ptr)
  1405  		v.AddArg(idx)
  1406  		v.AddArg(mem)
  1407  		return true
  1408  	}
  1409  	// match: (ADDL x (NEGL y))
  1410  	// cond:
  1411  	// result: (SUBL x y)
  1412  	for {
  1413  		_ = v.Args[1]
  1414  		x := v.Args[0]
  1415  		v_1 := v.Args[1]
  1416  		if v_1.Op != Op386NEGL {
  1417  			break
  1418  		}
  1419  		y := v_1.Args[0]
  1420  		v.reset(Op386SUBL)
  1421  		v.AddArg(x)
  1422  		v.AddArg(y)
  1423  		return true
  1424  	}
  1425  	// match: (ADDL (NEGL y) x)
  1426  	// cond:
  1427  	// result: (SUBL x y)
  1428  	for {
  1429  		_ = v.Args[1]
  1430  		v_0 := v.Args[0]
  1431  		if v_0.Op != Op386NEGL {
  1432  			break
  1433  		}
  1434  		y := v_0.Args[0]
  1435  		x := v.Args[1]
  1436  		v.reset(Op386SUBL)
  1437  		v.AddArg(x)
  1438  		v.AddArg(y)
  1439  		return true
  1440  	}
  1441  	return false
  1442  }
  1443  func rewriteValue386_Op386ADDLcarry_0(v *Value) bool {
  1444  	// match: (ADDLcarry x (MOVLconst [c]))
  1445  	// cond:
  1446  	// result: (ADDLconstcarry [c] x)
  1447  	for {
  1448  		_ = v.Args[1]
  1449  		x := v.Args[0]
  1450  		v_1 := v.Args[1]
  1451  		if v_1.Op != Op386MOVLconst {
  1452  			break
  1453  		}
  1454  		c := v_1.AuxInt
  1455  		v.reset(Op386ADDLconstcarry)
  1456  		v.AuxInt = c
  1457  		v.AddArg(x)
  1458  		return true
  1459  	}
  1460  	// match: (ADDLcarry (MOVLconst [c]) x)
  1461  	// cond:
  1462  	// result: (ADDLconstcarry [c] x)
  1463  	for {
  1464  		_ = v.Args[1]
  1465  		v_0 := v.Args[0]
  1466  		if v_0.Op != Op386MOVLconst {
  1467  			break
  1468  		}
  1469  		c := v_0.AuxInt
  1470  		x := v.Args[1]
  1471  		v.reset(Op386ADDLconstcarry)
  1472  		v.AuxInt = c
  1473  		v.AddArg(x)
  1474  		return true
  1475  	}
  1476  	return false
  1477  }
  1478  func rewriteValue386_Op386ADDLconst_0(v *Value) bool {
  1479  	// match: (ADDLconst [c] (ADDL x y))
  1480  	// cond:
  1481  	// result: (LEAL1 [c] x y)
  1482  	for {
  1483  		c := v.AuxInt
  1484  		v_0 := v.Args[0]
  1485  		if v_0.Op != Op386ADDL {
  1486  			break
  1487  		}
  1488  		_ = v_0.Args[1]
  1489  		x := v_0.Args[0]
  1490  		y := v_0.Args[1]
  1491  		v.reset(Op386LEAL1)
  1492  		v.AuxInt = c
  1493  		v.AddArg(x)
  1494  		v.AddArg(y)
  1495  		return true
  1496  	}
  1497  	// match: (ADDLconst [c] (LEAL [d] {s} x))
  1498  	// cond: is32Bit(c+d)
  1499  	// result: (LEAL [c+d] {s} x)
  1500  	for {
  1501  		c := v.AuxInt
  1502  		v_0 := v.Args[0]
  1503  		if v_0.Op != Op386LEAL {
  1504  			break
  1505  		}
  1506  		d := v_0.AuxInt
  1507  		s := v_0.Aux
  1508  		x := v_0.Args[0]
  1509  		if !(is32Bit(c + d)) {
  1510  			break
  1511  		}
  1512  		v.reset(Op386LEAL)
  1513  		v.AuxInt = c + d
  1514  		v.Aux = s
  1515  		v.AddArg(x)
  1516  		return true
  1517  	}
  1518  	// match: (ADDLconst [c] (LEAL1 [d] {s} x y))
  1519  	// cond: is32Bit(c+d)
  1520  	// result: (LEAL1 [c+d] {s} x y)
  1521  	for {
  1522  		c := v.AuxInt
  1523  		v_0 := v.Args[0]
  1524  		if v_0.Op != Op386LEAL1 {
  1525  			break
  1526  		}
  1527  		d := v_0.AuxInt
  1528  		s := v_0.Aux
  1529  		_ = v_0.Args[1]
  1530  		x := v_0.Args[0]
  1531  		y := v_0.Args[1]
  1532  		if !(is32Bit(c + d)) {
  1533  			break
  1534  		}
  1535  		v.reset(Op386LEAL1)
  1536  		v.AuxInt = c + d
  1537  		v.Aux = s
  1538  		v.AddArg(x)
  1539  		v.AddArg(y)
  1540  		return true
  1541  	}
  1542  	// match: (ADDLconst [c] (LEAL2 [d] {s} x y))
  1543  	// cond: is32Bit(c+d)
  1544  	// result: (LEAL2 [c+d] {s} x y)
  1545  	for {
  1546  		c := v.AuxInt
  1547  		v_0 := v.Args[0]
  1548  		if v_0.Op != Op386LEAL2 {
  1549  			break
  1550  		}
  1551  		d := v_0.AuxInt
  1552  		s := v_0.Aux
  1553  		_ = v_0.Args[1]
  1554  		x := v_0.Args[0]
  1555  		y := v_0.Args[1]
  1556  		if !(is32Bit(c + d)) {
  1557  			break
  1558  		}
  1559  		v.reset(Op386LEAL2)
  1560  		v.AuxInt = c + d
  1561  		v.Aux = s
  1562  		v.AddArg(x)
  1563  		v.AddArg(y)
  1564  		return true
  1565  	}
  1566  	// match: (ADDLconst [c] (LEAL4 [d] {s} x y))
  1567  	// cond: is32Bit(c+d)
  1568  	// result: (LEAL4 [c+d] {s} x y)
  1569  	for {
  1570  		c := v.AuxInt
  1571  		v_0 := v.Args[0]
  1572  		if v_0.Op != Op386LEAL4 {
  1573  			break
  1574  		}
  1575  		d := v_0.AuxInt
  1576  		s := v_0.Aux
  1577  		_ = v_0.Args[1]
  1578  		x := v_0.Args[0]
  1579  		y := v_0.Args[1]
  1580  		if !(is32Bit(c + d)) {
  1581  			break
  1582  		}
  1583  		v.reset(Op386LEAL4)
  1584  		v.AuxInt = c + d
  1585  		v.Aux = s
  1586  		v.AddArg(x)
  1587  		v.AddArg(y)
  1588  		return true
  1589  	}
  1590  	// match: (ADDLconst [c] (LEAL8 [d] {s} x y))
  1591  	// cond: is32Bit(c+d)
  1592  	// result: (LEAL8 [c+d] {s} x y)
  1593  	for {
  1594  		c := v.AuxInt
  1595  		v_0 := v.Args[0]
  1596  		if v_0.Op != Op386LEAL8 {
  1597  			break
  1598  		}
  1599  		d := v_0.AuxInt
  1600  		s := v_0.Aux
  1601  		_ = v_0.Args[1]
  1602  		x := v_0.Args[0]
  1603  		y := v_0.Args[1]
  1604  		if !(is32Bit(c + d)) {
  1605  			break
  1606  		}
  1607  		v.reset(Op386LEAL8)
  1608  		v.AuxInt = c + d
  1609  		v.Aux = s
  1610  		v.AddArg(x)
  1611  		v.AddArg(y)
  1612  		return true
  1613  	}
  1614  	// match: (ADDLconst [c] x)
  1615  	// cond: int32(c)==0
  1616  	// result: x
  1617  	for {
  1618  		c := v.AuxInt
  1619  		x := v.Args[0]
  1620  		if !(int32(c) == 0) {
  1621  			break
  1622  		}
  1623  		v.reset(OpCopy)
  1624  		v.Type = x.Type
  1625  		v.AddArg(x)
  1626  		return true
  1627  	}
  1628  	// match: (ADDLconst [c] (MOVLconst [d]))
  1629  	// cond:
  1630  	// result: (MOVLconst [int64(int32(c+d))])
  1631  	for {
  1632  		c := v.AuxInt
  1633  		v_0 := v.Args[0]
  1634  		if v_0.Op != Op386MOVLconst {
  1635  			break
  1636  		}
  1637  		d := v_0.AuxInt
  1638  		v.reset(Op386MOVLconst)
  1639  		v.AuxInt = int64(int32(c + d))
  1640  		return true
  1641  	}
  1642  	// match: (ADDLconst [c] (ADDLconst [d] x))
  1643  	// cond:
  1644  	// result: (ADDLconst [int64(int32(c+d))] x)
  1645  	for {
  1646  		c := v.AuxInt
  1647  		v_0 := v.Args[0]
  1648  		if v_0.Op != Op386ADDLconst {
  1649  			break
  1650  		}
  1651  		d := v_0.AuxInt
  1652  		x := v_0.Args[0]
  1653  		v.reset(Op386ADDLconst)
  1654  		v.AuxInt = int64(int32(c + d))
  1655  		v.AddArg(x)
  1656  		return true
  1657  	}
  1658  	return false
  1659  }
  1660  func rewriteValue386_Op386ADDLconstmodify_0(v *Value) bool {
  1661  	b := v.Block
  1662  	_ = b
  1663  	config := b.Func.Config
  1664  	_ = config
  1665  	// match: (ADDLconstmodify [valoff1] {sym} (ADDLconst [off2] base) mem)
  1666  	// cond: ValAndOff(valoff1).canAdd(off2)
  1667  	// result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  1668  	for {
  1669  		valoff1 := v.AuxInt
  1670  		sym := v.Aux
  1671  		_ = v.Args[1]
  1672  		v_0 := v.Args[0]
  1673  		if v_0.Op != Op386ADDLconst {
  1674  			break
  1675  		}
  1676  		off2 := v_0.AuxInt
  1677  		base := v_0.Args[0]
  1678  		mem := v.Args[1]
  1679  		if !(ValAndOff(valoff1).canAdd(off2)) {
  1680  			break
  1681  		}
  1682  		v.reset(Op386ADDLconstmodify)
  1683  		v.AuxInt = ValAndOff(valoff1).add(off2)
  1684  		v.Aux = sym
  1685  		v.AddArg(base)
  1686  		v.AddArg(mem)
  1687  		return true
  1688  	}
  1689  	// match: (ADDLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem)
  1690  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  1691  	// result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  1692  	for {
  1693  		valoff1 := v.AuxInt
  1694  		sym1 := v.Aux
  1695  		_ = v.Args[1]
  1696  		v_0 := v.Args[0]
  1697  		if v_0.Op != Op386LEAL {
  1698  			break
  1699  		}
  1700  		off2 := v_0.AuxInt
  1701  		sym2 := v_0.Aux
  1702  		base := v_0.Args[0]
  1703  		mem := v.Args[1]
  1704  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  1705  			break
  1706  		}
  1707  		v.reset(Op386ADDLconstmodify)
  1708  		v.AuxInt = ValAndOff(valoff1).add(off2)
  1709  		v.Aux = mergeSym(sym1, sym2)
  1710  		v.AddArg(base)
  1711  		v.AddArg(mem)
  1712  		return true
  1713  	}
  1714  	return false
  1715  }
  1716  func rewriteValue386_Op386ADDLconstmodifyidx4_0(v *Value) bool {
  1717  	b := v.Block
  1718  	_ = b
  1719  	config := b.Func.Config
  1720  	_ = config
  1721  	// match: (ADDLconstmodifyidx4 [valoff1] {sym} (ADDLconst [off2] base) idx mem)
  1722  	// cond: ValAndOff(valoff1).canAdd(off2)
  1723  	// result: (ADDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {sym} base idx mem)
  1724  	for {
  1725  		valoff1 := v.AuxInt
  1726  		sym := v.Aux
  1727  		_ = v.Args[2]
  1728  		v_0 := v.Args[0]
  1729  		if v_0.Op != Op386ADDLconst {
  1730  			break
  1731  		}
  1732  		off2 := v_0.AuxInt
  1733  		base := v_0.Args[0]
  1734  		idx := v.Args[1]
  1735  		mem := v.Args[2]
  1736  		if !(ValAndOff(valoff1).canAdd(off2)) {
  1737  			break
  1738  		}
  1739  		v.reset(Op386ADDLconstmodifyidx4)
  1740  		v.AuxInt = ValAndOff(valoff1).add(off2)
  1741  		v.Aux = sym
  1742  		v.AddArg(base)
  1743  		v.AddArg(idx)
  1744  		v.AddArg(mem)
  1745  		return true
  1746  	}
  1747  	// match: (ADDLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem)
  1748  	// cond: ValAndOff(valoff1).canAdd(off2*4)
  1749  	// result: (ADDLconstmodifyidx4 [ValAndOff(valoff1).add(off2*4)] {sym} base idx mem)
  1750  	for {
  1751  		valoff1 := v.AuxInt
  1752  		sym := v.Aux
  1753  		_ = v.Args[2]
  1754  		base := v.Args[0]
  1755  		v_1 := v.Args[1]
  1756  		if v_1.Op != Op386ADDLconst {
  1757  			break
  1758  		}
  1759  		off2 := v_1.AuxInt
  1760  		idx := v_1.Args[0]
  1761  		mem := v.Args[2]
  1762  		if !(ValAndOff(valoff1).canAdd(off2 * 4)) {
  1763  			break
  1764  		}
  1765  		v.reset(Op386ADDLconstmodifyidx4)
  1766  		v.AuxInt = ValAndOff(valoff1).add(off2 * 4)
  1767  		v.Aux = sym
  1768  		v.AddArg(base)
  1769  		v.AddArg(idx)
  1770  		v.AddArg(mem)
  1771  		return true
  1772  	}
  1773  	// match: (ADDLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem)
  1774  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  1775  	// result: (ADDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base idx mem)
  1776  	for {
  1777  		valoff1 := v.AuxInt
  1778  		sym1 := v.Aux
  1779  		_ = v.Args[2]
  1780  		v_0 := v.Args[0]
  1781  		if v_0.Op != Op386LEAL {
  1782  			break
  1783  		}
  1784  		off2 := v_0.AuxInt
  1785  		sym2 := v_0.Aux
  1786  		base := v_0.Args[0]
  1787  		idx := v.Args[1]
  1788  		mem := v.Args[2]
  1789  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  1790  			break
  1791  		}
  1792  		v.reset(Op386ADDLconstmodifyidx4)
  1793  		v.AuxInt = ValAndOff(valoff1).add(off2)
  1794  		v.Aux = mergeSym(sym1, sym2)
  1795  		v.AddArg(base)
  1796  		v.AddArg(idx)
  1797  		v.AddArg(mem)
  1798  		return true
  1799  	}
  1800  	return false
  1801  }
  1802  func rewriteValue386_Op386ADDLload_0(v *Value) bool {
  1803  	b := v.Block
  1804  	_ = b
  1805  	config := b.Func.Config
  1806  	_ = config
  1807  	// match: (ADDLload [off1] {sym} val (ADDLconst [off2] base) mem)
  1808  	// cond: is32Bit(off1+off2)
  1809  	// result: (ADDLload [off1+off2] {sym} val base mem)
  1810  	for {
  1811  		off1 := v.AuxInt
  1812  		sym := v.Aux
  1813  		_ = v.Args[2]
  1814  		val := v.Args[0]
  1815  		v_1 := v.Args[1]
  1816  		if v_1.Op != Op386ADDLconst {
  1817  			break
  1818  		}
  1819  		off2 := v_1.AuxInt
  1820  		base := v_1.Args[0]
  1821  		mem := v.Args[2]
  1822  		if !(is32Bit(off1 + off2)) {
  1823  			break
  1824  		}
  1825  		v.reset(Op386ADDLload)
  1826  		v.AuxInt = off1 + off2
  1827  		v.Aux = sym
  1828  		v.AddArg(val)
  1829  		v.AddArg(base)
  1830  		v.AddArg(mem)
  1831  		return true
  1832  	}
  1833  	// match: (ADDLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
  1834  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  1835  	// result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  1836  	for {
  1837  		off1 := v.AuxInt
  1838  		sym1 := v.Aux
  1839  		_ = v.Args[2]
  1840  		val := v.Args[0]
  1841  		v_1 := v.Args[1]
  1842  		if v_1.Op != Op386LEAL {
  1843  			break
  1844  		}
  1845  		off2 := v_1.AuxInt
  1846  		sym2 := v_1.Aux
  1847  		base := v_1.Args[0]
  1848  		mem := v.Args[2]
  1849  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  1850  			break
  1851  		}
  1852  		v.reset(Op386ADDLload)
  1853  		v.AuxInt = off1 + off2
  1854  		v.Aux = mergeSym(sym1, sym2)
  1855  		v.AddArg(val)
  1856  		v.AddArg(base)
  1857  		v.AddArg(mem)
  1858  		return true
  1859  	}
  1860  	// match: (ADDLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem)
  1861  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  1862  	// result: (ADDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem)
  1863  	for {
  1864  		off1 := v.AuxInt
  1865  		sym1 := v.Aux
  1866  		_ = v.Args[2]
  1867  		val := v.Args[0]
  1868  		v_1 := v.Args[1]
  1869  		if v_1.Op != Op386LEAL4 {
  1870  			break
  1871  		}
  1872  		off2 := v_1.AuxInt
  1873  		sym2 := v_1.Aux
  1874  		_ = v_1.Args[1]
  1875  		ptr := v_1.Args[0]
  1876  		idx := v_1.Args[1]
  1877  		mem := v.Args[2]
  1878  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  1879  			break
  1880  		}
  1881  		v.reset(Op386ADDLloadidx4)
  1882  		v.AuxInt = off1 + off2
  1883  		v.Aux = mergeSym(sym1, sym2)
  1884  		v.AddArg(val)
  1885  		v.AddArg(ptr)
  1886  		v.AddArg(idx)
  1887  		v.AddArg(mem)
  1888  		return true
  1889  	}
  1890  	return false
  1891  }
  1892  func rewriteValue386_Op386ADDLloadidx4_0(v *Value) bool {
  1893  	b := v.Block
  1894  	_ = b
  1895  	config := b.Func.Config
  1896  	_ = config
  1897  	// match: (ADDLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem)
  1898  	// cond: is32Bit(off1+off2)
  1899  	// result: (ADDLloadidx4 [off1+off2] {sym} val base idx mem)
  1900  	for {
  1901  		off1 := v.AuxInt
  1902  		sym := v.Aux
  1903  		_ = v.Args[3]
  1904  		val := v.Args[0]
  1905  		v_1 := v.Args[1]
  1906  		if v_1.Op != Op386ADDLconst {
  1907  			break
  1908  		}
  1909  		off2 := v_1.AuxInt
  1910  		base := v_1.Args[0]
  1911  		idx := v.Args[2]
  1912  		mem := v.Args[3]
  1913  		if !(is32Bit(off1 + off2)) {
  1914  			break
  1915  		}
  1916  		v.reset(Op386ADDLloadidx4)
  1917  		v.AuxInt = off1 + off2
  1918  		v.Aux = sym
  1919  		v.AddArg(val)
  1920  		v.AddArg(base)
  1921  		v.AddArg(idx)
  1922  		v.AddArg(mem)
  1923  		return true
  1924  	}
  1925  	// match: (ADDLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem)
  1926  	// cond: is32Bit(off1+off2*4)
  1927  	// result: (ADDLloadidx4 [off1+off2*4] {sym} val base idx mem)
  1928  	for {
  1929  		off1 := v.AuxInt
  1930  		sym := v.Aux
  1931  		_ = v.Args[3]
  1932  		val := v.Args[0]
  1933  		base := v.Args[1]
  1934  		v_2 := v.Args[2]
  1935  		if v_2.Op != Op386ADDLconst {
  1936  			break
  1937  		}
  1938  		off2 := v_2.AuxInt
  1939  		idx := v_2.Args[0]
  1940  		mem := v.Args[3]
  1941  		if !(is32Bit(off1 + off2*4)) {
  1942  			break
  1943  		}
  1944  		v.reset(Op386ADDLloadidx4)
  1945  		v.AuxInt = off1 + off2*4
  1946  		v.Aux = sym
  1947  		v.AddArg(val)
  1948  		v.AddArg(base)
  1949  		v.AddArg(idx)
  1950  		v.AddArg(mem)
  1951  		return true
  1952  	}
  1953  	// match: (ADDLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem)
  1954  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  1955  	// result: (ADDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem)
  1956  	for {
  1957  		off1 := v.AuxInt
  1958  		sym1 := v.Aux
  1959  		_ = v.Args[3]
  1960  		val := v.Args[0]
  1961  		v_1 := v.Args[1]
  1962  		if v_1.Op != Op386LEAL {
  1963  			break
  1964  		}
  1965  		off2 := v_1.AuxInt
  1966  		sym2 := v_1.Aux
  1967  		base := v_1.Args[0]
  1968  		idx := v.Args[2]
  1969  		mem := v.Args[3]
  1970  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  1971  			break
  1972  		}
  1973  		v.reset(Op386ADDLloadidx4)
  1974  		v.AuxInt = off1 + off2
  1975  		v.Aux = mergeSym(sym1, sym2)
  1976  		v.AddArg(val)
  1977  		v.AddArg(base)
  1978  		v.AddArg(idx)
  1979  		v.AddArg(mem)
  1980  		return true
  1981  	}
  1982  	return false
  1983  }
  1984  func rewriteValue386_Op386ADDLmodify_0(v *Value) bool {
  1985  	b := v.Block
  1986  	_ = b
  1987  	config := b.Func.Config
  1988  	_ = config
  1989  	// match: (ADDLmodify [off1] {sym} (ADDLconst [off2] base) val mem)
  1990  	// cond: is32Bit(off1+off2)
  1991  	// result: (ADDLmodify [off1+off2] {sym} base val mem)
  1992  	for {
  1993  		off1 := v.AuxInt
  1994  		sym := v.Aux
  1995  		_ = v.Args[2]
  1996  		v_0 := v.Args[0]
  1997  		if v_0.Op != Op386ADDLconst {
  1998  			break
  1999  		}
  2000  		off2 := v_0.AuxInt
  2001  		base := v_0.Args[0]
  2002  		val := v.Args[1]
  2003  		mem := v.Args[2]
  2004  		if !(is32Bit(off1 + off2)) {
  2005  			break
  2006  		}
  2007  		v.reset(Op386ADDLmodify)
  2008  		v.AuxInt = off1 + off2
  2009  		v.Aux = sym
  2010  		v.AddArg(base)
  2011  		v.AddArg(val)
  2012  		v.AddArg(mem)
  2013  		return true
  2014  	}
  2015  	// match: (ADDLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
  2016  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2017  	// result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  2018  	for {
  2019  		off1 := v.AuxInt
  2020  		sym1 := v.Aux
  2021  		_ = v.Args[2]
  2022  		v_0 := v.Args[0]
  2023  		if v_0.Op != Op386LEAL {
  2024  			break
  2025  		}
  2026  		off2 := v_0.AuxInt
  2027  		sym2 := v_0.Aux
  2028  		base := v_0.Args[0]
  2029  		val := v.Args[1]
  2030  		mem := v.Args[2]
  2031  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2032  			break
  2033  		}
  2034  		v.reset(Op386ADDLmodify)
  2035  		v.AuxInt = off1 + off2
  2036  		v.Aux = mergeSym(sym1, sym2)
  2037  		v.AddArg(base)
  2038  		v.AddArg(val)
  2039  		v.AddArg(mem)
  2040  		return true
  2041  	}
  2042  	return false
  2043  }
  2044  func rewriteValue386_Op386ADDLmodifyidx4_0(v *Value) bool {
  2045  	b := v.Block
  2046  	_ = b
  2047  	config := b.Func.Config
  2048  	_ = config
  2049  	// match: (ADDLmodifyidx4 [off1] {sym} (ADDLconst [off2] base) idx val mem)
  2050  	// cond: is32Bit(off1+off2)
  2051  	// result: (ADDLmodifyidx4 [off1+off2] {sym} base idx val mem)
  2052  	for {
  2053  		off1 := v.AuxInt
  2054  		sym := v.Aux
  2055  		_ = v.Args[3]
  2056  		v_0 := v.Args[0]
  2057  		if v_0.Op != Op386ADDLconst {
  2058  			break
  2059  		}
  2060  		off2 := v_0.AuxInt
  2061  		base := v_0.Args[0]
  2062  		idx := v.Args[1]
  2063  		val := v.Args[2]
  2064  		mem := v.Args[3]
  2065  		if !(is32Bit(off1 + off2)) {
  2066  			break
  2067  		}
  2068  		v.reset(Op386ADDLmodifyidx4)
  2069  		v.AuxInt = off1 + off2
  2070  		v.Aux = sym
  2071  		v.AddArg(base)
  2072  		v.AddArg(idx)
  2073  		v.AddArg(val)
  2074  		v.AddArg(mem)
  2075  		return true
  2076  	}
  2077  	// match: (ADDLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem)
  2078  	// cond: is32Bit(off1+off2*4)
  2079  	// result: (ADDLmodifyidx4 [off1+off2*4] {sym} base idx val mem)
  2080  	for {
  2081  		off1 := v.AuxInt
  2082  		sym := v.Aux
  2083  		_ = v.Args[3]
  2084  		base := v.Args[0]
  2085  		v_1 := v.Args[1]
  2086  		if v_1.Op != Op386ADDLconst {
  2087  			break
  2088  		}
  2089  		off2 := v_1.AuxInt
  2090  		idx := v_1.Args[0]
  2091  		val := v.Args[2]
  2092  		mem := v.Args[3]
  2093  		if !(is32Bit(off1 + off2*4)) {
  2094  			break
  2095  		}
  2096  		v.reset(Op386ADDLmodifyidx4)
  2097  		v.AuxInt = off1 + off2*4
  2098  		v.Aux = sym
  2099  		v.AddArg(base)
  2100  		v.AddArg(idx)
  2101  		v.AddArg(val)
  2102  		v.AddArg(mem)
  2103  		return true
  2104  	}
  2105  	// match: (ADDLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem)
  2106  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2107  	// result: (ADDLmodifyidx4 [off1+off2] {mergeSym(sym1,sym2)} base idx val mem)
  2108  	for {
  2109  		off1 := v.AuxInt
  2110  		sym1 := v.Aux
  2111  		_ = v.Args[3]
  2112  		v_0 := v.Args[0]
  2113  		if v_0.Op != Op386LEAL {
  2114  			break
  2115  		}
  2116  		off2 := v_0.AuxInt
  2117  		sym2 := v_0.Aux
  2118  		base := v_0.Args[0]
  2119  		idx := v.Args[1]
  2120  		val := v.Args[2]
  2121  		mem := v.Args[3]
  2122  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2123  			break
  2124  		}
  2125  		v.reset(Op386ADDLmodifyidx4)
  2126  		v.AuxInt = off1 + off2
  2127  		v.Aux = mergeSym(sym1, sym2)
  2128  		v.AddArg(base)
  2129  		v.AddArg(idx)
  2130  		v.AddArg(val)
  2131  		v.AddArg(mem)
  2132  		return true
  2133  	}
  2134  	// match: (ADDLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem)
  2135  	// cond: validValAndOff(c,off)
  2136  	// result: (ADDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem)
  2137  	for {
  2138  		off := v.AuxInt
  2139  		sym := v.Aux
  2140  		_ = v.Args[3]
  2141  		ptr := v.Args[0]
  2142  		idx := v.Args[1]
  2143  		v_2 := v.Args[2]
  2144  		if v_2.Op != Op386MOVLconst {
  2145  			break
  2146  		}
  2147  		c := v_2.AuxInt
  2148  		mem := v.Args[3]
  2149  		if !(validValAndOff(c, off)) {
  2150  			break
  2151  		}
  2152  		v.reset(Op386ADDLconstmodifyidx4)
  2153  		v.AuxInt = makeValAndOff(c, off)
  2154  		v.Aux = sym
  2155  		v.AddArg(ptr)
  2156  		v.AddArg(idx)
  2157  		v.AddArg(mem)
  2158  		return true
  2159  	}
  2160  	return false
  2161  }
  2162  func rewriteValue386_Op386ADDSD_0(v *Value) bool {
  2163  	b := v.Block
  2164  	_ = b
  2165  	config := b.Func.Config
  2166  	_ = config
  2167  	// match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem))
  2168  	// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
  2169  	// result: (ADDSDload x [off] {sym} ptr mem)
  2170  	for {
  2171  		_ = v.Args[1]
  2172  		x := v.Args[0]
  2173  		l := v.Args[1]
  2174  		if l.Op != Op386MOVSDload {
  2175  			break
  2176  		}
  2177  		off := l.AuxInt
  2178  		sym := l.Aux
  2179  		_ = l.Args[1]
  2180  		ptr := l.Args[0]
  2181  		mem := l.Args[1]
  2182  		if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
  2183  			break
  2184  		}
  2185  		v.reset(Op386ADDSDload)
  2186  		v.AuxInt = off
  2187  		v.Aux = sym
  2188  		v.AddArg(x)
  2189  		v.AddArg(ptr)
  2190  		v.AddArg(mem)
  2191  		return true
  2192  	}
  2193  	// match: (ADDSD l:(MOVSDload [off] {sym} ptr mem) x)
  2194  	// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
  2195  	// result: (ADDSDload x [off] {sym} ptr mem)
  2196  	for {
  2197  		_ = v.Args[1]
  2198  		l := v.Args[0]
  2199  		if l.Op != Op386MOVSDload {
  2200  			break
  2201  		}
  2202  		off := l.AuxInt
  2203  		sym := l.Aux
  2204  		_ = l.Args[1]
  2205  		ptr := l.Args[0]
  2206  		mem := l.Args[1]
  2207  		x := v.Args[1]
  2208  		if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
  2209  			break
  2210  		}
  2211  		v.reset(Op386ADDSDload)
  2212  		v.AuxInt = off
  2213  		v.Aux = sym
  2214  		v.AddArg(x)
  2215  		v.AddArg(ptr)
  2216  		v.AddArg(mem)
  2217  		return true
  2218  	}
  2219  	return false
  2220  }
  2221  func rewriteValue386_Op386ADDSDload_0(v *Value) bool {
  2222  	b := v.Block
  2223  	_ = b
  2224  	config := b.Func.Config
  2225  	_ = config
  2226  	// match: (ADDSDload [off1] {sym} val (ADDLconst [off2] base) mem)
  2227  	// cond: is32Bit(off1+off2)
  2228  	// result: (ADDSDload [off1+off2] {sym} val base mem)
  2229  	for {
  2230  		off1 := v.AuxInt
  2231  		sym := v.Aux
  2232  		_ = v.Args[2]
  2233  		val := v.Args[0]
  2234  		v_1 := v.Args[1]
  2235  		if v_1.Op != Op386ADDLconst {
  2236  			break
  2237  		}
  2238  		off2 := v_1.AuxInt
  2239  		base := v_1.Args[0]
  2240  		mem := v.Args[2]
  2241  		if !(is32Bit(off1 + off2)) {
  2242  			break
  2243  		}
  2244  		v.reset(Op386ADDSDload)
  2245  		v.AuxInt = off1 + off2
  2246  		v.Aux = sym
  2247  		v.AddArg(val)
  2248  		v.AddArg(base)
  2249  		v.AddArg(mem)
  2250  		return true
  2251  	}
  2252  	// match: (ADDSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
  2253  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2254  	// result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  2255  	for {
  2256  		off1 := v.AuxInt
  2257  		sym1 := v.Aux
  2258  		_ = v.Args[2]
  2259  		val := v.Args[0]
  2260  		v_1 := v.Args[1]
  2261  		if v_1.Op != Op386LEAL {
  2262  			break
  2263  		}
  2264  		off2 := v_1.AuxInt
  2265  		sym2 := v_1.Aux
  2266  		base := v_1.Args[0]
  2267  		mem := v.Args[2]
  2268  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2269  			break
  2270  		}
  2271  		v.reset(Op386ADDSDload)
  2272  		v.AuxInt = off1 + off2
  2273  		v.Aux = mergeSym(sym1, sym2)
  2274  		v.AddArg(val)
  2275  		v.AddArg(base)
  2276  		v.AddArg(mem)
  2277  		return true
  2278  	}
  2279  	return false
  2280  }
  2281  func rewriteValue386_Op386ADDSS_0(v *Value) bool {
  2282  	b := v.Block
  2283  	_ = b
  2284  	config := b.Func.Config
  2285  	_ = config
  2286  	// match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem))
  2287  	// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
  2288  	// result: (ADDSSload x [off] {sym} ptr mem)
  2289  	for {
  2290  		_ = v.Args[1]
  2291  		x := v.Args[0]
  2292  		l := v.Args[1]
  2293  		if l.Op != Op386MOVSSload {
  2294  			break
  2295  		}
  2296  		off := l.AuxInt
  2297  		sym := l.Aux
  2298  		_ = l.Args[1]
  2299  		ptr := l.Args[0]
  2300  		mem := l.Args[1]
  2301  		if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
  2302  			break
  2303  		}
  2304  		v.reset(Op386ADDSSload)
  2305  		v.AuxInt = off
  2306  		v.Aux = sym
  2307  		v.AddArg(x)
  2308  		v.AddArg(ptr)
  2309  		v.AddArg(mem)
  2310  		return true
  2311  	}
  2312  	// match: (ADDSS l:(MOVSSload [off] {sym} ptr mem) x)
  2313  	// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
  2314  	// result: (ADDSSload x [off] {sym} ptr mem)
  2315  	for {
  2316  		_ = v.Args[1]
  2317  		l := v.Args[0]
  2318  		if l.Op != Op386MOVSSload {
  2319  			break
  2320  		}
  2321  		off := l.AuxInt
  2322  		sym := l.Aux
  2323  		_ = l.Args[1]
  2324  		ptr := l.Args[0]
  2325  		mem := l.Args[1]
  2326  		x := v.Args[1]
  2327  		if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
  2328  			break
  2329  		}
  2330  		v.reset(Op386ADDSSload)
  2331  		v.AuxInt = off
  2332  		v.Aux = sym
  2333  		v.AddArg(x)
  2334  		v.AddArg(ptr)
  2335  		v.AddArg(mem)
  2336  		return true
  2337  	}
  2338  	return false
  2339  }
  2340  func rewriteValue386_Op386ADDSSload_0(v *Value) bool {
  2341  	b := v.Block
  2342  	_ = b
  2343  	config := b.Func.Config
  2344  	_ = config
  2345  	// match: (ADDSSload [off1] {sym} val (ADDLconst [off2] base) mem)
  2346  	// cond: is32Bit(off1+off2)
  2347  	// result: (ADDSSload [off1+off2] {sym} val base mem)
  2348  	for {
  2349  		off1 := v.AuxInt
  2350  		sym := v.Aux
  2351  		_ = v.Args[2]
  2352  		val := v.Args[0]
  2353  		v_1 := v.Args[1]
  2354  		if v_1.Op != Op386ADDLconst {
  2355  			break
  2356  		}
  2357  		off2 := v_1.AuxInt
  2358  		base := v_1.Args[0]
  2359  		mem := v.Args[2]
  2360  		if !(is32Bit(off1 + off2)) {
  2361  			break
  2362  		}
  2363  		v.reset(Op386ADDSSload)
  2364  		v.AuxInt = off1 + off2
  2365  		v.Aux = sym
  2366  		v.AddArg(val)
  2367  		v.AddArg(base)
  2368  		v.AddArg(mem)
  2369  		return true
  2370  	}
  2371  	// match: (ADDSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
  2372  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2373  	// result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  2374  	for {
  2375  		off1 := v.AuxInt
  2376  		sym1 := v.Aux
  2377  		_ = v.Args[2]
  2378  		val := v.Args[0]
  2379  		v_1 := v.Args[1]
  2380  		if v_1.Op != Op386LEAL {
  2381  			break
  2382  		}
  2383  		off2 := v_1.AuxInt
  2384  		sym2 := v_1.Aux
  2385  		base := v_1.Args[0]
  2386  		mem := v.Args[2]
  2387  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2388  			break
  2389  		}
  2390  		v.reset(Op386ADDSSload)
  2391  		v.AuxInt = off1 + off2
  2392  		v.Aux = mergeSym(sym1, sym2)
  2393  		v.AddArg(val)
  2394  		v.AddArg(base)
  2395  		v.AddArg(mem)
  2396  		return true
  2397  	}
  2398  	return false
  2399  }
  2400  func rewriteValue386_Op386ANDL_0(v *Value) bool {
  2401  	// match: (ANDL x (MOVLconst [c]))
  2402  	// cond:
  2403  	// result: (ANDLconst [c] x)
  2404  	for {
  2405  		_ = v.Args[1]
  2406  		x := v.Args[0]
  2407  		v_1 := v.Args[1]
  2408  		if v_1.Op != Op386MOVLconst {
  2409  			break
  2410  		}
  2411  		c := v_1.AuxInt
  2412  		v.reset(Op386ANDLconst)
  2413  		v.AuxInt = c
  2414  		v.AddArg(x)
  2415  		return true
  2416  	}
  2417  	// match: (ANDL (MOVLconst [c]) x)
  2418  	// cond:
  2419  	// result: (ANDLconst [c] x)
  2420  	for {
  2421  		_ = v.Args[1]
  2422  		v_0 := v.Args[0]
  2423  		if v_0.Op != Op386MOVLconst {
  2424  			break
  2425  		}
  2426  		c := v_0.AuxInt
  2427  		x := v.Args[1]
  2428  		v.reset(Op386ANDLconst)
  2429  		v.AuxInt = c
  2430  		v.AddArg(x)
  2431  		return true
  2432  	}
  2433  	// match: (ANDL x l:(MOVLload [off] {sym} ptr mem))
  2434  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  2435  	// result: (ANDLload x [off] {sym} ptr mem)
  2436  	for {
  2437  		_ = v.Args[1]
  2438  		x := v.Args[0]
  2439  		l := v.Args[1]
  2440  		if l.Op != Op386MOVLload {
  2441  			break
  2442  		}
  2443  		off := l.AuxInt
  2444  		sym := l.Aux
  2445  		_ = l.Args[1]
  2446  		ptr := l.Args[0]
  2447  		mem := l.Args[1]
  2448  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  2449  			break
  2450  		}
  2451  		v.reset(Op386ANDLload)
  2452  		v.AuxInt = off
  2453  		v.Aux = sym
  2454  		v.AddArg(x)
  2455  		v.AddArg(ptr)
  2456  		v.AddArg(mem)
  2457  		return true
  2458  	}
  2459  	// match: (ANDL l:(MOVLload [off] {sym} ptr mem) x)
  2460  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  2461  	// result: (ANDLload x [off] {sym} ptr mem)
  2462  	for {
  2463  		_ = v.Args[1]
  2464  		l := v.Args[0]
  2465  		if l.Op != Op386MOVLload {
  2466  			break
  2467  		}
  2468  		off := l.AuxInt
  2469  		sym := l.Aux
  2470  		_ = l.Args[1]
  2471  		ptr := l.Args[0]
  2472  		mem := l.Args[1]
  2473  		x := v.Args[1]
  2474  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  2475  			break
  2476  		}
  2477  		v.reset(Op386ANDLload)
  2478  		v.AuxInt = off
  2479  		v.Aux = sym
  2480  		v.AddArg(x)
  2481  		v.AddArg(ptr)
  2482  		v.AddArg(mem)
  2483  		return true
  2484  	}
  2485  	// match: (ANDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem))
  2486  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  2487  	// result: (ANDLloadidx4 x [off] {sym} ptr idx mem)
  2488  	for {
  2489  		_ = v.Args[1]
  2490  		x := v.Args[0]
  2491  		l := v.Args[1]
  2492  		if l.Op != Op386MOVLloadidx4 {
  2493  			break
  2494  		}
  2495  		off := l.AuxInt
  2496  		sym := l.Aux
  2497  		_ = l.Args[2]
  2498  		ptr := l.Args[0]
  2499  		idx := l.Args[1]
  2500  		mem := l.Args[2]
  2501  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  2502  			break
  2503  		}
  2504  		v.reset(Op386ANDLloadidx4)
  2505  		v.AuxInt = off
  2506  		v.Aux = sym
  2507  		v.AddArg(x)
  2508  		v.AddArg(ptr)
  2509  		v.AddArg(idx)
  2510  		v.AddArg(mem)
  2511  		return true
  2512  	}
  2513  	// match: (ANDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x)
  2514  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
  2515  	// result: (ANDLloadidx4 x [off] {sym} ptr idx mem)
  2516  	for {
  2517  		_ = v.Args[1]
  2518  		l := v.Args[0]
  2519  		if l.Op != Op386MOVLloadidx4 {
  2520  			break
  2521  		}
  2522  		off := l.AuxInt
  2523  		sym := l.Aux
  2524  		_ = l.Args[2]
  2525  		ptr := l.Args[0]
  2526  		idx := l.Args[1]
  2527  		mem := l.Args[2]
  2528  		x := v.Args[1]
  2529  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
  2530  			break
  2531  		}
  2532  		v.reset(Op386ANDLloadidx4)
  2533  		v.AuxInt = off
  2534  		v.Aux = sym
  2535  		v.AddArg(x)
  2536  		v.AddArg(ptr)
  2537  		v.AddArg(idx)
  2538  		v.AddArg(mem)
  2539  		return true
  2540  	}
  2541  	// match: (ANDL x x)
  2542  	// cond:
  2543  	// result: x
  2544  	for {
  2545  		_ = v.Args[1]
  2546  		x := v.Args[0]
  2547  		if x != v.Args[1] {
  2548  			break
  2549  		}
  2550  		v.reset(OpCopy)
  2551  		v.Type = x.Type
  2552  		v.AddArg(x)
  2553  		return true
  2554  	}
  2555  	return false
  2556  }
  2557  func rewriteValue386_Op386ANDLconst_0(v *Value) bool {
  2558  	// match: (ANDLconst [c] (ANDLconst [d] x))
  2559  	// cond:
  2560  	// result: (ANDLconst [c & d] x)
  2561  	for {
  2562  		c := v.AuxInt
  2563  		v_0 := v.Args[0]
  2564  		if v_0.Op != Op386ANDLconst {
  2565  			break
  2566  		}
  2567  		d := v_0.AuxInt
  2568  		x := v_0.Args[0]
  2569  		v.reset(Op386ANDLconst)
  2570  		v.AuxInt = c & d
  2571  		v.AddArg(x)
  2572  		return true
  2573  	}
  2574  	// match: (ANDLconst [c] _)
  2575  	// cond: int32(c)==0
  2576  	// result: (MOVLconst [0])
  2577  	for {
  2578  		c := v.AuxInt
  2579  		if !(int32(c) == 0) {
  2580  			break
  2581  		}
  2582  		v.reset(Op386MOVLconst)
  2583  		v.AuxInt = 0
  2584  		return true
  2585  	}
  2586  	// match: (ANDLconst [c] x)
  2587  	// cond: int32(c)==-1
  2588  	// result: x
  2589  	for {
  2590  		c := v.AuxInt
  2591  		x := v.Args[0]
  2592  		if !(int32(c) == -1) {
  2593  			break
  2594  		}
  2595  		v.reset(OpCopy)
  2596  		v.Type = x.Type
  2597  		v.AddArg(x)
  2598  		return true
  2599  	}
  2600  	// match: (ANDLconst [c] (MOVLconst [d]))
  2601  	// cond:
  2602  	// result: (MOVLconst [c&d])
  2603  	for {
  2604  		c := v.AuxInt
  2605  		v_0 := v.Args[0]
  2606  		if v_0.Op != Op386MOVLconst {
  2607  			break
  2608  		}
  2609  		d := v_0.AuxInt
  2610  		v.reset(Op386MOVLconst)
  2611  		v.AuxInt = c & d
  2612  		return true
  2613  	}
  2614  	return false
  2615  }
  2616  func rewriteValue386_Op386ANDLconstmodify_0(v *Value) bool {
  2617  	b := v.Block
  2618  	_ = b
  2619  	config := b.Func.Config
  2620  	_ = config
  2621  	// match: (ANDLconstmodify [valoff1] {sym} (ADDLconst [off2] base) mem)
  2622  	// cond: ValAndOff(valoff1).canAdd(off2)
  2623  	// result: (ANDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
  2624  	for {
  2625  		valoff1 := v.AuxInt
  2626  		sym := v.Aux
  2627  		_ = v.Args[1]
  2628  		v_0 := v.Args[0]
  2629  		if v_0.Op != Op386ADDLconst {
  2630  			break
  2631  		}
  2632  		off2 := v_0.AuxInt
  2633  		base := v_0.Args[0]
  2634  		mem := v.Args[1]
  2635  		if !(ValAndOff(valoff1).canAdd(off2)) {
  2636  			break
  2637  		}
  2638  		v.reset(Op386ANDLconstmodify)
  2639  		v.AuxInt = ValAndOff(valoff1).add(off2)
  2640  		v.Aux = sym
  2641  		v.AddArg(base)
  2642  		v.AddArg(mem)
  2643  		return true
  2644  	}
  2645  	// match: (ANDLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem)
  2646  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2647  	// result: (ANDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
  2648  	for {
  2649  		valoff1 := v.AuxInt
  2650  		sym1 := v.Aux
  2651  		_ = v.Args[1]
  2652  		v_0 := v.Args[0]
  2653  		if v_0.Op != Op386LEAL {
  2654  			break
  2655  		}
  2656  		off2 := v_0.AuxInt
  2657  		sym2 := v_0.Aux
  2658  		base := v_0.Args[0]
  2659  		mem := v.Args[1]
  2660  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2661  			break
  2662  		}
  2663  		v.reset(Op386ANDLconstmodify)
  2664  		v.AuxInt = ValAndOff(valoff1).add(off2)
  2665  		v.Aux = mergeSym(sym1, sym2)
  2666  		v.AddArg(base)
  2667  		v.AddArg(mem)
  2668  		return true
  2669  	}
  2670  	return false
  2671  }
  2672  func rewriteValue386_Op386ANDLconstmodifyidx4_0(v *Value) bool {
  2673  	b := v.Block
  2674  	_ = b
  2675  	config := b.Func.Config
  2676  	_ = config
  2677  	// match: (ANDLconstmodifyidx4 [valoff1] {sym} (ADDLconst [off2] base) idx mem)
  2678  	// cond: ValAndOff(valoff1).canAdd(off2)
  2679  	// result: (ANDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {sym} base idx mem)
  2680  	for {
  2681  		valoff1 := v.AuxInt
  2682  		sym := v.Aux
  2683  		_ = v.Args[2]
  2684  		v_0 := v.Args[0]
  2685  		if v_0.Op != Op386ADDLconst {
  2686  			break
  2687  		}
  2688  		off2 := v_0.AuxInt
  2689  		base := v_0.Args[0]
  2690  		idx := v.Args[1]
  2691  		mem := v.Args[2]
  2692  		if !(ValAndOff(valoff1).canAdd(off2)) {
  2693  			break
  2694  		}
  2695  		v.reset(Op386ANDLconstmodifyidx4)
  2696  		v.AuxInt = ValAndOff(valoff1).add(off2)
  2697  		v.Aux = sym
  2698  		v.AddArg(base)
  2699  		v.AddArg(idx)
  2700  		v.AddArg(mem)
  2701  		return true
  2702  	}
  2703  	// match: (ANDLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem)
  2704  	// cond: ValAndOff(valoff1).canAdd(off2*4)
  2705  	// result: (ANDLconstmodifyidx4 [ValAndOff(valoff1).add(off2*4)] {sym} base idx mem)
  2706  	for {
  2707  		valoff1 := v.AuxInt
  2708  		sym := v.Aux
  2709  		_ = v.Args[2]
  2710  		base := v.Args[0]
  2711  		v_1 := v.Args[1]
  2712  		if v_1.Op != Op386ADDLconst {
  2713  			break
  2714  		}
  2715  		off2 := v_1.AuxInt
  2716  		idx := v_1.Args[0]
  2717  		mem := v.Args[2]
  2718  		if !(ValAndOff(valoff1).canAdd(off2 * 4)) {
  2719  			break
  2720  		}
  2721  		v.reset(Op386ANDLconstmodifyidx4)
  2722  		v.AuxInt = ValAndOff(valoff1).add(off2 * 4)
  2723  		v.Aux = sym
  2724  		v.AddArg(base)
  2725  		v.AddArg(idx)
  2726  		v.AddArg(mem)
  2727  		return true
  2728  	}
  2729  	// match: (ANDLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem)
  2730  	// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2731  	// result: (ANDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base idx mem)
  2732  	for {
  2733  		valoff1 := v.AuxInt
  2734  		sym1 := v.Aux
  2735  		_ = v.Args[2]
  2736  		v_0 := v.Args[0]
  2737  		if v_0.Op != Op386LEAL {
  2738  			break
  2739  		}
  2740  		off2 := v_0.AuxInt
  2741  		sym2 := v_0.Aux
  2742  		base := v_0.Args[0]
  2743  		idx := v.Args[1]
  2744  		mem := v.Args[2]
  2745  		if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2746  			break
  2747  		}
  2748  		v.reset(Op386ANDLconstmodifyidx4)
  2749  		v.AuxInt = ValAndOff(valoff1).add(off2)
  2750  		v.Aux = mergeSym(sym1, sym2)
  2751  		v.AddArg(base)
  2752  		v.AddArg(idx)
  2753  		v.AddArg(mem)
  2754  		return true
  2755  	}
  2756  	return false
  2757  }
  2758  func rewriteValue386_Op386ANDLload_0(v *Value) bool {
  2759  	b := v.Block
  2760  	_ = b
  2761  	config := b.Func.Config
  2762  	_ = config
  2763  	// match: (ANDLload [off1] {sym} val (ADDLconst [off2] base) mem)
  2764  	// cond: is32Bit(off1+off2)
  2765  	// result: (ANDLload [off1+off2] {sym} val base mem)
  2766  	for {
  2767  		off1 := v.AuxInt
  2768  		sym := v.Aux
  2769  		_ = v.Args[2]
  2770  		val := v.Args[0]
  2771  		v_1 := v.Args[1]
  2772  		if v_1.Op != Op386ADDLconst {
  2773  			break
  2774  		}
  2775  		off2 := v_1.AuxInt
  2776  		base := v_1.Args[0]
  2777  		mem := v.Args[2]
  2778  		if !(is32Bit(off1 + off2)) {
  2779  			break
  2780  		}
  2781  		v.reset(Op386ANDLload)
  2782  		v.AuxInt = off1 + off2
  2783  		v.Aux = sym
  2784  		v.AddArg(val)
  2785  		v.AddArg(base)
  2786  		v.AddArg(mem)
  2787  		return true
  2788  	}
  2789  	// match: (ANDLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
  2790  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2791  	// result: (ANDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  2792  	for {
  2793  		off1 := v.AuxInt
  2794  		sym1 := v.Aux
  2795  		_ = v.Args[2]
  2796  		val := v.Args[0]
  2797  		v_1 := v.Args[1]
  2798  		if v_1.Op != Op386LEAL {
  2799  			break
  2800  		}
  2801  		off2 := v_1.AuxInt
  2802  		sym2 := v_1.Aux
  2803  		base := v_1.Args[0]
  2804  		mem := v.Args[2]
  2805  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2806  			break
  2807  		}
  2808  		v.reset(Op386ANDLload)
  2809  		v.AuxInt = off1 + off2
  2810  		v.Aux = mergeSym(sym1, sym2)
  2811  		v.AddArg(val)
  2812  		v.AddArg(base)
  2813  		v.AddArg(mem)
  2814  		return true
  2815  	}
  2816  	// match: (ANDLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem)
  2817  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  2818  	// result: (ANDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem)
  2819  	for {
  2820  		off1 := v.AuxInt
  2821  		sym1 := v.Aux
  2822  		_ = v.Args[2]
  2823  		val := v.Args[0]
  2824  		v_1 := v.Args[1]
  2825  		if v_1.Op != Op386LEAL4 {
  2826  			break
  2827  		}
  2828  		off2 := v_1.AuxInt
  2829  		sym2 := v_1.Aux
  2830  		_ = v_1.Args[1]
  2831  		ptr := v_1.Args[0]
  2832  		idx := v_1.Args[1]
  2833  		mem := v.Args[2]
  2834  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  2835  			break
  2836  		}
  2837  		v.reset(Op386ANDLloadidx4)
  2838  		v.AuxInt = off1 + off2
  2839  		v.Aux = mergeSym(sym1, sym2)
  2840  		v.AddArg(val)
  2841  		v.AddArg(ptr)
  2842  		v.AddArg(idx)
  2843  		v.AddArg(mem)
  2844  		return true
  2845  	}
  2846  	return false
  2847  }
  2848  func rewriteValue386_Op386ANDLloadidx4_0(v *Value) bool {
  2849  	b := v.Block
  2850  	_ = b
  2851  	config := b.Func.Config
  2852  	_ = config
  2853  	// match: (ANDLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem)
  2854  	// cond: is32Bit(off1+off2)
  2855  	// result: (ANDLloadidx4 [off1+off2] {sym} val base idx mem)
  2856  	for {
  2857  		off1 := v.AuxInt
  2858  		sym := v.Aux
  2859  		_ = v.Args[3]
  2860  		val := v.Args[0]
  2861  		v_1 := v.Args[1]
  2862  		if v_1.Op != Op386ADDLconst {
  2863  			break
  2864  		}
  2865  		off2 := v_1.AuxInt
  2866  		base := v_1.Args[0]
  2867  		idx := v.Args[2]
  2868  		mem := v.Args[3]
  2869  		if !(is32Bit(off1 + off2)) {
  2870  			break
  2871  		}
  2872  		v.reset(Op386ANDLloadidx4)
  2873  		v.AuxInt = off1 + off2
  2874  		v.Aux = sym
  2875  		v.AddArg(val)
  2876  		v.AddArg(base)
  2877  		v.AddArg(idx)
  2878  		v.AddArg(mem)
  2879  		return true
  2880  	}
  2881  	// match: (ANDLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem)
  2882  	// cond: is32Bit(off1+off2*4)
  2883  	// result: (ANDLloadidx4 [off1+off2*4] {sym} val base idx mem)
  2884  	for {
  2885  		off1 := v.AuxInt
  2886  		sym := v.Aux
  2887  		_ = v.Args[3]
  2888  		val := v.Args[0]
  2889  		base := v.Args[1]
  2890  		v_2 := v.Args[2]
  2891  		if v_2.Op != Op386ADDLconst {
  2892  			break
  2893  		}
  2894  		off2 := v_2.AuxInt
  2895  		idx := v_2.Args[0]
  2896  		mem := v.Args[3]
  2897  		if !(is32Bit(off1 + off2*4)) {
  2898  			break
  2899  		}
  2900  		v.reset(Op386ANDLloadidx4)
  2901  		v.AuxInt = off1 + off2*4
  2902  		v.Aux = sym
  2903  		v.AddArg(val)
  2904  		v.AddArg(base)
  2905  		v.AddArg(idx)
  2906  		v.AddArg(mem)
  2907  		return true
  2908  	}
  2909  	// match: (ANDLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem)
  2910  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2911  	// result: (ANDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem)
  2912  	for {
  2913  		off1 := v.AuxInt
  2914  		sym1 := v.Aux
  2915  		_ = v.Args[3]
  2916  		val := v.Args[0]
  2917  		v_1 := v.Args[1]
  2918  		if v_1.Op != Op386LEAL {
  2919  			break
  2920  		}
  2921  		off2 := v_1.AuxInt
  2922  		sym2 := v_1.Aux
  2923  		base := v_1.Args[0]
  2924  		idx := v.Args[2]
  2925  		mem := v.Args[3]
  2926  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2927  			break
  2928  		}
  2929  		v.reset(Op386ANDLloadidx4)
  2930  		v.AuxInt = off1 + off2
  2931  		v.Aux = mergeSym(sym1, sym2)
  2932  		v.AddArg(val)
  2933  		v.AddArg(base)
  2934  		v.AddArg(idx)
  2935  		v.AddArg(mem)
  2936  		return true
  2937  	}
  2938  	return false
  2939  }
  2940  func rewriteValue386_Op386ANDLmodify_0(v *Value) bool {
  2941  	b := v.Block
  2942  	_ = b
  2943  	config := b.Func.Config
  2944  	_ = config
  2945  	// match: (ANDLmodify [off1] {sym} (ADDLconst [off2] base) val mem)
  2946  	// cond: is32Bit(off1+off2)
  2947  	// result: (ANDLmodify [off1+off2] {sym} base val mem)
  2948  	for {
  2949  		off1 := v.AuxInt
  2950  		sym := v.Aux
  2951  		_ = v.Args[2]
  2952  		v_0 := v.Args[0]
  2953  		if v_0.Op != Op386ADDLconst {
  2954  			break
  2955  		}
  2956  		off2 := v_0.AuxInt
  2957  		base := v_0.Args[0]
  2958  		val := v.Args[1]
  2959  		mem := v.Args[2]
  2960  		if !(is32Bit(off1 + off2)) {
  2961  			break
  2962  		}
  2963  		v.reset(Op386ANDLmodify)
  2964  		v.AuxInt = off1 + off2
  2965  		v.Aux = sym
  2966  		v.AddArg(base)
  2967  		v.AddArg(val)
  2968  		v.AddArg(mem)
  2969  		return true
  2970  	}
  2971  	// match: (ANDLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
  2972  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  2973  	// result: (ANDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  2974  	for {
  2975  		off1 := v.AuxInt
  2976  		sym1 := v.Aux
  2977  		_ = v.Args[2]
  2978  		v_0 := v.Args[0]
  2979  		if v_0.Op != Op386LEAL {
  2980  			break
  2981  		}
  2982  		off2 := v_0.AuxInt
  2983  		sym2 := v_0.Aux
  2984  		base := v_0.Args[0]
  2985  		val := v.Args[1]
  2986  		mem := v.Args[2]
  2987  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  2988  			break
  2989  		}
  2990  		v.reset(Op386ANDLmodify)
  2991  		v.AuxInt = off1 + off2
  2992  		v.Aux = mergeSym(sym1, sym2)
  2993  		v.AddArg(base)
  2994  		v.AddArg(val)
  2995  		v.AddArg(mem)
  2996  		return true
  2997  	}
  2998  	return false
  2999  }
  3000  func rewriteValue386_Op386ANDLmodifyidx4_0(v *Value) bool {
  3001  	b := v.Block
  3002  	_ = b
  3003  	config := b.Func.Config
  3004  	_ = config
  3005  	// match: (ANDLmodifyidx4 [off1] {sym} (ADDLconst [off2] base) idx val mem)
  3006  	// cond: is32Bit(off1+off2)
  3007  	// result: (ANDLmodifyidx4 [off1+off2] {sym} base idx val mem)
  3008  	for {
  3009  		off1 := v.AuxInt
  3010  		sym := v.Aux
  3011  		_ = v.Args[3]
  3012  		v_0 := v.Args[0]
  3013  		if v_0.Op != Op386ADDLconst {
  3014  			break
  3015  		}
  3016  		off2 := v_0.AuxInt
  3017  		base := v_0.Args[0]
  3018  		idx := v.Args[1]
  3019  		val := v.Args[2]
  3020  		mem := v.Args[3]
  3021  		if !(is32Bit(off1 + off2)) {
  3022  			break
  3023  		}
  3024  		v.reset(Op386ANDLmodifyidx4)
  3025  		v.AuxInt = off1 + off2
  3026  		v.Aux = sym
  3027  		v.AddArg(base)
  3028  		v.AddArg(idx)
  3029  		v.AddArg(val)
  3030  		v.AddArg(mem)
  3031  		return true
  3032  	}
  3033  	// match: (ANDLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem)
  3034  	// cond: is32Bit(off1+off2*4)
  3035  	// result: (ANDLmodifyidx4 [off1+off2*4] {sym} base idx val mem)
  3036  	for {
  3037  		off1 := v.AuxInt
  3038  		sym := v.Aux
  3039  		_ = v.Args[3]
  3040  		base := v.Args[0]
  3041  		v_1 := v.Args[1]
  3042  		if v_1.Op != Op386ADDLconst {
  3043  			break
  3044  		}
  3045  		off2 := v_1.AuxInt
  3046  		idx := v_1.Args[0]
  3047  		val := v.Args[2]
  3048  		mem := v.Args[3]
  3049  		if !(is32Bit(off1 + off2*4)) {
  3050  			break
  3051  		}
  3052  		v.reset(Op386ANDLmodifyidx4)
  3053  		v.AuxInt = off1 + off2*4
  3054  		v.Aux = sym
  3055  		v.AddArg(base)
  3056  		v.AddArg(idx)
  3057  		v.AddArg(val)
  3058  		v.AddArg(mem)
  3059  		return true
  3060  	}
  3061  	// match: (ANDLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem)
  3062  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  3063  	// result: (ANDLmodifyidx4 [off1+off2] {mergeSym(sym1,sym2)} base idx val mem)
  3064  	for {
  3065  		off1 := v.AuxInt
  3066  		sym1 := v.Aux
  3067  		_ = v.Args[3]
  3068  		v_0 := v.Args[0]
  3069  		if v_0.Op != Op386LEAL {
  3070  			break
  3071  		}
  3072  		off2 := v_0.AuxInt
  3073  		sym2 := v_0.Aux
  3074  		base := v_0.Args[0]
  3075  		idx := v.Args[1]
  3076  		val := v.Args[2]
  3077  		mem := v.Args[3]
  3078  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  3079  			break
  3080  		}
  3081  		v.reset(Op386ANDLmodifyidx4)
  3082  		v.AuxInt = off1 + off2
  3083  		v.Aux = mergeSym(sym1, sym2)
  3084  		v.AddArg(base)
  3085  		v.AddArg(idx)
  3086  		v.AddArg(val)
  3087  		v.AddArg(mem)
  3088  		return true
  3089  	}
  3090  	// match: (ANDLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem)
  3091  	// cond: validValAndOff(c,off)
  3092  	// result: (ANDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem)
  3093  	for {
  3094  		off := v.AuxInt
  3095  		sym := v.Aux
  3096  		_ = v.Args[3]
  3097  		ptr := v.Args[0]
  3098  		idx := v.Args[1]
  3099  		v_2 := v.Args[2]
  3100  		if v_2.Op != Op386MOVLconst {
  3101  			break
  3102  		}
  3103  		c := v_2.AuxInt
  3104  		mem := v.Args[3]
  3105  		if !(validValAndOff(c, off)) {
  3106  			break
  3107  		}
  3108  		v.reset(Op386ANDLconstmodifyidx4)
  3109  		v.AuxInt = makeValAndOff(c, off)
  3110  		v.Aux = sym
  3111  		v.AddArg(ptr)
  3112  		v.AddArg(idx)
  3113  		v.AddArg(mem)
  3114  		return true
  3115  	}
  3116  	return false
  3117  }
  3118  func rewriteValue386_Op386CMPB_0(v *Value) bool {
  3119  	b := v.Block
  3120  	_ = b
  3121  	// match: (CMPB x (MOVLconst [c]))
  3122  	// cond:
  3123  	// result: (CMPBconst x [int64(int8(c))])
  3124  	for {
  3125  		_ = v.Args[1]
  3126  		x := v.Args[0]
  3127  		v_1 := v.Args[1]
  3128  		if v_1.Op != Op386MOVLconst {
  3129  			break
  3130  		}
  3131  		c := v_1.AuxInt
  3132  		v.reset(Op386CMPBconst)
  3133  		v.AuxInt = int64(int8(c))
  3134  		v.AddArg(x)
  3135  		return true
  3136  	}
  3137  	// match: (CMPB (MOVLconst [c]) x)
  3138  	// cond:
  3139  	// result: (InvertFlags (CMPBconst x [int64(int8(c))]))
  3140  	for {
  3141  		_ = v.Args[1]
  3142  		v_0 := v.Args[0]
  3143  		if v_0.Op != Op386MOVLconst {
  3144  			break
  3145  		}
  3146  		c := v_0.AuxInt
  3147  		x := v.Args[1]
  3148  		v.reset(Op386InvertFlags)
  3149  		v0 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags)
  3150  		v0.AuxInt = int64(int8(c))
  3151  		v0.AddArg(x)
  3152  		v.AddArg(v0)
  3153  		return true
  3154  	}
  3155  	// match: (CMPB l:(MOVBload {sym} [off] ptr mem) x)
  3156  	// cond: canMergeLoad(v, l) && clobber(l)
  3157  	// result: (CMPBload {sym} [off] ptr x mem)
  3158  	for {
  3159  		_ = v.Args[1]
  3160  		l := v.Args[0]
  3161  		if l.Op != Op386MOVBload {
  3162  			break
  3163  		}
  3164  		off := l.AuxInt
  3165  		sym := l.Aux
  3166  		_ = l.Args[1]
  3167  		ptr := l.Args[0]
  3168  		mem := l.Args[1]
  3169  		x := v.Args[1]
  3170  		if !(canMergeLoad(v, l) && clobber(l)) {
  3171  			break
  3172  		}
  3173  		v.reset(Op386CMPBload)
  3174  		v.AuxInt = off
  3175  		v.Aux = sym
  3176  		v.AddArg(ptr)
  3177  		v.AddArg(x)
  3178  		v.AddArg(mem)
  3179  		return true
  3180  	}
  3181  	// match: (CMPB x l:(MOVBload {sym} [off] ptr mem))
  3182  	// cond: canMergeLoad(v, l) && clobber(l)
  3183  	// result: (InvertFlags (CMPBload {sym} [off] ptr x mem))
  3184  	for {
  3185  		_ = v.Args[1]
  3186  		x := v.Args[0]
  3187  		l := v.Args[1]
  3188  		if l.Op != Op386MOVBload {
  3189  			break
  3190  		}
  3191  		off := l.AuxInt
  3192  		sym := l.Aux
  3193  		_ = l.Args[1]
  3194  		ptr := l.Args[0]
  3195  		mem := l.Args[1]
  3196  		if !(canMergeLoad(v, l) && clobber(l)) {
  3197  			break
  3198  		}
  3199  		v.reset(Op386InvertFlags)
  3200  		v0 := b.NewValue0(l.Pos, Op386CMPBload, types.TypeFlags)
  3201  		v0.AuxInt = off
  3202  		v0.Aux = sym
  3203  		v0.AddArg(ptr)
  3204  		v0.AddArg(x)
  3205  		v0.AddArg(mem)
  3206  		v.AddArg(v0)
  3207  		return true
  3208  	}
  3209  	return false
  3210  }
  3211  func rewriteValue386_Op386CMPBconst_0(v *Value) bool {
  3212  	b := v.Block
  3213  	_ = b
  3214  	// match: (CMPBconst (MOVLconst [x]) [y])
  3215  	// cond: int8(x)==int8(y)
  3216  	// result: (FlagEQ)
  3217  	for {
  3218  		y := v.AuxInt
  3219  		v_0 := v.Args[0]
  3220  		if v_0.Op != Op386MOVLconst {
  3221  			break
  3222  		}
  3223  		x := v_0.AuxInt
  3224  		if !(int8(x) == int8(y)) {
  3225  			break
  3226  		}
  3227  		v.reset(Op386FlagEQ)
  3228  		return true
  3229  	}
  3230  	// match: (CMPBconst (MOVLconst [x]) [y])
  3231  	// cond: int8(x)<int8(y) && uint8(x)<uint8(y)
  3232  	// result: (FlagLT_ULT)
  3233  	for {
  3234  		y := v.AuxInt
  3235  		v_0 := v.Args[0]
  3236  		if v_0.Op != Op386MOVLconst {
  3237  			break
  3238  		}
  3239  		x := v_0.AuxInt
  3240  		if !(int8(x) < int8(y) && uint8(x) < uint8(y)) {
  3241  			break
  3242  		}
  3243  		v.reset(Op386FlagLT_ULT)
  3244  		return true
  3245  	}
  3246  	// match: (CMPBconst (MOVLconst [x]) [y])
  3247  	// cond: int8(x)<int8(y) && uint8(x)>uint8(y)
  3248  	// result: (FlagLT_UGT)
  3249  	for {
  3250  		y := v.AuxInt
  3251  		v_0 := v.Args[0]
  3252  		if v_0.Op != Op386MOVLconst {
  3253  			break
  3254  		}
  3255  		x := v_0.AuxInt
  3256  		if !(int8(x) < int8(y) && uint8(x) > uint8(y)) {
  3257  			break
  3258  		}
  3259  		v.reset(Op386FlagLT_UGT)
  3260  		return true
  3261  	}
  3262  	// match: (CMPBconst (MOVLconst [x]) [y])
  3263  	// cond: int8(x)>int8(y) && uint8(x)<uint8(y)
  3264  	// result: (FlagGT_ULT)
  3265  	for {
  3266  		y := v.AuxInt
  3267  		v_0 := v.Args[0]
  3268  		if v_0.Op != Op386MOVLconst {
  3269  			break
  3270  		}
  3271  		x := v_0.AuxInt
  3272  		if !(int8(x) > int8(y) && uint8(x) < uint8(y)) {
  3273  			break
  3274  		}
  3275  		v.reset(Op386FlagGT_ULT)
  3276  		return true
  3277  	}
  3278  	// match: (CMPBconst (MOVLconst [x]) [y])
  3279  	// cond: int8(x)>int8(y) && uint8(x)>uint8(y)
  3280  	// result: (FlagGT_UGT)
  3281  	for {
  3282  		y := v.AuxInt
  3283  		v_0 := v.Args[0]
  3284  		if v_0.Op != Op386MOVLconst {
  3285  			break
  3286  		}
  3287  		x := v_0.AuxInt
  3288  		if !(int8(x) > int8(y) && uint8(x) > uint8(y)) {
  3289  			break
  3290  		}
  3291  		v.reset(Op386FlagGT_UGT)
  3292  		return true
  3293  	}
  3294  	// match: (CMPBconst (ANDLconst _ [m]) [n])
  3295  	// cond: 0 <= int8(m) && int8(m) < int8(n)
  3296  	// result: (FlagLT_ULT)
  3297  	for {
  3298  		n := v.AuxInt
  3299  		v_0 := v.Args[0]
  3300  		if v_0.Op != Op386ANDLconst {
  3301  			break
  3302  		}
  3303  		m := v_0.AuxInt
  3304  		if !(0 <= int8(m) && int8(m) < int8(n)) {
  3305  			break
  3306  		}
  3307  		v.reset(Op386FlagLT_ULT)
  3308  		return true
  3309  	}
  3310  	// match: (CMPBconst l:(ANDL x y) [0])
  3311  	// cond: l.Uses==1
  3312  	// result: (TESTB x y)
  3313  	for {
  3314  		if v.AuxInt != 0 {
  3315  			break
  3316  		}
  3317  		l := v.Args[0]
  3318  		if l.Op != Op386ANDL {
  3319  			break
  3320  		}
  3321  		_ = l.Args[1]
  3322  		x := l.Args[0]
  3323  		y := l.Args[1]
  3324  		if !(l.Uses == 1) {
  3325  			break
  3326  		}
  3327  		v.reset(Op386TESTB)
  3328  		v.AddArg(x)
  3329  		v.AddArg(y)
  3330  		return true
  3331  	}
  3332  	// match: (CMPBconst l:(ANDLconst [c] x) [0])
  3333  	// cond: l.Uses==1
  3334  	// result: (TESTBconst [int64(int8(c))] x)
  3335  	for {
  3336  		if v.AuxInt != 0 {
  3337  			break
  3338  		}
  3339  		l := v.Args[0]
  3340  		if l.Op != Op386ANDLconst {
  3341  			break
  3342  		}
  3343  		c := l.AuxInt
  3344  		x := l.Args[0]
  3345  		if !(l.Uses == 1) {
  3346  			break
  3347  		}
  3348  		v.reset(Op386TESTBconst)
  3349  		v.AuxInt = int64(int8(c))
  3350  		v.AddArg(x)
  3351  		return true
  3352  	}
  3353  	// match: (CMPBconst x [0])
  3354  	// cond:
  3355  	// result: (TESTB x x)
  3356  	for {
  3357  		if v.AuxInt != 0 {
  3358  			break
  3359  		}
  3360  		x := v.Args[0]
  3361  		v.reset(Op386TESTB)
  3362  		v.AddArg(x)
  3363  		v.AddArg(x)
  3364  		return true
  3365  	}
  3366  	// match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c])
  3367  	// cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l)
  3368  	// result: @l.Block (CMPBconstload {sym} [makeValAndOff(c,off)] ptr mem)
  3369  	for {
  3370  		c := v.AuxInt
  3371  		l := v.Args[0]
  3372  		if l.Op != Op386MOVBload {
  3373  			break
  3374  		}
  3375  		off := l.AuxInt
  3376  		sym := l.Aux
  3377  		_ = l.Args[1]
  3378  		ptr := l.Args[0]
  3379  		mem := l.Args[1]
  3380  		if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) {
  3381  			break
  3382  		}
  3383  		b = l.Block
  3384  		v0 := b.NewValue0(l.Pos, Op386CMPBconstload, types.TypeFlags)
  3385  		v.reset(OpCopy)
  3386  		v.AddArg(v0)
  3387  		v0.AuxInt = makeValAndOff(c, off)
  3388  		v0.Aux = sym
  3389  		v0.AddArg(ptr)
  3390  		v0.AddArg(mem)
  3391  		return true
  3392  	}
  3393  	return false
  3394  }
  3395  func rewriteValue386_Op386CMPBload_0(v *Value) bool {
  3396  	// match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem)
  3397  	// cond: validValAndOff(int64(int8(c)),off)
  3398  	// result: (CMPBconstload {sym} [makeValAndOff(int64(int8(c)),off)] ptr mem)
  3399  	for {
  3400  		off := v.AuxInt
  3401  		sym := v.Aux
  3402  		_ = v.Args[2]
  3403  		ptr := v.Args[0]
  3404  		v_1 := v.Args[1]
  3405  		if v_1.Op != Op386MOVLconst {
  3406  			break
  3407  		}
  3408  		c := v_1.AuxInt
  3409  		mem := v.Args[2]
  3410  		if !(validValAndOff(int64(int8(c)), off)) {
  3411  			break
  3412  		}
  3413  		v.reset(Op386CMPBconstload)
  3414  		v.AuxInt = makeValAndOff(int64(int8(c)), off)
  3415  		v.Aux = sym
  3416  		v.AddArg(ptr)
  3417  		v.AddArg(mem)
  3418  		return true
  3419  	}
  3420  	return false
  3421  }
  3422  func rewriteValue386_Op386CMPL_0(v *Value) bool {
  3423  	b := v.Block
  3424  	_ = b
  3425  	// match: (CMPL x (MOVLconst [c]))
  3426  	// cond:
  3427  	// result: (CMPLconst x [c])
  3428  	for {
  3429  		_ = v.Args[1]
  3430  		x := v.Args[0]
  3431  		v_1 := v.Args[1]
  3432  		if v_1.Op != Op386MOVLconst {
  3433  			break
  3434  		}
  3435  		c := v_1.AuxInt
  3436  		v.reset(Op386CMPLconst)
  3437  		v.AuxInt = c
  3438  		v.AddArg(x)
  3439  		return true
  3440  	}
  3441  	// match: (CMPL (MOVLconst [c]) x)
  3442  	// cond:
  3443  	// result: (InvertFlags (CMPLconst x [c]))
  3444  	for {
  3445  		_ = v.Args[1]
  3446  		v_0 := v.Args[0]
  3447  		if v_0.Op != Op386MOVLconst {
  3448  			break
  3449  		}
  3450  		c := v_0.AuxInt
  3451  		x := v.Args[1]
  3452  		v.reset(Op386InvertFlags)
  3453  		v0 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags)
  3454  		v0.AuxInt = c
  3455  		v0.AddArg(x)
  3456  		v.AddArg(v0)
  3457  		return true
  3458  	}
  3459  	// match: (CMPL l:(MOVLload {sym} [off] ptr mem) x)
  3460  	// cond: canMergeLoad(v, l) && clobber(l)
  3461  	// result: (CMPLload {sym} [off] ptr x mem)
  3462  	for {
  3463  		_ = v.Args[1]
  3464  		l := v.Args[0]
  3465  		if l.Op != Op386MOVLload {
  3466  			break
  3467  		}
  3468  		off := l.AuxInt
  3469  		sym := l.Aux
  3470  		_ = l.Args[1]
  3471  		ptr := l.Args[0]
  3472  		mem := l.Args[1]
  3473  		x := v.Args[1]
  3474  		if !(canMergeLoad(v, l) && clobber(l)) {
  3475  			break
  3476  		}
  3477  		v.reset(Op386CMPLload)
  3478  		v.AuxInt = off
  3479  		v.Aux = sym
  3480  		v.AddArg(ptr)
  3481  		v.AddArg(x)
  3482  		v.AddArg(mem)
  3483  		return true
  3484  	}
  3485  	// match: (CMPL x l:(MOVLload {sym} [off] ptr mem))
  3486  	// cond: canMergeLoad(v, l) && clobber(l)
  3487  	// result: (InvertFlags (CMPLload {sym} [off] ptr x mem))
  3488  	for {
  3489  		_ = v.Args[1]
  3490  		x := v.Args[0]
  3491  		l := v.Args[1]
  3492  		if l.Op != Op386MOVLload {
  3493  			break
  3494  		}
  3495  		off := l.AuxInt
  3496  		sym := l.Aux
  3497  		_ = l.Args[1]
  3498  		ptr := l.Args[0]
  3499  		mem := l.Args[1]
  3500  		if !(canMergeLoad(v, l) && clobber(l)) {
  3501  			break
  3502  		}
  3503  		v.reset(Op386InvertFlags)
  3504  		v0 := b.NewValue0(l.Pos, Op386CMPLload, types.TypeFlags)
  3505  		v0.AuxInt = off
  3506  		v0.Aux = sym
  3507  		v0.AddArg(ptr)
  3508  		v0.AddArg(x)
  3509  		v0.AddArg(mem)
  3510  		v.AddArg(v0)
  3511  		return true
  3512  	}
  3513  	return false
  3514  }
  3515  func rewriteValue386_Op386CMPLconst_0(v *Value) bool {
  3516  	// match: (CMPLconst (MOVLconst [x]) [y])
  3517  	// cond: int32(x)==int32(y)
  3518  	// result: (FlagEQ)
  3519  	for {
  3520  		y := v.AuxInt
  3521  		v_0 := v.Args[0]
  3522  		if v_0.Op != Op386MOVLconst {
  3523  			break
  3524  		}
  3525  		x := v_0.AuxInt
  3526  		if !(int32(x) == int32(y)) {
  3527  			break
  3528  		}
  3529  		v.reset(Op386FlagEQ)
  3530  		return true
  3531  	}
  3532  	// match: (CMPLconst (MOVLconst [x]) [y])
  3533  	// cond: int32(x)<int32(y) && uint32(x)<uint32(y)
  3534  	// result: (FlagLT_ULT)
  3535  	for {
  3536  		y := v.AuxInt
  3537  		v_0 := v.Args[0]
  3538  		if v_0.Op != Op386MOVLconst {
  3539  			break
  3540  		}
  3541  		x := v_0.AuxInt
  3542  		if !(int32(x) < int32(y) && uint32(x) < uint32(y)) {
  3543  			break
  3544  		}
  3545  		v.reset(Op386FlagLT_ULT)
  3546  		return true
  3547  	}
  3548  	// match: (CMPLconst (MOVLconst [x]) [y])
  3549  	// cond: int32(x)<int32(y) && uint32(x)>uint32(y)
  3550  	// result: (FlagLT_UGT)
  3551  	for {
  3552  		y := v.AuxInt
  3553  		v_0 := v.Args[0]
  3554  		if v_0.Op != Op386MOVLconst {
  3555  			break
  3556  		}
  3557  		x := v_0.AuxInt
  3558  		if !(int32(x) < int32(y) && uint32(x) > uint32(y)) {
  3559  			break
  3560  		}
  3561  		v.reset(Op386FlagLT_UGT)
  3562  		return true
  3563  	}
  3564  	// match: (CMPLconst (MOVLconst [x]) [y])
  3565  	// cond: int32(x)>int32(y) && uint32(x)<uint32(y)
  3566  	// result: (FlagGT_ULT)
  3567  	for {
  3568  		y := v.AuxInt
  3569  		v_0 := v.Args[0]
  3570  		if v_0.Op != Op386MOVLconst {
  3571  			break
  3572  		}
  3573  		x := v_0.AuxInt
  3574  		if !(int32(x) > int32(y) && uint32(x) < uint32(y)) {
  3575  			break
  3576  		}
  3577  		v.reset(Op386FlagGT_ULT)
  3578  		return true
  3579  	}
  3580  	// match: (CMPLconst (MOVLconst [x]) [y])
  3581  	// cond: int32(x)>int32(y) && uint32(x)>uint32(y)
  3582  	// result: (FlagGT_UGT)
  3583  	for {
  3584  		y := v.AuxInt
  3585  		v_0 := v.Args[0]
  3586  		if v_0.Op != Op386MOVLconst {
  3587  			break
  3588  		}
  3589  		x := v_0.AuxInt
  3590  		if !(int32(x) > int32(y) && uint32(x) > uint32(y)) {
  3591  			break
  3592  		}
  3593  		v.reset(Op386FlagGT_UGT)
  3594  		return true
  3595  	}
  3596  	// match: (CMPLconst (SHRLconst _ [c]) [n])
  3597  	// cond: 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n)
  3598  	// result: (FlagLT_ULT)
  3599  	for {
  3600  		n := v.AuxInt
  3601  		v_0 := v.Args[0]
  3602  		if v_0.Op != Op386SHRLconst {
  3603  			break
  3604  		}
  3605  		c := v_0.AuxInt
  3606  		if !(0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n)) {
  3607  			break
  3608  		}
  3609  		v.reset(Op386FlagLT_ULT)
  3610  		return true
  3611  	}
  3612  	// match: (CMPLconst (ANDLconst _ [m]) [n])
  3613  	// cond: 0 <= int32(m) && int32(m) < int32(n)
  3614  	// result: (FlagLT_ULT)
  3615  	for {
  3616  		n := v.AuxInt
  3617  		v_0 := v.Args[0]
  3618  		if v_0.Op != Op386ANDLconst {
  3619  			break
  3620  		}
  3621  		m := v_0.AuxInt
  3622  		if !(0 <= int32(m) && int32(m) < int32(n)) {
  3623  			break
  3624  		}
  3625  		v.reset(Op386FlagLT_ULT)
  3626  		return true
  3627  	}
  3628  	// match: (CMPLconst l:(ANDL x y) [0])
  3629  	// cond: l.Uses==1
  3630  	// result: (TESTL x y)
  3631  	for {
  3632  		if v.AuxInt != 0 {
  3633  			break
  3634  		}
  3635  		l := v.Args[0]
  3636  		if l.Op != Op386ANDL {
  3637  			break
  3638  		}
  3639  		_ = l.Args[1]
  3640  		x := l.Args[0]
  3641  		y := l.Args[1]
  3642  		if !(l.Uses == 1) {
  3643  			break
  3644  		}
  3645  		v.reset(Op386TESTL)
  3646  		v.AddArg(x)
  3647  		v.AddArg(y)
  3648  		return true
  3649  	}
  3650  	// match: (CMPLconst l:(ANDLconst [c] x) [0])
  3651  	// cond: l.Uses==1
  3652  	// result: (TESTLconst [c] x)
  3653  	for {
  3654  		if v.AuxInt != 0 {
  3655  			break
  3656  		}
  3657  		l := v.Args[0]
  3658  		if l.Op != Op386ANDLconst {
  3659  			break
  3660  		}
  3661  		c := l.AuxInt
  3662  		x := l.Args[0]
  3663  		if !(l.Uses == 1) {
  3664  			break
  3665  		}
  3666  		v.reset(Op386TESTLconst)
  3667  		v.AuxInt = c
  3668  		v.AddArg(x)
  3669  		return true
  3670  	}
  3671  	// match: (CMPLconst x [0])
  3672  	// cond:
  3673  	// result: (TESTL x x)
  3674  	for {
  3675  		if v.AuxInt != 0 {
  3676  			break
  3677  		}
  3678  		x := v.Args[0]
  3679  		v.reset(Op386TESTL)
  3680  		v.AddArg(x)
  3681  		v.AddArg(x)
  3682  		return true
  3683  	}
  3684  	return false
  3685  }
  3686  func rewriteValue386_Op386CMPLconst_10(v *Value) bool {
  3687  	b := v.Block
  3688  	_ = b
  3689  	// match: (CMPLconst l:(MOVLload {sym} [off] ptr mem) [c])
  3690  	// cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l)
  3691  	// result: @l.Block (CMPLconstload {sym} [makeValAndOff(c,off)] ptr mem)
  3692  	for {
  3693  		c := v.AuxInt
  3694  		l := v.Args[0]
  3695  		if l.Op != Op386MOVLload {
  3696  			break
  3697  		}
  3698  		off := l.AuxInt
  3699  		sym := l.Aux
  3700  		_ = l.Args[1]
  3701  		ptr := l.Args[0]
  3702  		mem := l.Args[1]
  3703  		if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) {
  3704  			break
  3705  		}
  3706  		b = l.Block
  3707  		v0 := b.NewValue0(l.Pos, Op386CMPLconstload, types.TypeFlags)
  3708  		v.reset(OpCopy)
  3709  		v.AddArg(v0)
  3710  		v0.AuxInt = makeValAndOff(c, off)
  3711  		v0.Aux = sym
  3712  		v0.AddArg(ptr)
  3713  		v0.AddArg(mem)
  3714  		return true
  3715  	}
  3716  	return false
  3717  }
  3718  func rewriteValue386_Op386CMPLload_0(v *Value) bool {
  3719  	// match: (CMPLload {sym} [off] ptr (MOVLconst [c]) mem)
  3720  	// cond: validValAndOff(int64(int32(c)),off)
  3721  	// result: (CMPLconstload {sym} [makeValAndOff(int64(int32(c)),off)] ptr mem)
  3722  	for {
  3723  		off := v.AuxInt
  3724  		sym := v.Aux
  3725  		_ = v.Args[2]
  3726  		ptr := v.Args[0]
  3727  		v_1 := v.Args[1]
  3728  		if v_1.Op != Op386MOVLconst {
  3729  			break
  3730  		}
  3731  		c := v_1.AuxInt
  3732  		mem := v.Args[2]
  3733  		if !(validValAndOff(int64(int32(c)), off)) {
  3734  			break
  3735  		}
  3736  		v.reset(Op386CMPLconstload)
  3737  		v.AuxInt = makeValAndOff(int64(int32(c)), off)
  3738  		v.Aux = sym
  3739  		v.AddArg(ptr)
  3740  		v.AddArg(mem)
  3741  		return true
  3742  	}
  3743  	return false
  3744  }
  3745  func rewriteValue386_Op386CMPW_0(v *Value) bool {
  3746  	b := v.Block
  3747  	_ = b
  3748  	// match: (CMPW x (MOVLconst [c]))
  3749  	// cond:
  3750  	// result: (CMPWconst x [int64(int16(c))])
  3751  	for {
  3752  		_ = v.Args[1]
  3753  		x := v.Args[0]
  3754  		v_1 := v.Args[1]
  3755  		if v_1.Op != Op386MOVLconst {
  3756  			break
  3757  		}
  3758  		c := v_1.AuxInt
  3759  		v.reset(Op386CMPWconst)
  3760  		v.AuxInt = int64(int16(c))
  3761  		v.AddArg(x)
  3762  		return true
  3763  	}
  3764  	// match: (CMPW (MOVLconst [c]) x)
  3765  	// cond:
  3766  	// result: (InvertFlags (CMPWconst x [int64(int16(c))]))
  3767  	for {
  3768  		_ = v.Args[1]
  3769  		v_0 := v.Args[0]
  3770  		if v_0.Op != Op386MOVLconst {
  3771  			break
  3772  		}
  3773  		c := v_0.AuxInt
  3774  		x := v.Args[1]
  3775  		v.reset(Op386InvertFlags)
  3776  		v0 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags)
  3777  		v0.AuxInt = int64(int16(c))
  3778  		v0.AddArg(x)
  3779  		v.AddArg(v0)
  3780  		return true
  3781  	}
  3782  	// match: (CMPW l:(MOVWload {sym} [off] ptr mem) x)
  3783  	// cond: canMergeLoad(v, l) && clobber(l)
  3784  	// result: (CMPWload {sym} [off] ptr x mem)
  3785  	for {
  3786  		_ = v.Args[1]
  3787  		l := v.Args[0]
  3788  		if l.Op != Op386MOVWload {
  3789  			break
  3790  		}
  3791  		off := l.AuxInt
  3792  		sym := l.Aux
  3793  		_ = l.Args[1]
  3794  		ptr := l.Args[0]
  3795  		mem := l.Args[1]
  3796  		x := v.Args[1]
  3797  		if !(canMergeLoad(v, l) && clobber(l)) {
  3798  			break
  3799  		}
  3800  		v.reset(Op386CMPWload)
  3801  		v.AuxInt = off
  3802  		v.Aux = sym
  3803  		v.AddArg(ptr)
  3804  		v.AddArg(x)
  3805  		v.AddArg(mem)
  3806  		return true
  3807  	}
  3808  	// match: (CMPW x l:(MOVWload {sym} [off] ptr mem))
  3809  	// cond: canMergeLoad(v, l) && clobber(l)
  3810  	// result: (InvertFlags (CMPWload {sym} [off] ptr x mem))
  3811  	for {
  3812  		_ = v.Args[1]
  3813  		x := v.Args[0]
  3814  		l := v.Args[1]
  3815  		if l.Op != Op386MOVWload {
  3816  			break
  3817  		}
  3818  		off := l.AuxInt
  3819  		sym := l.Aux
  3820  		_ = l.Args[1]
  3821  		ptr := l.Args[0]
  3822  		mem := l.Args[1]
  3823  		if !(canMergeLoad(v, l) && clobber(l)) {
  3824  			break
  3825  		}
  3826  		v.reset(Op386InvertFlags)
  3827  		v0 := b.NewValue0(l.Pos, Op386CMPWload, types.TypeFlags)
  3828  		v0.AuxInt = off
  3829  		v0.Aux = sym
  3830  		v0.AddArg(ptr)
  3831  		v0.AddArg(x)
  3832  		v0.AddArg(mem)
  3833  		v.AddArg(v0)
  3834  		return true
  3835  	}
  3836  	return false
  3837  }
  3838  func rewriteValue386_Op386CMPWconst_0(v *Value) bool {
  3839  	b := v.Block
  3840  	_ = b
  3841  	// match: (CMPWconst (MOVLconst [x]) [y])
  3842  	// cond: int16(x)==int16(y)
  3843  	// result: (FlagEQ)
  3844  	for {
  3845  		y := v.AuxInt
  3846  		v_0 := v.Args[0]
  3847  		if v_0.Op != Op386MOVLconst {
  3848  			break
  3849  		}
  3850  		x := v_0.AuxInt
  3851  		if !(int16(x) == int16(y)) {
  3852  			break
  3853  		}
  3854  		v.reset(Op386FlagEQ)
  3855  		return true
  3856  	}
  3857  	// match: (CMPWconst (MOVLconst [x]) [y])
  3858  	// cond: int16(x)<int16(y) && uint16(x)<uint16(y)
  3859  	// result: (FlagLT_ULT)
  3860  	for {
  3861  		y := v.AuxInt
  3862  		v_0 := v.Args[0]
  3863  		if v_0.Op != Op386MOVLconst {
  3864  			break
  3865  		}
  3866  		x := v_0.AuxInt
  3867  		if !(int16(x) < int16(y) && uint16(x) < uint16(y)) {
  3868  			break
  3869  		}
  3870  		v.reset(Op386FlagLT_ULT)
  3871  		return true
  3872  	}
  3873  	// match: (CMPWconst (MOVLconst [x]) [y])
  3874  	// cond: int16(x)<int16(y) && uint16(x)>uint16(y)
  3875  	// result: (FlagLT_UGT)
  3876  	for {
  3877  		y := v.AuxInt
  3878  		v_0 := v.Args[0]
  3879  		if v_0.Op != Op386MOVLconst {
  3880  			break
  3881  		}
  3882  		x := v_0.AuxInt
  3883  		if !(int16(x) < int16(y) && uint16(x) > uint16(y)) {
  3884  			break
  3885  		}
  3886  		v.reset(Op386FlagLT_UGT)
  3887  		return true
  3888  	}
  3889  	// match: (CMPWconst (MOVLconst [x]) [y])
  3890  	// cond: int16(x)>int16(y) && uint16(x)<uint16(y)
  3891  	// result: (FlagGT_ULT)
  3892  	for {
  3893  		y := v.AuxInt
  3894  		v_0 := v.Args[0]
  3895  		if v_0.Op != Op386MOVLconst {
  3896  			break
  3897  		}
  3898  		x := v_0.AuxInt
  3899  		if !(int16(x) > int16(y) && uint16(x) < uint16(y)) {
  3900  			break
  3901  		}
  3902  		v.reset(Op386FlagGT_ULT)
  3903  		return true
  3904  	}
  3905  	// match: (CMPWconst (MOVLconst [x]) [y])
  3906  	// cond: int16(x)>int16(y) && uint16(x)>uint16(y)
  3907  	// result: (FlagGT_UGT)
  3908  	for {
  3909  		y := v.AuxInt
  3910  		v_0 := v.Args[0]
  3911  		if v_0.Op != Op386MOVLconst {
  3912  			break
  3913  		}
  3914  		x := v_0.AuxInt
  3915  		if !(int16(x) > int16(y) && uint16(x) > uint16(y)) {
  3916  			break
  3917  		}
  3918  		v.reset(Op386FlagGT_UGT)
  3919  		return true
  3920  	}
  3921  	// match: (CMPWconst (ANDLconst _ [m]) [n])
  3922  	// cond: 0 <= int16(m) && int16(m) < int16(n)
  3923  	// result: (FlagLT_ULT)
  3924  	for {
  3925  		n := v.AuxInt
  3926  		v_0 := v.Args[0]
  3927  		if v_0.Op != Op386ANDLconst {
  3928  			break
  3929  		}
  3930  		m := v_0.AuxInt
  3931  		if !(0 <= int16(m) && int16(m) < int16(n)) {
  3932  			break
  3933  		}
  3934  		v.reset(Op386FlagLT_ULT)
  3935  		return true
  3936  	}
  3937  	// match: (CMPWconst l:(ANDL x y) [0])
  3938  	// cond: l.Uses==1
  3939  	// result: (TESTW x y)
  3940  	for {
  3941  		if v.AuxInt != 0 {
  3942  			break
  3943  		}
  3944  		l := v.Args[0]
  3945  		if l.Op != Op386ANDL {
  3946  			break
  3947  		}
  3948  		_ = l.Args[1]
  3949  		x := l.Args[0]
  3950  		y := l.Args[1]
  3951  		if !(l.Uses == 1) {
  3952  			break
  3953  		}
  3954  		v.reset(Op386TESTW)
  3955  		v.AddArg(x)
  3956  		v.AddArg(y)
  3957  		return true
  3958  	}
  3959  	// match: (CMPWconst l:(ANDLconst [c] x) [0])
  3960  	// cond: l.Uses==1
  3961  	// result: (TESTWconst [int64(int16(c))] x)
  3962  	for {
  3963  		if v.AuxInt != 0 {
  3964  			break
  3965  		}
  3966  		l := v.Args[0]
  3967  		if l.Op != Op386ANDLconst {
  3968  			break
  3969  		}
  3970  		c := l.AuxInt
  3971  		x := l.Args[0]
  3972  		if !(l.Uses == 1) {
  3973  			break
  3974  		}
  3975  		v.reset(Op386TESTWconst)
  3976  		v.AuxInt = int64(int16(c))
  3977  		v.AddArg(x)
  3978  		return true
  3979  	}
  3980  	// match: (CMPWconst x [0])
  3981  	// cond:
  3982  	// result: (TESTW x x)
  3983  	for {
  3984  		if v.AuxInt != 0 {
  3985  			break
  3986  		}
  3987  		x := v.Args[0]
  3988  		v.reset(Op386TESTW)
  3989  		v.AddArg(x)
  3990  		v.AddArg(x)
  3991  		return true
  3992  	}
  3993  	// match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c])
  3994  	// cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l)
  3995  	// result: @l.Block (CMPWconstload {sym} [makeValAndOff(c,off)] ptr mem)
  3996  	for {
  3997  		c := v.AuxInt
  3998  		l := v.Args[0]
  3999  		if l.Op != Op386MOVWload {
  4000  			break
  4001  		}
  4002  		off := l.AuxInt
  4003  		sym := l.Aux
  4004  		_ = l.Args[1]
  4005  		ptr := l.Args[0]
  4006  		mem := l.Args[1]
  4007  		if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) {
  4008  			break
  4009  		}
  4010  		b = l.Block
  4011  		v0 := b.NewValue0(l.Pos, Op386CMPWconstload, types.TypeFlags)
  4012  		v.reset(OpCopy)
  4013  		v.AddArg(v0)
  4014  		v0.AuxInt = makeValAndOff(c, off)
  4015  		v0.Aux = sym
  4016  		v0.AddArg(ptr)
  4017  		v0.AddArg(mem)
  4018  		return true
  4019  	}
  4020  	return false
  4021  }
  4022  func rewriteValue386_Op386CMPWload_0(v *Value) bool {
  4023  	// match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem)
  4024  	// cond: validValAndOff(int64(int16(c)),off)
  4025  	// result: (CMPWconstload {sym} [makeValAndOff(int64(int16(c)),off)] ptr mem)
  4026  	for {
  4027  		off := v.AuxInt
  4028  		sym := v.Aux
  4029  		_ = v.Args[2]
  4030  		ptr := v.Args[0]
  4031  		v_1 := v.Args[1]
  4032  		if v_1.Op != Op386MOVLconst {
  4033  			break
  4034  		}
  4035  		c := v_1.AuxInt
  4036  		mem := v.Args[2]
  4037  		if !(validValAndOff(int64(int16(c)), off)) {
  4038  			break
  4039  		}
  4040  		v.reset(Op386CMPWconstload)
  4041  		v.AuxInt = makeValAndOff(int64(int16(c)), off)
  4042  		v.Aux = sym
  4043  		v.AddArg(ptr)
  4044  		v.AddArg(mem)
  4045  		return true
  4046  	}
  4047  	return false
  4048  }
  4049  func rewriteValue386_Op386DIVSD_0(v *Value) bool {
  4050  	b := v.Block
  4051  	_ = b
  4052  	config := b.Func.Config
  4053  	_ = config
  4054  	// match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem))
  4055  	// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
  4056  	// result: (DIVSDload x [off] {sym} ptr mem)
  4057  	for {
  4058  		_ = v.Args[1]
  4059  		x := v.Args[0]
  4060  		l := v.Args[1]
  4061  		if l.Op != Op386MOVSDload {
  4062  			break
  4063  		}
  4064  		off := l.AuxInt
  4065  		sym := l.Aux
  4066  		_ = l.Args[1]
  4067  		ptr := l.Args[0]
  4068  		mem := l.Args[1]
  4069  		if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
  4070  			break
  4071  		}
  4072  		v.reset(Op386DIVSDload)
  4073  		v.AuxInt = off
  4074  		v.Aux = sym
  4075  		v.AddArg(x)
  4076  		v.AddArg(ptr)
  4077  		v.AddArg(mem)
  4078  		return true
  4079  	}
  4080  	return false
  4081  }
  4082  func rewriteValue386_Op386DIVSDload_0(v *Value) bool {
  4083  	b := v.Block
  4084  	_ = b
  4085  	config := b.Func.Config
  4086  	_ = config
  4087  	// match: (DIVSDload [off1] {sym} val (ADDLconst [off2] base) mem)
  4088  	// cond: is32Bit(off1+off2)
  4089  	// result: (DIVSDload [off1+off2] {sym} val base mem)
  4090  	for {
  4091  		off1 := v.AuxInt
  4092  		sym := v.Aux
  4093  		_ = v.Args[2]
  4094  		val := v.Args[0]
  4095  		v_1 := v.Args[1]
  4096  		if v_1.Op != Op386ADDLconst {
  4097  			break
  4098  		}
  4099  		off2 := v_1.AuxInt
  4100  		base := v_1.Args[0]
  4101  		mem := v.Args[2]
  4102  		if !(is32Bit(off1 + off2)) {
  4103  			break
  4104  		}
  4105  		v.reset(Op386DIVSDload)
  4106  		v.AuxInt = off1 + off2
  4107  		v.Aux = sym
  4108  		v.AddArg(val)
  4109  		v.AddArg(base)
  4110  		v.AddArg(mem)
  4111  		return true
  4112  	}
  4113  	// match: (DIVSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
  4114  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  4115  	// result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  4116  	for {
  4117  		off1 := v.AuxInt
  4118  		sym1 := v.Aux
  4119  		_ = v.Args[2]
  4120  		val := v.Args[0]
  4121  		v_1 := v.Args[1]
  4122  		if v_1.Op != Op386LEAL {
  4123  			break
  4124  		}
  4125  		off2 := v_1.AuxInt
  4126  		sym2 := v_1.Aux
  4127  		base := v_1.Args[0]
  4128  		mem := v.Args[2]
  4129  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  4130  			break
  4131  		}
  4132  		v.reset(Op386DIVSDload)
  4133  		v.AuxInt = off1 + off2
  4134  		v.Aux = mergeSym(sym1, sym2)
  4135  		v.AddArg(val)
  4136  		v.AddArg(base)
  4137  		v.AddArg(mem)
  4138  		return true
  4139  	}
  4140  	return false
  4141  }
  4142  func rewriteValue386_Op386DIVSS_0(v *Value) bool {
  4143  	b := v.Block
  4144  	_ = b
  4145  	config := b.Func.Config
  4146  	_ = config
  4147  	// match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem))
  4148  	// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
  4149  	// result: (DIVSSload x [off] {sym} ptr mem)
  4150  	for {
  4151  		_ = v.Args[1]
  4152  		x := v.Args[0]
  4153  		l := v.Args[1]
  4154  		if l.Op != Op386MOVSSload {
  4155  			break
  4156  		}
  4157  		off := l.AuxInt
  4158  		sym := l.Aux
  4159  		_ = l.Args[1]
  4160  		ptr := l.Args[0]
  4161  		mem := l.Args[1]
  4162  		if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
  4163  			break
  4164  		}
  4165  		v.reset(Op386DIVSSload)
  4166  		v.AuxInt = off
  4167  		v.Aux = sym
  4168  		v.AddArg(x)
  4169  		v.AddArg(ptr)
  4170  		v.AddArg(mem)
  4171  		return true
  4172  	}
  4173  	return false
  4174  }
  4175  func rewriteValue386_Op386DIVSSload_0(v *Value) bool {
  4176  	b := v.Block
  4177  	_ = b
  4178  	config := b.Func.Config
  4179  	_ = config
  4180  	// match: (DIVSSload [off1] {sym} val (ADDLconst [off2] base) mem)
  4181  	// cond: is32Bit(off1+off2)
  4182  	// result: (DIVSSload [off1+off2] {sym} val base mem)
  4183  	for {
  4184  		off1 := v.AuxInt
  4185  		sym := v.Aux
  4186  		_ = v.Args[2]
  4187  		val := v.Args[0]
  4188  		v_1 := v.Args[1]
  4189  		if v_1.Op != Op386ADDLconst {
  4190  			break
  4191  		}
  4192  		off2 := v_1.AuxInt
  4193  		base := v_1.Args[0]
  4194  		mem := v.Args[2]
  4195  		if !(is32Bit(off1 + off2)) {
  4196  			break
  4197  		}
  4198  		v.reset(Op386DIVSSload)
  4199  		v.AuxInt = off1 + off2
  4200  		v.Aux = sym
  4201  		v.AddArg(val)
  4202  		v.AddArg(base)
  4203  		v.AddArg(mem)
  4204  		return true
  4205  	}
  4206  	// match: (DIVSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
  4207  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  4208  	// result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
  4209  	for {
  4210  		off1 := v.AuxInt
  4211  		sym1 := v.Aux
  4212  		_ = v.Args[2]
  4213  		val := v.Args[0]
  4214  		v_1 := v.Args[1]
  4215  		if v_1.Op != Op386LEAL {
  4216  			break
  4217  		}
  4218  		off2 := v_1.AuxInt
  4219  		sym2 := v_1.Aux
  4220  		base := v_1.Args[0]
  4221  		mem := v.Args[2]
  4222  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  4223  			break
  4224  		}
  4225  		v.reset(Op386DIVSSload)
  4226  		v.AuxInt = off1 + off2
  4227  		v.Aux = mergeSym(sym1, sym2)
  4228  		v.AddArg(val)
  4229  		v.AddArg(base)
  4230  		v.AddArg(mem)
  4231  		return true
  4232  	}
  4233  	return false
  4234  }
  4235  func rewriteValue386_Op386LEAL_0(v *Value) bool {
  4236  	// match: (LEAL [c] {s} (ADDLconst [d] x))
  4237  	// cond: is32Bit(c+d)
  4238  	// result: (LEAL [c+d] {s} x)
  4239  	for {
  4240  		c := v.AuxInt
  4241  		s := v.Aux
  4242  		v_0 := v.Args[0]
  4243  		if v_0.Op != Op386ADDLconst {
  4244  			break
  4245  		}
  4246  		d := v_0.AuxInt
  4247  		x := v_0.Args[0]
  4248  		if !(is32Bit(c + d)) {
  4249  			break
  4250  		}
  4251  		v.reset(Op386LEAL)
  4252  		v.AuxInt = c + d
  4253  		v.Aux = s
  4254  		v.AddArg(x)
  4255  		return true
  4256  	}
  4257  	// match: (LEAL [c] {s} (ADDL x y))
  4258  	// cond: x.Op != OpSB && y.Op != OpSB
  4259  	// result: (LEAL1 [c] {s} x y)
  4260  	for {
  4261  		c := v.AuxInt
  4262  		s := v.Aux
  4263  		v_0 := v.Args[0]
  4264  		if v_0.Op != Op386ADDL {
  4265  			break
  4266  		}
  4267  		_ = v_0.Args[1]
  4268  		x := v_0.Args[0]
  4269  		y := v_0.Args[1]
  4270  		if !(x.Op != OpSB && y.Op != OpSB) {
  4271  			break
  4272  		}
  4273  		v.reset(Op386LEAL1)
  4274  		v.AuxInt = c
  4275  		v.Aux = s
  4276  		v.AddArg(x)
  4277  		v.AddArg(y)
  4278  		return true
  4279  	}
  4280  	// match: (LEAL [off1] {sym1} (LEAL [off2] {sym2} x))
  4281  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4282  	// result: (LEAL [off1+off2] {mergeSym(sym1,sym2)} x)
  4283  	for {
  4284  		off1 := v.AuxInt
  4285  		sym1 := v.Aux
  4286  		v_0 := v.Args[0]
  4287  		if v_0.Op != Op386LEAL {
  4288  			break
  4289  		}
  4290  		off2 := v_0.AuxInt
  4291  		sym2 := v_0.Aux
  4292  		x := v_0.Args[0]
  4293  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4294  			break
  4295  		}
  4296  		v.reset(Op386LEAL)
  4297  		v.AuxInt = off1 + off2
  4298  		v.Aux = mergeSym(sym1, sym2)
  4299  		v.AddArg(x)
  4300  		return true
  4301  	}
  4302  	// match: (LEAL [off1] {sym1} (LEAL1 [off2] {sym2} x y))
  4303  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4304  	// result: (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4305  	for {
  4306  		off1 := v.AuxInt
  4307  		sym1 := v.Aux
  4308  		v_0 := v.Args[0]
  4309  		if v_0.Op != Op386LEAL1 {
  4310  			break
  4311  		}
  4312  		off2 := v_0.AuxInt
  4313  		sym2 := v_0.Aux
  4314  		_ = v_0.Args[1]
  4315  		x := v_0.Args[0]
  4316  		y := v_0.Args[1]
  4317  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4318  			break
  4319  		}
  4320  		v.reset(Op386LEAL1)
  4321  		v.AuxInt = off1 + off2
  4322  		v.Aux = mergeSym(sym1, sym2)
  4323  		v.AddArg(x)
  4324  		v.AddArg(y)
  4325  		return true
  4326  	}
  4327  	// match: (LEAL [off1] {sym1} (LEAL2 [off2] {sym2} x y))
  4328  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4329  	// result: (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4330  	for {
  4331  		off1 := v.AuxInt
  4332  		sym1 := v.Aux
  4333  		v_0 := v.Args[0]
  4334  		if v_0.Op != Op386LEAL2 {
  4335  			break
  4336  		}
  4337  		off2 := v_0.AuxInt
  4338  		sym2 := v_0.Aux
  4339  		_ = v_0.Args[1]
  4340  		x := v_0.Args[0]
  4341  		y := v_0.Args[1]
  4342  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4343  			break
  4344  		}
  4345  		v.reset(Op386LEAL2)
  4346  		v.AuxInt = off1 + off2
  4347  		v.Aux = mergeSym(sym1, sym2)
  4348  		v.AddArg(x)
  4349  		v.AddArg(y)
  4350  		return true
  4351  	}
  4352  	// match: (LEAL [off1] {sym1} (LEAL4 [off2] {sym2} x y))
  4353  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4354  	// result: (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4355  	for {
  4356  		off1 := v.AuxInt
  4357  		sym1 := v.Aux
  4358  		v_0 := v.Args[0]
  4359  		if v_0.Op != Op386LEAL4 {
  4360  			break
  4361  		}
  4362  		off2 := v_0.AuxInt
  4363  		sym2 := v_0.Aux
  4364  		_ = v_0.Args[1]
  4365  		x := v_0.Args[0]
  4366  		y := v_0.Args[1]
  4367  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4368  			break
  4369  		}
  4370  		v.reset(Op386LEAL4)
  4371  		v.AuxInt = off1 + off2
  4372  		v.Aux = mergeSym(sym1, sym2)
  4373  		v.AddArg(x)
  4374  		v.AddArg(y)
  4375  		return true
  4376  	}
  4377  	// match: (LEAL [off1] {sym1} (LEAL8 [off2] {sym2} x y))
  4378  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  4379  	// result: (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4380  	for {
  4381  		off1 := v.AuxInt
  4382  		sym1 := v.Aux
  4383  		v_0 := v.Args[0]
  4384  		if v_0.Op != Op386LEAL8 {
  4385  			break
  4386  		}
  4387  		off2 := v_0.AuxInt
  4388  		sym2 := v_0.Aux
  4389  		_ = v_0.Args[1]
  4390  		x := v_0.Args[0]
  4391  		y := v_0.Args[1]
  4392  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  4393  			break
  4394  		}
  4395  		v.reset(Op386LEAL8)
  4396  		v.AuxInt = off1 + off2
  4397  		v.Aux = mergeSym(sym1, sym2)
  4398  		v.AddArg(x)
  4399  		v.AddArg(y)
  4400  		return true
  4401  	}
  4402  	return false
  4403  }
  4404  func rewriteValue386_Op386LEAL1_0(v *Value) bool {
  4405  	// match: (LEAL1 [c] {s} (ADDLconst [d] x) y)
  4406  	// cond: is32Bit(c+d) && x.Op != OpSB
  4407  	// result: (LEAL1 [c+d] {s} x y)
  4408  	for {
  4409  		c := v.AuxInt
  4410  		s := v.Aux
  4411  		_ = v.Args[1]
  4412  		v_0 := v.Args[0]
  4413  		if v_0.Op != Op386ADDLconst {
  4414  			break
  4415  		}
  4416  		d := v_0.AuxInt
  4417  		x := v_0.Args[0]
  4418  		y := v.Args[1]
  4419  		if !(is32Bit(c+d) && x.Op != OpSB) {
  4420  			break
  4421  		}
  4422  		v.reset(Op386LEAL1)
  4423  		v.AuxInt = c + d
  4424  		v.Aux = s
  4425  		v.AddArg(x)
  4426  		v.AddArg(y)
  4427  		return true
  4428  	}
  4429  	// match: (LEAL1 [c] {s} y (ADDLconst [d] x))
  4430  	// cond: is32Bit(c+d) && x.Op != OpSB
  4431  	// result: (LEAL1 [c+d] {s} x y)
  4432  	for {
  4433  		c := v.AuxInt
  4434  		s := v.Aux
  4435  		_ = v.Args[1]
  4436  		y := v.Args[0]
  4437  		v_1 := v.Args[1]
  4438  		if v_1.Op != Op386ADDLconst {
  4439  			break
  4440  		}
  4441  		d := v_1.AuxInt
  4442  		x := v_1.Args[0]
  4443  		if !(is32Bit(c+d) && x.Op != OpSB) {
  4444  			break
  4445  		}
  4446  		v.reset(Op386LEAL1)
  4447  		v.AuxInt = c + d
  4448  		v.Aux = s
  4449  		v.AddArg(x)
  4450  		v.AddArg(y)
  4451  		return true
  4452  	}
  4453  	// match: (LEAL1 [c] {s} x (SHLLconst [1] y))
  4454  	// cond:
  4455  	// result: (LEAL2 [c] {s} x y)
  4456  	for {
  4457  		c := v.AuxInt
  4458  		s := v.Aux
  4459  		_ = v.Args[1]
  4460  		x := v.Args[0]
  4461  		v_1 := v.Args[1]
  4462  		if v_1.Op != Op386SHLLconst {
  4463  			break
  4464  		}
  4465  		if v_1.AuxInt != 1 {
  4466  			break
  4467  		}
  4468  		y := v_1.Args[0]
  4469  		v.reset(Op386LEAL2)
  4470  		v.AuxInt = c
  4471  		v.Aux = s
  4472  		v.AddArg(x)
  4473  		v.AddArg(y)
  4474  		return true
  4475  	}
  4476  	// match: (LEAL1 [c] {s} (SHLLconst [1] y) x)
  4477  	// cond:
  4478  	// result: (LEAL2 [c] {s} x y)
  4479  	for {
  4480  		c := v.AuxInt
  4481  		s := v.Aux
  4482  		_ = v.Args[1]
  4483  		v_0 := v.Args[0]
  4484  		if v_0.Op != Op386SHLLconst {
  4485  			break
  4486  		}
  4487  		if v_0.AuxInt != 1 {
  4488  			break
  4489  		}
  4490  		y := v_0.Args[0]
  4491  		x := v.Args[1]
  4492  		v.reset(Op386LEAL2)
  4493  		v.AuxInt = c
  4494  		v.Aux = s
  4495  		v.AddArg(x)
  4496  		v.AddArg(y)
  4497  		return true
  4498  	}
  4499  	// match: (LEAL1 [c] {s} x (SHLLconst [2] y))
  4500  	// cond:
  4501  	// result: (LEAL4 [c] {s} x y)
  4502  	for {
  4503  		c := v.AuxInt
  4504  		s := v.Aux
  4505  		_ = v.Args[1]
  4506  		x := v.Args[0]
  4507  		v_1 := v.Args[1]
  4508  		if v_1.Op != Op386SHLLconst {
  4509  			break
  4510  		}
  4511  		if v_1.AuxInt != 2 {
  4512  			break
  4513  		}
  4514  		y := v_1.Args[0]
  4515  		v.reset(Op386LEAL4)
  4516  		v.AuxInt = c
  4517  		v.Aux = s
  4518  		v.AddArg(x)
  4519  		v.AddArg(y)
  4520  		return true
  4521  	}
  4522  	// match: (LEAL1 [c] {s} (SHLLconst [2] y) x)
  4523  	// cond:
  4524  	// result: (LEAL4 [c] {s} x y)
  4525  	for {
  4526  		c := v.AuxInt
  4527  		s := v.Aux
  4528  		_ = v.Args[1]
  4529  		v_0 := v.Args[0]
  4530  		if v_0.Op != Op386SHLLconst {
  4531  			break
  4532  		}
  4533  		if v_0.AuxInt != 2 {
  4534  			break
  4535  		}
  4536  		y := v_0.Args[0]
  4537  		x := v.Args[1]
  4538  		v.reset(Op386LEAL4)
  4539  		v.AuxInt = c
  4540  		v.Aux = s
  4541  		v.AddArg(x)
  4542  		v.AddArg(y)
  4543  		return true
  4544  	}
  4545  	// match: (LEAL1 [c] {s} x (SHLLconst [3] y))
  4546  	// cond:
  4547  	// result: (LEAL8 [c] {s} x y)
  4548  	for {
  4549  		c := v.AuxInt
  4550  		s := v.Aux
  4551  		_ = v.Args[1]
  4552  		x := v.Args[0]
  4553  		v_1 := v.Args[1]
  4554  		if v_1.Op != Op386SHLLconst {
  4555  			break
  4556  		}
  4557  		if v_1.AuxInt != 3 {
  4558  			break
  4559  		}
  4560  		y := v_1.Args[0]
  4561  		v.reset(Op386LEAL8)
  4562  		v.AuxInt = c
  4563  		v.Aux = s
  4564  		v.AddArg(x)
  4565  		v.AddArg(y)
  4566  		return true
  4567  	}
  4568  	// match: (LEAL1 [c] {s} (SHLLconst [3] y) x)
  4569  	// cond:
  4570  	// result: (LEAL8 [c] {s} x y)
  4571  	for {
  4572  		c := v.AuxInt
  4573  		s := v.Aux
  4574  		_ = v.Args[1]
  4575  		v_0 := v.Args[0]
  4576  		if v_0.Op != Op386SHLLconst {
  4577  			break
  4578  		}
  4579  		if v_0.AuxInt != 3 {
  4580  			break
  4581  		}
  4582  		y := v_0.Args[0]
  4583  		x := v.Args[1]
  4584  		v.reset(Op386LEAL8)
  4585  		v.AuxInt = c
  4586  		v.Aux = s
  4587  		v.AddArg(x)
  4588  		v.AddArg(y)
  4589  		return true
  4590  	}
  4591  	// match: (LEAL1 [off1] {sym1} (LEAL [off2] {sym2} x) y)
  4592  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
  4593  	// result: (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4594  	for {
  4595  		off1 := v.AuxInt
  4596  		sym1 := v.Aux
  4597  		_ = v.Args[1]
  4598  		v_0 := v.Args[0]
  4599  		if v_0.Op != Op386LEAL {
  4600  			break
  4601  		}
  4602  		off2 := v_0.AuxInt
  4603  		sym2 := v_0.Aux
  4604  		x := v_0.Args[0]
  4605  		y := v.Args[1]
  4606  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
  4607  			break
  4608  		}
  4609  		v.reset(Op386LEAL1)
  4610  		v.AuxInt = off1 + off2
  4611  		v.Aux = mergeSym(sym1, sym2)
  4612  		v.AddArg(x)
  4613  		v.AddArg(y)
  4614  		return true
  4615  	}
  4616  	// match: (LEAL1 [off1] {sym1} y (LEAL [off2] {sym2} x))
  4617  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
  4618  	// result: (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4619  	for {
  4620  		off1 := v.AuxInt
  4621  		sym1 := v.Aux
  4622  		_ = v.Args[1]
  4623  		y := v.Args[0]
  4624  		v_1 := v.Args[1]
  4625  		if v_1.Op != Op386LEAL {
  4626  			break
  4627  		}
  4628  		off2 := v_1.AuxInt
  4629  		sym2 := v_1.Aux
  4630  		x := v_1.Args[0]
  4631  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
  4632  			break
  4633  		}
  4634  		v.reset(Op386LEAL1)
  4635  		v.AuxInt = off1 + off2
  4636  		v.Aux = mergeSym(sym1, sym2)
  4637  		v.AddArg(x)
  4638  		v.AddArg(y)
  4639  		return true
  4640  	}
  4641  	return false
  4642  }
  4643  func rewriteValue386_Op386LEAL2_0(v *Value) bool {
  4644  	// match: (LEAL2 [c] {s} (ADDLconst [d] x) y)
  4645  	// cond: is32Bit(c+d) && x.Op != OpSB
  4646  	// result: (LEAL2 [c+d] {s} x y)
  4647  	for {
  4648  		c := v.AuxInt
  4649  		s := v.Aux
  4650  		_ = v.Args[1]
  4651  		v_0 := v.Args[0]
  4652  		if v_0.Op != Op386ADDLconst {
  4653  			break
  4654  		}
  4655  		d := v_0.AuxInt
  4656  		x := v_0.Args[0]
  4657  		y := v.Args[1]
  4658  		if !(is32Bit(c+d) && x.Op != OpSB) {
  4659  			break
  4660  		}
  4661  		v.reset(Op386LEAL2)
  4662  		v.AuxInt = c + d
  4663  		v.Aux = s
  4664  		v.AddArg(x)
  4665  		v.AddArg(y)
  4666  		return true
  4667  	}
  4668  	// match: (LEAL2 [c] {s} x (ADDLconst [d] y))
  4669  	// cond: is32Bit(c+2*d) && y.Op != OpSB
  4670  	// result: (LEAL2 [c+2*d] {s} x y)
  4671  	for {
  4672  		c := v.AuxInt
  4673  		s := v.Aux
  4674  		_ = v.Args[1]
  4675  		x := v.Args[0]
  4676  		v_1 := v.Args[1]
  4677  		if v_1.Op != Op386ADDLconst {
  4678  			break
  4679  		}
  4680  		d := v_1.AuxInt
  4681  		y := v_1.Args[0]
  4682  		if !(is32Bit(c+2*d) && y.Op != OpSB) {
  4683  			break
  4684  		}
  4685  		v.reset(Op386LEAL2)
  4686  		v.AuxInt = c + 2*d
  4687  		v.Aux = s
  4688  		v.AddArg(x)
  4689  		v.AddArg(y)
  4690  		return true
  4691  	}
  4692  	// match: (LEAL2 [c] {s} x (SHLLconst [1] y))
  4693  	// cond:
  4694  	// result: (LEAL4 [c] {s} x y)
  4695  	for {
  4696  		c := v.AuxInt
  4697  		s := v.Aux
  4698  		_ = v.Args[1]
  4699  		x := v.Args[0]
  4700  		v_1 := v.Args[1]
  4701  		if v_1.Op != Op386SHLLconst {
  4702  			break
  4703  		}
  4704  		if v_1.AuxInt != 1 {
  4705  			break
  4706  		}
  4707  		y := v_1.Args[0]
  4708  		v.reset(Op386LEAL4)
  4709  		v.AuxInt = c
  4710  		v.Aux = s
  4711  		v.AddArg(x)
  4712  		v.AddArg(y)
  4713  		return true
  4714  	}
  4715  	// match: (LEAL2 [c] {s} x (SHLLconst [2] y))
  4716  	// cond:
  4717  	// result: (LEAL8 [c] {s} x y)
  4718  	for {
  4719  		c := v.AuxInt
  4720  		s := v.Aux
  4721  		_ = v.Args[1]
  4722  		x := v.Args[0]
  4723  		v_1 := v.Args[1]
  4724  		if v_1.Op != Op386SHLLconst {
  4725  			break
  4726  		}
  4727  		if v_1.AuxInt != 2 {
  4728  			break
  4729  		}
  4730  		y := v_1.Args[0]
  4731  		v.reset(Op386LEAL8)
  4732  		v.AuxInt = c
  4733  		v.Aux = s
  4734  		v.AddArg(x)
  4735  		v.AddArg(y)
  4736  		return true
  4737  	}
  4738  	// match: (LEAL2 [off1] {sym1} (LEAL [off2] {sym2} x) y)
  4739  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
  4740  	// result: (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4741  	for {
  4742  		off1 := v.AuxInt
  4743  		sym1 := v.Aux
  4744  		_ = v.Args[1]
  4745  		v_0 := v.Args[0]
  4746  		if v_0.Op != Op386LEAL {
  4747  			break
  4748  		}
  4749  		off2 := v_0.AuxInt
  4750  		sym2 := v_0.Aux
  4751  		x := v_0.Args[0]
  4752  		y := v.Args[1]
  4753  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
  4754  			break
  4755  		}
  4756  		v.reset(Op386LEAL2)
  4757  		v.AuxInt = off1 + off2
  4758  		v.Aux = mergeSym(sym1, sym2)
  4759  		v.AddArg(x)
  4760  		v.AddArg(y)
  4761  		return true
  4762  	}
  4763  	return false
  4764  }
  4765  func rewriteValue386_Op386LEAL4_0(v *Value) bool {
  4766  	// match: (LEAL4 [c] {s} (ADDLconst [d] x) y)
  4767  	// cond: is32Bit(c+d) && x.Op != OpSB
  4768  	// result: (LEAL4 [c+d] {s} x y)
  4769  	for {
  4770  		c := v.AuxInt
  4771  		s := v.Aux
  4772  		_ = v.Args[1]
  4773  		v_0 := v.Args[0]
  4774  		if v_0.Op != Op386ADDLconst {
  4775  			break
  4776  		}
  4777  		d := v_0.AuxInt
  4778  		x := v_0.Args[0]
  4779  		y := v.Args[1]
  4780  		if !(is32Bit(c+d) && x.Op != OpSB) {
  4781  			break
  4782  		}
  4783  		v.reset(Op386LEAL4)
  4784  		v.AuxInt = c + d
  4785  		v.Aux = s
  4786  		v.AddArg(x)
  4787  		v.AddArg(y)
  4788  		return true
  4789  	}
  4790  	// match: (LEAL4 [c] {s} x (ADDLconst [d] y))
  4791  	// cond: is32Bit(c+4*d) && y.Op != OpSB
  4792  	// result: (LEAL4 [c+4*d] {s} x y)
  4793  	for {
  4794  		c := v.AuxInt
  4795  		s := v.Aux
  4796  		_ = v.Args[1]
  4797  		x := v.Args[0]
  4798  		v_1 := v.Args[1]
  4799  		if v_1.Op != Op386ADDLconst {
  4800  			break
  4801  		}
  4802  		d := v_1.AuxInt
  4803  		y := v_1.Args[0]
  4804  		if !(is32Bit(c+4*d) && y.Op != OpSB) {
  4805  			break
  4806  		}
  4807  		v.reset(Op386LEAL4)
  4808  		v.AuxInt = c + 4*d
  4809  		v.Aux = s
  4810  		v.AddArg(x)
  4811  		v.AddArg(y)
  4812  		return true
  4813  	}
  4814  	// match: (LEAL4 [c] {s} x (SHLLconst [1] y))
  4815  	// cond:
  4816  	// result: (LEAL8 [c] {s} x y)
  4817  	for {
  4818  		c := v.AuxInt
  4819  		s := v.Aux
  4820  		_ = v.Args[1]
  4821  		x := v.Args[0]
  4822  		v_1 := v.Args[1]
  4823  		if v_1.Op != Op386SHLLconst {
  4824  			break
  4825  		}
  4826  		if v_1.AuxInt != 1 {
  4827  			break
  4828  		}
  4829  		y := v_1.Args[0]
  4830  		v.reset(Op386LEAL8)
  4831  		v.AuxInt = c
  4832  		v.Aux = s
  4833  		v.AddArg(x)
  4834  		v.AddArg(y)
  4835  		return true
  4836  	}
  4837  	// match: (LEAL4 [off1] {sym1} (LEAL [off2] {sym2} x) y)
  4838  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
  4839  	// result: (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4840  	for {
  4841  		off1 := v.AuxInt
  4842  		sym1 := v.Aux
  4843  		_ = v.Args[1]
  4844  		v_0 := v.Args[0]
  4845  		if v_0.Op != Op386LEAL {
  4846  			break
  4847  		}
  4848  		off2 := v_0.AuxInt
  4849  		sym2 := v_0.Aux
  4850  		x := v_0.Args[0]
  4851  		y := v.Args[1]
  4852  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
  4853  			break
  4854  		}
  4855  		v.reset(Op386LEAL4)
  4856  		v.AuxInt = off1 + off2
  4857  		v.Aux = mergeSym(sym1, sym2)
  4858  		v.AddArg(x)
  4859  		v.AddArg(y)
  4860  		return true
  4861  	}
  4862  	return false
  4863  }
  4864  func rewriteValue386_Op386LEAL8_0(v *Value) bool {
  4865  	// match: (LEAL8 [c] {s} (ADDLconst [d] x) y)
  4866  	// cond: is32Bit(c+d) && x.Op != OpSB
  4867  	// result: (LEAL8 [c+d] {s} x y)
  4868  	for {
  4869  		c := v.AuxInt
  4870  		s := v.Aux
  4871  		_ = v.Args[1]
  4872  		v_0 := v.Args[0]
  4873  		if v_0.Op != Op386ADDLconst {
  4874  			break
  4875  		}
  4876  		d := v_0.AuxInt
  4877  		x := v_0.Args[0]
  4878  		y := v.Args[1]
  4879  		if !(is32Bit(c+d) && x.Op != OpSB) {
  4880  			break
  4881  		}
  4882  		v.reset(Op386LEAL8)
  4883  		v.AuxInt = c + d
  4884  		v.Aux = s
  4885  		v.AddArg(x)
  4886  		v.AddArg(y)
  4887  		return true
  4888  	}
  4889  	// match: (LEAL8 [c] {s} x (ADDLconst [d] y))
  4890  	// cond: is32Bit(c+8*d) && y.Op != OpSB
  4891  	// result: (LEAL8 [c+8*d] {s} x y)
  4892  	for {
  4893  		c := v.AuxInt
  4894  		s := v.Aux
  4895  		_ = v.Args[1]
  4896  		x := v.Args[0]
  4897  		v_1 := v.Args[1]
  4898  		if v_1.Op != Op386ADDLconst {
  4899  			break
  4900  		}
  4901  		d := v_1.AuxInt
  4902  		y := v_1.Args[0]
  4903  		if !(is32Bit(c+8*d) && y.Op != OpSB) {
  4904  			break
  4905  		}
  4906  		v.reset(Op386LEAL8)
  4907  		v.AuxInt = c + 8*d
  4908  		v.Aux = s
  4909  		v.AddArg(x)
  4910  		v.AddArg(y)
  4911  		return true
  4912  	}
  4913  	// match: (LEAL8 [off1] {sym1} (LEAL [off2] {sym2} x) y)
  4914  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB
  4915  	// result: (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y)
  4916  	for {
  4917  		off1 := v.AuxInt
  4918  		sym1 := v.Aux
  4919  		_ = v.Args[1]
  4920  		v_0 := v.Args[0]
  4921  		if v_0.Op != Op386LEAL {
  4922  			break
  4923  		}
  4924  		off2 := v_0.AuxInt
  4925  		sym2 := v_0.Aux
  4926  		x := v_0.Args[0]
  4927  		y := v.Args[1]
  4928  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) {
  4929  			break
  4930  		}
  4931  		v.reset(Op386LEAL8)
  4932  		v.AuxInt = off1 + off2
  4933  		v.Aux = mergeSym(sym1, sym2)
  4934  		v.AddArg(x)
  4935  		v.AddArg(y)
  4936  		return true
  4937  	}
  4938  	return false
  4939  }
  4940  func rewriteValue386_Op386MOVBLSX_0(v *Value) bool {
  4941  	b := v.Block
  4942  	_ = b
  4943  	// match: (MOVBLSX x:(MOVBload [off] {sym} ptr mem))
  4944  	// cond: x.Uses == 1 && clobber(x)
  4945  	// result: @x.Block (MOVBLSXload <v.Type> [off] {sym} ptr mem)
  4946  	for {
  4947  		x := v.Args[0]
  4948  		if x.Op != Op386MOVBload {
  4949  			break
  4950  		}
  4951  		off := x.AuxInt
  4952  		sym := x.Aux
  4953  		_ = x.Args[1]
  4954  		ptr := x.Args[0]
  4955  		mem := x.Args[1]
  4956  		if !(x.Uses == 1 && clobber(x)) {
  4957  			break
  4958  		}
  4959  		b = x.Block
  4960  		v0 := b.NewValue0(x.Pos, Op386MOVBLSXload, v.Type)
  4961  		v.reset(OpCopy)
  4962  		v.AddArg(v0)
  4963  		v0.AuxInt = off
  4964  		v0.Aux = sym
  4965  		v0.AddArg(ptr)
  4966  		v0.AddArg(mem)
  4967  		return true
  4968  	}
  4969  	// match: (MOVBLSX (ANDLconst [c] x))
  4970  	// cond: c & 0x80 == 0
  4971  	// result: (ANDLconst [c & 0x7f] x)
  4972  	for {
  4973  		v_0 := v.Args[0]
  4974  		if v_0.Op != Op386ANDLconst {
  4975  			break
  4976  		}
  4977  		c := v_0.AuxInt
  4978  		x := v_0.Args[0]
  4979  		if !(c&0x80 == 0) {
  4980  			break
  4981  		}
  4982  		v.reset(Op386ANDLconst)
  4983  		v.AuxInt = c & 0x7f
  4984  		v.AddArg(x)
  4985  		return true
  4986  	}
  4987  	return false
  4988  }
  4989  func rewriteValue386_Op386MOVBLSXload_0(v *Value) bool {
  4990  	b := v.Block
  4991  	_ = b
  4992  	config := b.Func.Config
  4993  	_ = config
  4994  	// match: (MOVBLSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _))
  4995  	// cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
  4996  	// result: (MOVBLSX x)
  4997  	for {
  4998  		off := v.AuxInt
  4999  		sym := v.Aux
  5000  		_ = v.Args[1]
  5001  		ptr := v.Args[0]
  5002  		v_1 := v.Args[1]
  5003  		if v_1.Op != Op386MOVBstore {
  5004  			break
  5005  		}
  5006  		off2 := v_1.AuxInt
  5007  		sym2 := v_1.Aux
  5008  		_ = v_1.Args[2]
  5009  		ptr2 := v_1.Args[0]
  5010  		x := v_1.Args[1]
  5011  		if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
  5012  			break
  5013  		}
  5014  		v.reset(Op386MOVBLSX)
  5015  		v.AddArg(x)
  5016  		return true
  5017  	}
  5018  	// match: (MOVBLSXload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
  5019  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  5020  	// result: (MOVBLSXload [off1+off2] {mergeSym(sym1,sym2)} base mem)
  5021  	for {
  5022  		off1 := v.AuxInt
  5023  		sym1 := v.Aux
  5024  		_ = v.Args[1]
  5025  		v_0 := v.Args[0]
  5026  		if v_0.Op != Op386LEAL {
  5027  			break
  5028  		}
  5029  		off2 := v_0.AuxInt
  5030  		sym2 := v_0.Aux
  5031  		base := v_0.Args[0]
  5032  		mem := v.Args[1]
  5033  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  5034  			break
  5035  		}
  5036  		v.reset(Op386MOVBLSXload)
  5037  		v.AuxInt = off1 + off2
  5038  		v.Aux = mergeSym(sym1, sym2)
  5039  		v.AddArg(base)
  5040  		v.AddArg(mem)
  5041  		return true
  5042  	}
  5043  	return false
  5044  }
  5045  func rewriteValue386_Op386MOVBLZX_0(v *Value) bool {
  5046  	b := v.Block
  5047  	_ = b
  5048  	// match: (MOVBLZX x:(MOVBload [off] {sym} ptr mem))
  5049  	// cond: x.Uses == 1 && clobber(x)
  5050  	// result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
  5051  	for {
  5052  		x := v.Args[0]
  5053  		if x.Op != Op386MOVBload {
  5054  			break
  5055  		}
  5056  		off := x.AuxInt
  5057  		sym := x.Aux
  5058  		_ = x.Args[1]
  5059  		ptr := x.Args[0]
  5060  		mem := x.Args[1]
  5061  		if !(x.Uses == 1 && clobber(x)) {
  5062  			break
  5063  		}
  5064  		b = x.Block
  5065  		v0 := b.NewValue0(x.Pos, Op386MOVBload, v.Type)
  5066  		v.reset(OpCopy)
  5067  		v.AddArg(v0)
  5068  		v0.AuxInt = off
  5069  		v0.Aux = sym
  5070  		v0.AddArg(ptr)
  5071  		v0.AddArg(mem)
  5072  		return true
  5073  	}
  5074  	// match: (MOVBLZX x:(MOVBloadidx1 [off] {sym} ptr idx mem))
  5075  	// cond: x.Uses == 1 && clobber(x)
  5076  	// result: @x.Block (MOVBloadidx1 <v.Type> [off] {sym} ptr idx mem)
  5077  	for {
  5078  		x := v.Args[0]
  5079  		if x.Op != Op386MOVBloadidx1 {
  5080  			break
  5081  		}
  5082  		off := x.AuxInt
  5083  		sym := x.Aux
  5084  		_ = x.Args[2]
  5085  		ptr := x.Args[0]
  5086  		idx := x.Args[1]
  5087  		mem := x.Args[2]
  5088  		if !(x.Uses == 1 && clobber(x)) {
  5089  			break
  5090  		}
  5091  		b = x.Block
  5092  		v0 := b.NewValue0(v.Pos, Op386MOVBloadidx1, v.Type)
  5093  		v.reset(OpCopy)
  5094  		v.AddArg(v0)
  5095  		v0.AuxInt = off
  5096  		v0.Aux = sym
  5097  		v0.AddArg(ptr)
  5098  		v0.AddArg(idx)
  5099  		v0.AddArg(mem)
  5100  		return true
  5101  	}
  5102  	// match: (MOVBLZX (ANDLconst [c] x))
  5103  	// cond:
  5104  	// result: (ANDLconst [c & 0xff] x)
  5105  	for {
  5106  		v_0 := v.Args[0]
  5107  		if v_0.Op != Op386ANDLconst {
  5108  			break
  5109  		}
  5110  		c := v_0.AuxInt
  5111  		x := v_0.Args[0]
  5112  		v.reset(Op386ANDLconst)
  5113  		v.AuxInt = c & 0xff
  5114  		v.AddArg(x)
  5115  		return true
  5116  	}
  5117  	return false
  5118  }
  5119  func rewriteValue386_Op386MOVBload_0(v *Value) bool {
  5120  	b := v.Block
  5121  	_ = b
  5122  	config := b.Func.Config
  5123  	_ = config
  5124  	// match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _))
  5125  	// cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
  5126  	// result: (MOVBLZX x)
  5127  	for {
  5128  		off := v.AuxInt
  5129  		sym := v.Aux
  5130  		_ = v.Args[1]
  5131  		ptr := v.Args[0]
  5132  		v_1 := v.Args[1]
  5133  		if v_1.Op != Op386MOVBstore {
  5134  			break
  5135  		}
  5136  		off2 := v_1.AuxInt
  5137  		sym2 := v_1.Aux
  5138  		_ = v_1.Args[2]
  5139  		ptr2 := v_1.Args[0]
  5140  		x := v_1.Args[1]
  5141  		if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
  5142  			break
  5143  		}
  5144  		v.reset(Op386MOVBLZX)
  5145  		v.AddArg(x)
  5146  		return true
  5147  	}
  5148  	// match: (MOVBload [off1] {sym} (ADDLconst [off2] ptr) mem)
  5149  	// cond: is32Bit(off1+off2)
  5150  	// result: (MOVBload [off1+off2] {sym} ptr mem)
  5151  	for {
  5152  		off1 := v.AuxInt
  5153  		sym := v.Aux
  5154  		_ = v.Args[1]
  5155  		v_0 := v.Args[0]
  5156  		if v_0.Op != Op386ADDLconst {
  5157  			break
  5158  		}
  5159  		off2 := v_0.AuxInt
  5160  		ptr := v_0.Args[0]
  5161  		mem := v.Args[1]
  5162  		if !(is32Bit(off1 + off2)) {
  5163  			break
  5164  		}
  5165  		v.reset(Op386MOVBload)
  5166  		v.AuxInt = off1 + off2
  5167  		v.Aux = sym
  5168  		v.AddArg(ptr)
  5169  		v.AddArg(mem)
  5170  		return true
  5171  	}
  5172  	// match: (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
  5173  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  5174  	// result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem)
  5175  	for {
  5176  		off1 := v.AuxInt
  5177  		sym1 := v.Aux
  5178  		_ = v.Args[1]
  5179  		v_0 := v.Args[0]
  5180  		if v_0.Op != Op386LEAL {
  5181  			break
  5182  		}
  5183  		off2 := v_0.AuxInt
  5184  		sym2 := v_0.Aux
  5185  		base := v_0.Args[0]
  5186  		mem := v.Args[1]
  5187  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  5188  			break
  5189  		}
  5190  		v.reset(Op386MOVBload)
  5191  		v.AuxInt = off1 + off2
  5192  		v.Aux = mergeSym(sym1, sym2)
  5193  		v.AddArg(base)
  5194  		v.AddArg(mem)
  5195  		return true
  5196  	}
  5197  	// match: (MOVBload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem)
  5198  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  5199  	// result: (MOVBloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
  5200  	for {
  5201  		off1 := v.AuxInt
  5202  		sym1 := v.Aux
  5203  		_ = v.Args[1]
  5204  		v_0 := v.Args[0]
  5205  		if v_0.Op != Op386LEAL1 {
  5206  			break
  5207  		}
  5208  		off2 := v_0.AuxInt
  5209  		sym2 := v_0.Aux
  5210  		_ = v_0.Args[1]
  5211  		ptr := v_0.Args[0]
  5212  		idx := v_0.Args[1]
  5213  		mem := v.Args[1]
  5214  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  5215  			break
  5216  		}
  5217  		v.reset(Op386MOVBloadidx1)
  5218  		v.AuxInt = off1 + off2
  5219  		v.Aux = mergeSym(sym1, sym2)
  5220  		v.AddArg(ptr)
  5221  		v.AddArg(idx)
  5222  		v.AddArg(mem)
  5223  		return true
  5224  	}
  5225  	// match: (MOVBload [off] {sym} (ADDL ptr idx) mem)
  5226  	// cond: ptr.Op != OpSB
  5227  	// result: (MOVBloadidx1 [off] {sym} ptr idx mem)
  5228  	for {
  5229  		off := v.AuxInt
  5230  		sym := v.Aux
  5231  		_ = v.Args[1]
  5232  		v_0 := v.Args[0]
  5233  		if v_0.Op != Op386ADDL {
  5234  			break
  5235  		}
  5236  		_ = v_0.Args[1]
  5237  		ptr := v_0.Args[0]
  5238  		idx := v_0.Args[1]
  5239  		mem := v.Args[1]
  5240  		if !(ptr.Op != OpSB) {
  5241  			break
  5242  		}
  5243  		v.reset(Op386MOVBloadidx1)
  5244  		v.AuxInt = off
  5245  		v.Aux = sym
  5246  		v.AddArg(ptr)
  5247  		v.AddArg(idx)
  5248  		v.AddArg(mem)
  5249  		return true
  5250  	}
  5251  	// match: (MOVBload [off] {sym} (SB) _)
  5252  	// cond: symIsRO(sym)
  5253  	// result: (MOVLconst [int64(read8(sym, off))])
  5254  	for {
  5255  		off := v.AuxInt
  5256  		sym := v.Aux
  5257  		_ = v.Args[1]
  5258  		v_0 := v.Args[0]
  5259  		if v_0.Op != OpSB {
  5260  			break
  5261  		}
  5262  		if !(symIsRO(sym)) {
  5263  			break
  5264  		}
  5265  		v.reset(Op386MOVLconst)
  5266  		v.AuxInt = int64(read8(sym, off))
  5267  		return true
  5268  	}
  5269  	return false
  5270  }
  5271  func rewriteValue386_Op386MOVBloadidx1_0(v *Value) bool {
  5272  	// match: (MOVBloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem)
  5273  	// cond:
  5274  	// result: (MOVBloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  5275  	for {
  5276  		c := v.AuxInt
  5277  		sym := v.Aux
  5278  		_ = v.Args[2]
  5279  		v_0 := v.Args[0]
  5280  		if v_0.Op != Op386ADDLconst {
  5281  			break
  5282  		}
  5283  		d := v_0.AuxInt
  5284  		ptr := v_0.Args[0]
  5285  		idx := v.Args[1]
  5286  		mem := v.Args[2]
  5287  		v.reset(Op386MOVBloadidx1)
  5288  		v.AuxInt = int64(int32(c + d))
  5289  		v.Aux = sym
  5290  		v.AddArg(ptr)
  5291  		v.AddArg(idx)
  5292  		v.AddArg(mem)
  5293  		return true
  5294  	}
  5295  	// match: (MOVBloadidx1 [c] {sym} idx (ADDLconst [d] ptr) mem)
  5296  	// cond:
  5297  	// result: (MOVBloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  5298  	for {
  5299  		c := v.AuxInt
  5300  		sym := v.Aux
  5301  		_ = v.Args[2]
  5302  		idx := v.Args[0]
  5303  		v_1 := v.Args[1]
  5304  		if v_1.Op != Op386ADDLconst {
  5305  			break
  5306  		}
  5307  		d := v_1.AuxInt
  5308  		ptr := v_1.Args[0]
  5309  		mem := v.Args[2]
  5310  		v.reset(Op386MOVBloadidx1)
  5311  		v.AuxInt = int64(int32(c + d))
  5312  		v.Aux = sym
  5313  		v.AddArg(ptr)
  5314  		v.AddArg(idx)
  5315  		v.AddArg(mem)
  5316  		return true
  5317  	}
  5318  	// match: (MOVBloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem)
  5319  	// cond:
  5320  	// result: (MOVBloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  5321  	for {
  5322  		c := v.AuxInt
  5323  		sym := v.Aux
  5324  		_ = v.Args[2]
  5325  		ptr := v.Args[0]
  5326  		v_1 := v.Args[1]
  5327  		if v_1.Op != Op386ADDLconst {
  5328  			break
  5329  		}
  5330  		d := v_1.AuxInt
  5331  		idx := v_1.Args[0]
  5332  		mem := v.Args[2]
  5333  		v.reset(Op386MOVBloadidx1)
  5334  		v.AuxInt = int64(int32(c + d))
  5335  		v.Aux = sym
  5336  		v.AddArg(ptr)
  5337  		v.AddArg(idx)
  5338  		v.AddArg(mem)
  5339  		return true
  5340  	}
  5341  	// match: (MOVBloadidx1 [c] {sym} (ADDLconst [d] idx) ptr mem)
  5342  	// cond:
  5343  	// result: (MOVBloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  5344  	for {
  5345  		c := v.AuxInt
  5346  		sym := v.Aux
  5347  		_ = v.Args[2]
  5348  		v_0 := v.Args[0]
  5349  		if v_0.Op != Op386ADDLconst {
  5350  			break
  5351  		}
  5352  		d := v_0.AuxInt
  5353  		idx := v_0.Args[0]
  5354  		ptr := v.Args[1]
  5355  		mem := v.Args[2]
  5356  		v.reset(Op386MOVBloadidx1)
  5357  		v.AuxInt = int64(int32(c + d))
  5358  		v.Aux = sym
  5359  		v.AddArg(ptr)
  5360  		v.AddArg(idx)
  5361  		v.AddArg(mem)
  5362  		return true
  5363  	}
  5364  	return false
  5365  }
  5366  func rewriteValue386_Op386MOVBstore_0(v *Value) bool {
  5367  	b := v.Block
  5368  	_ = b
  5369  	config := b.Func.Config
  5370  	_ = config
  5371  	// match: (MOVBstore [off] {sym} ptr (MOVBLSX x) mem)
  5372  	// cond:
  5373  	// result: (MOVBstore [off] {sym} ptr x mem)
  5374  	for {
  5375  		off := v.AuxInt
  5376  		sym := v.Aux
  5377  		_ = v.Args[2]
  5378  		ptr := v.Args[0]
  5379  		v_1 := v.Args[1]
  5380  		if v_1.Op != Op386MOVBLSX {
  5381  			break
  5382  		}
  5383  		x := v_1.Args[0]
  5384  		mem := v.Args[2]
  5385  		v.reset(Op386MOVBstore)
  5386  		v.AuxInt = off
  5387  		v.Aux = sym
  5388  		v.AddArg(ptr)
  5389  		v.AddArg(x)
  5390  		v.AddArg(mem)
  5391  		return true
  5392  	}
  5393  	// match: (MOVBstore [off] {sym} ptr (MOVBLZX x) mem)
  5394  	// cond:
  5395  	// result: (MOVBstore [off] {sym} ptr x mem)
  5396  	for {
  5397  		off := v.AuxInt
  5398  		sym := v.Aux
  5399  		_ = v.Args[2]
  5400  		ptr := v.Args[0]
  5401  		v_1 := v.Args[1]
  5402  		if v_1.Op != Op386MOVBLZX {
  5403  			break
  5404  		}
  5405  		x := v_1.Args[0]
  5406  		mem := v.Args[2]
  5407  		v.reset(Op386MOVBstore)
  5408  		v.AuxInt = off
  5409  		v.Aux = sym
  5410  		v.AddArg(ptr)
  5411  		v.AddArg(x)
  5412  		v.AddArg(mem)
  5413  		return true
  5414  	}
  5415  	// match: (MOVBstore [off1] {sym} (ADDLconst [off2] ptr) val mem)
  5416  	// cond: is32Bit(off1+off2)
  5417  	// result: (MOVBstore [off1+off2] {sym} ptr val mem)
  5418  	for {
  5419  		off1 := v.AuxInt
  5420  		sym := v.Aux
  5421  		_ = v.Args[2]
  5422  		v_0 := v.Args[0]
  5423  		if v_0.Op != Op386ADDLconst {
  5424  			break
  5425  		}
  5426  		off2 := v_0.AuxInt
  5427  		ptr := v_0.Args[0]
  5428  		val := v.Args[1]
  5429  		mem := v.Args[2]
  5430  		if !(is32Bit(off1 + off2)) {
  5431  			break
  5432  		}
  5433  		v.reset(Op386MOVBstore)
  5434  		v.AuxInt = off1 + off2
  5435  		v.Aux = sym
  5436  		v.AddArg(ptr)
  5437  		v.AddArg(val)
  5438  		v.AddArg(mem)
  5439  		return true
  5440  	}
  5441  	// match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem)
  5442  	// cond: validOff(off)
  5443  	// result: (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem)
  5444  	for {
  5445  		off := v.AuxInt
  5446  		sym := v.Aux
  5447  		_ = v.Args[2]
  5448  		ptr := v.Args[0]
  5449  		v_1 := v.Args[1]
  5450  		if v_1.Op != Op386MOVLconst {
  5451  			break
  5452  		}
  5453  		c := v_1.AuxInt
  5454  		mem := v.Args[2]
  5455  		if !(validOff(off)) {
  5456  			break
  5457  		}
  5458  		v.reset(Op386MOVBstoreconst)
  5459  		v.AuxInt = makeValAndOff(int64(int8(c)), off)
  5460  		v.Aux = sym
  5461  		v.AddArg(ptr)
  5462  		v.AddArg(mem)
  5463  		return true
  5464  	}
  5465  	// match: (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
  5466  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  5467  	// result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  5468  	for {
  5469  		off1 := v.AuxInt
  5470  		sym1 := v.Aux
  5471  		_ = v.Args[2]
  5472  		v_0 := v.Args[0]
  5473  		if v_0.Op != Op386LEAL {
  5474  			break
  5475  		}
  5476  		off2 := v_0.AuxInt
  5477  		sym2 := v_0.Aux
  5478  		base := v_0.Args[0]
  5479  		val := v.Args[1]
  5480  		mem := v.Args[2]
  5481  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  5482  			break
  5483  		}
  5484  		v.reset(Op386MOVBstore)
  5485  		v.AuxInt = off1 + off2
  5486  		v.Aux = mergeSym(sym1, sym2)
  5487  		v.AddArg(base)
  5488  		v.AddArg(val)
  5489  		v.AddArg(mem)
  5490  		return true
  5491  	}
  5492  	// match: (MOVBstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem)
  5493  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  5494  	// result: (MOVBstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
  5495  	for {
  5496  		off1 := v.AuxInt
  5497  		sym1 := v.Aux
  5498  		_ = v.Args[2]
  5499  		v_0 := v.Args[0]
  5500  		if v_0.Op != Op386LEAL1 {
  5501  			break
  5502  		}
  5503  		off2 := v_0.AuxInt
  5504  		sym2 := v_0.Aux
  5505  		_ = v_0.Args[1]
  5506  		ptr := v_0.Args[0]
  5507  		idx := v_0.Args[1]
  5508  		val := v.Args[1]
  5509  		mem := v.Args[2]
  5510  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  5511  			break
  5512  		}
  5513  		v.reset(Op386MOVBstoreidx1)
  5514  		v.AuxInt = off1 + off2
  5515  		v.Aux = mergeSym(sym1, sym2)
  5516  		v.AddArg(ptr)
  5517  		v.AddArg(idx)
  5518  		v.AddArg(val)
  5519  		v.AddArg(mem)
  5520  		return true
  5521  	}
  5522  	// match: (MOVBstore [off] {sym} (ADDL ptr idx) val mem)
  5523  	// cond: ptr.Op != OpSB
  5524  	// result: (MOVBstoreidx1 [off] {sym} ptr idx val mem)
  5525  	for {
  5526  		off := v.AuxInt
  5527  		sym := v.Aux
  5528  		_ = v.Args[2]
  5529  		v_0 := v.Args[0]
  5530  		if v_0.Op != Op386ADDL {
  5531  			break
  5532  		}
  5533  		_ = v_0.Args[1]
  5534  		ptr := v_0.Args[0]
  5535  		idx := v_0.Args[1]
  5536  		val := v.Args[1]
  5537  		mem := v.Args[2]
  5538  		if !(ptr.Op != OpSB) {
  5539  			break
  5540  		}
  5541  		v.reset(Op386MOVBstoreidx1)
  5542  		v.AuxInt = off
  5543  		v.Aux = sym
  5544  		v.AddArg(ptr)
  5545  		v.AddArg(idx)
  5546  		v.AddArg(val)
  5547  		v.AddArg(mem)
  5548  		return true
  5549  	}
  5550  	// match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem))
  5551  	// cond: x.Uses == 1 && clobber(x)
  5552  	// result: (MOVWstore [i-1] {s} p w mem)
  5553  	for {
  5554  		i := v.AuxInt
  5555  		s := v.Aux
  5556  		_ = v.Args[2]
  5557  		p := v.Args[0]
  5558  		v_1 := v.Args[1]
  5559  		if v_1.Op != Op386SHRWconst {
  5560  			break
  5561  		}
  5562  		if v_1.AuxInt != 8 {
  5563  			break
  5564  		}
  5565  		w := v_1.Args[0]
  5566  		x := v.Args[2]
  5567  		if x.Op != Op386MOVBstore {
  5568  			break
  5569  		}
  5570  		if x.AuxInt != i-1 {
  5571  			break
  5572  		}
  5573  		if x.Aux != s {
  5574  			break
  5575  		}
  5576  		_ = x.Args[2]
  5577  		if p != x.Args[0] {
  5578  			break
  5579  		}
  5580  		if w != x.Args[1] {
  5581  			break
  5582  		}
  5583  		mem := x.Args[2]
  5584  		if !(x.Uses == 1 && clobber(x)) {
  5585  			break
  5586  		}
  5587  		v.reset(Op386MOVWstore)
  5588  		v.AuxInt = i - 1
  5589  		v.Aux = s
  5590  		v.AddArg(p)
  5591  		v.AddArg(w)
  5592  		v.AddArg(mem)
  5593  		return true
  5594  	}
  5595  	// match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem))
  5596  	// cond: x.Uses == 1 && clobber(x)
  5597  	// result: (MOVWstore [i-1] {s} p w mem)
  5598  	for {
  5599  		i := v.AuxInt
  5600  		s := v.Aux
  5601  		_ = v.Args[2]
  5602  		p := v.Args[0]
  5603  		v_1 := v.Args[1]
  5604  		if v_1.Op != Op386SHRLconst {
  5605  			break
  5606  		}
  5607  		if v_1.AuxInt != 8 {
  5608  			break
  5609  		}
  5610  		w := v_1.Args[0]
  5611  		x := v.Args[2]
  5612  		if x.Op != Op386MOVBstore {
  5613  			break
  5614  		}
  5615  		if x.AuxInt != i-1 {
  5616  			break
  5617  		}
  5618  		if x.Aux != s {
  5619  			break
  5620  		}
  5621  		_ = x.Args[2]
  5622  		if p != x.Args[0] {
  5623  			break
  5624  		}
  5625  		if w != x.Args[1] {
  5626  			break
  5627  		}
  5628  		mem := x.Args[2]
  5629  		if !(x.Uses == 1 && clobber(x)) {
  5630  			break
  5631  		}
  5632  		v.reset(Op386MOVWstore)
  5633  		v.AuxInt = i - 1
  5634  		v.Aux = s
  5635  		v.AddArg(p)
  5636  		v.AddArg(w)
  5637  		v.AddArg(mem)
  5638  		return true
  5639  	}
  5640  	// match: (MOVBstore [i] {s} p w x:(MOVBstore {s} [i+1] p (SHRWconst [8] w) mem))
  5641  	// cond: x.Uses == 1 && clobber(x)
  5642  	// result: (MOVWstore [i] {s} p w mem)
  5643  	for {
  5644  		i := v.AuxInt
  5645  		s := v.Aux
  5646  		_ = v.Args[2]
  5647  		p := v.Args[0]
  5648  		w := v.Args[1]
  5649  		x := v.Args[2]
  5650  		if x.Op != Op386MOVBstore {
  5651  			break
  5652  		}
  5653  		if x.AuxInt != i+1 {
  5654  			break
  5655  		}
  5656  		if x.Aux != s {
  5657  			break
  5658  		}
  5659  		_ = x.Args[2]
  5660  		if p != x.Args[0] {
  5661  			break
  5662  		}
  5663  		x_1 := x.Args[1]
  5664  		if x_1.Op != Op386SHRWconst {
  5665  			break
  5666  		}
  5667  		if x_1.AuxInt != 8 {
  5668  			break
  5669  		}
  5670  		if w != x_1.Args[0] {
  5671  			break
  5672  		}
  5673  		mem := x.Args[2]
  5674  		if !(x.Uses == 1 && clobber(x)) {
  5675  			break
  5676  		}
  5677  		v.reset(Op386MOVWstore)
  5678  		v.AuxInt = i
  5679  		v.Aux = s
  5680  		v.AddArg(p)
  5681  		v.AddArg(w)
  5682  		v.AddArg(mem)
  5683  		return true
  5684  	}
  5685  	return false
  5686  }
  5687  func rewriteValue386_Op386MOVBstore_10(v *Value) bool {
  5688  	// match: (MOVBstore [i] {s} p w x:(MOVBstore {s} [i+1] p (SHRLconst [8] w) mem))
  5689  	// cond: x.Uses == 1 && clobber(x)
  5690  	// result: (MOVWstore [i] {s} p w mem)
  5691  	for {
  5692  		i := v.AuxInt
  5693  		s := v.Aux
  5694  		_ = v.Args[2]
  5695  		p := v.Args[0]
  5696  		w := v.Args[1]
  5697  		x := v.Args[2]
  5698  		if x.Op != Op386MOVBstore {
  5699  			break
  5700  		}
  5701  		if x.AuxInt != i+1 {
  5702  			break
  5703  		}
  5704  		if x.Aux != s {
  5705  			break
  5706  		}
  5707  		_ = x.Args[2]
  5708  		if p != x.Args[0] {
  5709  			break
  5710  		}
  5711  		x_1 := x.Args[1]
  5712  		if x_1.Op != Op386SHRLconst {
  5713  			break
  5714  		}
  5715  		if x_1.AuxInt != 8 {
  5716  			break
  5717  		}
  5718  		if w != x_1.Args[0] {
  5719  			break
  5720  		}
  5721  		mem := x.Args[2]
  5722  		if !(x.Uses == 1 && clobber(x)) {
  5723  			break
  5724  		}
  5725  		v.reset(Op386MOVWstore)
  5726  		v.AuxInt = i
  5727  		v.Aux = s
  5728  		v.AddArg(p)
  5729  		v.AddArg(w)
  5730  		v.AddArg(mem)
  5731  		return true
  5732  	}
  5733  	// match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem))
  5734  	// cond: x.Uses == 1 && clobber(x)
  5735  	// result: (MOVWstore [i-1] {s} p w0 mem)
  5736  	for {
  5737  		i := v.AuxInt
  5738  		s := v.Aux
  5739  		_ = v.Args[2]
  5740  		p := v.Args[0]
  5741  		v_1 := v.Args[1]
  5742  		if v_1.Op != Op386SHRLconst {
  5743  			break
  5744  		}
  5745  		j := v_1.AuxInt
  5746  		w := v_1.Args[0]
  5747  		x := v.Args[2]
  5748  		if x.Op != Op386MOVBstore {
  5749  			break
  5750  		}
  5751  		if x.AuxInt != i-1 {
  5752  			break
  5753  		}
  5754  		if x.Aux != s {
  5755  			break
  5756  		}
  5757  		_ = x.Args[2]
  5758  		if p != x.Args[0] {
  5759  			break
  5760  		}
  5761  		w0 := x.Args[1]
  5762  		if w0.Op != Op386SHRLconst {
  5763  			break
  5764  		}
  5765  		if w0.AuxInt != j-8 {
  5766  			break
  5767  		}
  5768  		if w != w0.Args[0] {
  5769  			break
  5770  		}
  5771  		mem := x.Args[2]
  5772  		if !(x.Uses == 1 && clobber(x)) {
  5773  			break
  5774  		}
  5775  		v.reset(Op386MOVWstore)
  5776  		v.AuxInt = i - 1
  5777  		v.Aux = s
  5778  		v.AddArg(p)
  5779  		v.AddArg(w0)
  5780  		v.AddArg(mem)
  5781  		return true
  5782  	}
  5783  	return false
  5784  }
  5785  func rewriteValue386_Op386MOVBstoreconst_0(v *Value) bool {
  5786  	b := v.Block
  5787  	_ = b
  5788  	config := b.Func.Config
  5789  	_ = config
  5790  	// match: (MOVBstoreconst [sc] {s} (ADDLconst [off] ptr) mem)
  5791  	// cond: ValAndOff(sc).canAdd(off)
  5792  	// result: (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem)
  5793  	for {
  5794  		sc := v.AuxInt
  5795  		s := v.Aux
  5796  		_ = v.Args[1]
  5797  		v_0 := v.Args[0]
  5798  		if v_0.Op != Op386ADDLconst {
  5799  			break
  5800  		}
  5801  		off := v_0.AuxInt
  5802  		ptr := v_0.Args[0]
  5803  		mem := v.Args[1]
  5804  		if !(ValAndOff(sc).canAdd(off)) {
  5805  			break
  5806  		}
  5807  		v.reset(Op386MOVBstoreconst)
  5808  		v.AuxInt = ValAndOff(sc).add(off)
  5809  		v.Aux = s
  5810  		v.AddArg(ptr)
  5811  		v.AddArg(mem)
  5812  		return true
  5813  	}
  5814  	// match: (MOVBstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem)
  5815  	// cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  5816  	// result: (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem)
  5817  	for {
  5818  		sc := v.AuxInt
  5819  		sym1 := v.Aux
  5820  		_ = v.Args[1]
  5821  		v_0 := v.Args[0]
  5822  		if v_0.Op != Op386LEAL {
  5823  			break
  5824  		}
  5825  		off := v_0.AuxInt
  5826  		sym2 := v_0.Aux
  5827  		ptr := v_0.Args[0]
  5828  		mem := v.Args[1]
  5829  		if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  5830  			break
  5831  		}
  5832  		v.reset(Op386MOVBstoreconst)
  5833  		v.AuxInt = ValAndOff(sc).add(off)
  5834  		v.Aux = mergeSym(sym1, sym2)
  5835  		v.AddArg(ptr)
  5836  		v.AddArg(mem)
  5837  		return true
  5838  	}
  5839  	// match: (MOVBstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem)
  5840  	// cond: canMergeSym(sym1, sym2)
  5841  	// result: (MOVBstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem)
  5842  	for {
  5843  		x := v.AuxInt
  5844  		sym1 := v.Aux
  5845  		_ = v.Args[1]
  5846  		v_0 := v.Args[0]
  5847  		if v_0.Op != Op386LEAL1 {
  5848  			break
  5849  		}
  5850  		off := v_0.AuxInt
  5851  		sym2 := v_0.Aux
  5852  		_ = v_0.Args[1]
  5853  		ptr := v_0.Args[0]
  5854  		idx := v_0.Args[1]
  5855  		mem := v.Args[1]
  5856  		if !(canMergeSym(sym1, sym2)) {
  5857  			break
  5858  		}
  5859  		v.reset(Op386MOVBstoreconstidx1)
  5860  		v.AuxInt = ValAndOff(x).add(off)
  5861  		v.Aux = mergeSym(sym1, sym2)
  5862  		v.AddArg(ptr)
  5863  		v.AddArg(idx)
  5864  		v.AddArg(mem)
  5865  		return true
  5866  	}
  5867  	// match: (MOVBstoreconst [x] {sym} (ADDL ptr idx) mem)
  5868  	// cond:
  5869  	// result: (MOVBstoreconstidx1 [x] {sym} ptr idx mem)
  5870  	for {
  5871  		x := v.AuxInt
  5872  		sym := v.Aux
  5873  		_ = v.Args[1]
  5874  		v_0 := v.Args[0]
  5875  		if v_0.Op != Op386ADDL {
  5876  			break
  5877  		}
  5878  		_ = v_0.Args[1]
  5879  		ptr := v_0.Args[0]
  5880  		idx := v_0.Args[1]
  5881  		mem := v.Args[1]
  5882  		v.reset(Op386MOVBstoreconstidx1)
  5883  		v.AuxInt = x
  5884  		v.Aux = sym
  5885  		v.AddArg(ptr)
  5886  		v.AddArg(idx)
  5887  		v.AddArg(mem)
  5888  		return true
  5889  	}
  5890  	// match: (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem))
  5891  	// cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x)
  5892  	// result: (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem)
  5893  	for {
  5894  		c := v.AuxInt
  5895  		s := v.Aux
  5896  		_ = v.Args[1]
  5897  		p := v.Args[0]
  5898  		x := v.Args[1]
  5899  		if x.Op != Op386MOVBstoreconst {
  5900  			break
  5901  		}
  5902  		a := x.AuxInt
  5903  		if x.Aux != s {
  5904  			break
  5905  		}
  5906  		_ = x.Args[1]
  5907  		if p != x.Args[0] {
  5908  			break
  5909  		}
  5910  		mem := x.Args[1]
  5911  		if !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) {
  5912  			break
  5913  		}
  5914  		v.reset(Op386MOVWstoreconst)
  5915  		v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off())
  5916  		v.Aux = s
  5917  		v.AddArg(p)
  5918  		v.AddArg(mem)
  5919  		return true
  5920  	}
  5921  	// match: (MOVBstoreconst [a] {s} p x:(MOVBstoreconst [c] {s} p mem))
  5922  	// cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x)
  5923  	// result: (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem)
  5924  	for {
  5925  		a := v.AuxInt
  5926  		s := v.Aux
  5927  		_ = v.Args[1]
  5928  		p := v.Args[0]
  5929  		x := v.Args[1]
  5930  		if x.Op != Op386MOVBstoreconst {
  5931  			break
  5932  		}
  5933  		c := x.AuxInt
  5934  		if x.Aux != s {
  5935  			break
  5936  		}
  5937  		_ = x.Args[1]
  5938  		if p != x.Args[0] {
  5939  			break
  5940  		}
  5941  		mem := x.Args[1]
  5942  		if !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) {
  5943  			break
  5944  		}
  5945  		v.reset(Op386MOVWstoreconst)
  5946  		v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off())
  5947  		v.Aux = s
  5948  		v.AddArg(p)
  5949  		v.AddArg(mem)
  5950  		return true
  5951  	}
  5952  	return false
  5953  }
  5954  func rewriteValue386_Op386MOVBstoreconstidx1_0(v *Value) bool {
  5955  	// match: (MOVBstoreconstidx1 [x] {sym} (ADDLconst [c] ptr) idx mem)
  5956  	// cond:
  5957  	// result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem)
  5958  	for {
  5959  		x := v.AuxInt
  5960  		sym := v.Aux
  5961  		_ = v.Args[2]
  5962  		v_0 := v.Args[0]
  5963  		if v_0.Op != Op386ADDLconst {
  5964  			break
  5965  		}
  5966  		c := v_0.AuxInt
  5967  		ptr := v_0.Args[0]
  5968  		idx := v.Args[1]
  5969  		mem := v.Args[2]
  5970  		v.reset(Op386MOVBstoreconstidx1)
  5971  		v.AuxInt = ValAndOff(x).add(c)
  5972  		v.Aux = sym
  5973  		v.AddArg(ptr)
  5974  		v.AddArg(idx)
  5975  		v.AddArg(mem)
  5976  		return true
  5977  	}
  5978  	// match: (MOVBstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem)
  5979  	// cond:
  5980  	// result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem)
  5981  	for {
  5982  		x := v.AuxInt
  5983  		sym := v.Aux
  5984  		_ = v.Args[2]
  5985  		ptr := v.Args[0]
  5986  		v_1 := v.Args[1]
  5987  		if v_1.Op != Op386ADDLconst {
  5988  			break
  5989  		}
  5990  		c := v_1.AuxInt
  5991  		idx := v_1.Args[0]
  5992  		mem := v.Args[2]
  5993  		v.reset(Op386MOVBstoreconstidx1)
  5994  		v.AuxInt = ValAndOff(x).add(c)
  5995  		v.Aux = sym
  5996  		v.AddArg(ptr)
  5997  		v.AddArg(idx)
  5998  		v.AddArg(mem)
  5999  		return true
  6000  	}
  6001  	// match: (MOVBstoreconstidx1 [c] {s} p i x:(MOVBstoreconstidx1 [a] {s} p i mem))
  6002  	// cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x)
  6003  	// result: (MOVWstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p i mem)
  6004  	for {
  6005  		c := v.AuxInt
  6006  		s := v.Aux
  6007  		_ = v.Args[2]
  6008  		p := v.Args[0]
  6009  		i := v.Args[1]
  6010  		x := v.Args[2]
  6011  		if x.Op != Op386MOVBstoreconstidx1 {
  6012  			break
  6013  		}
  6014  		a := x.AuxInt
  6015  		if x.Aux != s {
  6016  			break
  6017  		}
  6018  		_ = x.Args[2]
  6019  		if p != x.Args[0] {
  6020  			break
  6021  		}
  6022  		if i != x.Args[1] {
  6023  			break
  6024  		}
  6025  		mem := x.Args[2]
  6026  		if !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) {
  6027  			break
  6028  		}
  6029  		v.reset(Op386MOVWstoreconstidx1)
  6030  		v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off())
  6031  		v.Aux = s
  6032  		v.AddArg(p)
  6033  		v.AddArg(i)
  6034  		v.AddArg(mem)
  6035  		return true
  6036  	}
  6037  	return false
  6038  }
  6039  func rewriteValue386_Op386MOVBstoreidx1_0(v *Value) bool {
  6040  	// match: (MOVBstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem)
  6041  	// cond:
  6042  	// result: (MOVBstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  6043  	for {
  6044  		c := v.AuxInt
  6045  		sym := v.Aux
  6046  		_ = v.Args[3]
  6047  		v_0 := v.Args[0]
  6048  		if v_0.Op != Op386ADDLconst {
  6049  			break
  6050  		}
  6051  		d := v_0.AuxInt
  6052  		ptr := v_0.Args[0]
  6053  		idx := v.Args[1]
  6054  		val := v.Args[2]
  6055  		mem := v.Args[3]
  6056  		v.reset(Op386MOVBstoreidx1)
  6057  		v.AuxInt = int64(int32(c + d))
  6058  		v.Aux = sym
  6059  		v.AddArg(ptr)
  6060  		v.AddArg(idx)
  6061  		v.AddArg(val)
  6062  		v.AddArg(mem)
  6063  		return true
  6064  	}
  6065  	// match: (MOVBstoreidx1 [c] {sym} idx (ADDLconst [d] ptr) val mem)
  6066  	// cond:
  6067  	// result: (MOVBstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  6068  	for {
  6069  		c := v.AuxInt
  6070  		sym := v.Aux
  6071  		_ = v.Args[3]
  6072  		idx := v.Args[0]
  6073  		v_1 := v.Args[1]
  6074  		if v_1.Op != Op386ADDLconst {
  6075  			break
  6076  		}
  6077  		d := v_1.AuxInt
  6078  		ptr := v_1.Args[0]
  6079  		val := v.Args[2]
  6080  		mem := v.Args[3]
  6081  		v.reset(Op386MOVBstoreidx1)
  6082  		v.AuxInt = int64(int32(c + d))
  6083  		v.Aux = sym
  6084  		v.AddArg(ptr)
  6085  		v.AddArg(idx)
  6086  		v.AddArg(val)
  6087  		v.AddArg(mem)
  6088  		return true
  6089  	}
  6090  	// match: (MOVBstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem)
  6091  	// cond:
  6092  	// result: (MOVBstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  6093  	for {
  6094  		c := v.AuxInt
  6095  		sym := v.Aux
  6096  		_ = v.Args[3]
  6097  		ptr := v.Args[0]
  6098  		v_1 := v.Args[1]
  6099  		if v_1.Op != Op386ADDLconst {
  6100  			break
  6101  		}
  6102  		d := v_1.AuxInt
  6103  		idx := v_1.Args[0]
  6104  		val := v.Args[2]
  6105  		mem := v.Args[3]
  6106  		v.reset(Op386MOVBstoreidx1)
  6107  		v.AuxInt = int64(int32(c + d))
  6108  		v.Aux = sym
  6109  		v.AddArg(ptr)
  6110  		v.AddArg(idx)
  6111  		v.AddArg(val)
  6112  		v.AddArg(mem)
  6113  		return true
  6114  	}
  6115  	// match: (MOVBstoreidx1 [c] {sym} (ADDLconst [d] idx) ptr val mem)
  6116  	// cond:
  6117  	// result: (MOVBstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  6118  	for {
  6119  		c := v.AuxInt
  6120  		sym := v.Aux
  6121  		_ = v.Args[3]
  6122  		v_0 := v.Args[0]
  6123  		if v_0.Op != Op386ADDLconst {
  6124  			break
  6125  		}
  6126  		d := v_0.AuxInt
  6127  		idx := v_0.Args[0]
  6128  		ptr := v.Args[1]
  6129  		val := v.Args[2]
  6130  		mem := v.Args[3]
  6131  		v.reset(Op386MOVBstoreidx1)
  6132  		v.AuxInt = int64(int32(c + d))
  6133  		v.Aux = sym
  6134  		v.AddArg(ptr)
  6135  		v.AddArg(idx)
  6136  		v.AddArg(val)
  6137  		v.AddArg(mem)
  6138  		return true
  6139  	}
  6140  	// match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem))
  6141  	// cond: x.Uses == 1 && clobber(x)
  6142  	// result: (MOVWstoreidx1 [i-1] {s} p idx w mem)
  6143  	for {
  6144  		i := v.AuxInt
  6145  		s := v.Aux
  6146  		_ = v.Args[3]
  6147  		p := v.Args[0]
  6148  		idx := v.Args[1]
  6149  		v_2 := v.Args[2]
  6150  		if v_2.Op != Op386SHRLconst {
  6151  			break
  6152  		}
  6153  		if v_2.AuxInt != 8 {
  6154  			break
  6155  		}
  6156  		w := v_2.Args[0]
  6157  		x := v.Args[3]
  6158  		if x.Op != Op386MOVBstoreidx1 {
  6159  			break
  6160  		}
  6161  		if x.AuxInt != i-1 {
  6162  			break
  6163  		}
  6164  		if x.Aux != s {
  6165  			break
  6166  		}
  6167  		_ = x.Args[3]
  6168  		if p != x.Args[0] {
  6169  			break
  6170  		}
  6171  		if idx != x.Args[1] {
  6172  			break
  6173  		}
  6174  		if w != x.Args[2] {
  6175  			break
  6176  		}
  6177  		mem := x.Args[3]
  6178  		if !(x.Uses == 1 && clobber(x)) {
  6179  			break
  6180  		}
  6181  		v.reset(Op386MOVWstoreidx1)
  6182  		v.AuxInt = i - 1
  6183  		v.Aux = s
  6184  		v.AddArg(p)
  6185  		v.AddArg(idx)
  6186  		v.AddArg(w)
  6187  		v.AddArg(mem)
  6188  		return true
  6189  	}
  6190  	// match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem))
  6191  	// cond: x.Uses == 1 && clobber(x)
  6192  	// result: (MOVWstoreidx1 [i-1] {s} p idx w mem)
  6193  	for {
  6194  		i := v.AuxInt
  6195  		s := v.Aux
  6196  		_ = v.Args[3]
  6197  		p := v.Args[0]
  6198  		idx := v.Args[1]
  6199  		v_2 := v.Args[2]
  6200  		if v_2.Op != Op386SHRLconst {
  6201  			break
  6202  		}
  6203  		if v_2.AuxInt != 8 {
  6204  			break
  6205  		}
  6206  		w := v_2.Args[0]
  6207  		x := v.Args[3]
  6208  		if x.Op != Op386MOVBstoreidx1 {
  6209  			break
  6210  		}
  6211  		if x.AuxInt != i-1 {
  6212  			break
  6213  		}
  6214  		if x.Aux != s {
  6215  			break
  6216  		}
  6217  		_ = x.Args[3]
  6218  		if idx != x.Args[0] {
  6219  			break
  6220  		}
  6221  		if p != x.Args[1] {
  6222  			break
  6223  		}
  6224  		if w != x.Args[2] {
  6225  			break
  6226  		}
  6227  		mem := x.Args[3]
  6228  		if !(x.Uses == 1 && clobber(x)) {
  6229  			break
  6230  		}
  6231  		v.reset(Op386MOVWstoreidx1)
  6232  		v.AuxInt = i - 1
  6233  		v.Aux = s
  6234  		v.AddArg(p)
  6235  		v.AddArg(idx)
  6236  		v.AddArg(w)
  6237  		v.AddArg(mem)
  6238  		return true
  6239  	}
  6240  	// match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem))
  6241  	// cond: x.Uses == 1 && clobber(x)
  6242  	// result: (MOVWstoreidx1 [i-1] {s} p idx w mem)
  6243  	for {
  6244  		i := v.AuxInt
  6245  		s := v.Aux
  6246  		_ = v.Args[3]
  6247  		idx := v.Args[0]
  6248  		p := v.Args[1]
  6249  		v_2 := v.Args[2]
  6250  		if v_2.Op != Op386SHRLconst {
  6251  			break
  6252  		}
  6253  		if v_2.AuxInt != 8 {
  6254  			break
  6255  		}
  6256  		w := v_2.Args[0]
  6257  		x := v.Args[3]
  6258  		if x.Op != Op386MOVBstoreidx1 {
  6259  			break
  6260  		}
  6261  		if x.AuxInt != i-1 {
  6262  			break
  6263  		}
  6264  		if x.Aux != s {
  6265  			break
  6266  		}
  6267  		_ = x.Args[3]
  6268  		if p != x.Args[0] {
  6269  			break
  6270  		}
  6271  		if idx != x.Args[1] {
  6272  			break
  6273  		}
  6274  		if w != x.Args[2] {
  6275  			break
  6276  		}
  6277  		mem := x.Args[3]
  6278  		if !(x.Uses == 1 && clobber(x)) {
  6279  			break
  6280  		}
  6281  		v.reset(Op386MOVWstoreidx1)
  6282  		v.AuxInt = i - 1
  6283  		v.Aux = s
  6284  		v.AddArg(p)
  6285  		v.AddArg(idx)
  6286  		v.AddArg(w)
  6287  		v.AddArg(mem)
  6288  		return true
  6289  	}
  6290  	// match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem))
  6291  	// cond: x.Uses == 1 && clobber(x)
  6292  	// result: (MOVWstoreidx1 [i-1] {s} p idx w mem)
  6293  	for {
  6294  		i := v.AuxInt
  6295  		s := v.Aux
  6296  		_ = v.Args[3]
  6297  		idx := v.Args[0]
  6298  		p := v.Args[1]
  6299  		v_2 := v.Args[2]
  6300  		if v_2.Op != Op386SHRLconst {
  6301  			break
  6302  		}
  6303  		if v_2.AuxInt != 8 {
  6304  			break
  6305  		}
  6306  		w := v_2.Args[0]
  6307  		x := v.Args[3]
  6308  		if x.Op != Op386MOVBstoreidx1 {
  6309  			break
  6310  		}
  6311  		if x.AuxInt != i-1 {
  6312  			break
  6313  		}
  6314  		if x.Aux != s {
  6315  			break
  6316  		}
  6317  		_ = x.Args[3]
  6318  		if idx != x.Args[0] {
  6319  			break
  6320  		}
  6321  		if p != x.Args[1] {
  6322  			break
  6323  		}
  6324  		if w != x.Args[2] {
  6325  			break
  6326  		}
  6327  		mem := x.Args[3]
  6328  		if !(x.Uses == 1 && clobber(x)) {
  6329  			break
  6330  		}
  6331  		v.reset(Op386MOVWstoreidx1)
  6332  		v.AuxInt = i - 1
  6333  		v.Aux = s
  6334  		v.AddArg(p)
  6335  		v.AddArg(idx)
  6336  		v.AddArg(w)
  6337  		v.AddArg(mem)
  6338  		return true
  6339  	}
  6340  	// match: (MOVBstoreidx1 [i] {s} p idx (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem))
  6341  	// cond: x.Uses == 1 && clobber(x)
  6342  	// result: (MOVWstoreidx1 [i-1] {s} p idx w mem)
  6343  	for {
  6344  		i := v.AuxInt
  6345  		s := v.Aux
  6346  		_ = v.Args[3]
  6347  		p := v.Args[0]
  6348  		idx := v.Args[1]
  6349  		v_2 := v.Args[2]
  6350  		if v_2.Op != Op386SHRWconst {
  6351  			break
  6352  		}
  6353  		if v_2.AuxInt != 8 {
  6354  			break
  6355  		}
  6356  		w := v_2.Args[0]
  6357  		x := v.Args[3]
  6358  		if x.Op != Op386MOVBstoreidx1 {
  6359  			break
  6360  		}
  6361  		if x.AuxInt != i-1 {
  6362  			break
  6363  		}
  6364  		if x.Aux != s {
  6365  			break
  6366  		}
  6367  		_ = x.Args[3]
  6368  		if p != x.Args[0] {
  6369  			break
  6370  		}
  6371  		if idx != x.Args[1] {
  6372  			break
  6373  		}
  6374  		if w != x.Args[2] {
  6375  			break
  6376  		}
  6377  		mem := x.Args[3]
  6378  		if !(x.Uses == 1 && clobber(x)) {
  6379  			break
  6380  		}
  6381  		v.reset(Op386MOVWstoreidx1)
  6382  		v.AuxInt = i - 1
  6383  		v.Aux = s
  6384  		v.AddArg(p)
  6385  		v.AddArg(idx)
  6386  		v.AddArg(w)
  6387  		v.AddArg(mem)
  6388  		return true
  6389  	}
  6390  	// match: (MOVBstoreidx1 [i] {s} p idx (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem))
  6391  	// cond: x.Uses == 1 && clobber(x)
  6392  	// result: (MOVWstoreidx1 [i-1] {s} p idx w mem)
  6393  	for {
  6394  		i := v.AuxInt
  6395  		s := v.Aux
  6396  		_ = v.Args[3]
  6397  		p := v.Args[0]
  6398  		idx := v.Args[1]
  6399  		v_2 := v.Args[2]
  6400  		if v_2.Op != Op386SHRWconst {
  6401  			break
  6402  		}
  6403  		if v_2.AuxInt != 8 {
  6404  			break
  6405  		}
  6406  		w := v_2.Args[0]
  6407  		x := v.Args[3]
  6408  		if x.Op != Op386MOVBstoreidx1 {
  6409  			break
  6410  		}
  6411  		if x.AuxInt != i-1 {
  6412  			break
  6413  		}
  6414  		if x.Aux != s {
  6415  			break
  6416  		}
  6417  		_ = x.Args[3]
  6418  		if idx != x.Args[0] {
  6419  			break
  6420  		}
  6421  		if p != x.Args[1] {
  6422  			break
  6423  		}
  6424  		if w != x.Args[2] {
  6425  			break
  6426  		}
  6427  		mem := x.Args[3]
  6428  		if !(x.Uses == 1 && clobber(x)) {
  6429  			break
  6430  		}
  6431  		v.reset(Op386MOVWstoreidx1)
  6432  		v.AuxInt = i - 1
  6433  		v.Aux = s
  6434  		v.AddArg(p)
  6435  		v.AddArg(idx)
  6436  		v.AddArg(w)
  6437  		v.AddArg(mem)
  6438  		return true
  6439  	}
  6440  	return false
  6441  }
  6442  func rewriteValue386_Op386MOVBstoreidx1_10(v *Value) bool {
  6443  	// match: (MOVBstoreidx1 [i] {s} idx p (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem))
  6444  	// cond: x.Uses == 1 && clobber(x)
  6445  	// result: (MOVWstoreidx1 [i-1] {s} p idx w mem)
  6446  	for {
  6447  		i := v.AuxInt
  6448  		s := v.Aux
  6449  		_ = v.Args[3]
  6450  		idx := v.Args[0]
  6451  		p := v.Args[1]
  6452  		v_2 := v.Args[2]
  6453  		if v_2.Op != Op386SHRWconst {
  6454  			break
  6455  		}
  6456  		if v_2.AuxInt != 8 {
  6457  			break
  6458  		}
  6459  		w := v_2.Args[0]
  6460  		x := v.Args[3]
  6461  		if x.Op != Op386MOVBstoreidx1 {
  6462  			break
  6463  		}
  6464  		if x.AuxInt != i-1 {
  6465  			break
  6466  		}
  6467  		if x.Aux != s {
  6468  			break
  6469  		}
  6470  		_ = x.Args[3]
  6471  		if p != x.Args[0] {
  6472  			break
  6473  		}
  6474  		if idx != x.Args[1] {
  6475  			break
  6476  		}
  6477  		if w != x.Args[2] {
  6478  			break
  6479  		}
  6480  		mem := x.Args[3]
  6481  		if !(x.Uses == 1 && clobber(x)) {
  6482  			break
  6483  		}
  6484  		v.reset(Op386MOVWstoreidx1)
  6485  		v.AuxInt = i - 1
  6486  		v.Aux = s
  6487  		v.AddArg(p)
  6488  		v.AddArg(idx)
  6489  		v.AddArg(w)
  6490  		v.AddArg(mem)
  6491  		return true
  6492  	}
  6493  	// match: (MOVBstoreidx1 [i] {s} idx p (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem))
  6494  	// cond: x.Uses == 1 && clobber(x)
  6495  	// result: (MOVWstoreidx1 [i-1] {s} p idx w mem)
  6496  	for {
  6497  		i := v.AuxInt
  6498  		s := v.Aux
  6499  		_ = v.Args[3]
  6500  		idx := v.Args[0]
  6501  		p := v.Args[1]
  6502  		v_2 := v.Args[2]
  6503  		if v_2.Op != Op386SHRWconst {
  6504  			break
  6505  		}
  6506  		if v_2.AuxInt != 8 {
  6507  			break
  6508  		}
  6509  		w := v_2.Args[0]
  6510  		x := v.Args[3]
  6511  		if x.Op != Op386MOVBstoreidx1 {
  6512  			break
  6513  		}
  6514  		if x.AuxInt != i-1 {
  6515  			break
  6516  		}
  6517  		if x.Aux != s {
  6518  			break
  6519  		}
  6520  		_ = x.Args[3]
  6521  		if idx != x.Args[0] {
  6522  			break
  6523  		}
  6524  		if p != x.Args[1] {
  6525  			break
  6526  		}
  6527  		if w != x.Args[2] {
  6528  			break
  6529  		}
  6530  		mem := x.Args[3]
  6531  		if !(x.Uses == 1 && clobber(x)) {
  6532  			break
  6533  		}
  6534  		v.reset(Op386MOVWstoreidx1)
  6535  		v.AuxInt = i - 1
  6536  		v.Aux = s
  6537  		v.AddArg(p)
  6538  		v.AddArg(idx)
  6539  		v.AddArg(w)
  6540  		v.AddArg(mem)
  6541  		return true
  6542  	}
  6543  	// match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRLconst [8] w) mem))
  6544  	// cond: x.Uses == 1 && clobber(x)
  6545  	// result: (MOVWstoreidx1 [i] {s} p idx w mem)
  6546  	for {
  6547  		i := v.AuxInt
  6548  		s := v.Aux
  6549  		_ = v.Args[3]
  6550  		p := v.Args[0]
  6551  		idx := v.Args[1]
  6552  		w := v.Args[2]
  6553  		x := v.Args[3]
  6554  		if x.Op != Op386MOVBstoreidx1 {
  6555  			break
  6556  		}
  6557  		if x.AuxInt != i+1 {
  6558  			break
  6559  		}
  6560  		if x.Aux != s {
  6561  			break
  6562  		}
  6563  		_ = x.Args[3]
  6564  		if p != x.Args[0] {
  6565  			break
  6566  		}
  6567  		if idx != x.Args[1] {
  6568  			break
  6569  		}
  6570  		x_2 := x.Args[2]
  6571  		if x_2.Op != Op386SHRLconst {
  6572  			break
  6573  		}
  6574  		if x_2.AuxInt != 8 {
  6575  			break
  6576  		}
  6577  		if w != x_2.Args[0] {
  6578  			break
  6579  		}
  6580  		mem := x.Args[3]
  6581  		if !(x.Uses == 1 && clobber(x)) {
  6582  			break
  6583  		}
  6584  		v.reset(Op386MOVWstoreidx1)
  6585  		v.AuxInt = i
  6586  		v.Aux = s
  6587  		v.AddArg(p)
  6588  		v.AddArg(idx)
  6589  		v.AddArg(w)
  6590  		v.AddArg(mem)
  6591  		return true
  6592  	}
  6593  	// match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRLconst [8] w) mem))
  6594  	// cond: x.Uses == 1 && clobber(x)
  6595  	// result: (MOVWstoreidx1 [i] {s} p idx w mem)
  6596  	for {
  6597  		i := v.AuxInt
  6598  		s := v.Aux
  6599  		_ = v.Args[3]
  6600  		p := v.Args[0]
  6601  		idx := v.Args[1]
  6602  		w := v.Args[2]
  6603  		x := v.Args[3]
  6604  		if x.Op != Op386MOVBstoreidx1 {
  6605  			break
  6606  		}
  6607  		if x.AuxInt != i+1 {
  6608  			break
  6609  		}
  6610  		if x.Aux != s {
  6611  			break
  6612  		}
  6613  		_ = x.Args[3]
  6614  		if idx != x.Args[0] {
  6615  			break
  6616  		}
  6617  		if p != x.Args[1] {
  6618  			break
  6619  		}
  6620  		x_2 := x.Args[2]
  6621  		if x_2.Op != Op386SHRLconst {
  6622  			break
  6623  		}
  6624  		if x_2.AuxInt != 8 {
  6625  			break
  6626  		}
  6627  		if w != x_2.Args[0] {
  6628  			break
  6629  		}
  6630  		mem := x.Args[3]
  6631  		if !(x.Uses == 1 && clobber(x)) {
  6632  			break
  6633  		}
  6634  		v.reset(Op386MOVWstoreidx1)
  6635  		v.AuxInt = i
  6636  		v.Aux = s
  6637  		v.AddArg(p)
  6638  		v.AddArg(idx)
  6639  		v.AddArg(w)
  6640  		v.AddArg(mem)
  6641  		return true
  6642  	}
  6643  	// match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRLconst [8] w) mem))
  6644  	// cond: x.Uses == 1 && clobber(x)
  6645  	// result: (MOVWstoreidx1 [i] {s} p idx w mem)
  6646  	for {
  6647  		i := v.AuxInt
  6648  		s := v.Aux
  6649  		_ = v.Args[3]
  6650  		idx := v.Args[0]
  6651  		p := v.Args[1]
  6652  		w := v.Args[2]
  6653  		x := v.Args[3]
  6654  		if x.Op != Op386MOVBstoreidx1 {
  6655  			break
  6656  		}
  6657  		if x.AuxInt != i+1 {
  6658  			break
  6659  		}
  6660  		if x.Aux != s {
  6661  			break
  6662  		}
  6663  		_ = x.Args[3]
  6664  		if p != x.Args[0] {
  6665  			break
  6666  		}
  6667  		if idx != x.Args[1] {
  6668  			break
  6669  		}
  6670  		x_2 := x.Args[2]
  6671  		if x_2.Op != Op386SHRLconst {
  6672  			break
  6673  		}
  6674  		if x_2.AuxInt != 8 {
  6675  			break
  6676  		}
  6677  		if w != x_2.Args[0] {
  6678  			break
  6679  		}
  6680  		mem := x.Args[3]
  6681  		if !(x.Uses == 1 && clobber(x)) {
  6682  			break
  6683  		}
  6684  		v.reset(Op386MOVWstoreidx1)
  6685  		v.AuxInt = i
  6686  		v.Aux = s
  6687  		v.AddArg(p)
  6688  		v.AddArg(idx)
  6689  		v.AddArg(w)
  6690  		v.AddArg(mem)
  6691  		return true
  6692  	}
  6693  	// match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRLconst [8] w) mem))
  6694  	// cond: x.Uses == 1 && clobber(x)
  6695  	// result: (MOVWstoreidx1 [i] {s} p idx w mem)
  6696  	for {
  6697  		i := v.AuxInt
  6698  		s := v.Aux
  6699  		_ = v.Args[3]
  6700  		idx := v.Args[0]
  6701  		p := v.Args[1]
  6702  		w := v.Args[2]
  6703  		x := v.Args[3]
  6704  		if x.Op != Op386MOVBstoreidx1 {
  6705  			break
  6706  		}
  6707  		if x.AuxInt != i+1 {
  6708  			break
  6709  		}
  6710  		if x.Aux != s {
  6711  			break
  6712  		}
  6713  		_ = x.Args[3]
  6714  		if idx != x.Args[0] {
  6715  			break
  6716  		}
  6717  		if p != x.Args[1] {
  6718  			break
  6719  		}
  6720  		x_2 := x.Args[2]
  6721  		if x_2.Op != Op386SHRLconst {
  6722  			break
  6723  		}
  6724  		if x_2.AuxInt != 8 {
  6725  			break
  6726  		}
  6727  		if w != x_2.Args[0] {
  6728  			break
  6729  		}
  6730  		mem := x.Args[3]
  6731  		if !(x.Uses == 1 && clobber(x)) {
  6732  			break
  6733  		}
  6734  		v.reset(Op386MOVWstoreidx1)
  6735  		v.AuxInt = i
  6736  		v.Aux = s
  6737  		v.AddArg(p)
  6738  		v.AddArg(idx)
  6739  		v.AddArg(w)
  6740  		v.AddArg(mem)
  6741  		return true
  6742  	}
  6743  	// match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRWconst [8] w) mem))
  6744  	// cond: x.Uses == 1 && clobber(x)
  6745  	// result: (MOVWstoreidx1 [i] {s} p idx w mem)
  6746  	for {
  6747  		i := v.AuxInt
  6748  		s := v.Aux
  6749  		_ = v.Args[3]
  6750  		p := v.Args[0]
  6751  		idx := v.Args[1]
  6752  		w := v.Args[2]
  6753  		x := v.Args[3]
  6754  		if x.Op != Op386MOVBstoreidx1 {
  6755  			break
  6756  		}
  6757  		if x.AuxInt != i+1 {
  6758  			break
  6759  		}
  6760  		if x.Aux != s {
  6761  			break
  6762  		}
  6763  		_ = x.Args[3]
  6764  		if p != x.Args[0] {
  6765  			break
  6766  		}
  6767  		if idx != x.Args[1] {
  6768  			break
  6769  		}
  6770  		x_2 := x.Args[2]
  6771  		if x_2.Op != Op386SHRWconst {
  6772  			break
  6773  		}
  6774  		if x_2.AuxInt != 8 {
  6775  			break
  6776  		}
  6777  		if w != x_2.Args[0] {
  6778  			break
  6779  		}
  6780  		mem := x.Args[3]
  6781  		if !(x.Uses == 1 && clobber(x)) {
  6782  			break
  6783  		}
  6784  		v.reset(Op386MOVWstoreidx1)
  6785  		v.AuxInt = i
  6786  		v.Aux = s
  6787  		v.AddArg(p)
  6788  		v.AddArg(idx)
  6789  		v.AddArg(w)
  6790  		v.AddArg(mem)
  6791  		return true
  6792  	}
  6793  	// match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRWconst [8] w) mem))
  6794  	// cond: x.Uses == 1 && clobber(x)
  6795  	// result: (MOVWstoreidx1 [i] {s} p idx w mem)
  6796  	for {
  6797  		i := v.AuxInt
  6798  		s := v.Aux
  6799  		_ = v.Args[3]
  6800  		p := v.Args[0]
  6801  		idx := v.Args[1]
  6802  		w := v.Args[2]
  6803  		x := v.Args[3]
  6804  		if x.Op != Op386MOVBstoreidx1 {
  6805  			break
  6806  		}
  6807  		if x.AuxInt != i+1 {
  6808  			break
  6809  		}
  6810  		if x.Aux != s {
  6811  			break
  6812  		}
  6813  		_ = x.Args[3]
  6814  		if idx != x.Args[0] {
  6815  			break
  6816  		}
  6817  		if p != x.Args[1] {
  6818  			break
  6819  		}
  6820  		x_2 := x.Args[2]
  6821  		if x_2.Op != Op386SHRWconst {
  6822  			break
  6823  		}
  6824  		if x_2.AuxInt != 8 {
  6825  			break
  6826  		}
  6827  		if w != x_2.Args[0] {
  6828  			break
  6829  		}
  6830  		mem := x.Args[3]
  6831  		if !(x.Uses == 1 && clobber(x)) {
  6832  			break
  6833  		}
  6834  		v.reset(Op386MOVWstoreidx1)
  6835  		v.AuxInt = i
  6836  		v.Aux = s
  6837  		v.AddArg(p)
  6838  		v.AddArg(idx)
  6839  		v.AddArg(w)
  6840  		v.AddArg(mem)
  6841  		return true
  6842  	}
  6843  	// match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRWconst [8] w) mem))
  6844  	// cond: x.Uses == 1 && clobber(x)
  6845  	// result: (MOVWstoreidx1 [i] {s} p idx w mem)
  6846  	for {
  6847  		i := v.AuxInt
  6848  		s := v.Aux
  6849  		_ = v.Args[3]
  6850  		idx := v.Args[0]
  6851  		p := v.Args[1]
  6852  		w := v.Args[2]
  6853  		x := v.Args[3]
  6854  		if x.Op != Op386MOVBstoreidx1 {
  6855  			break
  6856  		}
  6857  		if x.AuxInt != i+1 {
  6858  			break
  6859  		}
  6860  		if x.Aux != s {
  6861  			break
  6862  		}
  6863  		_ = x.Args[3]
  6864  		if p != x.Args[0] {
  6865  			break
  6866  		}
  6867  		if idx != x.Args[1] {
  6868  			break
  6869  		}
  6870  		x_2 := x.Args[2]
  6871  		if x_2.Op != Op386SHRWconst {
  6872  			break
  6873  		}
  6874  		if x_2.AuxInt != 8 {
  6875  			break
  6876  		}
  6877  		if w != x_2.Args[0] {
  6878  			break
  6879  		}
  6880  		mem := x.Args[3]
  6881  		if !(x.Uses == 1 && clobber(x)) {
  6882  			break
  6883  		}
  6884  		v.reset(Op386MOVWstoreidx1)
  6885  		v.AuxInt = i
  6886  		v.Aux = s
  6887  		v.AddArg(p)
  6888  		v.AddArg(idx)
  6889  		v.AddArg(w)
  6890  		v.AddArg(mem)
  6891  		return true
  6892  	}
  6893  	// match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRWconst [8] w) mem))
  6894  	// cond: x.Uses == 1 && clobber(x)
  6895  	// result: (MOVWstoreidx1 [i] {s} p idx w mem)
  6896  	for {
  6897  		i := v.AuxInt
  6898  		s := v.Aux
  6899  		_ = v.Args[3]
  6900  		idx := v.Args[0]
  6901  		p := v.Args[1]
  6902  		w := v.Args[2]
  6903  		x := v.Args[3]
  6904  		if x.Op != Op386MOVBstoreidx1 {
  6905  			break
  6906  		}
  6907  		if x.AuxInt != i+1 {
  6908  			break
  6909  		}
  6910  		if x.Aux != s {
  6911  			break
  6912  		}
  6913  		_ = x.Args[3]
  6914  		if idx != x.Args[0] {
  6915  			break
  6916  		}
  6917  		if p != x.Args[1] {
  6918  			break
  6919  		}
  6920  		x_2 := x.Args[2]
  6921  		if x_2.Op != Op386SHRWconst {
  6922  			break
  6923  		}
  6924  		if x_2.AuxInt != 8 {
  6925  			break
  6926  		}
  6927  		if w != x_2.Args[0] {
  6928  			break
  6929  		}
  6930  		mem := x.Args[3]
  6931  		if !(x.Uses == 1 && clobber(x)) {
  6932  			break
  6933  		}
  6934  		v.reset(Op386MOVWstoreidx1)
  6935  		v.AuxInt = i
  6936  		v.Aux = s
  6937  		v.AddArg(p)
  6938  		v.AddArg(idx)
  6939  		v.AddArg(w)
  6940  		v.AddArg(mem)
  6941  		return true
  6942  	}
  6943  	return false
  6944  }
  6945  func rewriteValue386_Op386MOVBstoreidx1_20(v *Value) bool {
  6946  	// match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem))
  6947  	// cond: x.Uses == 1 && clobber(x)
  6948  	// result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem)
  6949  	for {
  6950  		i := v.AuxInt
  6951  		s := v.Aux
  6952  		_ = v.Args[3]
  6953  		p := v.Args[0]
  6954  		idx := v.Args[1]
  6955  		v_2 := v.Args[2]
  6956  		if v_2.Op != Op386SHRLconst {
  6957  			break
  6958  		}
  6959  		j := v_2.AuxInt
  6960  		w := v_2.Args[0]
  6961  		x := v.Args[3]
  6962  		if x.Op != Op386MOVBstoreidx1 {
  6963  			break
  6964  		}
  6965  		if x.AuxInt != i-1 {
  6966  			break
  6967  		}
  6968  		if x.Aux != s {
  6969  			break
  6970  		}
  6971  		_ = x.Args[3]
  6972  		if p != x.Args[0] {
  6973  			break
  6974  		}
  6975  		if idx != x.Args[1] {
  6976  			break
  6977  		}
  6978  		w0 := x.Args[2]
  6979  		if w0.Op != Op386SHRLconst {
  6980  			break
  6981  		}
  6982  		if w0.AuxInt != j-8 {
  6983  			break
  6984  		}
  6985  		if w != w0.Args[0] {
  6986  			break
  6987  		}
  6988  		mem := x.Args[3]
  6989  		if !(x.Uses == 1 && clobber(x)) {
  6990  			break
  6991  		}
  6992  		v.reset(Op386MOVWstoreidx1)
  6993  		v.AuxInt = i - 1
  6994  		v.Aux = s
  6995  		v.AddArg(p)
  6996  		v.AddArg(idx)
  6997  		v.AddArg(w0)
  6998  		v.AddArg(mem)
  6999  		return true
  7000  	}
  7001  	// match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} idx p w0:(SHRLconst [j-8] w) mem))
  7002  	// cond: x.Uses == 1 && clobber(x)
  7003  	// result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem)
  7004  	for {
  7005  		i := v.AuxInt
  7006  		s := v.Aux
  7007  		_ = v.Args[3]
  7008  		p := v.Args[0]
  7009  		idx := v.Args[1]
  7010  		v_2 := v.Args[2]
  7011  		if v_2.Op != Op386SHRLconst {
  7012  			break
  7013  		}
  7014  		j := v_2.AuxInt
  7015  		w := v_2.Args[0]
  7016  		x := v.Args[3]
  7017  		if x.Op != Op386MOVBstoreidx1 {
  7018  			break
  7019  		}
  7020  		if x.AuxInt != i-1 {
  7021  			break
  7022  		}
  7023  		if x.Aux != s {
  7024  			break
  7025  		}
  7026  		_ = x.Args[3]
  7027  		if idx != x.Args[0] {
  7028  			break
  7029  		}
  7030  		if p != x.Args[1] {
  7031  			break
  7032  		}
  7033  		w0 := x.Args[2]
  7034  		if w0.Op != Op386SHRLconst {
  7035  			break
  7036  		}
  7037  		if w0.AuxInt != j-8 {
  7038  			break
  7039  		}
  7040  		if w != w0.Args[0] {
  7041  			break
  7042  		}
  7043  		mem := x.Args[3]
  7044  		if !(x.Uses == 1 && clobber(x)) {
  7045  			break
  7046  		}
  7047  		v.reset(Op386MOVWstoreidx1)
  7048  		v.AuxInt = i - 1
  7049  		v.Aux = s
  7050  		v.AddArg(p)
  7051  		v.AddArg(idx)
  7052  		v.AddArg(w0)
  7053  		v.AddArg(mem)
  7054  		return true
  7055  	}
  7056  	// match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem))
  7057  	// cond: x.Uses == 1 && clobber(x)
  7058  	// result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem)
  7059  	for {
  7060  		i := v.AuxInt
  7061  		s := v.Aux
  7062  		_ = v.Args[3]
  7063  		idx := v.Args[0]
  7064  		p := v.Args[1]
  7065  		v_2 := v.Args[2]
  7066  		if v_2.Op != Op386SHRLconst {
  7067  			break
  7068  		}
  7069  		j := v_2.AuxInt
  7070  		w := v_2.Args[0]
  7071  		x := v.Args[3]
  7072  		if x.Op != Op386MOVBstoreidx1 {
  7073  			break
  7074  		}
  7075  		if x.AuxInt != i-1 {
  7076  			break
  7077  		}
  7078  		if x.Aux != s {
  7079  			break
  7080  		}
  7081  		_ = x.Args[3]
  7082  		if p != x.Args[0] {
  7083  			break
  7084  		}
  7085  		if idx != x.Args[1] {
  7086  			break
  7087  		}
  7088  		w0 := x.Args[2]
  7089  		if w0.Op != Op386SHRLconst {
  7090  			break
  7091  		}
  7092  		if w0.AuxInt != j-8 {
  7093  			break
  7094  		}
  7095  		if w != w0.Args[0] {
  7096  			break
  7097  		}
  7098  		mem := x.Args[3]
  7099  		if !(x.Uses == 1 && clobber(x)) {
  7100  			break
  7101  		}
  7102  		v.reset(Op386MOVWstoreidx1)
  7103  		v.AuxInt = i - 1
  7104  		v.Aux = s
  7105  		v.AddArg(p)
  7106  		v.AddArg(idx)
  7107  		v.AddArg(w0)
  7108  		v.AddArg(mem)
  7109  		return true
  7110  	}
  7111  	// match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} idx p w0:(SHRLconst [j-8] w) mem))
  7112  	// cond: x.Uses == 1 && clobber(x)
  7113  	// result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem)
  7114  	for {
  7115  		i := v.AuxInt
  7116  		s := v.Aux
  7117  		_ = v.Args[3]
  7118  		idx := v.Args[0]
  7119  		p := v.Args[1]
  7120  		v_2 := v.Args[2]
  7121  		if v_2.Op != Op386SHRLconst {
  7122  			break
  7123  		}
  7124  		j := v_2.AuxInt
  7125  		w := v_2.Args[0]
  7126  		x := v.Args[3]
  7127  		if x.Op != Op386MOVBstoreidx1 {
  7128  			break
  7129  		}
  7130  		if x.AuxInt != i-1 {
  7131  			break
  7132  		}
  7133  		if x.Aux != s {
  7134  			break
  7135  		}
  7136  		_ = x.Args[3]
  7137  		if idx != x.Args[0] {
  7138  			break
  7139  		}
  7140  		if p != x.Args[1] {
  7141  			break
  7142  		}
  7143  		w0 := x.Args[2]
  7144  		if w0.Op != Op386SHRLconst {
  7145  			break
  7146  		}
  7147  		if w0.AuxInt != j-8 {
  7148  			break
  7149  		}
  7150  		if w != w0.Args[0] {
  7151  			break
  7152  		}
  7153  		mem := x.Args[3]
  7154  		if !(x.Uses == 1 && clobber(x)) {
  7155  			break
  7156  		}
  7157  		v.reset(Op386MOVWstoreidx1)
  7158  		v.AuxInt = i - 1
  7159  		v.Aux = s
  7160  		v.AddArg(p)
  7161  		v.AddArg(idx)
  7162  		v.AddArg(w0)
  7163  		v.AddArg(mem)
  7164  		return true
  7165  	}
  7166  	return false
  7167  }
  7168  func rewriteValue386_Op386MOVLload_0(v *Value) bool {
  7169  	b := v.Block
  7170  	_ = b
  7171  	config := b.Func.Config
  7172  	_ = config
  7173  	// match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _))
  7174  	// cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
  7175  	// result: x
  7176  	for {
  7177  		off := v.AuxInt
  7178  		sym := v.Aux
  7179  		_ = v.Args[1]
  7180  		ptr := v.Args[0]
  7181  		v_1 := v.Args[1]
  7182  		if v_1.Op != Op386MOVLstore {
  7183  			break
  7184  		}
  7185  		off2 := v_1.AuxInt
  7186  		sym2 := v_1.Aux
  7187  		_ = v_1.Args[2]
  7188  		ptr2 := v_1.Args[0]
  7189  		x := v_1.Args[1]
  7190  		if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
  7191  			break
  7192  		}
  7193  		v.reset(OpCopy)
  7194  		v.Type = x.Type
  7195  		v.AddArg(x)
  7196  		return true
  7197  	}
  7198  	// match: (MOVLload [off1] {sym} (ADDLconst [off2] ptr) mem)
  7199  	// cond: is32Bit(off1+off2)
  7200  	// result: (MOVLload [off1+off2] {sym} ptr mem)
  7201  	for {
  7202  		off1 := v.AuxInt
  7203  		sym := v.Aux
  7204  		_ = v.Args[1]
  7205  		v_0 := v.Args[0]
  7206  		if v_0.Op != Op386ADDLconst {
  7207  			break
  7208  		}
  7209  		off2 := v_0.AuxInt
  7210  		ptr := v_0.Args[0]
  7211  		mem := v.Args[1]
  7212  		if !(is32Bit(off1 + off2)) {
  7213  			break
  7214  		}
  7215  		v.reset(Op386MOVLload)
  7216  		v.AuxInt = off1 + off2
  7217  		v.Aux = sym
  7218  		v.AddArg(ptr)
  7219  		v.AddArg(mem)
  7220  		return true
  7221  	}
  7222  	// match: (MOVLload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
  7223  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  7224  	// result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem)
  7225  	for {
  7226  		off1 := v.AuxInt
  7227  		sym1 := v.Aux
  7228  		_ = v.Args[1]
  7229  		v_0 := v.Args[0]
  7230  		if v_0.Op != Op386LEAL {
  7231  			break
  7232  		}
  7233  		off2 := v_0.AuxInt
  7234  		sym2 := v_0.Aux
  7235  		base := v_0.Args[0]
  7236  		mem := v.Args[1]
  7237  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  7238  			break
  7239  		}
  7240  		v.reset(Op386MOVLload)
  7241  		v.AuxInt = off1 + off2
  7242  		v.Aux = mergeSym(sym1, sym2)
  7243  		v.AddArg(base)
  7244  		v.AddArg(mem)
  7245  		return true
  7246  	}
  7247  	// match: (MOVLload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem)
  7248  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  7249  	// result: (MOVLloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
  7250  	for {
  7251  		off1 := v.AuxInt
  7252  		sym1 := v.Aux
  7253  		_ = v.Args[1]
  7254  		v_0 := v.Args[0]
  7255  		if v_0.Op != Op386LEAL1 {
  7256  			break
  7257  		}
  7258  		off2 := v_0.AuxInt
  7259  		sym2 := v_0.Aux
  7260  		_ = v_0.Args[1]
  7261  		ptr := v_0.Args[0]
  7262  		idx := v_0.Args[1]
  7263  		mem := v.Args[1]
  7264  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  7265  			break
  7266  		}
  7267  		v.reset(Op386MOVLloadidx1)
  7268  		v.AuxInt = off1 + off2
  7269  		v.Aux = mergeSym(sym1, sym2)
  7270  		v.AddArg(ptr)
  7271  		v.AddArg(idx)
  7272  		v.AddArg(mem)
  7273  		return true
  7274  	}
  7275  	// match: (MOVLload [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) mem)
  7276  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  7277  	// result: (MOVLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
  7278  	for {
  7279  		off1 := v.AuxInt
  7280  		sym1 := v.Aux
  7281  		_ = v.Args[1]
  7282  		v_0 := v.Args[0]
  7283  		if v_0.Op != Op386LEAL4 {
  7284  			break
  7285  		}
  7286  		off2 := v_0.AuxInt
  7287  		sym2 := v_0.Aux
  7288  		_ = v_0.Args[1]
  7289  		ptr := v_0.Args[0]
  7290  		idx := v_0.Args[1]
  7291  		mem := v.Args[1]
  7292  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  7293  			break
  7294  		}
  7295  		v.reset(Op386MOVLloadidx4)
  7296  		v.AuxInt = off1 + off2
  7297  		v.Aux = mergeSym(sym1, sym2)
  7298  		v.AddArg(ptr)
  7299  		v.AddArg(idx)
  7300  		v.AddArg(mem)
  7301  		return true
  7302  	}
  7303  	// match: (MOVLload [off] {sym} (ADDL ptr idx) mem)
  7304  	// cond: ptr.Op != OpSB
  7305  	// result: (MOVLloadidx1 [off] {sym} ptr idx mem)
  7306  	for {
  7307  		off := v.AuxInt
  7308  		sym := v.Aux
  7309  		_ = v.Args[1]
  7310  		v_0 := v.Args[0]
  7311  		if v_0.Op != Op386ADDL {
  7312  			break
  7313  		}
  7314  		_ = v_0.Args[1]
  7315  		ptr := v_0.Args[0]
  7316  		idx := v_0.Args[1]
  7317  		mem := v.Args[1]
  7318  		if !(ptr.Op != OpSB) {
  7319  			break
  7320  		}
  7321  		v.reset(Op386MOVLloadidx1)
  7322  		v.AuxInt = off
  7323  		v.Aux = sym
  7324  		v.AddArg(ptr)
  7325  		v.AddArg(idx)
  7326  		v.AddArg(mem)
  7327  		return true
  7328  	}
  7329  	// match: (MOVLload [off] {sym} (SB) _)
  7330  	// cond: symIsRO(sym)
  7331  	// result: (MOVLconst [int64(int32(read32(sym, off, config.BigEndian)))])
  7332  	for {
  7333  		off := v.AuxInt
  7334  		sym := v.Aux
  7335  		_ = v.Args[1]
  7336  		v_0 := v.Args[0]
  7337  		if v_0.Op != OpSB {
  7338  			break
  7339  		}
  7340  		if !(symIsRO(sym)) {
  7341  			break
  7342  		}
  7343  		v.reset(Op386MOVLconst)
  7344  		v.AuxInt = int64(int32(read32(sym, off, config.BigEndian)))
  7345  		return true
  7346  	}
  7347  	return false
  7348  }
  7349  func rewriteValue386_Op386MOVLloadidx1_0(v *Value) bool {
  7350  	// match: (MOVLloadidx1 [c] {sym} ptr (SHLLconst [2] idx) mem)
  7351  	// cond:
  7352  	// result: (MOVLloadidx4 [c] {sym} ptr idx mem)
  7353  	for {
  7354  		c := v.AuxInt
  7355  		sym := v.Aux
  7356  		_ = v.Args[2]
  7357  		ptr := v.Args[0]
  7358  		v_1 := v.Args[1]
  7359  		if v_1.Op != Op386SHLLconst {
  7360  			break
  7361  		}
  7362  		if v_1.AuxInt != 2 {
  7363  			break
  7364  		}
  7365  		idx := v_1.Args[0]
  7366  		mem := v.Args[2]
  7367  		v.reset(Op386MOVLloadidx4)
  7368  		v.AuxInt = c
  7369  		v.Aux = sym
  7370  		v.AddArg(ptr)
  7371  		v.AddArg(idx)
  7372  		v.AddArg(mem)
  7373  		return true
  7374  	}
  7375  	// match: (MOVLloadidx1 [c] {sym} (SHLLconst [2] idx) ptr mem)
  7376  	// cond:
  7377  	// result: (MOVLloadidx4 [c] {sym} ptr idx mem)
  7378  	for {
  7379  		c := v.AuxInt
  7380  		sym := v.Aux
  7381  		_ = v.Args[2]
  7382  		v_0 := v.Args[0]
  7383  		if v_0.Op != Op386SHLLconst {
  7384  			break
  7385  		}
  7386  		if v_0.AuxInt != 2 {
  7387  			break
  7388  		}
  7389  		idx := v_0.Args[0]
  7390  		ptr := v.Args[1]
  7391  		mem := v.Args[2]
  7392  		v.reset(Op386MOVLloadidx4)
  7393  		v.AuxInt = c
  7394  		v.Aux = sym
  7395  		v.AddArg(ptr)
  7396  		v.AddArg(idx)
  7397  		v.AddArg(mem)
  7398  		return true
  7399  	}
  7400  	// match: (MOVLloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem)
  7401  	// cond:
  7402  	// result: (MOVLloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  7403  	for {
  7404  		c := v.AuxInt
  7405  		sym := v.Aux
  7406  		_ = v.Args[2]
  7407  		v_0 := v.Args[0]
  7408  		if v_0.Op != Op386ADDLconst {
  7409  			break
  7410  		}
  7411  		d := v_0.AuxInt
  7412  		ptr := v_0.Args[0]
  7413  		idx := v.Args[1]
  7414  		mem := v.Args[2]
  7415  		v.reset(Op386MOVLloadidx1)
  7416  		v.AuxInt = int64(int32(c + d))
  7417  		v.Aux = sym
  7418  		v.AddArg(ptr)
  7419  		v.AddArg(idx)
  7420  		v.AddArg(mem)
  7421  		return true
  7422  	}
  7423  	// match: (MOVLloadidx1 [c] {sym} idx (ADDLconst [d] ptr) mem)
  7424  	// cond:
  7425  	// result: (MOVLloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  7426  	for {
  7427  		c := v.AuxInt
  7428  		sym := v.Aux
  7429  		_ = v.Args[2]
  7430  		idx := v.Args[0]
  7431  		v_1 := v.Args[1]
  7432  		if v_1.Op != Op386ADDLconst {
  7433  			break
  7434  		}
  7435  		d := v_1.AuxInt
  7436  		ptr := v_1.Args[0]
  7437  		mem := v.Args[2]
  7438  		v.reset(Op386MOVLloadidx1)
  7439  		v.AuxInt = int64(int32(c + d))
  7440  		v.Aux = sym
  7441  		v.AddArg(ptr)
  7442  		v.AddArg(idx)
  7443  		v.AddArg(mem)
  7444  		return true
  7445  	}
  7446  	// match: (MOVLloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem)
  7447  	// cond:
  7448  	// result: (MOVLloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  7449  	for {
  7450  		c := v.AuxInt
  7451  		sym := v.Aux
  7452  		_ = v.Args[2]
  7453  		ptr := v.Args[0]
  7454  		v_1 := v.Args[1]
  7455  		if v_1.Op != Op386ADDLconst {
  7456  			break
  7457  		}
  7458  		d := v_1.AuxInt
  7459  		idx := v_1.Args[0]
  7460  		mem := v.Args[2]
  7461  		v.reset(Op386MOVLloadidx1)
  7462  		v.AuxInt = int64(int32(c + d))
  7463  		v.Aux = sym
  7464  		v.AddArg(ptr)
  7465  		v.AddArg(idx)
  7466  		v.AddArg(mem)
  7467  		return true
  7468  	}
  7469  	// match: (MOVLloadidx1 [c] {sym} (ADDLconst [d] idx) ptr mem)
  7470  	// cond:
  7471  	// result: (MOVLloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  7472  	for {
  7473  		c := v.AuxInt
  7474  		sym := v.Aux
  7475  		_ = v.Args[2]
  7476  		v_0 := v.Args[0]
  7477  		if v_0.Op != Op386ADDLconst {
  7478  			break
  7479  		}
  7480  		d := v_0.AuxInt
  7481  		idx := v_0.Args[0]
  7482  		ptr := v.Args[1]
  7483  		mem := v.Args[2]
  7484  		v.reset(Op386MOVLloadidx1)
  7485  		v.AuxInt = int64(int32(c + d))
  7486  		v.Aux = sym
  7487  		v.AddArg(ptr)
  7488  		v.AddArg(idx)
  7489  		v.AddArg(mem)
  7490  		return true
  7491  	}
  7492  	return false
  7493  }
  7494  func rewriteValue386_Op386MOVLloadidx4_0(v *Value) bool {
  7495  	// match: (MOVLloadidx4 [c] {sym} (ADDLconst [d] ptr) idx mem)
  7496  	// cond:
  7497  	// result: (MOVLloadidx4 [int64(int32(c+d))] {sym} ptr idx mem)
  7498  	for {
  7499  		c := v.AuxInt
  7500  		sym := v.Aux
  7501  		_ = v.Args[2]
  7502  		v_0 := v.Args[0]
  7503  		if v_0.Op != Op386ADDLconst {
  7504  			break
  7505  		}
  7506  		d := v_0.AuxInt
  7507  		ptr := v_0.Args[0]
  7508  		idx := v.Args[1]
  7509  		mem := v.Args[2]
  7510  		v.reset(Op386MOVLloadidx4)
  7511  		v.AuxInt = int64(int32(c + d))
  7512  		v.Aux = sym
  7513  		v.AddArg(ptr)
  7514  		v.AddArg(idx)
  7515  		v.AddArg(mem)
  7516  		return true
  7517  	}
  7518  	// match: (MOVLloadidx4 [c] {sym} ptr (ADDLconst [d] idx) mem)
  7519  	// cond:
  7520  	// result: (MOVLloadidx4 [int64(int32(c+4*d))] {sym} ptr idx mem)
  7521  	for {
  7522  		c := v.AuxInt
  7523  		sym := v.Aux
  7524  		_ = v.Args[2]
  7525  		ptr := v.Args[0]
  7526  		v_1 := v.Args[1]
  7527  		if v_1.Op != Op386ADDLconst {
  7528  			break
  7529  		}
  7530  		d := v_1.AuxInt
  7531  		idx := v_1.Args[0]
  7532  		mem := v.Args[2]
  7533  		v.reset(Op386MOVLloadidx4)
  7534  		v.AuxInt = int64(int32(c + 4*d))
  7535  		v.Aux = sym
  7536  		v.AddArg(ptr)
  7537  		v.AddArg(idx)
  7538  		v.AddArg(mem)
  7539  		return true
  7540  	}
  7541  	return false
  7542  }
  7543  func rewriteValue386_Op386MOVLstore_0(v *Value) bool {
  7544  	b := v.Block
  7545  	_ = b
  7546  	config := b.Func.Config
  7547  	_ = config
  7548  	// match: (MOVLstore [off1] {sym} (ADDLconst [off2] ptr) val mem)
  7549  	// cond: is32Bit(off1+off2)
  7550  	// result: (MOVLstore [off1+off2] {sym} ptr val mem)
  7551  	for {
  7552  		off1 := v.AuxInt
  7553  		sym := v.Aux
  7554  		_ = v.Args[2]
  7555  		v_0 := v.Args[0]
  7556  		if v_0.Op != Op386ADDLconst {
  7557  			break
  7558  		}
  7559  		off2 := v_0.AuxInt
  7560  		ptr := v_0.Args[0]
  7561  		val := v.Args[1]
  7562  		mem := v.Args[2]
  7563  		if !(is32Bit(off1 + off2)) {
  7564  			break
  7565  		}
  7566  		v.reset(Op386MOVLstore)
  7567  		v.AuxInt = off1 + off2
  7568  		v.Aux = sym
  7569  		v.AddArg(ptr)
  7570  		v.AddArg(val)
  7571  		v.AddArg(mem)
  7572  		return true
  7573  	}
  7574  	// match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem)
  7575  	// cond: validOff(off)
  7576  	// result: (MOVLstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem)
  7577  	for {
  7578  		off := v.AuxInt
  7579  		sym := v.Aux
  7580  		_ = v.Args[2]
  7581  		ptr := v.Args[0]
  7582  		v_1 := v.Args[1]
  7583  		if v_1.Op != Op386MOVLconst {
  7584  			break
  7585  		}
  7586  		c := v_1.AuxInt
  7587  		mem := v.Args[2]
  7588  		if !(validOff(off)) {
  7589  			break
  7590  		}
  7591  		v.reset(Op386MOVLstoreconst)
  7592  		v.AuxInt = makeValAndOff(int64(int32(c)), off)
  7593  		v.Aux = sym
  7594  		v.AddArg(ptr)
  7595  		v.AddArg(mem)
  7596  		return true
  7597  	}
  7598  	// match: (MOVLstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
  7599  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  7600  	// result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  7601  	for {
  7602  		off1 := v.AuxInt
  7603  		sym1 := v.Aux
  7604  		_ = v.Args[2]
  7605  		v_0 := v.Args[0]
  7606  		if v_0.Op != Op386LEAL {
  7607  			break
  7608  		}
  7609  		off2 := v_0.AuxInt
  7610  		sym2 := v_0.Aux
  7611  		base := v_0.Args[0]
  7612  		val := v.Args[1]
  7613  		mem := v.Args[2]
  7614  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  7615  			break
  7616  		}
  7617  		v.reset(Op386MOVLstore)
  7618  		v.AuxInt = off1 + off2
  7619  		v.Aux = mergeSym(sym1, sym2)
  7620  		v.AddArg(base)
  7621  		v.AddArg(val)
  7622  		v.AddArg(mem)
  7623  		return true
  7624  	}
  7625  	// match: (MOVLstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem)
  7626  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  7627  	// result: (MOVLstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
  7628  	for {
  7629  		off1 := v.AuxInt
  7630  		sym1 := v.Aux
  7631  		_ = v.Args[2]
  7632  		v_0 := v.Args[0]
  7633  		if v_0.Op != Op386LEAL1 {
  7634  			break
  7635  		}
  7636  		off2 := v_0.AuxInt
  7637  		sym2 := v_0.Aux
  7638  		_ = v_0.Args[1]
  7639  		ptr := v_0.Args[0]
  7640  		idx := v_0.Args[1]
  7641  		val := v.Args[1]
  7642  		mem := v.Args[2]
  7643  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  7644  			break
  7645  		}
  7646  		v.reset(Op386MOVLstoreidx1)
  7647  		v.AuxInt = off1 + off2
  7648  		v.Aux = mergeSym(sym1, sym2)
  7649  		v.AddArg(ptr)
  7650  		v.AddArg(idx)
  7651  		v.AddArg(val)
  7652  		v.AddArg(mem)
  7653  		return true
  7654  	}
  7655  	// match: (MOVLstore [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) val mem)
  7656  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  7657  	// result: (MOVLstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
  7658  	for {
  7659  		off1 := v.AuxInt
  7660  		sym1 := v.Aux
  7661  		_ = v.Args[2]
  7662  		v_0 := v.Args[0]
  7663  		if v_0.Op != Op386LEAL4 {
  7664  			break
  7665  		}
  7666  		off2 := v_0.AuxInt
  7667  		sym2 := v_0.Aux
  7668  		_ = v_0.Args[1]
  7669  		ptr := v_0.Args[0]
  7670  		idx := v_0.Args[1]
  7671  		val := v.Args[1]
  7672  		mem := v.Args[2]
  7673  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  7674  			break
  7675  		}
  7676  		v.reset(Op386MOVLstoreidx4)
  7677  		v.AuxInt = off1 + off2
  7678  		v.Aux = mergeSym(sym1, sym2)
  7679  		v.AddArg(ptr)
  7680  		v.AddArg(idx)
  7681  		v.AddArg(val)
  7682  		v.AddArg(mem)
  7683  		return true
  7684  	}
  7685  	// match: (MOVLstore [off] {sym} (ADDL ptr idx) val mem)
  7686  	// cond: ptr.Op != OpSB
  7687  	// result: (MOVLstoreidx1 [off] {sym} ptr idx val mem)
  7688  	for {
  7689  		off := v.AuxInt
  7690  		sym := v.Aux
  7691  		_ = v.Args[2]
  7692  		v_0 := v.Args[0]
  7693  		if v_0.Op != Op386ADDL {
  7694  			break
  7695  		}
  7696  		_ = v_0.Args[1]
  7697  		ptr := v_0.Args[0]
  7698  		idx := v_0.Args[1]
  7699  		val := v.Args[1]
  7700  		mem := v.Args[2]
  7701  		if !(ptr.Op != OpSB) {
  7702  			break
  7703  		}
  7704  		v.reset(Op386MOVLstoreidx1)
  7705  		v.AuxInt = off
  7706  		v.Aux = sym
  7707  		v.AddArg(ptr)
  7708  		v.AddArg(idx)
  7709  		v.AddArg(val)
  7710  		v.AddArg(mem)
  7711  		return true
  7712  	}
  7713  	// match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem)
  7714  	// cond: y.Uses==1 && clobber(y)
  7715  	// result: (ADDLmodify [off] {sym} ptr x mem)
  7716  	for {
  7717  		off := v.AuxInt
  7718  		sym := v.Aux
  7719  		_ = v.Args[2]
  7720  		ptr := v.Args[0]
  7721  		y := v.Args[1]
  7722  		if y.Op != Op386ADDLload {
  7723  			break
  7724  		}
  7725  		if y.AuxInt != off {
  7726  			break
  7727  		}
  7728  		if y.Aux != sym {
  7729  			break
  7730  		}
  7731  		_ = y.Args[2]
  7732  		x := y.Args[0]
  7733  		if ptr != y.Args[1] {
  7734  			break
  7735  		}
  7736  		mem := y.Args[2]
  7737  		if mem != v.Args[2] {
  7738  			break
  7739  		}
  7740  		if !(y.Uses == 1 && clobber(y)) {
  7741  			break
  7742  		}
  7743  		v.reset(Op386ADDLmodify)
  7744  		v.AuxInt = off
  7745  		v.Aux = sym
  7746  		v.AddArg(ptr)
  7747  		v.AddArg(x)
  7748  		v.AddArg(mem)
  7749  		return true
  7750  	}
  7751  	// match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem)
  7752  	// cond: y.Uses==1 && clobber(y)
  7753  	// result: (ANDLmodify [off] {sym} ptr x mem)
  7754  	for {
  7755  		off := v.AuxInt
  7756  		sym := v.Aux
  7757  		_ = v.Args[2]
  7758  		ptr := v.Args[0]
  7759  		y := v.Args[1]
  7760  		if y.Op != Op386ANDLload {
  7761  			break
  7762  		}
  7763  		if y.AuxInt != off {
  7764  			break
  7765  		}
  7766  		if y.Aux != sym {
  7767  			break
  7768  		}
  7769  		_ = y.Args[2]
  7770  		x := y.Args[0]
  7771  		if ptr != y.Args[1] {
  7772  			break
  7773  		}
  7774  		mem := y.Args[2]
  7775  		if mem != v.Args[2] {
  7776  			break
  7777  		}
  7778  		if !(y.Uses == 1 && clobber(y)) {
  7779  			break
  7780  		}
  7781  		v.reset(Op386ANDLmodify)
  7782  		v.AuxInt = off
  7783  		v.Aux = sym
  7784  		v.AddArg(ptr)
  7785  		v.AddArg(x)
  7786  		v.AddArg(mem)
  7787  		return true
  7788  	}
  7789  	// match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem)
  7790  	// cond: y.Uses==1 && clobber(y)
  7791  	// result: (ORLmodify [off] {sym} ptr x mem)
  7792  	for {
  7793  		off := v.AuxInt
  7794  		sym := v.Aux
  7795  		_ = v.Args[2]
  7796  		ptr := v.Args[0]
  7797  		y := v.Args[1]
  7798  		if y.Op != Op386ORLload {
  7799  			break
  7800  		}
  7801  		if y.AuxInt != off {
  7802  			break
  7803  		}
  7804  		if y.Aux != sym {
  7805  			break
  7806  		}
  7807  		_ = y.Args[2]
  7808  		x := y.Args[0]
  7809  		if ptr != y.Args[1] {
  7810  			break
  7811  		}
  7812  		mem := y.Args[2]
  7813  		if mem != v.Args[2] {
  7814  			break
  7815  		}
  7816  		if !(y.Uses == 1 && clobber(y)) {
  7817  			break
  7818  		}
  7819  		v.reset(Op386ORLmodify)
  7820  		v.AuxInt = off
  7821  		v.Aux = sym
  7822  		v.AddArg(ptr)
  7823  		v.AddArg(x)
  7824  		v.AddArg(mem)
  7825  		return true
  7826  	}
  7827  	// match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem)
  7828  	// cond: y.Uses==1 && clobber(y)
  7829  	// result: (XORLmodify [off] {sym} ptr x mem)
  7830  	for {
  7831  		off := v.AuxInt
  7832  		sym := v.Aux
  7833  		_ = v.Args[2]
  7834  		ptr := v.Args[0]
  7835  		y := v.Args[1]
  7836  		if y.Op != Op386XORLload {
  7837  			break
  7838  		}
  7839  		if y.AuxInt != off {
  7840  			break
  7841  		}
  7842  		if y.Aux != sym {
  7843  			break
  7844  		}
  7845  		_ = y.Args[2]
  7846  		x := y.Args[0]
  7847  		if ptr != y.Args[1] {
  7848  			break
  7849  		}
  7850  		mem := y.Args[2]
  7851  		if mem != v.Args[2] {
  7852  			break
  7853  		}
  7854  		if !(y.Uses == 1 && clobber(y)) {
  7855  			break
  7856  		}
  7857  		v.reset(Op386XORLmodify)
  7858  		v.AuxInt = off
  7859  		v.Aux = sym
  7860  		v.AddArg(ptr)
  7861  		v.AddArg(x)
  7862  		v.AddArg(mem)
  7863  		return true
  7864  	}
  7865  	return false
  7866  }
  7867  func rewriteValue386_Op386MOVLstore_10(v *Value) bool {
  7868  	// match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem)
  7869  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  7870  	// result: (ADDLmodify [off] {sym} ptr x mem)
  7871  	for {
  7872  		off := v.AuxInt
  7873  		sym := v.Aux
  7874  		_ = v.Args[2]
  7875  		ptr := v.Args[0]
  7876  		y := v.Args[1]
  7877  		if y.Op != Op386ADDL {
  7878  			break
  7879  		}
  7880  		_ = y.Args[1]
  7881  		l := y.Args[0]
  7882  		if l.Op != Op386MOVLload {
  7883  			break
  7884  		}
  7885  		if l.AuxInt != off {
  7886  			break
  7887  		}
  7888  		if l.Aux != sym {
  7889  			break
  7890  		}
  7891  		_ = l.Args[1]
  7892  		if ptr != l.Args[0] {
  7893  			break
  7894  		}
  7895  		mem := l.Args[1]
  7896  		x := y.Args[1]
  7897  		if mem != v.Args[2] {
  7898  			break
  7899  		}
  7900  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  7901  			break
  7902  		}
  7903  		v.reset(Op386ADDLmodify)
  7904  		v.AuxInt = off
  7905  		v.Aux = sym
  7906  		v.AddArg(ptr)
  7907  		v.AddArg(x)
  7908  		v.AddArg(mem)
  7909  		return true
  7910  	}
  7911  	// match: (MOVLstore {sym} [off] ptr y:(ADDL x l:(MOVLload [off] {sym} ptr mem)) mem)
  7912  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  7913  	// result: (ADDLmodify [off] {sym} ptr x mem)
  7914  	for {
  7915  		off := v.AuxInt
  7916  		sym := v.Aux
  7917  		_ = v.Args[2]
  7918  		ptr := v.Args[0]
  7919  		y := v.Args[1]
  7920  		if y.Op != Op386ADDL {
  7921  			break
  7922  		}
  7923  		_ = y.Args[1]
  7924  		x := y.Args[0]
  7925  		l := y.Args[1]
  7926  		if l.Op != Op386MOVLload {
  7927  			break
  7928  		}
  7929  		if l.AuxInt != off {
  7930  			break
  7931  		}
  7932  		if l.Aux != sym {
  7933  			break
  7934  		}
  7935  		_ = l.Args[1]
  7936  		if ptr != l.Args[0] {
  7937  			break
  7938  		}
  7939  		mem := l.Args[1]
  7940  		if mem != v.Args[2] {
  7941  			break
  7942  		}
  7943  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  7944  			break
  7945  		}
  7946  		v.reset(Op386ADDLmodify)
  7947  		v.AuxInt = off
  7948  		v.Aux = sym
  7949  		v.AddArg(ptr)
  7950  		v.AddArg(x)
  7951  		v.AddArg(mem)
  7952  		return true
  7953  	}
  7954  	// match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem)
  7955  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  7956  	// result: (SUBLmodify [off] {sym} ptr x mem)
  7957  	for {
  7958  		off := v.AuxInt
  7959  		sym := v.Aux
  7960  		_ = v.Args[2]
  7961  		ptr := v.Args[0]
  7962  		y := v.Args[1]
  7963  		if y.Op != Op386SUBL {
  7964  			break
  7965  		}
  7966  		_ = y.Args[1]
  7967  		l := y.Args[0]
  7968  		if l.Op != Op386MOVLload {
  7969  			break
  7970  		}
  7971  		if l.AuxInt != off {
  7972  			break
  7973  		}
  7974  		if l.Aux != sym {
  7975  			break
  7976  		}
  7977  		_ = l.Args[1]
  7978  		if ptr != l.Args[0] {
  7979  			break
  7980  		}
  7981  		mem := l.Args[1]
  7982  		x := y.Args[1]
  7983  		if mem != v.Args[2] {
  7984  			break
  7985  		}
  7986  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  7987  			break
  7988  		}
  7989  		v.reset(Op386SUBLmodify)
  7990  		v.AuxInt = off
  7991  		v.Aux = sym
  7992  		v.AddArg(ptr)
  7993  		v.AddArg(x)
  7994  		v.AddArg(mem)
  7995  		return true
  7996  	}
  7997  	// match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem)
  7998  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  7999  	// result: (ANDLmodify [off] {sym} ptr x mem)
  8000  	for {
  8001  		off := v.AuxInt
  8002  		sym := v.Aux
  8003  		_ = v.Args[2]
  8004  		ptr := v.Args[0]
  8005  		y := v.Args[1]
  8006  		if y.Op != Op386ANDL {
  8007  			break
  8008  		}
  8009  		_ = y.Args[1]
  8010  		l := y.Args[0]
  8011  		if l.Op != Op386MOVLload {
  8012  			break
  8013  		}
  8014  		if l.AuxInt != off {
  8015  			break
  8016  		}
  8017  		if l.Aux != sym {
  8018  			break
  8019  		}
  8020  		_ = l.Args[1]
  8021  		if ptr != l.Args[0] {
  8022  			break
  8023  		}
  8024  		mem := l.Args[1]
  8025  		x := y.Args[1]
  8026  		if mem != v.Args[2] {
  8027  			break
  8028  		}
  8029  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  8030  			break
  8031  		}
  8032  		v.reset(Op386ANDLmodify)
  8033  		v.AuxInt = off
  8034  		v.Aux = sym
  8035  		v.AddArg(ptr)
  8036  		v.AddArg(x)
  8037  		v.AddArg(mem)
  8038  		return true
  8039  	}
  8040  	// match: (MOVLstore {sym} [off] ptr y:(ANDL x l:(MOVLload [off] {sym} ptr mem)) mem)
  8041  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  8042  	// result: (ANDLmodify [off] {sym} ptr x mem)
  8043  	for {
  8044  		off := v.AuxInt
  8045  		sym := v.Aux
  8046  		_ = v.Args[2]
  8047  		ptr := v.Args[0]
  8048  		y := v.Args[1]
  8049  		if y.Op != Op386ANDL {
  8050  			break
  8051  		}
  8052  		_ = y.Args[1]
  8053  		x := y.Args[0]
  8054  		l := y.Args[1]
  8055  		if l.Op != Op386MOVLload {
  8056  			break
  8057  		}
  8058  		if l.AuxInt != off {
  8059  			break
  8060  		}
  8061  		if l.Aux != sym {
  8062  			break
  8063  		}
  8064  		_ = l.Args[1]
  8065  		if ptr != l.Args[0] {
  8066  			break
  8067  		}
  8068  		mem := l.Args[1]
  8069  		if mem != v.Args[2] {
  8070  			break
  8071  		}
  8072  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  8073  			break
  8074  		}
  8075  		v.reset(Op386ANDLmodify)
  8076  		v.AuxInt = off
  8077  		v.Aux = sym
  8078  		v.AddArg(ptr)
  8079  		v.AddArg(x)
  8080  		v.AddArg(mem)
  8081  		return true
  8082  	}
  8083  	// match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem)
  8084  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  8085  	// result: (ORLmodify [off] {sym} ptr x mem)
  8086  	for {
  8087  		off := v.AuxInt
  8088  		sym := v.Aux
  8089  		_ = v.Args[2]
  8090  		ptr := v.Args[0]
  8091  		y := v.Args[1]
  8092  		if y.Op != Op386ORL {
  8093  			break
  8094  		}
  8095  		_ = y.Args[1]
  8096  		l := y.Args[0]
  8097  		if l.Op != Op386MOVLload {
  8098  			break
  8099  		}
  8100  		if l.AuxInt != off {
  8101  			break
  8102  		}
  8103  		if l.Aux != sym {
  8104  			break
  8105  		}
  8106  		_ = l.Args[1]
  8107  		if ptr != l.Args[0] {
  8108  			break
  8109  		}
  8110  		mem := l.Args[1]
  8111  		x := y.Args[1]
  8112  		if mem != v.Args[2] {
  8113  			break
  8114  		}
  8115  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  8116  			break
  8117  		}
  8118  		v.reset(Op386ORLmodify)
  8119  		v.AuxInt = off
  8120  		v.Aux = sym
  8121  		v.AddArg(ptr)
  8122  		v.AddArg(x)
  8123  		v.AddArg(mem)
  8124  		return true
  8125  	}
  8126  	// match: (MOVLstore {sym} [off] ptr y:(ORL x l:(MOVLload [off] {sym} ptr mem)) mem)
  8127  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  8128  	// result: (ORLmodify [off] {sym} ptr x mem)
  8129  	for {
  8130  		off := v.AuxInt
  8131  		sym := v.Aux
  8132  		_ = v.Args[2]
  8133  		ptr := v.Args[0]
  8134  		y := v.Args[1]
  8135  		if y.Op != Op386ORL {
  8136  			break
  8137  		}
  8138  		_ = y.Args[1]
  8139  		x := y.Args[0]
  8140  		l := y.Args[1]
  8141  		if l.Op != Op386MOVLload {
  8142  			break
  8143  		}
  8144  		if l.AuxInt != off {
  8145  			break
  8146  		}
  8147  		if l.Aux != sym {
  8148  			break
  8149  		}
  8150  		_ = l.Args[1]
  8151  		if ptr != l.Args[0] {
  8152  			break
  8153  		}
  8154  		mem := l.Args[1]
  8155  		if mem != v.Args[2] {
  8156  			break
  8157  		}
  8158  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  8159  			break
  8160  		}
  8161  		v.reset(Op386ORLmodify)
  8162  		v.AuxInt = off
  8163  		v.Aux = sym
  8164  		v.AddArg(ptr)
  8165  		v.AddArg(x)
  8166  		v.AddArg(mem)
  8167  		return true
  8168  	}
  8169  	// match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem)
  8170  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  8171  	// result: (XORLmodify [off] {sym} ptr x mem)
  8172  	for {
  8173  		off := v.AuxInt
  8174  		sym := v.Aux
  8175  		_ = v.Args[2]
  8176  		ptr := v.Args[0]
  8177  		y := v.Args[1]
  8178  		if y.Op != Op386XORL {
  8179  			break
  8180  		}
  8181  		_ = y.Args[1]
  8182  		l := y.Args[0]
  8183  		if l.Op != Op386MOVLload {
  8184  			break
  8185  		}
  8186  		if l.AuxInt != off {
  8187  			break
  8188  		}
  8189  		if l.Aux != sym {
  8190  			break
  8191  		}
  8192  		_ = l.Args[1]
  8193  		if ptr != l.Args[0] {
  8194  			break
  8195  		}
  8196  		mem := l.Args[1]
  8197  		x := y.Args[1]
  8198  		if mem != v.Args[2] {
  8199  			break
  8200  		}
  8201  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  8202  			break
  8203  		}
  8204  		v.reset(Op386XORLmodify)
  8205  		v.AuxInt = off
  8206  		v.Aux = sym
  8207  		v.AddArg(ptr)
  8208  		v.AddArg(x)
  8209  		v.AddArg(mem)
  8210  		return true
  8211  	}
  8212  	// match: (MOVLstore {sym} [off] ptr y:(XORL x l:(MOVLload [off] {sym} ptr mem)) mem)
  8213  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  8214  	// result: (XORLmodify [off] {sym} ptr x mem)
  8215  	for {
  8216  		off := v.AuxInt
  8217  		sym := v.Aux
  8218  		_ = v.Args[2]
  8219  		ptr := v.Args[0]
  8220  		y := v.Args[1]
  8221  		if y.Op != Op386XORL {
  8222  			break
  8223  		}
  8224  		_ = y.Args[1]
  8225  		x := y.Args[0]
  8226  		l := y.Args[1]
  8227  		if l.Op != Op386MOVLload {
  8228  			break
  8229  		}
  8230  		if l.AuxInt != off {
  8231  			break
  8232  		}
  8233  		if l.Aux != sym {
  8234  			break
  8235  		}
  8236  		_ = l.Args[1]
  8237  		if ptr != l.Args[0] {
  8238  			break
  8239  		}
  8240  		mem := l.Args[1]
  8241  		if mem != v.Args[2] {
  8242  			break
  8243  		}
  8244  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  8245  			break
  8246  		}
  8247  		v.reset(Op386XORLmodify)
  8248  		v.AuxInt = off
  8249  		v.Aux = sym
  8250  		v.AddArg(ptr)
  8251  		v.AddArg(x)
  8252  		v.AddArg(mem)
  8253  		return true
  8254  	}
  8255  	// match: (MOVLstore {sym} [off] ptr y:(ADDLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem)
  8256  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off)
  8257  	// result: (ADDLconstmodify [makeValAndOff(c,off)] {sym} ptr mem)
  8258  	for {
  8259  		off := v.AuxInt
  8260  		sym := v.Aux
  8261  		_ = v.Args[2]
  8262  		ptr := v.Args[0]
  8263  		y := v.Args[1]
  8264  		if y.Op != Op386ADDLconst {
  8265  			break
  8266  		}
  8267  		c := y.AuxInt
  8268  		l := y.Args[0]
  8269  		if l.Op != Op386MOVLload {
  8270  			break
  8271  		}
  8272  		if l.AuxInt != off {
  8273  			break
  8274  		}
  8275  		if l.Aux != sym {
  8276  			break
  8277  		}
  8278  		_ = l.Args[1]
  8279  		if ptr != l.Args[0] {
  8280  			break
  8281  		}
  8282  		mem := l.Args[1]
  8283  		if mem != v.Args[2] {
  8284  			break
  8285  		}
  8286  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) {
  8287  			break
  8288  		}
  8289  		v.reset(Op386ADDLconstmodify)
  8290  		v.AuxInt = makeValAndOff(c, off)
  8291  		v.Aux = sym
  8292  		v.AddArg(ptr)
  8293  		v.AddArg(mem)
  8294  		return true
  8295  	}
  8296  	return false
  8297  }
  8298  func rewriteValue386_Op386MOVLstore_20(v *Value) bool {
  8299  	// match: (MOVLstore {sym} [off] ptr y:(ANDLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem)
  8300  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off)
  8301  	// result: (ANDLconstmodify [makeValAndOff(c,off)] {sym} ptr mem)
  8302  	for {
  8303  		off := v.AuxInt
  8304  		sym := v.Aux
  8305  		_ = v.Args[2]
  8306  		ptr := v.Args[0]
  8307  		y := v.Args[1]
  8308  		if y.Op != Op386ANDLconst {
  8309  			break
  8310  		}
  8311  		c := y.AuxInt
  8312  		l := y.Args[0]
  8313  		if l.Op != Op386MOVLload {
  8314  			break
  8315  		}
  8316  		if l.AuxInt != off {
  8317  			break
  8318  		}
  8319  		if l.Aux != sym {
  8320  			break
  8321  		}
  8322  		_ = l.Args[1]
  8323  		if ptr != l.Args[0] {
  8324  			break
  8325  		}
  8326  		mem := l.Args[1]
  8327  		if mem != v.Args[2] {
  8328  			break
  8329  		}
  8330  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) {
  8331  			break
  8332  		}
  8333  		v.reset(Op386ANDLconstmodify)
  8334  		v.AuxInt = makeValAndOff(c, off)
  8335  		v.Aux = sym
  8336  		v.AddArg(ptr)
  8337  		v.AddArg(mem)
  8338  		return true
  8339  	}
  8340  	// match: (MOVLstore {sym} [off] ptr y:(ORLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem)
  8341  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off)
  8342  	// result: (ORLconstmodify [makeValAndOff(c,off)] {sym} ptr mem)
  8343  	for {
  8344  		off := v.AuxInt
  8345  		sym := v.Aux
  8346  		_ = v.Args[2]
  8347  		ptr := v.Args[0]
  8348  		y := v.Args[1]
  8349  		if y.Op != Op386ORLconst {
  8350  			break
  8351  		}
  8352  		c := y.AuxInt
  8353  		l := y.Args[0]
  8354  		if l.Op != Op386MOVLload {
  8355  			break
  8356  		}
  8357  		if l.AuxInt != off {
  8358  			break
  8359  		}
  8360  		if l.Aux != sym {
  8361  			break
  8362  		}
  8363  		_ = l.Args[1]
  8364  		if ptr != l.Args[0] {
  8365  			break
  8366  		}
  8367  		mem := l.Args[1]
  8368  		if mem != v.Args[2] {
  8369  			break
  8370  		}
  8371  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) {
  8372  			break
  8373  		}
  8374  		v.reset(Op386ORLconstmodify)
  8375  		v.AuxInt = makeValAndOff(c, off)
  8376  		v.Aux = sym
  8377  		v.AddArg(ptr)
  8378  		v.AddArg(mem)
  8379  		return true
  8380  	}
  8381  	// match: (MOVLstore {sym} [off] ptr y:(XORLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem)
  8382  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off)
  8383  	// result: (XORLconstmodify [makeValAndOff(c,off)] {sym} ptr mem)
  8384  	for {
  8385  		off := v.AuxInt
  8386  		sym := v.Aux
  8387  		_ = v.Args[2]
  8388  		ptr := v.Args[0]
  8389  		y := v.Args[1]
  8390  		if y.Op != Op386XORLconst {
  8391  			break
  8392  		}
  8393  		c := y.AuxInt
  8394  		l := y.Args[0]
  8395  		if l.Op != Op386MOVLload {
  8396  			break
  8397  		}
  8398  		if l.AuxInt != off {
  8399  			break
  8400  		}
  8401  		if l.Aux != sym {
  8402  			break
  8403  		}
  8404  		_ = l.Args[1]
  8405  		if ptr != l.Args[0] {
  8406  			break
  8407  		}
  8408  		mem := l.Args[1]
  8409  		if mem != v.Args[2] {
  8410  			break
  8411  		}
  8412  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) {
  8413  			break
  8414  		}
  8415  		v.reset(Op386XORLconstmodify)
  8416  		v.AuxInt = makeValAndOff(c, off)
  8417  		v.Aux = sym
  8418  		v.AddArg(ptr)
  8419  		v.AddArg(mem)
  8420  		return true
  8421  	}
  8422  	return false
  8423  }
  8424  func rewriteValue386_Op386MOVLstoreconst_0(v *Value) bool {
  8425  	b := v.Block
  8426  	_ = b
  8427  	config := b.Func.Config
  8428  	_ = config
  8429  	// match: (MOVLstoreconst [sc] {s} (ADDLconst [off] ptr) mem)
  8430  	// cond: ValAndOff(sc).canAdd(off)
  8431  	// result: (MOVLstoreconst [ValAndOff(sc).add(off)] {s} ptr mem)
  8432  	for {
  8433  		sc := v.AuxInt
  8434  		s := v.Aux
  8435  		_ = v.Args[1]
  8436  		v_0 := v.Args[0]
  8437  		if v_0.Op != Op386ADDLconst {
  8438  			break
  8439  		}
  8440  		off := v_0.AuxInt
  8441  		ptr := v_0.Args[0]
  8442  		mem := v.Args[1]
  8443  		if !(ValAndOff(sc).canAdd(off)) {
  8444  			break
  8445  		}
  8446  		v.reset(Op386MOVLstoreconst)
  8447  		v.AuxInt = ValAndOff(sc).add(off)
  8448  		v.Aux = s
  8449  		v.AddArg(ptr)
  8450  		v.AddArg(mem)
  8451  		return true
  8452  	}
  8453  	// match: (MOVLstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem)
  8454  	// cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
  8455  	// result: (MOVLstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem)
  8456  	for {
  8457  		sc := v.AuxInt
  8458  		sym1 := v.Aux
  8459  		_ = v.Args[1]
  8460  		v_0 := v.Args[0]
  8461  		if v_0.Op != Op386LEAL {
  8462  			break
  8463  		}
  8464  		off := v_0.AuxInt
  8465  		sym2 := v_0.Aux
  8466  		ptr := v_0.Args[0]
  8467  		mem := v.Args[1]
  8468  		if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
  8469  			break
  8470  		}
  8471  		v.reset(Op386MOVLstoreconst)
  8472  		v.AuxInt = ValAndOff(sc).add(off)
  8473  		v.Aux = mergeSym(sym1, sym2)
  8474  		v.AddArg(ptr)
  8475  		v.AddArg(mem)
  8476  		return true
  8477  	}
  8478  	// match: (MOVLstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem)
  8479  	// cond: canMergeSym(sym1, sym2)
  8480  	// result: (MOVLstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem)
  8481  	for {
  8482  		x := v.AuxInt
  8483  		sym1 := v.Aux
  8484  		_ = v.Args[1]
  8485  		v_0 := v.Args[0]
  8486  		if v_0.Op != Op386LEAL1 {
  8487  			break
  8488  		}
  8489  		off := v_0.AuxInt
  8490  		sym2 := v_0.Aux
  8491  		_ = v_0.Args[1]
  8492  		ptr := v_0.Args[0]
  8493  		idx := v_0.Args[1]
  8494  		mem := v.Args[1]
  8495  		if !(canMergeSym(sym1, sym2)) {
  8496  			break
  8497  		}
  8498  		v.reset(Op386MOVLstoreconstidx1)
  8499  		v.AuxInt = ValAndOff(x).add(off)
  8500  		v.Aux = mergeSym(sym1, sym2)
  8501  		v.AddArg(ptr)
  8502  		v.AddArg(idx)
  8503  		v.AddArg(mem)
  8504  		return true
  8505  	}
  8506  	// match: (MOVLstoreconst [x] {sym1} (LEAL4 [off] {sym2} ptr idx) mem)
  8507  	// cond: canMergeSym(sym1, sym2)
  8508  	// result: (MOVLstoreconstidx4 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem)
  8509  	for {
  8510  		x := v.AuxInt
  8511  		sym1 := v.Aux
  8512  		_ = v.Args[1]
  8513  		v_0 := v.Args[0]
  8514  		if v_0.Op != Op386LEAL4 {
  8515  			break
  8516  		}
  8517  		off := v_0.AuxInt
  8518  		sym2 := v_0.Aux
  8519  		_ = v_0.Args[1]
  8520  		ptr := v_0.Args[0]
  8521  		idx := v_0.Args[1]
  8522  		mem := v.Args[1]
  8523  		if !(canMergeSym(sym1, sym2)) {
  8524  			break
  8525  		}
  8526  		v.reset(Op386MOVLstoreconstidx4)
  8527  		v.AuxInt = ValAndOff(x).add(off)
  8528  		v.Aux = mergeSym(sym1, sym2)
  8529  		v.AddArg(ptr)
  8530  		v.AddArg(idx)
  8531  		v.AddArg(mem)
  8532  		return true
  8533  	}
  8534  	// match: (MOVLstoreconst [x] {sym} (ADDL ptr idx) mem)
  8535  	// cond:
  8536  	// result: (MOVLstoreconstidx1 [x] {sym} ptr idx mem)
  8537  	for {
  8538  		x := v.AuxInt
  8539  		sym := v.Aux
  8540  		_ = v.Args[1]
  8541  		v_0 := v.Args[0]
  8542  		if v_0.Op != Op386ADDL {
  8543  			break
  8544  		}
  8545  		_ = v_0.Args[1]
  8546  		ptr := v_0.Args[0]
  8547  		idx := v_0.Args[1]
  8548  		mem := v.Args[1]
  8549  		v.reset(Op386MOVLstoreconstidx1)
  8550  		v.AuxInt = x
  8551  		v.Aux = sym
  8552  		v.AddArg(ptr)
  8553  		v.AddArg(idx)
  8554  		v.AddArg(mem)
  8555  		return true
  8556  	}
  8557  	return false
  8558  }
  8559  func rewriteValue386_Op386MOVLstoreconstidx1_0(v *Value) bool {
  8560  	// match: (MOVLstoreconstidx1 [c] {sym} ptr (SHLLconst [2] idx) mem)
  8561  	// cond:
  8562  	// result: (MOVLstoreconstidx4 [c] {sym} ptr idx mem)
  8563  	for {
  8564  		c := v.AuxInt
  8565  		sym := v.Aux
  8566  		_ = v.Args[2]
  8567  		ptr := v.Args[0]
  8568  		v_1 := v.Args[1]
  8569  		if v_1.Op != Op386SHLLconst {
  8570  			break
  8571  		}
  8572  		if v_1.AuxInt != 2 {
  8573  			break
  8574  		}
  8575  		idx := v_1.Args[0]
  8576  		mem := v.Args[2]
  8577  		v.reset(Op386MOVLstoreconstidx4)
  8578  		v.AuxInt = c
  8579  		v.Aux = sym
  8580  		v.AddArg(ptr)
  8581  		v.AddArg(idx)
  8582  		v.AddArg(mem)
  8583  		return true
  8584  	}
  8585  	// match: (MOVLstoreconstidx1 [x] {sym} (ADDLconst [c] ptr) idx mem)
  8586  	// cond:
  8587  	// result: (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem)
  8588  	for {
  8589  		x := v.AuxInt
  8590  		sym := v.Aux
  8591  		_ = v.Args[2]
  8592  		v_0 := v.Args[0]
  8593  		if v_0.Op != Op386ADDLconst {
  8594  			break
  8595  		}
  8596  		c := v_0.AuxInt
  8597  		ptr := v_0.Args[0]
  8598  		idx := v.Args[1]
  8599  		mem := v.Args[2]
  8600  		v.reset(Op386MOVLstoreconstidx1)
  8601  		v.AuxInt = ValAndOff(x).add(c)
  8602  		v.Aux = sym
  8603  		v.AddArg(ptr)
  8604  		v.AddArg(idx)
  8605  		v.AddArg(mem)
  8606  		return true
  8607  	}
  8608  	// match: (MOVLstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem)
  8609  	// cond:
  8610  	// result: (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem)
  8611  	for {
  8612  		x := v.AuxInt
  8613  		sym := v.Aux
  8614  		_ = v.Args[2]
  8615  		ptr := v.Args[0]
  8616  		v_1 := v.Args[1]
  8617  		if v_1.Op != Op386ADDLconst {
  8618  			break
  8619  		}
  8620  		c := v_1.AuxInt
  8621  		idx := v_1.Args[0]
  8622  		mem := v.Args[2]
  8623  		v.reset(Op386MOVLstoreconstidx1)
  8624  		v.AuxInt = ValAndOff(x).add(c)
  8625  		v.Aux = sym
  8626  		v.AddArg(ptr)
  8627  		v.AddArg(idx)
  8628  		v.AddArg(mem)
  8629  		return true
  8630  	}
  8631  	return false
  8632  }
  8633  func rewriteValue386_Op386MOVLstoreconstidx4_0(v *Value) bool {
  8634  	// match: (MOVLstoreconstidx4 [x] {sym} (ADDLconst [c] ptr) idx mem)
  8635  	// cond:
  8636  	// result: (MOVLstoreconstidx4 [ValAndOff(x).add(c)] {sym} ptr idx mem)
  8637  	for {
  8638  		x := v.AuxInt
  8639  		sym := v.Aux
  8640  		_ = v.Args[2]
  8641  		v_0 := v.Args[0]
  8642  		if v_0.Op != Op386ADDLconst {
  8643  			break
  8644  		}
  8645  		c := v_0.AuxInt
  8646  		ptr := v_0.Args[0]
  8647  		idx := v.Args[1]
  8648  		mem := v.Args[2]
  8649  		v.reset(Op386MOVLstoreconstidx4)
  8650  		v.AuxInt = ValAndOff(x).add(c)
  8651  		v.Aux = sym
  8652  		v.AddArg(ptr)
  8653  		v.AddArg(idx)
  8654  		v.AddArg(mem)
  8655  		return true
  8656  	}
  8657  	// match: (MOVLstoreconstidx4 [x] {sym} ptr (ADDLconst [c] idx) mem)
  8658  	// cond:
  8659  	// result: (MOVLstoreconstidx4 [ValAndOff(x).add(4*c)] {sym} ptr idx mem)
  8660  	for {
  8661  		x := v.AuxInt
  8662  		sym := v.Aux
  8663  		_ = v.Args[2]
  8664  		ptr := v.Args[0]
  8665  		v_1 := v.Args[1]
  8666  		if v_1.Op != Op386ADDLconst {
  8667  			break
  8668  		}
  8669  		c := v_1.AuxInt
  8670  		idx := v_1.Args[0]
  8671  		mem := v.Args[2]
  8672  		v.reset(Op386MOVLstoreconstidx4)
  8673  		v.AuxInt = ValAndOff(x).add(4 * c)
  8674  		v.Aux = sym
  8675  		v.AddArg(ptr)
  8676  		v.AddArg(idx)
  8677  		v.AddArg(mem)
  8678  		return true
  8679  	}
  8680  	return false
  8681  }
  8682  func rewriteValue386_Op386MOVLstoreidx1_0(v *Value) bool {
  8683  	// match: (MOVLstoreidx1 [c] {sym} ptr (SHLLconst [2] idx) val mem)
  8684  	// cond:
  8685  	// result: (MOVLstoreidx4 [c] {sym} ptr idx val mem)
  8686  	for {
  8687  		c := v.AuxInt
  8688  		sym := v.Aux
  8689  		_ = v.Args[3]
  8690  		ptr := v.Args[0]
  8691  		v_1 := v.Args[1]
  8692  		if v_1.Op != Op386SHLLconst {
  8693  			break
  8694  		}
  8695  		if v_1.AuxInt != 2 {
  8696  			break
  8697  		}
  8698  		idx := v_1.Args[0]
  8699  		val := v.Args[2]
  8700  		mem := v.Args[3]
  8701  		v.reset(Op386MOVLstoreidx4)
  8702  		v.AuxInt = c
  8703  		v.Aux = sym
  8704  		v.AddArg(ptr)
  8705  		v.AddArg(idx)
  8706  		v.AddArg(val)
  8707  		v.AddArg(mem)
  8708  		return true
  8709  	}
  8710  	// match: (MOVLstoreidx1 [c] {sym} (SHLLconst [2] idx) ptr val mem)
  8711  	// cond:
  8712  	// result: (MOVLstoreidx4 [c] {sym} ptr idx val mem)
  8713  	for {
  8714  		c := v.AuxInt
  8715  		sym := v.Aux
  8716  		_ = v.Args[3]
  8717  		v_0 := v.Args[0]
  8718  		if v_0.Op != Op386SHLLconst {
  8719  			break
  8720  		}
  8721  		if v_0.AuxInt != 2 {
  8722  			break
  8723  		}
  8724  		idx := v_0.Args[0]
  8725  		ptr := v.Args[1]
  8726  		val := v.Args[2]
  8727  		mem := v.Args[3]
  8728  		v.reset(Op386MOVLstoreidx4)
  8729  		v.AuxInt = c
  8730  		v.Aux = sym
  8731  		v.AddArg(ptr)
  8732  		v.AddArg(idx)
  8733  		v.AddArg(val)
  8734  		v.AddArg(mem)
  8735  		return true
  8736  	}
  8737  	// match: (MOVLstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem)
  8738  	// cond:
  8739  	// result: (MOVLstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  8740  	for {
  8741  		c := v.AuxInt
  8742  		sym := v.Aux
  8743  		_ = v.Args[3]
  8744  		v_0 := v.Args[0]
  8745  		if v_0.Op != Op386ADDLconst {
  8746  			break
  8747  		}
  8748  		d := v_0.AuxInt
  8749  		ptr := v_0.Args[0]
  8750  		idx := v.Args[1]
  8751  		val := v.Args[2]
  8752  		mem := v.Args[3]
  8753  		v.reset(Op386MOVLstoreidx1)
  8754  		v.AuxInt = int64(int32(c + d))
  8755  		v.Aux = sym
  8756  		v.AddArg(ptr)
  8757  		v.AddArg(idx)
  8758  		v.AddArg(val)
  8759  		v.AddArg(mem)
  8760  		return true
  8761  	}
  8762  	// match: (MOVLstoreidx1 [c] {sym} idx (ADDLconst [d] ptr) val mem)
  8763  	// cond:
  8764  	// result: (MOVLstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  8765  	for {
  8766  		c := v.AuxInt
  8767  		sym := v.Aux
  8768  		_ = v.Args[3]
  8769  		idx := v.Args[0]
  8770  		v_1 := v.Args[1]
  8771  		if v_1.Op != Op386ADDLconst {
  8772  			break
  8773  		}
  8774  		d := v_1.AuxInt
  8775  		ptr := v_1.Args[0]
  8776  		val := v.Args[2]
  8777  		mem := v.Args[3]
  8778  		v.reset(Op386MOVLstoreidx1)
  8779  		v.AuxInt = int64(int32(c + d))
  8780  		v.Aux = sym
  8781  		v.AddArg(ptr)
  8782  		v.AddArg(idx)
  8783  		v.AddArg(val)
  8784  		v.AddArg(mem)
  8785  		return true
  8786  	}
  8787  	// match: (MOVLstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem)
  8788  	// cond:
  8789  	// result: (MOVLstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  8790  	for {
  8791  		c := v.AuxInt
  8792  		sym := v.Aux
  8793  		_ = v.Args[3]
  8794  		ptr := v.Args[0]
  8795  		v_1 := v.Args[1]
  8796  		if v_1.Op != Op386ADDLconst {
  8797  			break
  8798  		}
  8799  		d := v_1.AuxInt
  8800  		idx := v_1.Args[0]
  8801  		val := v.Args[2]
  8802  		mem := v.Args[3]
  8803  		v.reset(Op386MOVLstoreidx1)
  8804  		v.AuxInt = int64(int32(c + d))
  8805  		v.Aux = sym
  8806  		v.AddArg(ptr)
  8807  		v.AddArg(idx)
  8808  		v.AddArg(val)
  8809  		v.AddArg(mem)
  8810  		return true
  8811  	}
  8812  	// match: (MOVLstoreidx1 [c] {sym} (ADDLconst [d] idx) ptr val mem)
  8813  	// cond:
  8814  	// result: (MOVLstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
  8815  	for {
  8816  		c := v.AuxInt
  8817  		sym := v.Aux
  8818  		_ = v.Args[3]
  8819  		v_0 := v.Args[0]
  8820  		if v_0.Op != Op386ADDLconst {
  8821  			break
  8822  		}
  8823  		d := v_0.AuxInt
  8824  		idx := v_0.Args[0]
  8825  		ptr := v.Args[1]
  8826  		val := v.Args[2]
  8827  		mem := v.Args[3]
  8828  		v.reset(Op386MOVLstoreidx1)
  8829  		v.AuxInt = int64(int32(c + d))
  8830  		v.Aux = sym
  8831  		v.AddArg(ptr)
  8832  		v.AddArg(idx)
  8833  		v.AddArg(val)
  8834  		v.AddArg(mem)
  8835  		return true
  8836  	}
  8837  	return false
  8838  }
  8839  func rewriteValue386_Op386MOVLstoreidx4_0(v *Value) bool {
  8840  	// match: (MOVLstoreidx4 [c] {sym} (ADDLconst [d] ptr) idx val mem)
  8841  	// cond:
  8842  	// result: (MOVLstoreidx4 [int64(int32(c+d))] {sym} ptr idx val mem)
  8843  	for {
  8844  		c := v.AuxInt
  8845  		sym := v.Aux
  8846  		_ = v.Args[3]
  8847  		v_0 := v.Args[0]
  8848  		if v_0.Op != Op386ADDLconst {
  8849  			break
  8850  		}
  8851  		d := v_0.AuxInt
  8852  		ptr := v_0.Args[0]
  8853  		idx := v.Args[1]
  8854  		val := v.Args[2]
  8855  		mem := v.Args[3]
  8856  		v.reset(Op386MOVLstoreidx4)
  8857  		v.AuxInt = int64(int32(c + d))
  8858  		v.Aux = sym
  8859  		v.AddArg(ptr)
  8860  		v.AddArg(idx)
  8861  		v.AddArg(val)
  8862  		v.AddArg(mem)
  8863  		return true
  8864  	}
  8865  	// match: (MOVLstoreidx4 [c] {sym} ptr (ADDLconst [d] idx) val mem)
  8866  	// cond:
  8867  	// result: (MOVLstoreidx4 [int64(int32(c+4*d))] {sym} ptr idx val mem)
  8868  	for {
  8869  		c := v.AuxInt
  8870  		sym := v.Aux
  8871  		_ = v.Args[3]
  8872  		ptr := v.Args[0]
  8873  		v_1 := v.Args[1]
  8874  		if v_1.Op != Op386ADDLconst {
  8875  			break
  8876  		}
  8877  		d := v_1.AuxInt
  8878  		idx := v_1.Args[0]
  8879  		val := v.Args[2]
  8880  		mem := v.Args[3]
  8881  		v.reset(Op386MOVLstoreidx4)
  8882  		v.AuxInt = int64(int32(c + 4*d))
  8883  		v.Aux = sym
  8884  		v.AddArg(ptr)
  8885  		v.AddArg(idx)
  8886  		v.AddArg(val)
  8887  		v.AddArg(mem)
  8888  		return true
  8889  	}
  8890  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDLloadidx4 x [off] {sym} ptr idx mem) mem)
  8891  	// cond: y.Uses==1 && clobber(y)
  8892  	// result: (ADDLmodifyidx4 [off] {sym} ptr idx x mem)
  8893  	for {
  8894  		off := v.AuxInt
  8895  		sym := v.Aux
  8896  		_ = v.Args[3]
  8897  		ptr := v.Args[0]
  8898  		idx := v.Args[1]
  8899  		y := v.Args[2]
  8900  		if y.Op != Op386ADDLloadidx4 {
  8901  			break
  8902  		}
  8903  		if y.AuxInt != off {
  8904  			break
  8905  		}
  8906  		if y.Aux != sym {
  8907  			break
  8908  		}
  8909  		_ = y.Args[3]
  8910  		x := y.Args[0]
  8911  		if ptr != y.Args[1] {
  8912  			break
  8913  		}
  8914  		if idx != y.Args[2] {
  8915  			break
  8916  		}
  8917  		mem := y.Args[3]
  8918  		if mem != v.Args[3] {
  8919  			break
  8920  		}
  8921  		if !(y.Uses == 1 && clobber(y)) {
  8922  			break
  8923  		}
  8924  		v.reset(Op386ADDLmodifyidx4)
  8925  		v.AuxInt = off
  8926  		v.Aux = sym
  8927  		v.AddArg(ptr)
  8928  		v.AddArg(idx)
  8929  		v.AddArg(x)
  8930  		v.AddArg(mem)
  8931  		return true
  8932  	}
  8933  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDLloadidx4 x [off] {sym} ptr idx mem) mem)
  8934  	// cond: y.Uses==1 && clobber(y)
  8935  	// result: (ANDLmodifyidx4 [off] {sym} ptr idx x mem)
  8936  	for {
  8937  		off := v.AuxInt
  8938  		sym := v.Aux
  8939  		_ = v.Args[3]
  8940  		ptr := v.Args[0]
  8941  		idx := v.Args[1]
  8942  		y := v.Args[2]
  8943  		if y.Op != Op386ANDLloadidx4 {
  8944  			break
  8945  		}
  8946  		if y.AuxInt != off {
  8947  			break
  8948  		}
  8949  		if y.Aux != sym {
  8950  			break
  8951  		}
  8952  		_ = y.Args[3]
  8953  		x := y.Args[0]
  8954  		if ptr != y.Args[1] {
  8955  			break
  8956  		}
  8957  		if idx != y.Args[2] {
  8958  			break
  8959  		}
  8960  		mem := y.Args[3]
  8961  		if mem != v.Args[3] {
  8962  			break
  8963  		}
  8964  		if !(y.Uses == 1 && clobber(y)) {
  8965  			break
  8966  		}
  8967  		v.reset(Op386ANDLmodifyidx4)
  8968  		v.AuxInt = off
  8969  		v.Aux = sym
  8970  		v.AddArg(ptr)
  8971  		v.AddArg(idx)
  8972  		v.AddArg(x)
  8973  		v.AddArg(mem)
  8974  		return true
  8975  	}
  8976  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORLloadidx4 x [off] {sym} ptr idx mem) mem)
  8977  	// cond: y.Uses==1 && clobber(y)
  8978  	// result: (ORLmodifyidx4 [off] {sym} ptr idx x mem)
  8979  	for {
  8980  		off := v.AuxInt
  8981  		sym := v.Aux
  8982  		_ = v.Args[3]
  8983  		ptr := v.Args[0]
  8984  		idx := v.Args[1]
  8985  		y := v.Args[2]
  8986  		if y.Op != Op386ORLloadidx4 {
  8987  			break
  8988  		}
  8989  		if y.AuxInt != off {
  8990  			break
  8991  		}
  8992  		if y.Aux != sym {
  8993  			break
  8994  		}
  8995  		_ = y.Args[3]
  8996  		x := y.Args[0]
  8997  		if ptr != y.Args[1] {
  8998  			break
  8999  		}
  9000  		if idx != y.Args[2] {
  9001  			break
  9002  		}
  9003  		mem := y.Args[3]
  9004  		if mem != v.Args[3] {
  9005  			break
  9006  		}
  9007  		if !(y.Uses == 1 && clobber(y)) {
  9008  			break
  9009  		}
  9010  		v.reset(Op386ORLmodifyidx4)
  9011  		v.AuxInt = off
  9012  		v.Aux = sym
  9013  		v.AddArg(ptr)
  9014  		v.AddArg(idx)
  9015  		v.AddArg(x)
  9016  		v.AddArg(mem)
  9017  		return true
  9018  	}
  9019  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORLloadidx4 x [off] {sym} ptr idx mem) mem)
  9020  	// cond: y.Uses==1 && clobber(y)
  9021  	// result: (XORLmodifyidx4 [off] {sym} ptr idx x mem)
  9022  	for {
  9023  		off := v.AuxInt
  9024  		sym := v.Aux
  9025  		_ = v.Args[3]
  9026  		ptr := v.Args[0]
  9027  		idx := v.Args[1]
  9028  		y := v.Args[2]
  9029  		if y.Op != Op386XORLloadidx4 {
  9030  			break
  9031  		}
  9032  		if y.AuxInt != off {
  9033  			break
  9034  		}
  9035  		if y.Aux != sym {
  9036  			break
  9037  		}
  9038  		_ = y.Args[3]
  9039  		x := y.Args[0]
  9040  		if ptr != y.Args[1] {
  9041  			break
  9042  		}
  9043  		if idx != y.Args[2] {
  9044  			break
  9045  		}
  9046  		mem := y.Args[3]
  9047  		if mem != v.Args[3] {
  9048  			break
  9049  		}
  9050  		if !(y.Uses == 1 && clobber(y)) {
  9051  			break
  9052  		}
  9053  		v.reset(Op386XORLmodifyidx4)
  9054  		v.AuxInt = off
  9055  		v.Aux = sym
  9056  		v.AddArg(ptr)
  9057  		v.AddArg(idx)
  9058  		v.AddArg(x)
  9059  		v.AddArg(mem)
  9060  		return true
  9061  	}
  9062  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem)
  9063  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  9064  	// result: (ADDLmodifyidx4 [off] {sym} ptr idx x mem)
  9065  	for {
  9066  		off := v.AuxInt
  9067  		sym := v.Aux
  9068  		_ = v.Args[3]
  9069  		ptr := v.Args[0]
  9070  		idx := v.Args[1]
  9071  		y := v.Args[2]
  9072  		if y.Op != Op386ADDL {
  9073  			break
  9074  		}
  9075  		_ = y.Args[1]
  9076  		l := y.Args[0]
  9077  		if l.Op != Op386MOVLloadidx4 {
  9078  			break
  9079  		}
  9080  		if l.AuxInt != off {
  9081  			break
  9082  		}
  9083  		if l.Aux != sym {
  9084  			break
  9085  		}
  9086  		_ = l.Args[2]
  9087  		if ptr != l.Args[0] {
  9088  			break
  9089  		}
  9090  		if idx != l.Args[1] {
  9091  			break
  9092  		}
  9093  		mem := l.Args[2]
  9094  		x := y.Args[1]
  9095  		if mem != v.Args[3] {
  9096  			break
  9097  		}
  9098  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  9099  			break
  9100  		}
  9101  		v.reset(Op386ADDLmodifyidx4)
  9102  		v.AuxInt = off
  9103  		v.Aux = sym
  9104  		v.AddArg(ptr)
  9105  		v.AddArg(idx)
  9106  		v.AddArg(x)
  9107  		v.AddArg(mem)
  9108  		return true
  9109  	}
  9110  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
  9111  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  9112  	// result: (ADDLmodifyidx4 [off] {sym} ptr idx x mem)
  9113  	for {
  9114  		off := v.AuxInt
  9115  		sym := v.Aux
  9116  		_ = v.Args[3]
  9117  		ptr := v.Args[0]
  9118  		idx := v.Args[1]
  9119  		y := v.Args[2]
  9120  		if y.Op != Op386ADDL {
  9121  			break
  9122  		}
  9123  		_ = y.Args[1]
  9124  		x := y.Args[0]
  9125  		l := y.Args[1]
  9126  		if l.Op != Op386MOVLloadidx4 {
  9127  			break
  9128  		}
  9129  		if l.AuxInt != off {
  9130  			break
  9131  		}
  9132  		if l.Aux != sym {
  9133  			break
  9134  		}
  9135  		_ = l.Args[2]
  9136  		if ptr != l.Args[0] {
  9137  			break
  9138  		}
  9139  		if idx != l.Args[1] {
  9140  			break
  9141  		}
  9142  		mem := l.Args[2]
  9143  		if mem != v.Args[3] {
  9144  			break
  9145  		}
  9146  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  9147  			break
  9148  		}
  9149  		v.reset(Op386ADDLmodifyidx4)
  9150  		v.AuxInt = off
  9151  		v.Aux = sym
  9152  		v.AddArg(ptr)
  9153  		v.AddArg(idx)
  9154  		v.AddArg(x)
  9155  		v.AddArg(mem)
  9156  		return true
  9157  	}
  9158  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(SUBL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem)
  9159  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  9160  	// result: (SUBLmodifyidx4 [off] {sym} ptr idx x mem)
  9161  	for {
  9162  		off := v.AuxInt
  9163  		sym := v.Aux
  9164  		_ = v.Args[3]
  9165  		ptr := v.Args[0]
  9166  		idx := v.Args[1]
  9167  		y := v.Args[2]
  9168  		if y.Op != Op386SUBL {
  9169  			break
  9170  		}
  9171  		_ = y.Args[1]
  9172  		l := y.Args[0]
  9173  		if l.Op != Op386MOVLloadidx4 {
  9174  			break
  9175  		}
  9176  		if l.AuxInt != off {
  9177  			break
  9178  		}
  9179  		if l.Aux != sym {
  9180  			break
  9181  		}
  9182  		_ = l.Args[2]
  9183  		if ptr != l.Args[0] {
  9184  			break
  9185  		}
  9186  		if idx != l.Args[1] {
  9187  			break
  9188  		}
  9189  		mem := l.Args[2]
  9190  		x := y.Args[1]
  9191  		if mem != v.Args[3] {
  9192  			break
  9193  		}
  9194  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  9195  			break
  9196  		}
  9197  		v.reset(Op386SUBLmodifyidx4)
  9198  		v.AuxInt = off
  9199  		v.Aux = sym
  9200  		v.AddArg(ptr)
  9201  		v.AddArg(idx)
  9202  		v.AddArg(x)
  9203  		v.AddArg(mem)
  9204  		return true
  9205  	}
  9206  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem)
  9207  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  9208  	// result: (ANDLmodifyidx4 [off] {sym} ptr idx x mem)
  9209  	for {
  9210  		off := v.AuxInt
  9211  		sym := v.Aux
  9212  		_ = v.Args[3]
  9213  		ptr := v.Args[0]
  9214  		idx := v.Args[1]
  9215  		y := v.Args[2]
  9216  		if y.Op != Op386ANDL {
  9217  			break
  9218  		}
  9219  		_ = y.Args[1]
  9220  		l := y.Args[0]
  9221  		if l.Op != Op386MOVLloadidx4 {
  9222  			break
  9223  		}
  9224  		if l.AuxInt != off {
  9225  			break
  9226  		}
  9227  		if l.Aux != sym {
  9228  			break
  9229  		}
  9230  		_ = l.Args[2]
  9231  		if ptr != l.Args[0] {
  9232  			break
  9233  		}
  9234  		if idx != l.Args[1] {
  9235  			break
  9236  		}
  9237  		mem := l.Args[2]
  9238  		x := y.Args[1]
  9239  		if mem != v.Args[3] {
  9240  			break
  9241  		}
  9242  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  9243  			break
  9244  		}
  9245  		v.reset(Op386ANDLmodifyidx4)
  9246  		v.AuxInt = off
  9247  		v.Aux = sym
  9248  		v.AddArg(ptr)
  9249  		v.AddArg(idx)
  9250  		v.AddArg(x)
  9251  		v.AddArg(mem)
  9252  		return true
  9253  	}
  9254  	return false
  9255  }
  9256  func rewriteValue386_Op386MOVLstoreidx4_10(v *Value) bool {
  9257  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
  9258  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  9259  	// result: (ANDLmodifyidx4 [off] {sym} ptr idx x mem)
  9260  	for {
  9261  		off := v.AuxInt
  9262  		sym := v.Aux
  9263  		_ = v.Args[3]
  9264  		ptr := v.Args[0]
  9265  		idx := v.Args[1]
  9266  		y := v.Args[2]
  9267  		if y.Op != Op386ANDL {
  9268  			break
  9269  		}
  9270  		_ = y.Args[1]
  9271  		x := y.Args[0]
  9272  		l := y.Args[1]
  9273  		if l.Op != Op386MOVLloadidx4 {
  9274  			break
  9275  		}
  9276  		if l.AuxInt != off {
  9277  			break
  9278  		}
  9279  		if l.Aux != sym {
  9280  			break
  9281  		}
  9282  		_ = l.Args[2]
  9283  		if ptr != l.Args[0] {
  9284  			break
  9285  		}
  9286  		if idx != l.Args[1] {
  9287  			break
  9288  		}
  9289  		mem := l.Args[2]
  9290  		if mem != v.Args[3] {
  9291  			break
  9292  		}
  9293  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  9294  			break
  9295  		}
  9296  		v.reset(Op386ANDLmodifyidx4)
  9297  		v.AuxInt = off
  9298  		v.Aux = sym
  9299  		v.AddArg(ptr)
  9300  		v.AddArg(idx)
  9301  		v.AddArg(x)
  9302  		v.AddArg(mem)
  9303  		return true
  9304  	}
  9305  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem)
  9306  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  9307  	// result: (ORLmodifyidx4 [off] {sym} ptr idx x mem)
  9308  	for {
  9309  		off := v.AuxInt
  9310  		sym := v.Aux
  9311  		_ = v.Args[3]
  9312  		ptr := v.Args[0]
  9313  		idx := v.Args[1]
  9314  		y := v.Args[2]
  9315  		if y.Op != Op386ORL {
  9316  			break
  9317  		}
  9318  		_ = y.Args[1]
  9319  		l := y.Args[0]
  9320  		if l.Op != Op386MOVLloadidx4 {
  9321  			break
  9322  		}
  9323  		if l.AuxInt != off {
  9324  			break
  9325  		}
  9326  		if l.Aux != sym {
  9327  			break
  9328  		}
  9329  		_ = l.Args[2]
  9330  		if ptr != l.Args[0] {
  9331  			break
  9332  		}
  9333  		if idx != l.Args[1] {
  9334  			break
  9335  		}
  9336  		mem := l.Args[2]
  9337  		x := y.Args[1]
  9338  		if mem != v.Args[3] {
  9339  			break
  9340  		}
  9341  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  9342  			break
  9343  		}
  9344  		v.reset(Op386ORLmodifyidx4)
  9345  		v.AuxInt = off
  9346  		v.Aux = sym
  9347  		v.AddArg(ptr)
  9348  		v.AddArg(idx)
  9349  		v.AddArg(x)
  9350  		v.AddArg(mem)
  9351  		return true
  9352  	}
  9353  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
  9354  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  9355  	// result: (ORLmodifyidx4 [off] {sym} ptr idx x mem)
  9356  	for {
  9357  		off := v.AuxInt
  9358  		sym := v.Aux
  9359  		_ = v.Args[3]
  9360  		ptr := v.Args[0]
  9361  		idx := v.Args[1]
  9362  		y := v.Args[2]
  9363  		if y.Op != Op386ORL {
  9364  			break
  9365  		}
  9366  		_ = y.Args[1]
  9367  		x := y.Args[0]
  9368  		l := y.Args[1]
  9369  		if l.Op != Op386MOVLloadidx4 {
  9370  			break
  9371  		}
  9372  		if l.AuxInt != off {
  9373  			break
  9374  		}
  9375  		if l.Aux != sym {
  9376  			break
  9377  		}
  9378  		_ = l.Args[2]
  9379  		if ptr != l.Args[0] {
  9380  			break
  9381  		}
  9382  		if idx != l.Args[1] {
  9383  			break
  9384  		}
  9385  		mem := l.Args[2]
  9386  		if mem != v.Args[3] {
  9387  			break
  9388  		}
  9389  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  9390  			break
  9391  		}
  9392  		v.reset(Op386ORLmodifyidx4)
  9393  		v.AuxInt = off
  9394  		v.Aux = sym
  9395  		v.AddArg(ptr)
  9396  		v.AddArg(idx)
  9397  		v.AddArg(x)
  9398  		v.AddArg(mem)
  9399  		return true
  9400  	}
  9401  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem)
  9402  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  9403  	// result: (XORLmodifyidx4 [off] {sym} ptr idx x mem)
  9404  	for {
  9405  		off := v.AuxInt
  9406  		sym := v.Aux
  9407  		_ = v.Args[3]
  9408  		ptr := v.Args[0]
  9409  		idx := v.Args[1]
  9410  		y := v.Args[2]
  9411  		if y.Op != Op386XORL {
  9412  			break
  9413  		}
  9414  		_ = y.Args[1]
  9415  		l := y.Args[0]
  9416  		if l.Op != Op386MOVLloadidx4 {
  9417  			break
  9418  		}
  9419  		if l.AuxInt != off {
  9420  			break
  9421  		}
  9422  		if l.Aux != sym {
  9423  			break
  9424  		}
  9425  		_ = l.Args[2]
  9426  		if ptr != l.Args[0] {
  9427  			break
  9428  		}
  9429  		if idx != l.Args[1] {
  9430  			break
  9431  		}
  9432  		mem := l.Args[2]
  9433  		x := y.Args[1]
  9434  		if mem != v.Args[3] {
  9435  			break
  9436  		}
  9437  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  9438  			break
  9439  		}
  9440  		v.reset(Op386XORLmodifyidx4)
  9441  		v.AuxInt = off
  9442  		v.Aux = sym
  9443  		v.AddArg(ptr)
  9444  		v.AddArg(idx)
  9445  		v.AddArg(x)
  9446  		v.AddArg(mem)
  9447  		return true
  9448  	}
  9449  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
  9450  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l)
  9451  	// result: (XORLmodifyidx4 [off] {sym} ptr idx x mem)
  9452  	for {
  9453  		off := v.AuxInt
  9454  		sym := v.Aux
  9455  		_ = v.Args[3]
  9456  		ptr := v.Args[0]
  9457  		idx := v.Args[1]
  9458  		y := v.Args[2]
  9459  		if y.Op != Op386XORL {
  9460  			break
  9461  		}
  9462  		_ = y.Args[1]
  9463  		x := y.Args[0]
  9464  		l := y.Args[1]
  9465  		if l.Op != Op386MOVLloadidx4 {
  9466  			break
  9467  		}
  9468  		if l.AuxInt != off {
  9469  			break
  9470  		}
  9471  		if l.Aux != sym {
  9472  			break
  9473  		}
  9474  		_ = l.Args[2]
  9475  		if ptr != l.Args[0] {
  9476  			break
  9477  		}
  9478  		if idx != l.Args[1] {
  9479  			break
  9480  		}
  9481  		mem := l.Args[2]
  9482  		if mem != v.Args[3] {
  9483  			break
  9484  		}
  9485  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) {
  9486  			break
  9487  		}
  9488  		v.reset(Op386XORLmodifyidx4)
  9489  		v.AuxInt = off
  9490  		v.Aux = sym
  9491  		v.AddArg(ptr)
  9492  		v.AddArg(idx)
  9493  		v.AddArg(x)
  9494  		v.AddArg(mem)
  9495  		return true
  9496  	}
  9497  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
  9498  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off)
  9499  	// result: (ADDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem)
  9500  	for {
  9501  		off := v.AuxInt
  9502  		sym := v.Aux
  9503  		_ = v.Args[3]
  9504  		ptr := v.Args[0]
  9505  		idx := v.Args[1]
  9506  		y := v.Args[2]
  9507  		if y.Op != Op386ADDLconst {
  9508  			break
  9509  		}
  9510  		c := y.AuxInt
  9511  		l := y.Args[0]
  9512  		if l.Op != Op386MOVLloadidx4 {
  9513  			break
  9514  		}
  9515  		if l.AuxInt != off {
  9516  			break
  9517  		}
  9518  		if l.Aux != sym {
  9519  			break
  9520  		}
  9521  		_ = l.Args[2]
  9522  		if ptr != l.Args[0] {
  9523  			break
  9524  		}
  9525  		if idx != l.Args[1] {
  9526  			break
  9527  		}
  9528  		mem := l.Args[2]
  9529  		if mem != v.Args[3] {
  9530  			break
  9531  		}
  9532  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) {
  9533  			break
  9534  		}
  9535  		v.reset(Op386ADDLconstmodifyidx4)
  9536  		v.AuxInt = makeValAndOff(c, off)
  9537  		v.Aux = sym
  9538  		v.AddArg(ptr)
  9539  		v.AddArg(idx)
  9540  		v.AddArg(mem)
  9541  		return true
  9542  	}
  9543  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
  9544  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off)
  9545  	// result: (ANDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem)
  9546  	for {
  9547  		off := v.AuxInt
  9548  		sym := v.Aux
  9549  		_ = v.Args[3]
  9550  		ptr := v.Args[0]
  9551  		idx := v.Args[1]
  9552  		y := v.Args[2]
  9553  		if y.Op != Op386ANDLconst {
  9554  			break
  9555  		}
  9556  		c := y.AuxInt
  9557  		l := y.Args[0]
  9558  		if l.Op != Op386MOVLloadidx4 {
  9559  			break
  9560  		}
  9561  		if l.AuxInt != off {
  9562  			break
  9563  		}
  9564  		if l.Aux != sym {
  9565  			break
  9566  		}
  9567  		_ = l.Args[2]
  9568  		if ptr != l.Args[0] {
  9569  			break
  9570  		}
  9571  		if idx != l.Args[1] {
  9572  			break
  9573  		}
  9574  		mem := l.Args[2]
  9575  		if mem != v.Args[3] {
  9576  			break
  9577  		}
  9578  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) {
  9579  			break
  9580  		}
  9581  		v.reset(Op386ANDLconstmodifyidx4)
  9582  		v.AuxInt = makeValAndOff(c, off)
  9583  		v.Aux = sym
  9584  		v.AddArg(ptr)
  9585  		v.AddArg(idx)
  9586  		v.AddArg(mem)
  9587  		return true
  9588  	}
  9589  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
  9590  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off)
  9591  	// result: (ORLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem)
  9592  	for {
  9593  		off := v.AuxInt
  9594  		sym := v.Aux
  9595  		_ = v.Args[3]
  9596  		ptr := v.Args[0]
  9597  		idx := v.Args[1]
  9598  		y := v.Args[2]
  9599  		if y.Op != Op386ORLconst {
  9600  			break
  9601  		}
  9602  		c := y.AuxInt
  9603  		l := y.Args[0]
  9604  		if l.Op != Op386MOVLloadidx4 {
  9605  			break
  9606  		}
  9607  		if l.AuxInt != off {
  9608  			break
  9609  		}
  9610  		if l.Aux != sym {
  9611  			break
  9612  		}
  9613  		_ = l.Args[2]
  9614  		if ptr != l.Args[0] {
  9615  			break
  9616  		}
  9617  		if idx != l.Args[1] {
  9618  			break
  9619  		}
  9620  		mem := l.Args[2]
  9621  		if mem != v.Args[3] {
  9622  			break
  9623  		}
  9624  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) {
  9625  			break
  9626  		}
  9627  		v.reset(Op386ORLconstmodifyidx4)
  9628  		v.AuxInt = makeValAndOff(c, off)
  9629  		v.Aux = sym
  9630  		v.AddArg(ptr)
  9631  		v.AddArg(idx)
  9632  		v.AddArg(mem)
  9633  		return true
  9634  	}
  9635  	// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
  9636  	// cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off)
  9637  	// result: (XORLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem)
  9638  	for {
  9639  		off := v.AuxInt
  9640  		sym := v.Aux
  9641  		_ = v.Args[3]
  9642  		ptr := v.Args[0]
  9643  		idx := v.Args[1]
  9644  		y := v.Args[2]
  9645  		if y.Op != Op386XORLconst {
  9646  			break
  9647  		}
  9648  		c := y.AuxInt
  9649  		l := y.Args[0]
  9650  		if l.Op != Op386MOVLloadidx4 {
  9651  			break
  9652  		}
  9653  		if l.AuxInt != off {
  9654  			break
  9655  		}
  9656  		if l.Aux != sym {
  9657  			break
  9658  		}
  9659  		_ = l.Args[2]
  9660  		if ptr != l.Args[0] {
  9661  			break
  9662  		}
  9663  		if idx != l.Args[1] {
  9664  			break
  9665  		}
  9666  		mem := l.Args[2]
  9667  		if mem != v.Args[3] {
  9668  			break
  9669  		}
  9670  		if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) {
  9671  			break
  9672  		}
  9673  		v.reset(Op386XORLconstmodifyidx4)
  9674  		v.AuxInt = makeValAndOff(c, off)
  9675  		v.Aux = sym
  9676  		v.AddArg(ptr)
  9677  		v.AddArg(idx)
  9678  		v.AddArg(mem)
  9679  		return true
  9680  	}
  9681  	return false
  9682  }
  9683  func rewriteValue386_Op386MOVSDconst_0(v *Value) bool {
  9684  	b := v.Block
  9685  	_ = b
  9686  	config := b.Func.Config
  9687  	_ = config
  9688  	typ := &b.Func.Config.Types
  9689  	_ = typ
  9690  	// match: (MOVSDconst [c])
  9691  	// cond: config.ctxt.Flag_shared
  9692  	// result: (MOVSDconst2 (MOVSDconst1 [c]))
  9693  	for {
  9694  		c := v.AuxInt
  9695  		if !(config.ctxt.Flag_shared) {
  9696  			break
  9697  		}
  9698  		v.reset(Op386MOVSDconst2)
  9699  		v0 := b.NewValue0(v.Pos, Op386MOVSDconst1, typ.UInt32)
  9700  		v0.AuxInt = c
  9701  		v.AddArg(v0)
  9702  		return true
  9703  	}
  9704  	return false
  9705  }
  9706  func rewriteValue386_Op386MOVSDload_0(v *Value) bool {
  9707  	b := v.Block
  9708  	_ = b
  9709  	config := b.Func.Config
  9710  	_ = config
  9711  	// match: (MOVSDload [off1] {sym} (ADDLconst [off2] ptr) mem)
  9712  	// cond: is32Bit(off1+off2)
  9713  	// result: (MOVSDload [off1+off2] {sym} ptr mem)
  9714  	for {
  9715  		off1 := v.AuxInt
  9716  		sym := v.Aux
  9717  		_ = v.Args[1]
  9718  		v_0 := v.Args[0]
  9719  		if v_0.Op != Op386ADDLconst {
  9720  			break
  9721  		}
  9722  		off2 := v_0.AuxInt
  9723  		ptr := v_0.Args[0]
  9724  		mem := v.Args[1]
  9725  		if !(is32Bit(off1 + off2)) {
  9726  			break
  9727  		}
  9728  		v.reset(Op386MOVSDload)
  9729  		v.AuxInt = off1 + off2
  9730  		v.Aux = sym
  9731  		v.AddArg(ptr)
  9732  		v.AddArg(mem)
  9733  		return true
  9734  	}
  9735  	// match: (MOVSDload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
  9736  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  9737  	// result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem)
  9738  	for {
  9739  		off1 := v.AuxInt
  9740  		sym1 := v.Aux
  9741  		_ = v.Args[1]
  9742  		v_0 := v.Args[0]
  9743  		if v_0.Op != Op386LEAL {
  9744  			break
  9745  		}
  9746  		off2 := v_0.AuxInt
  9747  		sym2 := v_0.Aux
  9748  		base := v_0.Args[0]
  9749  		mem := v.Args[1]
  9750  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  9751  			break
  9752  		}
  9753  		v.reset(Op386MOVSDload)
  9754  		v.AuxInt = off1 + off2
  9755  		v.Aux = mergeSym(sym1, sym2)
  9756  		v.AddArg(base)
  9757  		v.AddArg(mem)
  9758  		return true
  9759  	}
  9760  	// match: (MOVSDload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem)
  9761  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  9762  	// result: (MOVSDloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
  9763  	for {
  9764  		off1 := v.AuxInt
  9765  		sym1 := v.Aux
  9766  		_ = v.Args[1]
  9767  		v_0 := v.Args[0]
  9768  		if v_0.Op != Op386LEAL1 {
  9769  			break
  9770  		}
  9771  		off2 := v_0.AuxInt
  9772  		sym2 := v_0.Aux
  9773  		_ = v_0.Args[1]
  9774  		ptr := v_0.Args[0]
  9775  		idx := v_0.Args[1]
  9776  		mem := v.Args[1]
  9777  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  9778  			break
  9779  		}
  9780  		v.reset(Op386MOVSDloadidx1)
  9781  		v.AuxInt = off1 + off2
  9782  		v.Aux = mergeSym(sym1, sym2)
  9783  		v.AddArg(ptr)
  9784  		v.AddArg(idx)
  9785  		v.AddArg(mem)
  9786  		return true
  9787  	}
  9788  	// match: (MOVSDload [off1] {sym1} (LEAL8 [off2] {sym2} ptr idx) mem)
  9789  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
  9790  	// result: (MOVSDloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
  9791  	for {
  9792  		off1 := v.AuxInt
  9793  		sym1 := v.Aux
  9794  		_ = v.Args[1]
  9795  		v_0 := v.Args[0]
  9796  		if v_0.Op != Op386LEAL8 {
  9797  			break
  9798  		}
  9799  		off2 := v_0.AuxInt
  9800  		sym2 := v_0.Aux
  9801  		_ = v_0.Args[1]
  9802  		ptr := v_0.Args[0]
  9803  		idx := v_0.Args[1]
  9804  		mem := v.Args[1]
  9805  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
  9806  			break
  9807  		}
  9808  		v.reset(Op386MOVSDloadidx8)
  9809  		v.AuxInt = off1 + off2
  9810  		v.Aux = mergeSym(sym1, sym2)
  9811  		v.AddArg(ptr)
  9812  		v.AddArg(idx)
  9813  		v.AddArg(mem)
  9814  		return true
  9815  	}
  9816  	// match: (MOVSDload [off] {sym} (ADDL ptr idx) mem)
  9817  	// cond: ptr.Op != OpSB
  9818  	// result: (MOVSDloadidx1 [off] {sym} ptr idx mem)
  9819  	for {
  9820  		off := v.AuxInt
  9821  		sym := v.Aux
  9822  		_ = v.Args[1]
  9823  		v_0 := v.Args[0]
  9824  		if v_0.Op != Op386ADDL {
  9825  			break
  9826  		}
  9827  		_ = v_0.Args[1]
  9828  		ptr := v_0.Args[0]
  9829  		idx := v_0.Args[1]
  9830  		mem := v.Args[1]
  9831  		if !(ptr.Op != OpSB) {
  9832  			break
  9833  		}
  9834  		v.reset(Op386MOVSDloadidx1)
  9835  		v.AuxInt = off
  9836  		v.Aux = sym
  9837  		v.AddArg(ptr)
  9838  		v.AddArg(idx)
  9839  		v.AddArg(mem)
  9840  		return true
  9841  	}
  9842  	return false
  9843  }
  9844  func rewriteValue386_Op386MOVSDloadidx1_0(v *Value) bool {
  9845  	// match: (MOVSDloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem)
  9846  	// cond:
  9847  	// result: (MOVSDloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  9848  	for {
  9849  		c := v.AuxInt
  9850  		sym := v.Aux
  9851  		_ = v.Args[2]
  9852  		v_0 := v.Args[0]
  9853  		if v_0.Op != Op386ADDLconst {
  9854  			break
  9855  		}
  9856  		d := v_0.AuxInt
  9857  		ptr := v_0.Args[0]
  9858  		idx := v.Args[1]
  9859  		mem := v.Args[2]
  9860  		v.reset(Op386MOVSDloadidx1)
  9861  		v.AuxInt = int64(int32(c + d))
  9862  		v.Aux = sym
  9863  		v.AddArg(ptr)
  9864  		v.AddArg(idx)
  9865  		v.AddArg(mem)
  9866  		return true
  9867  	}
  9868  	// match: (MOVSDloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem)
  9869  	// cond:
  9870  	// result: (MOVSDloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
  9871  	for {
  9872  		c := v.AuxInt
  9873  		sym := v.Aux
  9874  		_ = v.Args[2]
  9875  		ptr := v.Args[0]
  9876  		v_1 := v.Args[1]
  9877  		if v_1.Op != Op386ADDLconst {
  9878  			break
  9879  		}
  9880  		d := v_1.AuxInt
  9881  		idx := v_1.Args[0]
  9882  		mem := v.Args[2]
  9883  		v.reset(Op386MOVSDloadidx1)
  9884  		v.AuxInt = int64(int32(c + d))
  9885  		v.Aux = sym
  9886  		v.AddArg(ptr)
  9887  		v.AddArg(idx)
  9888  		v.AddArg(mem)
  9889  		return true
  9890  	}
  9891  	return false
  9892  }
  9893  func rewriteValue386_Op386MOVSDloadidx8_0(v *Value) bool {
  9894  	// match: (MOVSDloadidx8 [c] {sym} (ADDLconst [d] ptr) idx mem)
  9895  	// cond:
  9896  	// result: (MOVSDloadidx8 [int64(int32(c+d))] {sym} ptr idx mem)
  9897  	for {
  9898  		c := v.AuxInt
  9899  		sym := v.Aux
  9900  		_ = v.Args[2]
  9901  		v_0 := v.Args[0]
  9902  		if v_0.Op != Op386ADDLconst {
  9903  			break
  9904  		}
  9905  		d := v_0.AuxInt
  9906  		ptr := v_0.Args[0]
  9907  		idx := v.Args[1]
  9908  		mem := v.Args[2]
  9909  		v.reset(Op386MOVSDloadidx8)
  9910  		v.AuxInt = int64(int32(c + d))
  9911  		v.Aux = sym
  9912  		v.AddArg(ptr)
  9913  		v.AddArg(idx)
  9914  		v.AddArg(mem)
  9915  		return true
  9916  	}
  9917  	// match: (MOVSDloadidx8 [c] {sym} ptr (ADDLconst [d] idx) mem)
  9918  	// cond:
  9919  	// result: (MOVSDloadidx8 [int64(int32(c+8*d))] {sym} ptr idx mem)
  9920  	for {
  9921  		c := v.AuxInt
  9922  		sym := v.Aux
  9923  		_ = v.Args[2]
  9924  		ptr := v.Args[0]
  9925  		v_1 := v.Args[1]
  9926  		if v_1.Op != Op386ADDLconst {
  9927  			break
  9928  		}
  9929  		d := v_1.AuxInt
  9930  		idx := v_1.Args[0]
  9931  		mem := v.Args[2]
  9932  		v.reset(Op386MOVSDloadidx8)
  9933  		v.AuxInt = int64(int32(c + 8*d))
  9934  		v.Aux = sym
  9935  		v.AddArg(ptr)
  9936  		v.AddArg(idx)
  9937  		v.AddArg(mem)
  9938  		return true
  9939  	}
  9940  	return false
  9941  }
  9942  func rewriteValue386_Op386MOVSDstore_0(v *Value) bool {
  9943  	b := v.Block
  9944  	_ = b
  9945  	config := b.Func.Config
  9946  	_ = config
  9947  	// match: (MOVSDstore [off1] {sym} (ADDLconst [off2] ptr) val mem)
  9948  	// cond: is32Bit(off1+off2)
  9949  	// result: (MOVSDstore [off1+off2] {sym} ptr val mem)
  9950  	for {
  9951  		off1 := v.AuxInt
  9952  		sym := v.Aux
  9953  		_ = v.Args[2]
  9954  		v_0 := v.Args[0]
  9955  		if v_0.Op != Op386ADDLconst {
  9956  			break
  9957  		}
  9958  		off2 := v_0.AuxInt
  9959  		ptr := v_0.Args[0]
  9960  		val := v.Args[1]
  9961  		mem := v.Args[2]
  9962  		if !(is32Bit(off1 + off2)) {
  9963  			break
  9964  		}
  9965  		v.reset(Op386MOVSDstore)
  9966  		v.AuxInt = off1 + off2
  9967  		v.Aux = sym
  9968  		v.AddArg(ptr)
  9969  		v.AddArg(val)
  9970  		v.AddArg(mem)
  9971  		return true
  9972  	}
  9973  	// match: (MOVSDstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
  9974  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
  9975  	// result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
  9976  	for {
  9977  		off1 := v.AuxInt
  9978  		sym1 := v.Aux
  9979  		_ = v.Args[2]
  9980  		v_0 := v.Args[0]
  9981  		if v_0.Op != Op386LEAL {
  9982  			break
  9983  		}
  9984  		off2 := v_0.AuxInt
  9985  		sym2 := v_0.Aux
  9986  		base := v_0.Args[0]
  9987  		val := v.Args[1]
  9988  		mem := v.Args[2]
  9989  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
  9990  			break
  9991  		}
  9992  		v.reset(Op386MOVSDstore)
  9993  		v.AuxInt = off1 + off2
  9994  		v.Aux = mergeSym(sym1, sym2)
  9995  		v.AddArg(base)
  9996  		v.AddArg(val)
  9997  		v.AddArg(mem)
  9998  		return true
  9999  	}
 10000  	// match: (MOVSDstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem)
 10001  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10002  	// result: (MOVSDstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
 10003  	for {
 10004  		off1 := v.AuxInt
 10005  		sym1 := v.Aux
 10006  		_ = v.Args[2]
 10007  		v_0 := v.Args[0]
 10008  		if v_0.Op != Op386LEAL1 {
 10009  			break
 10010  		}
 10011  		off2 := v_0.AuxInt
 10012  		sym2 := v_0.Aux
 10013  		_ = v_0.Args[1]
 10014  		ptr := v_0.Args[0]
 10015  		idx := v_0.Args[1]
 10016  		val := v.Args[1]
 10017  		mem := v.Args[2]
 10018  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10019  			break
 10020  		}
 10021  		v.reset(Op386MOVSDstoreidx1)
 10022  		v.AuxInt = off1 + off2
 10023  		v.Aux = mergeSym(sym1, sym2)
 10024  		v.AddArg(ptr)
 10025  		v.AddArg(idx)
 10026  		v.AddArg(val)
 10027  		v.AddArg(mem)
 10028  		return true
 10029  	}
 10030  	// match: (MOVSDstore [off1] {sym1} (LEAL8 [off2] {sym2} ptr idx) val mem)
 10031  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10032  	// result: (MOVSDstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
 10033  	for {
 10034  		off1 := v.AuxInt
 10035  		sym1 := v.Aux
 10036  		_ = v.Args[2]
 10037  		v_0 := v.Args[0]
 10038  		if v_0.Op != Op386LEAL8 {
 10039  			break
 10040  		}
 10041  		off2 := v_0.AuxInt
 10042  		sym2 := v_0.Aux
 10043  		_ = v_0.Args[1]
 10044  		ptr := v_0.Args[0]
 10045  		idx := v_0.Args[1]
 10046  		val := v.Args[1]
 10047  		mem := v.Args[2]
 10048  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10049  			break
 10050  		}
 10051  		v.reset(Op386MOVSDstoreidx8)
 10052  		v.AuxInt = off1 + off2
 10053  		v.Aux = mergeSym(sym1, sym2)
 10054  		v.AddArg(ptr)
 10055  		v.AddArg(idx)
 10056  		v.AddArg(val)
 10057  		v.AddArg(mem)
 10058  		return true
 10059  	}
 10060  	// match: (MOVSDstore [off] {sym} (ADDL ptr idx) val mem)
 10061  	// cond: ptr.Op != OpSB
 10062  	// result: (MOVSDstoreidx1 [off] {sym} ptr idx val mem)
 10063  	for {
 10064  		off := v.AuxInt
 10065  		sym := v.Aux
 10066  		_ = v.Args[2]
 10067  		v_0 := v.Args[0]
 10068  		if v_0.Op != Op386ADDL {
 10069  			break
 10070  		}
 10071  		_ = v_0.Args[1]
 10072  		ptr := v_0.Args[0]
 10073  		idx := v_0.Args[1]
 10074  		val := v.Args[1]
 10075  		mem := v.Args[2]
 10076  		if !(ptr.Op != OpSB) {
 10077  			break
 10078  		}
 10079  		v.reset(Op386MOVSDstoreidx1)
 10080  		v.AuxInt = off
 10081  		v.Aux = sym
 10082  		v.AddArg(ptr)
 10083  		v.AddArg(idx)
 10084  		v.AddArg(val)
 10085  		v.AddArg(mem)
 10086  		return true
 10087  	}
 10088  	return false
 10089  }
 10090  func rewriteValue386_Op386MOVSDstoreidx1_0(v *Value) bool {
 10091  	// match: (MOVSDstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem)
 10092  	// cond:
 10093  	// result: (MOVSDstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
 10094  	for {
 10095  		c := v.AuxInt
 10096  		sym := v.Aux
 10097  		_ = v.Args[3]
 10098  		v_0 := v.Args[0]
 10099  		if v_0.Op != Op386ADDLconst {
 10100  			break
 10101  		}
 10102  		d := v_0.AuxInt
 10103  		ptr := v_0.Args[0]
 10104  		idx := v.Args[1]
 10105  		val := v.Args[2]
 10106  		mem := v.Args[3]
 10107  		v.reset(Op386MOVSDstoreidx1)
 10108  		v.AuxInt = int64(int32(c + d))
 10109  		v.Aux = sym
 10110  		v.AddArg(ptr)
 10111  		v.AddArg(idx)
 10112  		v.AddArg(val)
 10113  		v.AddArg(mem)
 10114  		return true
 10115  	}
 10116  	// match: (MOVSDstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem)
 10117  	// cond:
 10118  	// result: (MOVSDstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
 10119  	for {
 10120  		c := v.AuxInt
 10121  		sym := v.Aux
 10122  		_ = v.Args[3]
 10123  		ptr := v.Args[0]
 10124  		v_1 := v.Args[1]
 10125  		if v_1.Op != Op386ADDLconst {
 10126  			break
 10127  		}
 10128  		d := v_1.AuxInt
 10129  		idx := v_1.Args[0]
 10130  		val := v.Args[2]
 10131  		mem := v.Args[3]
 10132  		v.reset(Op386MOVSDstoreidx1)
 10133  		v.AuxInt = int64(int32(c + d))
 10134  		v.Aux = sym
 10135  		v.AddArg(ptr)
 10136  		v.AddArg(idx)
 10137  		v.AddArg(val)
 10138  		v.AddArg(mem)
 10139  		return true
 10140  	}
 10141  	return false
 10142  }
 10143  func rewriteValue386_Op386MOVSDstoreidx8_0(v *Value) bool {
 10144  	// match: (MOVSDstoreidx8 [c] {sym} (ADDLconst [d] ptr) idx val mem)
 10145  	// cond:
 10146  	// result: (MOVSDstoreidx8 [int64(int32(c+d))] {sym} ptr idx val mem)
 10147  	for {
 10148  		c := v.AuxInt
 10149  		sym := v.Aux
 10150  		_ = v.Args[3]
 10151  		v_0 := v.Args[0]
 10152  		if v_0.Op != Op386ADDLconst {
 10153  			break
 10154  		}
 10155  		d := v_0.AuxInt
 10156  		ptr := v_0.Args[0]
 10157  		idx := v.Args[1]
 10158  		val := v.Args[2]
 10159  		mem := v.Args[3]
 10160  		v.reset(Op386MOVSDstoreidx8)
 10161  		v.AuxInt = int64(int32(c + d))
 10162  		v.Aux = sym
 10163  		v.AddArg(ptr)
 10164  		v.AddArg(idx)
 10165  		v.AddArg(val)
 10166  		v.AddArg(mem)
 10167  		return true
 10168  	}
 10169  	// match: (MOVSDstoreidx8 [c] {sym} ptr (ADDLconst [d] idx) val mem)
 10170  	// cond:
 10171  	// result: (MOVSDstoreidx8 [int64(int32(c+8*d))] {sym} ptr idx val mem)
 10172  	for {
 10173  		c := v.AuxInt
 10174  		sym := v.Aux
 10175  		_ = v.Args[3]
 10176  		ptr := v.Args[0]
 10177  		v_1 := v.Args[1]
 10178  		if v_1.Op != Op386ADDLconst {
 10179  			break
 10180  		}
 10181  		d := v_1.AuxInt
 10182  		idx := v_1.Args[0]
 10183  		val := v.Args[2]
 10184  		mem := v.Args[3]
 10185  		v.reset(Op386MOVSDstoreidx8)
 10186  		v.AuxInt = int64(int32(c + 8*d))
 10187  		v.Aux = sym
 10188  		v.AddArg(ptr)
 10189  		v.AddArg(idx)
 10190  		v.AddArg(val)
 10191  		v.AddArg(mem)
 10192  		return true
 10193  	}
 10194  	return false
 10195  }
 10196  func rewriteValue386_Op386MOVSSconst_0(v *Value) bool {
 10197  	b := v.Block
 10198  	_ = b
 10199  	config := b.Func.Config
 10200  	_ = config
 10201  	typ := &b.Func.Config.Types
 10202  	_ = typ
 10203  	// match: (MOVSSconst [c])
 10204  	// cond: config.ctxt.Flag_shared
 10205  	// result: (MOVSSconst2 (MOVSSconst1 [c]))
 10206  	for {
 10207  		c := v.AuxInt
 10208  		if !(config.ctxt.Flag_shared) {
 10209  			break
 10210  		}
 10211  		v.reset(Op386MOVSSconst2)
 10212  		v0 := b.NewValue0(v.Pos, Op386MOVSSconst1, typ.UInt32)
 10213  		v0.AuxInt = c
 10214  		v.AddArg(v0)
 10215  		return true
 10216  	}
 10217  	return false
 10218  }
 10219  func rewriteValue386_Op386MOVSSload_0(v *Value) bool {
 10220  	b := v.Block
 10221  	_ = b
 10222  	config := b.Func.Config
 10223  	_ = config
 10224  	// match: (MOVSSload [off1] {sym} (ADDLconst [off2] ptr) mem)
 10225  	// cond: is32Bit(off1+off2)
 10226  	// result: (MOVSSload [off1+off2] {sym} ptr mem)
 10227  	for {
 10228  		off1 := v.AuxInt
 10229  		sym := v.Aux
 10230  		_ = v.Args[1]
 10231  		v_0 := v.Args[0]
 10232  		if v_0.Op != Op386ADDLconst {
 10233  			break
 10234  		}
 10235  		off2 := v_0.AuxInt
 10236  		ptr := v_0.Args[0]
 10237  		mem := v.Args[1]
 10238  		if !(is32Bit(off1 + off2)) {
 10239  			break
 10240  		}
 10241  		v.reset(Op386MOVSSload)
 10242  		v.AuxInt = off1 + off2
 10243  		v.Aux = sym
 10244  		v.AddArg(ptr)
 10245  		v.AddArg(mem)
 10246  		return true
 10247  	}
 10248  	// match: (MOVSSload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
 10249  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
 10250  	// result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem)
 10251  	for {
 10252  		off1 := v.AuxInt
 10253  		sym1 := v.Aux
 10254  		_ = v.Args[1]
 10255  		v_0 := v.Args[0]
 10256  		if v_0.Op != Op386LEAL {
 10257  			break
 10258  		}
 10259  		off2 := v_0.AuxInt
 10260  		sym2 := v_0.Aux
 10261  		base := v_0.Args[0]
 10262  		mem := v.Args[1]
 10263  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
 10264  			break
 10265  		}
 10266  		v.reset(Op386MOVSSload)
 10267  		v.AuxInt = off1 + off2
 10268  		v.Aux = mergeSym(sym1, sym2)
 10269  		v.AddArg(base)
 10270  		v.AddArg(mem)
 10271  		return true
 10272  	}
 10273  	// match: (MOVSSload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem)
 10274  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10275  	// result: (MOVSSloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
 10276  	for {
 10277  		off1 := v.AuxInt
 10278  		sym1 := v.Aux
 10279  		_ = v.Args[1]
 10280  		v_0 := v.Args[0]
 10281  		if v_0.Op != Op386LEAL1 {
 10282  			break
 10283  		}
 10284  		off2 := v_0.AuxInt
 10285  		sym2 := v_0.Aux
 10286  		_ = v_0.Args[1]
 10287  		ptr := v_0.Args[0]
 10288  		idx := v_0.Args[1]
 10289  		mem := v.Args[1]
 10290  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10291  			break
 10292  		}
 10293  		v.reset(Op386MOVSSloadidx1)
 10294  		v.AuxInt = off1 + off2
 10295  		v.Aux = mergeSym(sym1, sym2)
 10296  		v.AddArg(ptr)
 10297  		v.AddArg(idx)
 10298  		v.AddArg(mem)
 10299  		return true
 10300  	}
 10301  	// match: (MOVSSload [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) mem)
 10302  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10303  	// result: (MOVSSloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
 10304  	for {
 10305  		off1 := v.AuxInt
 10306  		sym1 := v.Aux
 10307  		_ = v.Args[1]
 10308  		v_0 := v.Args[0]
 10309  		if v_0.Op != Op386LEAL4 {
 10310  			break
 10311  		}
 10312  		off2 := v_0.AuxInt
 10313  		sym2 := v_0.Aux
 10314  		_ = v_0.Args[1]
 10315  		ptr := v_0.Args[0]
 10316  		idx := v_0.Args[1]
 10317  		mem := v.Args[1]
 10318  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10319  			break
 10320  		}
 10321  		v.reset(Op386MOVSSloadidx4)
 10322  		v.AuxInt = off1 + off2
 10323  		v.Aux = mergeSym(sym1, sym2)
 10324  		v.AddArg(ptr)
 10325  		v.AddArg(idx)
 10326  		v.AddArg(mem)
 10327  		return true
 10328  	}
 10329  	// match: (MOVSSload [off] {sym} (ADDL ptr idx) mem)
 10330  	// cond: ptr.Op != OpSB
 10331  	// result: (MOVSSloadidx1 [off] {sym} ptr idx mem)
 10332  	for {
 10333  		off := v.AuxInt
 10334  		sym := v.Aux
 10335  		_ = v.Args[1]
 10336  		v_0 := v.Args[0]
 10337  		if v_0.Op != Op386ADDL {
 10338  			break
 10339  		}
 10340  		_ = v_0.Args[1]
 10341  		ptr := v_0.Args[0]
 10342  		idx := v_0.Args[1]
 10343  		mem := v.Args[1]
 10344  		if !(ptr.Op != OpSB) {
 10345  			break
 10346  		}
 10347  		v.reset(Op386MOVSSloadidx1)
 10348  		v.AuxInt = off
 10349  		v.Aux = sym
 10350  		v.AddArg(ptr)
 10351  		v.AddArg(idx)
 10352  		v.AddArg(mem)
 10353  		return true
 10354  	}
 10355  	return false
 10356  }
 10357  func rewriteValue386_Op386MOVSSloadidx1_0(v *Value) bool {
 10358  	// match: (MOVSSloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem)
 10359  	// cond:
 10360  	// result: (MOVSSloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
 10361  	for {
 10362  		c := v.AuxInt
 10363  		sym := v.Aux
 10364  		_ = v.Args[2]
 10365  		v_0 := v.Args[0]
 10366  		if v_0.Op != Op386ADDLconst {
 10367  			break
 10368  		}
 10369  		d := v_0.AuxInt
 10370  		ptr := v_0.Args[0]
 10371  		idx := v.Args[1]
 10372  		mem := v.Args[2]
 10373  		v.reset(Op386MOVSSloadidx1)
 10374  		v.AuxInt = int64(int32(c + d))
 10375  		v.Aux = sym
 10376  		v.AddArg(ptr)
 10377  		v.AddArg(idx)
 10378  		v.AddArg(mem)
 10379  		return true
 10380  	}
 10381  	// match: (MOVSSloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem)
 10382  	// cond:
 10383  	// result: (MOVSSloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
 10384  	for {
 10385  		c := v.AuxInt
 10386  		sym := v.Aux
 10387  		_ = v.Args[2]
 10388  		ptr := v.Args[0]
 10389  		v_1 := v.Args[1]
 10390  		if v_1.Op != Op386ADDLconst {
 10391  			break
 10392  		}
 10393  		d := v_1.AuxInt
 10394  		idx := v_1.Args[0]
 10395  		mem := v.Args[2]
 10396  		v.reset(Op386MOVSSloadidx1)
 10397  		v.AuxInt = int64(int32(c + d))
 10398  		v.Aux = sym
 10399  		v.AddArg(ptr)
 10400  		v.AddArg(idx)
 10401  		v.AddArg(mem)
 10402  		return true
 10403  	}
 10404  	return false
 10405  }
 10406  func rewriteValue386_Op386MOVSSloadidx4_0(v *Value) bool {
 10407  	// match: (MOVSSloadidx4 [c] {sym} (ADDLconst [d] ptr) idx mem)
 10408  	// cond:
 10409  	// result: (MOVSSloadidx4 [int64(int32(c+d))] {sym} ptr idx mem)
 10410  	for {
 10411  		c := v.AuxInt
 10412  		sym := v.Aux
 10413  		_ = v.Args[2]
 10414  		v_0 := v.Args[0]
 10415  		if v_0.Op != Op386ADDLconst {
 10416  			break
 10417  		}
 10418  		d := v_0.AuxInt
 10419  		ptr := v_0.Args[0]
 10420  		idx := v.Args[1]
 10421  		mem := v.Args[2]
 10422  		v.reset(Op386MOVSSloadidx4)
 10423  		v.AuxInt = int64(int32(c + d))
 10424  		v.Aux = sym
 10425  		v.AddArg(ptr)
 10426  		v.AddArg(idx)
 10427  		v.AddArg(mem)
 10428  		return true
 10429  	}
 10430  	// match: (MOVSSloadidx4 [c] {sym} ptr (ADDLconst [d] idx) mem)
 10431  	// cond:
 10432  	// result: (MOVSSloadidx4 [int64(int32(c+4*d))] {sym} ptr idx mem)
 10433  	for {
 10434  		c := v.AuxInt
 10435  		sym := v.Aux
 10436  		_ = v.Args[2]
 10437  		ptr := v.Args[0]
 10438  		v_1 := v.Args[1]
 10439  		if v_1.Op != Op386ADDLconst {
 10440  			break
 10441  		}
 10442  		d := v_1.AuxInt
 10443  		idx := v_1.Args[0]
 10444  		mem := v.Args[2]
 10445  		v.reset(Op386MOVSSloadidx4)
 10446  		v.AuxInt = int64(int32(c + 4*d))
 10447  		v.Aux = sym
 10448  		v.AddArg(ptr)
 10449  		v.AddArg(idx)
 10450  		v.AddArg(mem)
 10451  		return true
 10452  	}
 10453  	return false
 10454  }
 10455  func rewriteValue386_Op386MOVSSstore_0(v *Value) bool {
 10456  	b := v.Block
 10457  	_ = b
 10458  	config := b.Func.Config
 10459  	_ = config
 10460  	// match: (MOVSSstore [off1] {sym} (ADDLconst [off2] ptr) val mem)
 10461  	// cond: is32Bit(off1+off2)
 10462  	// result: (MOVSSstore [off1+off2] {sym} ptr val mem)
 10463  	for {
 10464  		off1 := v.AuxInt
 10465  		sym := v.Aux
 10466  		_ = v.Args[2]
 10467  		v_0 := v.Args[0]
 10468  		if v_0.Op != Op386ADDLconst {
 10469  			break
 10470  		}
 10471  		off2 := v_0.AuxInt
 10472  		ptr := v_0.Args[0]
 10473  		val := v.Args[1]
 10474  		mem := v.Args[2]
 10475  		if !(is32Bit(off1 + off2)) {
 10476  			break
 10477  		}
 10478  		v.reset(Op386MOVSSstore)
 10479  		v.AuxInt = off1 + off2
 10480  		v.Aux = sym
 10481  		v.AddArg(ptr)
 10482  		v.AddArg(val)
 10483  		v.AddArg(mem)
 10484  		return true
 10485  	}
 10486  	// match: (MOVSSstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
 10487  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
 10488  	// result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
 10489  	for {
 10490  		off1 := v.AuxInt
 10491  		sym1 := v.Aux
 10492  		_ = v.Args[2]
 10493  		v_0 := v.Args[0]
 10494  		if v_0.Op != Op386LEAL {
 10495  			break
 10496  		}
 10497  		off2 := v_0.AuxInt
 10498  		sym2 := v_0.Aux
 10499  		base := v_0.Args[0]
 10500  		val := v.Args[1]
 10501  		mem := v.Args[2]
 10502  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
 10503  			break
 10504  		}
 10505  		v.reset(Op386MOVSSstore)
 10506  		v.AuxInt = off1 + off2
 10507  		v.Aux = mergeSym(sym1, sym2)
 10508  		v.AddArg(base)
 10509  		v.AddArg(val)
 10510  		v.AddArg(mem)
 10511  		return true
 10512  	}
 10513  	// match: (MOVSSstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem)
 10514  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10515  	// result: (MOVSSstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
 10516  	for {
 10517  		off1 := v.AuxInt
 10518  		sym1 := v.Aux
 10519  		_ = v.Args[2]
 10520  		v_0 := v.Args[0]
 10521  		if v_0.Op != Op386LEAL1 {
 10522  			break
 10523  		}
 10524  		off2 := v_0.AuxInt
 10525  		sym2 := v_0.Aux
 10526  		_ = v_0.Args[1]
 10527  		ptr := v_0.Args[0]
 10528  		idx := v_0.Args[1]
 10529  		val := v.Args[1]
 10530  		mem := v.Args[2]
 10531  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10532  			break
 10533  		}
 10534  		v.reset(Op386MOVSSstoreidx1)
 10535  		v.AuxInt = off1 + off2
 10536  		v.Aux = mergeSym(sym1, sym2)
 10537  		v.AddArg(ptr)
 10538  		v.AddArg(idx)
 10539  		v.AddArg(val)
 10540  		v.AddArg(mem)
 10541  		return true
 10542  	}
 10543  	// match: (MOVSSstore [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) val mem)
 10544  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10545  	// result: (MOVSSstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
 10546  	for {
 10547  		off1 := v.AuxInt
 10548  		sym1 := v.Aux
 10549  		_ = v.Args[2]
 10550  		v_0 := v.Args[0]
 10551  		if v_0.Op != Op386LEAL4 {
 10552  			break
 10553  		}
 10554  		off2 := v_0.AuxInt
 10555  		sym2 := v_0.Aux
 10556  		_ = v_0.Args[1]
 10557  		ptr := v_0.Args[0]
 10558  		idx := v_0.Args[1]
 10559  		val := v.Args[1]
 10560  		mem := v.Args[2]
 10561  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 10562  			break
 10563  		}
 10564  		v.reset(Op386MOVSSstoreidx4)
 10565  		v.AuxInt = off1 + off2
 10566  		v.Aux = mergeSym(sym1, sym2)
 10567  		v.AddArg(ptr)
 10568  		v.AddArg(idx)
 10569  		v.AddArg(val)
 10570  		v.AddArg(mem)
 10571  		return true
 10572  	}
 10573  	// match: (MOVSSstore [off] {sym} (ADDL ptr idx) val mem)
 10574  	// cond: ptr.Op != OpSB
 10575  	// result: (MOVSSstoreidx1 [off] {sym} ptr idx val mem)
 10576  	for {
 10577  		off := v.AuxInt
 10578  		sym := v.Aux
 10579  		_ = v.Args[2]
 10580  		v_0 := v.Args[0]
 10581  		if v_0.Op != Op386ADDL {
 10582  			break
 10583  		}
 10584  		_ = v_0.Args[1]
 10585  		ptr := v_0.Args[0]
 10586  		idx := v_0.Args[1]
 10587  		val := v.Args[1]
 10588  		mem := v.Args[2]
 10589  		if !(ptr.Op != OpSB) {
 10590  			break
 10591  		}
 10592  		v.reset(Op386MOVSSstoreidx1)
 10593  		v.AuxInt = off
 10594  		v.Aux = sym
 10595  		v.AddArg(ptr)
 10596  		v.AddArg(idx)
 10597  		v.AddArg(val)
 10598  		v.AddArg(mem)
 10599  		return true
 10600  	}
 10601  	return false
 10602  }
 10603  func rewriteValue386_Op386MOVSSstoreidx1_0(v *Value) bool {
 10604  	// match: (MOVSSstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem)
 10605  	// cond:
 10606  	// result: (MOVSSstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
 10607  	for {
 10608  		c := v.AuxInt
 10609  		sym := v.Aux
 10610  		_ = v.Args[3]
 10611  		v_0 := v.Args[0]
 10612  		if v_0.Op != Op386ADDLconst {
 10613  			break
 10614  		}
 10615  		d := v_0.AuxInt
 10616  		ptr := v_0.Args[0]
 10617  		idx := v.Args[1]
 10618  		val := v.Args[2]
 10619  		mem := v.Args[3]
 10620  		v.reset(Op386MOVSSstoreidx1)
 10621  		v.AuxInt = int64(int32(c + d))
 10622  		v.Aux = sym
 10623  		v.AddArg(ptr)
 10624  		v.AddArg(idx)
 10625  		v.AddArg(val)
 10626  		v.AddArg(mem)
 10627  		return true
 10628  	}
 10629  	// match: (MOVSSstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem)
 10630  	// cond:
 10631  	// result: (MOVSSstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
 10632  	for {
 10633  		c := v.AuxInt
 10634  		sym := v.Aux
 10635  		_ = v.Args[3]
 10636  		ptr := v.Args[0]
 10637  		v_1 := v.Args[1]
 10638  		if v_1.Op != Op386ADDLconst {
 10639  			break
 10640  		}
 10641  		d := v_1.AuxInt
 10642  		idx := v_1.Args[0]
 10643  		val := v.Args[2]
 10644  		mem := v.Args[3]
 10645  		v.reset(Op386MOVSSstoreidx1)
 10646  		v.AuxInt = int64(int32(c + d))
 10647  		v.Aux = sym
 10648  		v.AddArg(ptr)
 10649  		v.AddArg(idx)
 10650  		v.AddArg(val)
 10651  		v.AddArg(mem)
 10652  		return true
 10653  	}
 10654  	return false
 10655  }
 10656  func rewriteValue386_Op386MOVSSstoreidx4_0(v *Value) bool {
 10657  	// match: (MOVSSstoreidx4 [c] {sym} (ADDLconst [d] ptr) idx val mem)
 10658  	// cond:
 10659  	// result: (MOVSSstoreidx4 [int64(int32(c+d))] {sym} ptr idx val mem)
 10660  	for {
 10661  		c := v.AuxInt
 10662  		sym := v.Aux
 10663  		_ = v.Args[3]
 10664  		v_0 := v.Args[0]
 10665  		if v_0.Op != Op386ADDLconst {
 10666  			break
 10667  		}
 10668  		d := v_0.AuxInt
 10669  		ptr := v_0.Args[0]
 10670  		idx := v.Args[1]
 10671  		val := v.Args[2]
 10672  		mem := v.Args[3]
 10673  		v.reset(Op386MOVSSstoreidx4)
 10674  		v.AuxInt = int64(int32(c + d))
 10675  		v.Aux = sym
 10676  		v.AddArg(ptr)
 10677  		v.AddArg(idx)
 10678  		v.AddArg(val)
 10679  		v.AddArg(mem)
 10680  		return true
 10681  	}
 10682  	// match: (MOVSSstoreidx4 [c] {sym} ptr (ADDLconst [d] idx) val mem)
 10683  	// cond:
 10684  	// result: (MOVSSstoreidx4 [int64(int32(c+4*d))] {sym} ptr idx val mem)
 10685  	for {
 10686  		c := v.AuxInt
 10687  		sym := v.Aux
 10688  		_ = v.Args[3]
 10689  		ptr := v.Args[0]
 10690  		v_1 := v.Args[1]
 10691  		if v_1.Op != Op386ADDLconst {
 10692  			break
 10693  		}
 10694  		d := v_1.AuxInt
 10695  		idx := v_1.Args[0]
 10696  		val := v.Args[2]
 10697  		mem := v.Args[3]
 10698  		v.reset(Op386MOVSSstoreidx4)
 10699  		v.AuxInt = int64(int32(c + 4*d))
 10700  		v.Aux = sym
 10701  		v.AddArg(ptr)
 10702  		v.AddArg(idx)
 10703  		v.AddArg(val)
 10704  		v.AddArg(mem)
 10705  		return true
 10706  	}
 10707  	return false
 10708  }
 10709  func rewriteValue386_Op386MOVWLSX_0(v *Value) bool {
 10710  	b := v.Block
 10711  	_ = b
 10712  	// match: (MOVWLSX x:(MOVWload [off] {sym} ptr mem))
 10713  	// cond: x.Uses == 1 && clobber(x)
 10714  	// result: @x.Block (MOVWLSXload <v.Type> [off] {sym} ptr mem)
 10715  	for {
 10716  		x := v.Args[0]
 10717  		if x.Op != Op386MOVWload {
 10718  			break
 10719  		}
 10720  		off := x.AuxInt
 10721  		sym := x.Aux
 10722  		_ = x.Args[1]
 10723  		ptr := x.Args[0]
 10724  		mem := x.Args[1]
 10725  		if !(x.Uses == 1 && clobber(x)) {
 10726  			break
 10727  		}
 10728  		b = x.Block
 10729  		v0 := b.NewValue0(x.Pos, Op386MOVWLSXload, v.Type)
 10730  		v.reset(OpCopy)
 10731  		v.AddArg(v0)
 10732  		v0.AuxInt = off
 10733  		v0.Aux = sym
 10734  		v0.AddArg(ptr)
 10735  		v0.AddArg(mem)
 10736  		return true
 10737  	}
 10738  	// match: (MOVWLSX (ANDLconst [c] x))
 10739  	// cond: c & 0x8000 == 0
 10740  	// result: (ANDLconst [c & 0x7fff] x)
 10741  	for {
 10742  		v_0 := v.Args[0]
 10743  		if v_0.Op != Op386ANDLconst {
 10744  			break
 10745  		}
 10746  		c := v_0.AuxInt
 10747  		x := v_0.Args[0]
 10748  		if !(c&0x8000 == 0) {
 10749  			break
 10750  		}
 10751  		v.reset(Op386ANDLconst)
 10752  		v.AuxInt = c & 0x7fff
 10753  		v.AddArg(x)
 10754  		return true
 10755  	}
 10756  	return false
 10757  }
 10758  func rewriteValue386_Op386MOVWLSXload_0(v *Value) bool {
 10759  	b := v.Block
 10760  	_ = b
 10761  	config := b.Func.Config
 10762  	_ = config
 10763  	// match: (MOVWLSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _))
 10764  	// cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
 10765  	// result: (MOVWLSX x)
 10766  	for {
 10767  		off := v.AuxInt
 10768  		sym := v.Aux
 10769  		_ = v.Args[1]
 10770  		ptr := v.Args[0]
 10771  		v_1 := v.Args[1]
 10772  		if v_1.Op != Op386MOVWstore {
 10773  			break
 10774  		}
 10775  		off2 := v_1.AuxInt
 10776  		sym2 := v_1.Aux
 10777  		_ = v_1.Args[2]
 10778  		ptr2 := v_1.Args[0]
 10779  		x := v_1.Args[1]
 10780  		if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
 10781  			break
 10782  		}
 10783  		v.reset(Op386MOVWLSX)
 10784  		v.AddArg(x)
 10785  		return true
 10786  	}
 10787  	// match: (MOVWLSXload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
 10788  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
 10789  	// result: (MOVWLSXload [off1+off2] {mergeSym(sym1,sym2)} base mem)
 10790  	for {
 10791  		off1 := v.AuxInt
 10792  		sym1 := v.Aux
 10793  		_ = v.Args[1]
 10794  		v_0 := v.Args[0]
 10795  		if v_0.Op != Op386LEAL {
 10796  			break
 10797  		}
 10798  		off2 := v_0.AuxInt
 10799  		sym2 := v_0.Aux
 10800  		base := v_0.Args[0]
 10801  		mem := v.Args[1]
 10802  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
 10803  			break
 10804  		}
 10805  		v.reset(Op386MOVWLSXload)
 10806  		v.AuxInt = off1 + off2
 10807  		v.Aux = mergeSym(sym1, sym2)
 10808  		v.AddArg(base)
 10809  		v.AddArg(mem)
 10810  		return true
 10811  	}
 10812  	return false
 10813  }
 10814  func rewriteValue386_Op386MOVWLZX_0(v *Value) bool {
 10815  	b := v.Block
 10816  	_ = b
 10817  	// match: (MOVWLZX x:(MOVWload [off] {sym} ptr mem))
 10818  	// cond: x.Uses == 1 && clobber(x)
 10819  	// result: @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
 10820  	for {
 10821  		x := v.Args[0]
 10822  		if x.Op != Op386MOVWload {
 10823  			break
 10824  		}
 10825  		off := x.AuxInt
 10826  		sym := x.Aux
 10827  		_ = x.Args[1]
 10828  		ptr := x.Args[0]
 10829  		mem := x.Args[1]
 10830  		if !(x.Uses == 1 && clobber(x)) {
 10831  			break
 10832  		}
 10833  		b = x.Block
 10834  		v0 := b.NewValue0(x.Pos, Op386MOVWload, v.Type)
 10835  		v.reset(OpCopy)
 10836  		v.AddArg(v0)
 10837  		v0.AuxInt = off
 10838  		v0.Aux = sym
 10839  		v0.AddArg(ptr)
 10840  		v0.AddArg(mem)
 10841  		return true
 10842  	}
 10843  	// match: (MOVWLZX x:(MOVWloadidx1 [off] {sym} ptr idx mem))
 10844  	// cond: x.Uses == 1 && clobber(x)
 10845  	// result: @x.Block (MOVWloadidx1 <v.Type> [off] {sym} ptr idx mem)
 10846  	for {
 10847  		x := v.Args[0]
 10848  		if x.Op != Op386MOVWloadidx1 {
 10849  			break
 10850  		}
 10851  		off := x.AuxInt
 10852  		sym := x.Aux
 10853  		_ = x.Args[2]
 10854  		ptr := x.Args[0]
 10855  		idx := x.Args[1]
 10856  		mem := x.Args[2]
 10857  		if !(x.Uses == 1 && clobber(x)) {
 10858  			break
 10859  		}
 10860  		b = x.Block
 10861  		v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type)
 10862  		v.reset(OpCopy)
 10863  		v.AddArg(v0)
 10864  		v0.AuxInt = off
 10865  		v0.Aux = sym
 10866  		v0.AddArg(ptr)
 10867  		v0.AddArg(idx)
 10868  		v0.AddArg(mem)
 10869  		return true
 10870  	}
 10871  	// match: (MOVWLZX x:(MOVWloadidx2 [off] {sym} ptr idx mem))
 10872  	// cond: x.Uses == 1 && clobber(x)
 10873  	// result: @x.Block (MOVWloadidx2 <v.Type> [off] {sym} ptr idx mem)
 10874  	for {
 10875  		x := v.Args[0]
 10876  		if x.Op != Op386MOVWloadidx2 {
 10877  			break
 10878  		}
 10879  		off := x.AuxInt
 10880  		sym := x.Aux
 10881  		_ = x.Args[2]
 10882  		ptr := x.Args[0]
 10883  		idx := x.Args[1]
 10884  		mem := x.Args[2]
 10885  		if !(x.Uses == 1 && clobber(x)) {
 10886  			break
 10887  		}
 10888  		b = x.Block
 10889  		v0 := b.NewValue0(v.Pos, Op386MOVWloadidx2, v.Type)
 10890  		v.reset(OpCopy)
 10891  		v.AddArg(v0)
 10892  		v0.AuxInt = off
 10893  		v0.Aux = sym
 10894  		v0.AddArg(ptr)
 10895  		v0.AddArg(idx)
 10896  		v0.AddArg(mem)
 10897  		return true
 10898  	}
 10899  	// match: (MOVWLZX (ANDLconst [c] x))
 10900  	// cond:
 10901  	// result: (ANDLconst [c & 0xffff] x)
 10902  	for {
 10903  		v_0 := v.Args[0]
 10904  		if v_0.Op != Op386ANDLconst {
 10905  			break
 10906  		}
 10907  		c := v_0.AuxInt
 10908  		x := v_0.Args[0]
 10909  		v.reset(Op386ANDLconst)
 10910  		v.AuxInt = c & 0xffff
 10911  		v.AddArg(x)
 10912  		return true
 10913  	}
 10914  	return false
 10915  }
 10916  func rewriteValue386_Op386MOVWload_0(v *Value) bool {
 10917  	b := v.Block
 10918  	_ = b
 10919  	config := b.Func.Config
 10920  	_ = config
 10921  	// match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _))
 10922  	// cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
 10923  	// result: (MOVWLZX x)
 10924  	for {
 10925  		off := v.AuxInt
 10926  		sym := v.Aux
 10927  		_ = v.Args[1]
 10928  		ptr := v.Args[0]
 10929  		v_1 := v.Args[1]
 10930  		if v_1.Op != Op386MOVWstore {
 10931  			break
 10932  		}
 10933  		off2 := v_1.AuxInt
 10934  		sym2 := v_1.Aux
 10935  		_ = v_1.Args[2]
 10936  		ptr2 := v_1.Args[0]
 10937  		x := v_1.Args[1]
 10938  		if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
 10939  			break
 10940  		}
 10941  		v.reset(Op386MOVWLZX)
 10942  		v.AddArg(x)
 10943  		return true
 10944  	}
 10945  	// match: (MOVWload [off1] {sym} (ADDLconst [off2] ptr) mem)
 10946  	// cond: is32Bit(off1+off2)
 10947  	// result: (MOVWload [off1+off2] {sym} ptr mem)
 10948  	for {
 10949  		off1 := v.AuxInt
 10950  		sym := v.Aux
 10951  		_ = v.Args[1]
 10952  		v_0 := v.Args[0]
 10953  		if v_0.Op != Op386ADDLconst {
 10954  			break
 10955  		}
 10956  		off2 := v_0.AuxInt
 10957  		ptr := v_0.Args[0]
 10958  		mem := v.Args[1]
 10959  		if !(is32Bit(off1 + off2)) {
 10960  			break
 10961  		}
 10962  		v.reset(Op386MOVWload)
 10963  		v.AuxInt = off1 + off2
 10964  		v.Aux = sym
 10965  		v.AddArg(ptr)
 10966  		v.AddArg(mem)
 10967  		return true
 10968  	}
 10969  	// match: (MOVWload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
 10970  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
 10971  	// result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem)
 10972  	for {
 10973  		off1 := v.AuxInt
 10974  		sym1 := v.Aux
 10975  		_ = v.Args[1]
 10976  		v_0 := v.Args[0]
 10977  		if v_0.Op != Op386LEAL {
 10978  			break
 10979  		}
 10980  		off2 := v_0.AuxInt
 10981  		sym2 := v_0.Aux
 10982  		base := v_0.Args[0]
 10983  		mem := v.Args[1]
 10984  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
 10985  			break
 10986  		}
 10987  		v.reset(Op386MOVWload)
 10988  		v.AuxInt = off1 + off2
 10989  		v.Aux = mergeSym(sym1, sym2)
 10990  		v.AddArg(base)
 10991  		v.AddArg(mem)
 10992  		return true
 10993  	}
 10994  	// match: (MOVWload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem)
 10995  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 10996  	// result: (MOVWloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
 10997  	for {
 10998  		off1 := v.AuxInt
 10999  		sym1 := v.Aux
 11000  		_ = v.Args[1]
 11001  		v_0 := v.Args[0]
 11002  		if v_0.Op != Op386LEAL1 {
 11003  			break
 11004  		}
 11005  		off2 := v_0.AuxInt
 11006  		sym2 := v_0.Aux
 11007  		_ = v_0.Args[1]
 11008  		ptr := v_0.Args[0]
 11009  		idx := v_0.Args[1]
 11010  		mem := v.Args[1]
 11011  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 11012  			break
 11013  		}
 11014  		v.reset(Op386MOVWloadidx1)
 11015  		v.AuxInt = off1 + off2
 11016  		v.Aux = mergeSym(sym1, sym2)
 11017  		v.AddArg(ptr)
 11018  		v.AddArg(idx)
 11019  		v.AddArg(mem)
 11020  		return true
 11021  	}
 11022  	// match: (MOVWload [off1] {sym1} (LEAL2 [off2] {sym2} ptr idx) mem)
 11023  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 11024  	// result: (MOVWloadidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
 11025  	for {
 11026  		off1 := v.AuxInt
 11027  		sym1 := v.Aux
 11028  		_ = v.Args[1]
 11029  		v_0 := v.Args[0]
 11030  		if v_0.Op != Op386LEAL2 {
 11031  			break
 11032  		}
 11033  		off2 := v_0.AuxInt
 11034  		sym2 := v_0.Aux
 11035  		_ = v_0.Args[1]
 11036  		ptr := v_0.Args[0]
 11037  		idx := v_0.Args[1]
 11038  		mem := v.Args[1]
 11039  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 11040  			break
 11041  		}
 11042  		v.reset(Op386MOVWloadidx2)
 11043  		v.AuxInt = off1 + off2
 11044  		v.Aux = mergeSym(sym1, sym2)
 11045  		v.AddArg(ptr)
 11046  		v.AddArg(idx)
 11047  		v.AddArg(mem)
 11048  		return true
 11049  	}
 11050  	// match: (MOVWload [off] {sym} (ADDL ptr idx) mem)
 11051  	// cond: ptr.Op != OpSB
 11052  	// result: (MOVWloadidx1 [off] {sym} ptr idx mem)
 11053  	for {
 11054  		off := v.AuxInt
 11055  		sym := v.Aux
 11056  		_ = v.Args[1]
 11057  		v_0 := v.Args[0]
 11058  		if v_0.Op != Op386ADDL {
 11059  			break
 11060  		}
 11061  		_ = v_0.Args[1]
 11062  		ptr := v_0.Args[0]
 11063  		idx := v_0.Args[1]
 11064  		mem := v.Args[1]
 11065  		if !(ptr.Op != OpSB) {
 11066  			break
 11067  		}
 11068  		v.reset(Op386MOVWloadidx1)
 11069  		v.AuxInt = off
 11070  		v.Aux = sym
 11071  		v.AddArg(ptr)
 11072  		v.AddArg(idx)
 11073  		v.AddArg(mem)
 11074  		return true
 11075  	}
 11076  	// match: (MOVWload [off] {sym} (SB) _)
 11077  	// cond: symIsRO(sym)
 11078  	// result: (MOVLconst [int64(read16(sym, off, config.BigEndian))])
 11079  	for {
 11080  		off := v.AuxInt
 11081  		sym := v.Aux
 11082  		_ = v.Args[1]
 11083  		v_0 := v.Args[0]
 11084  		if v_0.Op != OpSB {
 11085  			break
 11086  		}
 11087  		if !(symIsRO(sym)) {
 11088  			break
 11089  		}
 11090  		v.reset(Op386MOVLconst)
 11091  		v.AuxInt = int64(read16(sym, off, config.BigEndian))
 11092  		return true
 11093  	}
 11094  	return false
 11095  }
 11096  func rewriteValue386_Op386MOVWloadidx1_0(v *Value) bool {
 11097  	// match: (MOVWloadidx1 [c] {sym} ptr (SHLLconst [1] idx) mem)
 11098  	// cond:
 11099  	// result: (MOVWloadidx2 [c] {sym} ptr idx mem)
 11100  	for {
 11101  		c := v.AuxInt
 11102  		sym := v.Aux
 11103  		_ = v.Args[2]
 11104  		ptr := v.Args[0]
 11105  		v_1 := v.Args[1]
 11106  		if v_1.Op != Op386SHLLconst {
 11107  			break
 11108  		}
 11109  		if v_1.AuxInt != 1 {
 11110  			break
 11111  		}
 11112  		idx := v_1.Args[0]
 11113  		mem := v.Args[2]
 11114  		v.reset(Op386MOVWloadidx2)
 11115  		v.AuxInt = c
 11116  		v.Aux = sym
 11117  		v.AddArg(ptr)
 11118  		v.AddArg(idx)
 11119  		v.AddArg(mem)
 11120  		return true
 11121  	}
 11122  	// match: (MOVWloadidx1 [c] {sym} (SHLLconst [1] idx) ptr mem)
 11123  	// cond:
 11124  	// result: (MOVWloadidx2 [c] {sym} ptr idx mem)
 11125  	for {
 11126  		c := v.AuxInt
 11127  		sym := v.Aux
 11128  		_ = v.Args[2]
 11129  		v_0 := v.Args[0]
 11130  		if v_0.Op != Op386SHLLconst {
 11131  			break
 11132  		}
 11133  		if v_0.AuxInt != 1 {
 11134  			break
 11135  		}
 11136  		idx := v_0.Args[0]
 11137  		ptr := v.Args[1]
 11138  		mem := v.Args[2]
 11139  		v.reset(Op386MOVWloadidx2)
 11140  		v.AuxInt = c
 11141  		v.Aux = sym
 11142  		v.AddArg(ptr)
 11143  		v.AddArg(idx)
 11144  		v.AddArg(mem)
 11145  		return true
 11146  	}
 11147  	// match: (MOVWloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem)
 11148  	// cond:
 11149  	// result: (MOVWloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
 11150  	for {
 11151  		c := v.AuxInt
 11152  		sym := v.Aux
 11153  		_ = v.Args[2]
 11154  		v_0 := v.Args[0]
 11155  		if v_0.Op != Op386ADDLconst {
 11156  			break
 11157  		}
 11158  		d := v_0.AuxInt
 11159  		ptr := v_0.Args[0]
 11160  		idx := v.Args[1]
 11161  		mem := v.Args[2]
 11162  		v.reset(Op386MOVWloadidx1)
 11163  		v.AuxInt = int64(int32(c + d))
 11164  		v.Aux = sym
 11165  		v.AddArg(ptr)
 11166  		v.AddArg(idx)
 11167  		v.AddArg(mem)
 11168  		return true
 11169  	}
 11170  	// match: (MOVWloadidx1 [c] {sym} idx (ADDLconst [d] ptr) mem)
 11171  	// cond:
 11172  	// result: (MOVWloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
 11173  	for {
 11174  		c := v.AuxInt
 11175  		sym := v.Aux
 11176  		_ = v.Args[2]
 11177  		idx := v.Args[0]
 11178  		v_1 := v.Args[1]
 11179  		if v_1.Op != Op386ADDLconst {
 11180  			break
 11181  		}
 11182  		d := v_1.AuxInt
 11183  		ptr := v_1.Args[0]
 11184  		mem := v.Args[2]
 11185  		v.reset(Op386MOVWloadidx1)
 11186  		v.AuxInt = int64(int32(c + d))
 11187  		v.Aux = sym
 11188  		v.AddArg(ptr)
 11189  		v.AddArg(idx)
 11190  		v.AddArg(mem)
 11191  		return true
 11192  	}
 11193  	// match: (MOVWloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem)
 11194  	// cond:
 11195  	// result: (MOVWloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
 11196  	for {
 11197  		c := v.AuxInt
 11198  		sym := v.Aux
 11199  		_ = v.Args[2]
 11200  		ptr := v.Args[0]
 11201  		v_1 := v.Args[1]
 11202  		if v_1.Op != Op386ADDLconst {
 11203  			break
 11204  		}
 11205  		d := v_1.AuxInt
 11206  		idx := v_1.Args[0]
 11207  		mem := v.Args[2]
 11208  		v.reset(Op386MOVWloadidx1)
 11209  		v.AuxInt = int64(int32(c + d))
 11210  		v.Aux = sym
 11211  		v.AddArg(ptr)
 11212  		v.AddArg(idx)
 11213  		v.AddArg(mem)
 11214  		return true
 11215  	}
 11216  	// match: (MOVWloadidx1 [c] {sym} (ADDLconst [d] idx) ptr mem)
 11217  	// cond:
 11218  	// result: (MOVWloadidx1 [int64(int32(c+d))] {sym} ptr idx mem)
 11219  	for {
 11220  		c := v.AuxInt
 11221  		sym := v.Aux
 11222  		_ = v.Args[2]
 11223  		v_0 := v.Args[0]
 11224  		if v_0.Op != Op386ADDLconst {
 11225  			break
 11226  		}
 11227  		d := v_0.AuxInt
 11228  		idx := v_0.Args[0]
 11229  		ptr := v.Args[1]
 11230  		mem := v.Args[2]
 11231  		v.reset(Op386MOVWloadidx1)
 11232  		v.AuxInt = int64(int32(c + d))
 11233  		v.Aux = sym
 11234  		v.AddArg(ptr)
 11235  		v.AddArg(idx)
 11236  		v.AddArg(mem)
 11237  		return true
 11238  	}
 11239  	return false
 11240  }
 11241  func rewriteValue386_Op386MOVWloadidx2_0(v *Value) bool {
 11242  	// match: (MOVWloadidx2 [c] {sym} (ADDLconst [d] ptr) idx mem)
 11243  	// cond:
 11244  	// result: (MOVWloadidx2 [int64(int32(c+d))] {sym} ptr idx mem)
 11245  	for {
 11246  		c := v.AuxInt
 11247  		sym := v.Aux
 11248  		_ = v.Args[2]
 11249  		v_0 := v.Args[0]
 11250  		if v_0.Op != Op386ADDLconst {
 11251  			break
 11252  		}
 11253  		d := v_0.AuxInt
 11254  		ptr := v_0.Args[0]
 11255  		idx := v.Args[1]
 11256  		mem := v.Args[2]
 11257  		v.reset(Op386MOVWloadidx2)
 11258  		v.AuxInt = int64(int32(c + d))
 11259  		v.Aux = sym
 11260  		v.AddArg(ptr)
 11261  		v.AddArg(idx)
 11262  		v.AddArg(mem)
 11263  		return true
 11264  	}
 11265  	// match: (MOVWloadidx2 [c] {sym} ptr (ADDLconst [d] idx) mem)
 11266  	// cond:
 11267  	// result: (MOVWloadidx2 [int64(int32(c+2*d))] {sym} ptr idx mem)
 11268  	for {
 11269  		c := v.AuxInt
 11270  		sym := v.Aux
 11271  		_ = v.Args[2]
 11272  		ptr := v.Args[0]
 11273  		v_1 := v.Args[1]
 11274  		if v_1.Op != Op386ADDLconst {
 11275  			break
 11276  		}
 11277  		d := v_1.AuxInt
 11278  		idx := v_1.Args[0]
 11279  		mem := v.Args[2]
 11280  		v.reset(Op386MOVWloadidx2)
 11281  		v.AuxInt = int64(int32(c + 2*d))
 11282  		v.Aux = sym
 11283  		v.AddArg(ptr)
 11284  		v.AddArg(idx)
 11285  		v.AddArg(mem)
 11286  		return true
 11287  	}
 11288  	return false
 11289  }
 11290  func rewriteValue386_Op386MOVWstore_0(v *Value) bool {
 11291  	b := v.Block
 11292  	_ = b
 11293  	config := b.Func.Config
 11294  	_ = config
 11295  	// match: (MOVWstore [off] {sym} ptr (MOVWLSX x) mem)
 11296  	// cond:
 11297  	// result: (MOVWstore [off] {sym} ptr x mem)
 11298  	for {
 11299  		off := v.AuxInt
 11300  		sym := v.Aux
 11301  		_ = v.Args[2]
 11302  		ptr := v.Args[0]
 11303  		v_1 := v.Args[1]
 11304  		if v_1.Op != Op386MOVWLSX {
 11305  			break
 11306  		}
 11307  		x := v_1.Args[0]
 11308  		mem := v.Args[2]
 11309  		v.reset(Op386MOVWstore)
 11310  		v.AuxInt = off
 11311  		v.Aux = sym
 11312  		v.AddArg(ptr)
 11313  		v.AddArg(x)
 11314  		v.AddArg(mem)
 11315  		return true
 11316  	}
 11317  	// match: (MOVWstore [off] {sym} ptr (MOVWLZX x) mem)
 11318  	// cond:
 11319  	// result: (MOVWstore [off] {sym} ptr x mem)
 11320  	for {
 11321  		off := v.AuxInt
 11322  		sym := v.Aux
 11323  		_ = v.Args[2]
 11324  		ptr := v.Args[0]
 11325  		v_1 := v.Args[1]
 11326  		if v_1.Op != Op386MOVWLZX {
 11327  			break
 11328  		}
 11329  		x := v_1.Args[0]
 11330  		mem := v.Args[2]
 11331  		v.reset(Op386MOVWstore)
 11332  		v.AuxInt = off
 11333  		v.Aux = sym
 11334  		v.AddArg(ptr)
 11335  		v.AddArg(x)
 11336  		v.AddArg(mem)
 11337  		return true
 11338  	}
 11339  	// match: (MOVWstore [off1] {sym} (ADDLconst [off2] ptr) val mem)
 11340  	// cond: is32Bit(off1+off2)
 11341  	// result: (MOVWstore [off1+off2] {sym} ptr val mem)
 11342  	for {
 11343  		off1 := v.AuxInt
 11344  		sym := v.Aux
 11345  		_ = v.Args[2]
 11346  		v_0 := v.Args[0]
 11347  		if v_0.Op != Op386ADDLconst {
 11348  			break
 11349  		}
 11350  		off2 := v_0.AuxInt
 11351  		ptr := v_0.Args[0]
 11352  		val := v.Args[1]
 11353  		mem := v.Args[2]
 11354  		if !(is32Bit(off1 + off2)) {
 11355  			break
 11356  		}
 11357  		v.reset(Op386MOVWstore)
 11358  		v.AuxInt = off1 + off2
 11359  		v.Aux = sym
 11360  		v.AddArg(ptr)
 11361  		v.AddArg(val)
 11362  		v.AddArg(mem)
 11363  		return true
 11364  	}
 11365  	// match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem)
 11366  	// cond: validOff(off)
 11367  	// result: (MOVWstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem)
 11368  	for {
 11369  		off := v.AuxInt
 11370  		sym := v.Aux
 11371  		_ = v.Args[2]
 11372  		ptr := v.Args[0]
 11373  		v_1 := v.Args[1]
 11374  		if v_1.Op != Op386MOVLconst {
 11375  			break
 11376  		}
 11377  		c := v_1.AuxInt
 11378  		mem := v.Args[2]
 11379  		if !(validOff(off)) {
 11380  			break
 11381  		}
 11382  		v.reset(Op386MOVWstoreconst)
 11383  		v.AuxInt = makeValAndOff(int64(int16(c)), off)
 11384  		v.Aux = sym
 11385  		v.AddArg(ptr)
 11386  		v.AddArg(mem)
 11387  		return true
 11388  	}
 11389  	// match: (MOVWstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
 11390  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
 11391  	// result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
 11392  	for {
 11393  		off1 := v.AuxInt
 11394  		sym1 := v.Aux
 11395  		_ = v.Args[2]
 11396  		v_0 := v.Args[0]
 11397  		if v_0.Op != Op386LEAL {
 11398  			break
 11399  		}
 11400  		off2 := v_0.AuxInt
 11401  		sym2 := v_0.Aux
 11402  		base := v_0.Args[0]
 11403  		val := v.Args[1]
 11404  		mem := v.Args[2]
 11405  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
 11406  			break
 11407  		}
 11408  		v.reset(Op386MOVWstore)
 11409  		v.AuxInt = off1 + off2
 11410  		v.Aux = mergeSym(sym1, sym2)
 11411  		v.AddArg(base)
 11412  		v.AddArg(val)
 11413  		v.AddArg(mem)
 11414  		return true
 11415  	}
 11416  	// match: (MOVWstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem)
 11417  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 11418  	// result: (MOVWstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
 11419  	for {
 11420  		off1 := v.AuxInt
 11421  		sym1 := v.Aux
 11422  		_ = v.Args[2]
 11423  		v_0 := v.Args[0]
 11424  		if v_0.Op != Op386LEAL1 {
 11425  			break
 11426  		}
 11427  		off2 := v_0.AuxInt
 11428  		sym2 := v_0.Aux
 11429  		_ = v_0.Args[1]
 11430  		ptr := v_0.Args[0]
 11431  		idx := v_0.Args[1]
 11432  		val := v.Args[1]
 11433  		mem := v.Args[2]
 11434  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 11435  			break
 11436  		}
 11437  		v.reset(Op386MOVWstoreidx1)
 11438  		v.AuxInt = off1 + off2
 11439  		v.Aux = mergeSym(sym1, sym2)
 11440  		v.AddArg(ptr)
 11441  		v.AddArg(idx)
 11442  		v.AddArg(val)
 11443  		v.AddArg(mem)
 11444  		return true
 11445  	}
 11446  	// match: (MOVWstore [off1] {sym1} (LEAL2 [off2] {sym2} ptr idx) val mem)
 11447  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 11448  	// result: (MOVWstoreidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
 11449  	for {
 11450  		off1 := v.AuxInt
 11451  		sym1 := v.Aux
 11452  		_ = v.Args[2]
 11453  		v_0 := v.Args[0]
 11454  		if v_0.Op != Op386LEAL2 {
 11455  			break
 11456  		}
 11457  		off2 := v_0.AuxInt
 11458  		sym2 := v_0.Aux
 11459  		_ = v_0.Args[1]
 11460  		ptr := v_0.Args[0]
 11461  		idx := v_0.Args[1]
 11462  		val := v.Args[1]
 11463  		mem := v.Args[2]
 11464  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 11465  			break
 11466  		}
 11467  		v.reset(Op386MOVWstoreidx2)
 11468  		v.AuxInt = off1 + off2
 11469  		v.Aux = mergeSym(sym1, sym2)
 11470  		v.AddArg(ptr)
 11471  		v.AddArg(idx)
 11472  		v.AddArg(val)
 11473  		v.AddArg(mem)
 11474  		return true
 11475  	}
 11476  	// match: (MOVWstore [off] {sym} (ADDL ptr idx) val mem)
 11477  	// cond: ptr.Op != OpSB
 11478  	// result: (MOVWstoreidx1 [off] {sym} ptr idx val mem)
 11479  	for {
 11480  		off := v.AuxInt
 11481  		sym := v.Aux
 11482  		_ = v.Args[2]
 11483  		v_0 := v.Args[0]
 11484  		if v_0.Op != Op386ADDL {
 11485  			break
 11486  		}
 11487  		_ = v_0.Args[1]
 11488  		ptr := v_0.Args[0]
 11489  		idx := v_0.Args[1]
 11490  		val := v.Args[1]
 11491  		mem := v.Args[2]
 11492  		if !(ptr.Op != OpSB) {
 11493  			break
 11494  		}
 11495  		v.reset(Op386MOVWstoreidx1)
 11496  		v.AuxInt = off
 11497  		v.Aux = sym
 11498  		v.AddArg(ptr)
 11499  		v.AddArg(idx)
 11500  		v.AddArg(val)
 11501  		v.AddArg(mem)
 11502  		return true
 11503  	}
 11504  	// match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem))
 11505  	// cond: x.Uses == 1 && clobber(x)
 11506  	// result: (MOVLstore [i-2] {s} p w mem)
 11507  	for {
 11508  		i := v.AuxInt
 11509  		s := v.Aux
 11510  		_ = v.Args[2]
 11511  		p := v.Args[0]
 11512  		v_1 := v.Args[1]
 11513  		if v_1.Op != Op386SHRLconst {
 11514  			break
 11515  		}
 11516  		if v_1.AuxInt != 16 {
 11517  			break
 11518  		}
 11519  		w := v_1.Args[0]
 11520  		x := v.Args[2]
 11521  		if x.Op != Op386MOVWstore {
 11522  			break
 11523  		}
 11524  		if x.AuxInt != i-2 {
 11525  			break
 11526  		}
 11527  		if x.Aux != s {
 11528  			break
 11529  		}
 11530  		_ = x.Args[2]
 11531  		if p != x.Args[0] {
 11532  			break
 11533  		}
 11534  		if w != x.Args[1] {
 11535  			break
 11536  		}
 11537  		mem := x.Args[2]
 11538  		if !(x.Uses == 1 && clobber(x)) {
 11539  			break
 11540  		}
 11541  		v.reset(Op386MOVLstore)
 11542  		v.AuxInt = i - 2
 11543  		v.Aux = s
 11544  		v.AddArg(p)
 11545  		v.AddArg(w)
 11546  		v.AddArg(mem)
 11547  		return true
 11548  	}
 11549  	// match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem))
 11550  	// cond: x.Uses == 1 && clobber(x)
 11551  	// result: (MOVLstore [i-2] {s} p w0 mem)
 11552  	for {
 11553  		i := v.AuxInt
 11554  		s := v.Aux
 11555  		_ = v.Args[2]
 11556  		p := v.Args[0]
 11557  		v_1 := v.Args[1]
 11558  		if v_1.Op != Op386SHRLconst {
 11559  			break
 11560  		}
 11561  		j := v_1.AuxInt
 11562  		w := v_1.Args[0]
 11563  		x := v.Args[2]
 11564  		if x.Op != Op386MOVWstore {
 11565  			break
 11566  		}
 11567  		if x.AuxInt != i-2 {
 11568  			break
 11569  		}
 11570  		if x.Aux != s {
 11571  			break
 11572  		}
 11573  		_ = x.Args[2]
 11574  		if p != x.Args[0] {
 11575  			break
 11576  		}
 11577  		w0 := x.Args[1]
 11578  		if w0.Op != Op386SHRLconst {
 11579  			break
 11580  		}
 11581  		if w0.AuxInt != j-16 {
 11582  			break
 11583  		}
 11584  		if w != w0.Args[0] {
 11585  			break
 11586  		}
 11587  		mem := x.Args[2]
 11588  		if !(x.Uses == 1 && clobber(x)) {
 11589  			break
 11590  		}
 11591  		v.reset(Op386MOVLstore)
 11592  		v.AuxInt = i - 2
 11593  		v.Aux = s
 11594  		v.AddArg(p)
 11595  		v.AddArg(w0)
 11596  		v.AddArg(mem)
 11597  		return true
 11598  	}
 11599  	return false
 11600  }
 11601  func rewriteValue386_Op386MOVWstoreconst_0(v *Value) bool {
 11602  	b := v.Block
 11603  	_ = b
 11604  	config := b.Func.Config
 11605  	_ = config
 11606  	// match: (MOVWstoreconst [sc] {s} (ADDLconst [off] ptr) mem)
 11607  	// cond: ValAndOff(sc).canAdd(off)
 11608  	// result: (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem)
 11609  	for {
 11610  		sc := v.AuxInt
 11611  		s := v.Aux
 11612  		_ = v.Args[1]
 11613  		v_0 := v.Args[0]
 11614  		if v_0.Op != Op386ADDLconst {
 11615  			break
 11616  		}
 11617  		off := v_0.AuxInt
 11618  		ptr := v_0.Args[0]
 11619  		mem := v.Args[1]
 11620  		if !(ValAndOff(sc).canAdd(off)) {
 11621  			break
 11622  		}
 11623  		v.reset(Op386MOVWstoreconst)
 11624  		v.AuxInt = ValAndOff(sc).add(off)
 11625  		v.Aux = s
 11626  		v.AddArg(ptr)
 11627  		v.AddArg(mem)
 11628  		return true
 11629  	}
 11630  	// match: (MOVWstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem)
 11631  	// cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
 11632  	// result: (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem)
 11633  	for {
 11634  		sc := v.AuxInt
 11635  		sym1 := v.Aux
 11636  		_ = v.Args[1]
 11637  		v_0 := v.Args[0]
 11638  		if v_0.Op != Op386LEAL {
 11639  			break
 11640  		}
 11641  		off := v_0.AuxInt
 11642  		sym2 := v_0.Aux
 11643  		ptr := v_0.Args[0]
 11644  		mem := v.Args[1]
 11645  		if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) {
 11646  			break
 11647  		}
 11648  		v.reset(Op386MOVWstoreconst)
 11649  		v.AuxInt = ValAndOff(sc).add(off)
 11650  		v.Aux = mergeSym(sym1, sym2)
 11651  		v.AddArg(ptr)
 11652  		v.AddArg(mem)
 11653  		return true
 11654  	}
 11655  	// match: (MOVWstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem)
 11656  	// cond: canMergeSym(sym1, sym2)
 11657  	// result: (MOVWstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem)
 11658  	for {
 11659  		x := v.AuxInt
 11660  		sym1 := v.Aux
 11661  		_ = v.Args[1]
 11662  		v_0 := v.Args[0]
 11663  		if v_0.Op != Op386LEAL1 {
 11664  			break
 11665  		}
 11666  		off := v_0.AuxInt
 11667  		sym2 := v_0.Aux
 11668  		_ = v_0.Args[1]
 11669  		ptr := v_0.Args[0]
 11670  		idx := v_0.Args[1]
 11671  		mem := v.Args[1]
 11672  		if !(canMergeSym(sym1, sym2)) {
 11673  			break
 11674  		}
 11675  		v.reset(Op386MOVWstoreconstidx1)
 11676  		v.AuxInt = ValAndOff(x).add(off)
 11677  		v.Aux = mergeSym(sym1, sym2)
 11678  		v.AddArg(ptr)
 11679  		v.AddArg(idx)
 11680  		v.AddArg(mem)
 11681  		return true
 11682  	}
 11683  	// match: (MOVWstoreconst [x] {sym1} (LEAL2 [off] {sym2} ptr idx) mem)
 11684  	// cond: canMergeSym(sym1, sym2)
 11685  	// result: (MOVWstoreconstidx2 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem)
 11686  	for {
 11687  		x := v.AuxInt
 11688  		sym1 := v.Aux
 11689  		_ = v.Args[1]
 11690  		v_0 := v.Args[0]
 11691  		if v_0.Op != Op386LEAL2 {
 11692  			break
 11693  		}
 11694  		off := v_0.AuxInt
 11695  		sym2 := v_0.Aux
 11696  		_ = v_0.Args[1]
 11697  		ptr := v_0.Args[0]
 11698  		idx := v_0.Args[1]
 11699  		mem := v.Args[1]
 11700  		if !(canMergeSym(sym1, sym2)) {
 11701  			break
 11702  		}
 11703  		v.reset(Op386MOVWstoreconstidx2)
 11704  		v.AuxInt = ValAndOff(x).add(off)
 11705  		v.Aux = mergeSym(sym1, sym2)
 11706  		v.AddArg(ptr)
 11707  		v.AddArg(idx)
 11708  		v.AddArg(mem)
 11709  		return true
 11710  	}
 11711  	// match: (MOVWstoreconst [x] {sym} (ADDL ptr idx) mem)
 11712  	// cond:
 11713  	// result: (MOVWstoreconstidx1 [x] {sym} ptr idx mem)
 11714  	for {
 11715  		x := v.AuxInt
 11716  		sym := v.Aux
 11717  		_ = v.Args[1]
 11718  		v_0 := v.Args[0]
 11719  		if v_0.Op != Op386ADDL {
 11720  			break
 11721  		}
 11722  		_ = v_0.Args[1]
 11723  		ptr := v_0.Args[0]
 11724  		idx := v_0.Args[1]
 11725  		mem := v.Args[1]
 11726  		v.reset(Op386MOVWstoreconstidx1)
 11727  		v.AuxInt = x
 11728  		v.Aux = sym
 11729  		v.AddArg(ptr)
 11730  		v.AddArg(idx)
 11731  		v.AddArg(mem)
 11732  		return true
 11733  	}
 11734  	// match: (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem))
 11735  	// cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x)
 11736  	// result: (MOVLstoreconst [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p mem)
 11737  	for {
 11738  		c := v.AuxInt
 11739  		s := v.Aux
 11740  		_ = v.Args[1]
 11741  		p := v.Args[0]
 11742  		x := v.Args[1]
 11743  		if x.Op != Op386MOVWstoreconst {
 11744  			break
 11745  		}
 11746  		a := x.AuxInt
 11747  		if x.Aux != s {
 11748  			break
 11749  		}
 11750  		_ = x.Args[1]
 11751  		if p != x.Args[0] {
 11752  			break
 11753  		}
 11754  		mem := x.Args[1]
 11755  		if !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) {
 11756  			break
 11757  		}
 11758  		v.reset(Op386MOVLstoreconst)
 11759  		v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off())
 11760  		v.Aux = s
 11761  		v.AddArg(p)
 11762  		v.AddArg(mem)
 11763  		return true
 11764  	}
 11765  	// match: (MOVWstoreconst [a] {s} p x:(MOVWstoreconst [c] {s} p mem))
 11766  	// cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x)
 11767  	// result: (MOVLstoreconst [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p mem)
 11768  	for {
 11769  		a := v.AuxInt
 11770  		s := v.Aux
 11771  		_ = v.Args[1]
 11772  		p := v.Args[0]
 11773  		x := v.Args[1]
 11774  		if x.Op != Op386MOVWstoreconst {
 11775  			break
 11776  		}
 11777  		c := x.AuxInt
 11778  		if x.Aux != s {
 11779  			break
 11780  		}
 11781  		_ = x.Args[1]
 11782  		if p != x.Args[0] {
 11783  			break
 11784  		}
 11785  		mem := x.Args[1]
 11786  		if !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) {
 11787  			break
 11788  		}
 11789  		v.reset(Op386MOVLstoreconst)
 11790  		v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off())
 11791  		v.Aux = s
 11792  		v.AddArg(p)
 11793  		v.AddArg(mem)
 11794  		return true
 11795  	}
 11796  	return false
 11797  }
 11798  func rewriteValue386_Op386MOVWstoreconstidx1_0(v *Value) bool {
 11799  	// match: (MOVWstoreconstidx1 [c] {sym} ptr (SHLLconst [1] idx) mem)
 11800  	// cond:
 11801  	// result: (MOVWstoreconstidx2 [c] {sym} ptr idx mem)
 11802  	for {
 11803  		c := v.AuxInt
 11804  		sym := v.Aux
 11805  		_ = v.Args[2]
 11806  		ptr := v.Args[0]
 11807  		v_1 := v.Args[1]
 11808  		if v_1.Op != Op386SHLLconst {
 11809  			break
 11810  		}
 11811  		if v_1.AuxInt != 1 {
 11812  			break
 11813  		}
 11814  		idx := v_1.Args[0]
 11815  		mem := v.Args[2]
 11816  		v.reset(Op386MOVWstoreconstidx2)
 11817  		v.AuxInt = c
 11818  		v.Aux = sym
 11819  		v.AddArg(ptr)
 11820  		v.AddArg(idx)
 11821  		v.AddArg(mem)
 11822  		return true
 11823  	}
 11824  	// match: (MOVWstoreconstidx1 [x] {sym} (ADDLconst [c] ptr) idx mem)
 11825  	// cond:
 11826  	// result: (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem)
 11827  	for {
 11828  		x := v.AuxInt
 11829  		sym := v.Aux
 11830  		_ = v.Args[2]
 11831  		v_0 := v.Args[0]
 11832  		if v_0.Op != Op386ADDLconst {
 11833  			break
 11834  		}
 11835  		c := v_0.AuxInt
 11836  		ptr := v_0.Args[0]
 11837  		idx := v.Args[1]
 11838  		mem := v.Args[2]
 11839  		v.reset(Op386MOVWstoreconstidx1)
 11840  		v.AuxInt = ValAndOff(x).add(c)
 11841  		v.Aux = sym
 11842  		v.AddArg(ptr)
 11843  		v.AddArg(idx)
 11844  		v.AddArg(mem)
 11845  		return true
 11846  	}
 11847  	// match: (MOVWstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem)
 11848  	// cond:
 11849  	// result: (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem)
 11850  	for {
 11851  		x := v.AuxInt
 11852  		sym := v.Aux
 11853  		_ = v.Args[2]
 11854  		ptr := v.Args[0]
 11855  		v_1 := v.Args[1]
 11856  		if v_1.Op != Op386ADDLconst {
 11857  			break
 11858  		}
 11859  		c := v_1.AuxInt
 11860  		idx := v_1.Args[0]
 11861  		mem := v.Args[2]
 11862  		v.reset(Op386MOVWstoreconstidx1)
 11863  		v.AuxInt = ValAndOff(x).add(c)
 11864  		v.Aux = sym
 11865  		v.AddArg(ptr)
 11866  		v.AddArg(idx)
 11867  		v.AddArg(mem)
 11868  		return true
 11869  	}
 11870  	// match: (MOVWstoreconstidx1 [c] {s} p i x:(MOVWstoreconstidx1 [a] {s} p i mem))
 11871  	// cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x)
 11872  	// result: (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p i mem)
 11873  	for {
 11874  		c := v.AuxInt
 11875  		s := v.Aux
 11876  		_ = v.Args[2]
 11877  		p := v.Args[0]
 11878  		i := v.Args[1]
 11879  		x := v.Args[2]
 11880  		if x.Op != Op386MOVWstoreconstidx1 {
 11881  			break
 11882  		}
 11883  		a := x.AuxInt
 11884  		if x.Aux != s {
 11885  			break
 11886  		}
 11887  		_ = x.Args[2]
 11888  		if p != x.Args[0] {
 11889  			break
 11890  		}
 11891  		if i != x.Args[1] {
 11892  			break
 11893  		}
 11894  		mem := x.Args[2]
 11895  		if !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) {
 11896  			break
 11897  		}
 11898  		v.reset(Op386MOVLstoreconstidx1)
 11899  		v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off())
 11900  		v.Aux = s
 11901  		v.AddArg(p)
 11902  		v.AddArg(i)
 11903  		v.AddArg(mem)
 11904  		return true
 11905  	}
 11906  	return false
 11907  }
 11908  func rewriteValue386_Op386MOVWstoreconstidx2_0(v *Value) bool {
 11909  	b := v.Block
 11910  	_ = b
 11911  	// match: (MOVWstoreconstidx2 [x] {sym} (ADDLconst [c] ptr) idx mem)
 11912  	// cond:
 11913  	// result: (MOVWstoreconstidx2 [ValAndOff(x).add(c)] {sym} ptr idx mem)
 11914  	for {
 11915  		x := v.AuxInt
 11916  		sym := v.Aux
 11917  		_ = v.Args[2]
 11918  		v_0 := v.Args[0]
 11919  		if v_0.Op != Op386ADDLconst {
 11920  			break
 11921  		}
 11922  		c := v_0.AuxInt
 11923  		ptr := v_0.Args[0]
 11924  		idx := v.Args[1]
 11925  		mem := v.Args[2]
 11926  		v.reset(Op386MOVWstoreconstidx2)
 11927  		v.AuxInt = ValAndOff(x).add(c)
 11928  		v.Aux = sym
 11929  		v.AddArg(ptr)
 11930  		v.AddArg(idx)
 11931  		v.AddArg(mem)
 11932  		return true
 11933  	}
 11934  	// match: (MOVWstoreconstidx2 [x] {sym} ptr (ADDLconst [c] idx) mem)
 11935  	// cond:
 11936  	// result: (MOVWstoreconstidx2 [ValAndOff(x).add(2*c)] {sym} ptr idx mem)
 11937  	for {
 11938  		x := v.AuxInt
 11939  		sym := v.Aux
 11940  		_ = v.Args[2]
 11941  		ptr := v.Args[0]
 11942  		v_1 := v.Args[1]
 11943  		if v_1.Op != Op386ADDLconst {
 11944  			break
 11945  		}
 11946  		c := v_1.AuxInt
 11947  		idx := v_1.Args[0]
 11948  		mem := v.Args[2]
 11949  		v.reset(Op386MOVWstoreconstidx2)
 11950  		v.AuxInt = ValAndOff(x).add(2 * c)
 11951  		v.Aux = sym
 11952  		v.AddArg(ptr)
 11953  		v.AddArg(idx)
 11954  		v.AddArg(mem)
 11955  		return true
 11956  	}
 11957  	// match: (MOVWstoreconstidx2 [c] {s} p i x:(MOVWstoreconstidx2 [a] {s} p i mem))
 11958  	// cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x)
 11959  	// result: (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p (SHLLconst <i.Type> [1] i) mem)
 11960  	for {
 11961  		c := v.AuxInt
 11962  		s := v.Aux
 11963  		_ = v.Args[2]
 11964  		p := v.Args[0]
 11965  		i := v.Args[1]
 11966  		x := v.Args[2]
 11967  		if x.Op != Op386MOVWstoreconstidx2 {
 11968  			break
 11969  		}
 11970  		a := x.AuxInt
 11971  		if x.Aux != s {
 11972  			break
 11973  		}
 11974  		_ = x.Args[2]
 11975  		if p != x.Args[0] {
 11976  			break
 11977  		}
 11978  		if i != x.Args[1] {
 11979  			break
 11980  		}
 11981  		mem := x.Args[2]
 11982  		if !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) {
 11983  			break
 11984  		}
 11985  		v.reset(Op386MOVLstoreconstidx1)
 11986  		v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off())
 11987  		v.Aux = s
 11988  		v.AddArg(p)
 11989  		v0 := b.NewValue0(v.Pos, Op386SHLLconst, i.Type)
 11990  		v0.AuxInt = 1
 11991  		v0.AddArg(i)
 11992  		v.AddArg(v0)
 11993  		v.AddArg(mem)
 11994  		return true
 11995  	}
 11996  	return false
 11997  }
 11998  func rewriteValue386_Op386MOVWstoreidx1_0(v *Value) bool {
 11999  	// match: (MOVWstoreidx1 [c] {sym} ptr (SHLLconst [1] idx) val mem)
 12000  	// cond:
 12001  	// result: (MOVWstoreidx2 [c] {sym} ptr idx val mem)
 12002  	for {
 12003  		c := v.AuxInt
 12004  		sym := v.Aux
 12005  		_ = v.Args[3]
 12006  		ptr := v.Args[0]
 12007  		v_1 := v.Args[1]
 12008  		if v_1.Op != Op386SHLLconst {
 12009  			break
 12010  		}
 12011  		if v_1.AuxInt != 1 {
 12012  			break
 12013  		}
 12014  		idx := v_1.Args[0]
 12015  		val := v.Args[2]
 12016  		mem := v.Args[3]
 12017  		v.reset(Op386MOVWstoreidx2)
 12018  		v.AuxInt = c
 12019  		v.Aux = sym
 12020  		v.AddArg(ptr)
 12021  		v.AddArg(idx)
 12022  		v.AddArg(val)
 12023  		v.AddArg(mem)
 12024  		return true
 12025  	}
 12026  	// match: (MOVWstoreidx1 [c] {sym} (SHLLconst [1] idx) ptr val mem)
 12027  	// cond:
 12028  	// result: (MOVWstoreidx2 [c] {sym} ptr idx val mem)
 12029  	for {
 12030  		c := v.AuxInt
 12031  		sym := v.Aux
 12032  		_ = v.Args[3]
 12033  		v_0 := v.Args[0]
 12034  		if v_0.Op != Op386SHLLconst {
 12035  			break
 12036  		}
 12037  		if v_0.AuxInt != 1 {
 12038  			break
 12039  		}
 12040  		idx := v_0.Args[0]
 12041  		ptr := v.Args[1]
 12042  		val := v.Args[2]
 12043  		mem := v.Args[3]
 12044  		v.reset(Op386MOVWstoreidx2)
 12045  		v.AuxInt = c
 12046  		v.Aux = sym
 12047  		v.AddArg(ptr)
 12048  		v.AddArg(idx)
 12049  		v.AddArg(val)
 12050  		v.AddArg(mem)
 12051  		return true
 12052  	}
 12053  	// match: (MOVWstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem)
 12054  	// cond:
 12055  	// result: (MOVWstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
 12056  	for {
 12057  		c := v.AuxInt
 12058  		sym := v.Aux
 12059  		_ = v.Args[3]
 12060  		v_0 := v.Args[0]
 12061  		if v_0.Op != Op386ADDLconst {
 12062  			break
 12063  		}
 12064  		d := v_0.AuxInt
 12065  		ptr := v_0.Args[0]
 12066  		idx := v.Args[1]
 12067  		val := v.Args[2]
 12068  		mem := v.Args[3]
 12069  		v.reset(Op386MOVWstoreidx1)
 12070  		v.AuxInt = int64(int32(c + d))
 12071  		v.Aux = sym
 12072  		v.AddArg(ptr)
 12073  		v.AddArg(idx)
 12074  		v.AddArg(val)
 12075  		v.AddArg(mem)
 12076  		return true
 12077  	}
 12078  	// match: (MOVWstoreidx1 [c] {sym} idx (ADDLconst [d] ptr) val mem)
 12079  	// cond:
 12080  	// result: (MOVWstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
 12081  	for {
 12082  		c := v.AuxInt
 12083  		sym := v.Aux
 12084  		_ = v.Args[3]
 12085  		idx := v.Args[0]
 12086  		v_1 := v.Args[1]
 12087  		if v_1.Op != Op386ADDLconst {
 12088  			break
 12089  		}
 12090  		d := v_1.AuxInt
 12091  		ptr := v_1.Args[0]
 12092  		val := v.Args[2]
 12093  		mem := v.Args[3]
 12094  		v.reset(Op386MOVWstoreidx1)
 12095  		v.AuxInt = int64(int32(c + d))
 12096  		v.Aux = sym
 12097  		v.AddArg(ptr)
 12098  		v.AddArg(idx)
 12099  		v.AddArg(val)
 12100  		v.AddArg(mem)
 12101  		return true
 12102  	}
 12103  	// match: (MOVWstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem)
 12104  	// cond:
 12105  	// result: (MOVWstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
 12106  	for {
 12107  		c := v.AuxInt
 12108  		sym := v.Aux
 12109  		_ = v.Args[3]
 12110  		ptr := v.Args[0]
 12111  		v_1 := v.Args[1]
 12112  		if v_1.Op != Op386ADDLconst {
 12113  			break
 12114  		}
 12115  		d := v_1.AuxInt
 12116  		idx := v_1.Args[0]
 12117  		val := v.Args[2]
 12118  		mem := v.Args[3]
 12119  		v.reset(Op386MOVWstoreidx1)
 12120  		v.AuxInt = int64(int32(c + d))
 12121  		v.Aux = sym
 12122  		v.AddArg(ptr)
 12123  		v.AddArg(idx)
 12124  		v.AddArg(val)
 12125  		v.AddArg(mem)
 12126  		return true
 12127  	}
 12128  	// match: (MOVWstoreidx1 [c] {sym} (ADDLconst [d] idx) ptr val mem)
 12129  	// cond:
 12130  	// result: (MOVWstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem)
 12131  	for {
 12132  		c := v.AuxInt
 12133  		sym := v.Aux
 12134  		_ = v.Args[3]
 12135  		v_0 := v.Args[0]
 12136  		if v_0.Op != Op386ADDLconst {
 12137  			break
 12138  		}
 12139  		d := v_0.AuxInt
 12140  		idx := v_0.Args[0]
 12141  		ptr := v.Args[1]
 12142  		val := v.Args[2]
 12143  		mem := v.Args[3]
 12144  		v.reset(Op386MOVWstoreidx1)
 12145  		v.AuxInt = int64(int32(c + d))
 12146  		v.Aux = sym
 12147  		v.AddArg(ptr)
 12148  		v.AddArg(idx)
 12149  		v.AddArg(val)
 12150  		v.AddArg(mem)
 12151  		return true
 12152  	}
 12153  	// match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem))
 12154  	// cond: x.Uses == 1 && clobber(x)
 12155  	// result: (MOVLstoreidx1 [i-2] {s} p idx w mem)
 12156  	for {
 12157  		i := v.AuxInt
 12158  		s := v.Aux
 12159  		_ = v.Args[3]
 12160  		p := v.Args[0]
 12161  		idx := v.Args[1]
 12162  		v_2 := v.Args[2]
 12163  		if v_2.Op != Op386SHRLconst {
 12164  			break
 12165  		}
 12166  		if v_2.AuxInt != 16 {
 12167  			break
 12168  		}
 12169  		w := v_2.Args[0]
 12170  		x := v.Args[3]
 12171  		if x.Op != Op386MOVWstoreidx1 {
 12172  			break
 12173  		}
 12174  		if x.AuxInt != i-2 {
 12175  			break
 12176  		}
 12177  		if x.Aux != s {
 12178  			break
 12179  		}
 12180  		_ = x.Args[3]
 12181  		if p != x.Args[0] {
 12182  			break
 12183  		}
 12184  		if idx != x.Args[1] {
 12185  			break
 12186  		}
 12187  		if w != x.Args[2] {
 12188  			break
 12189  		}
 12190  		mem := x.Args[3]
 12191  		if !(x.Uses == 1 && clobber(x)) {
 12192  			break
 12193  		}
 12194  		v.reset(Op386MOVLstoreidx1)
 12195  		v.AuxInt = i - 2
 12196  		v.Aux = s
 12197  		v.AddArg(p)
 12198  		v.AddArg(idx)
 12199  		v.AddArg(w)
 12200  		v.AddArg(mem)
 12201  		return true
 12202  	}
 12203  	// match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} idx p w mem))
 12204  	// cond: x.Uses == 1 && clobber(x)
 12205  	// result: (MOVLstoreidx1 [i-2] {s} p idx w mem)
 12206  	for {
 12207  		i := v.AuxInt
 12208  		s := v.Aux
 12209  		_ = v.Args[3]
 12210  		p := v.Args[0]
 12211  		idx := v.Args[1]
 12212  		v_2 := v.Args[2]
 12213  		if v_2.Op != Op386SHRLconst {
 12214  			break
 12215  		}
 12216  		if v_2.AuxInt != 16 {
 12217  			break
 12218  		}
 12219  		w := v_2.Args[0]
 12220  		x := v.Args[3]
 12221  		if x.Op != Op386MOVWstoreidx1 {
 12222  			break
 12223  		}
 12224  		if x.AuxInt != i-2 {
 12225  			break
 12226  		}
 12227  		if x.Aux != s {
 12228  			break
 12229  		}
 12230  		_ = x.Args[3]
 12231  		if idx != x.Args[0] {
 12232  			break
 12233  		}
 12234  		if p != x.Args[1] {
 12235  			break
 12236  		}
 12237  		if w != x.Args[2] {
 12238  			break
 12239  		}
 12240  		mem := x.Args[3]
 12241  		if !(x.Uses == 1 && clobber(x)) {
 12242  			break
 12243  		}
 12244  		v.reset(Op386MOVLstoreidx1)
 12245  		v.AuxInt = i - 2
 12246  		v.Aux = s
 12247  		v.AddArg(p)
 12248  		v.AddArg(idx)
 12249  		v.AddArg(w)
 12250  		v.AddArg(mem)
 12251  		return true
 12252  	}
 12253  	// match: (MOVWstoreidx1 [i] {s} idx p (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem))
 12254  	// cond: x.Uses == 1 && clobber(x)
 12255  	// result: (MOVLstoreidx1 [i-2] {s} p idx w mem)
 12256  	for {
 12257  		i := v.AuxInt
 12258  		s := v.Aux
 12259  		_ = v.Args[3]
 12260  		idx := v.Args[0]
 12261  		p := v.Args[1]
 12262  		v_2 := v.Args[2]
 12263  		if v_2.Op != Op386SHRLconst {
 12264  			break
 12265  		}
 12266  		if v_2.AuxInt != 16 {
 12267  			break
 12268  		}
 12269  		w := v_2.Args[0]
 12270  		x := v.Args[3]
 12271  		if x.Op != Op386MOVWstoreidx1 {
 12272  			break
 12273  		}
 12274  		if x.AuxInt != i-2 {
 12275  			break
 12276  		}
 12277  		if x.Aux != s {
 12278  			break
 12279  		}
 12280  		_ = x.Args[3]
 12281  		if p != x.Args[0] {
 12282  			break
 12283  		}
 12284  		if idx != x.Args[1] {
 12285  			break
 12286  		}
 12287  		if w != x.Args[2] {
 12288  			break
 12289  		}
 12290  		mem := x.Args[3]
 12291  		if !(x.Uses == 1 && clobber(x)) {
 12292  			break
 12293  		}
 12294  		v.reset(Op386MOVLstoreidx1)
 12295  		v.AuxInt = i - 2
 12296  		v.Aux = s
 12297  		v.AddArg(p)
 12298  		v.AddArg(idx)
 12299  		v.AddArg(w)
 12300  		v.AddArg(mem)
 12301  		return true
 12302  	}
 12303  	// match: (MOVWstoreidx1 [i] {s} idx p (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} idx p w mem))
 12304  	// cond: x.Uses == 1 && clobber(x)
 12305  	// result: (MOVLstoreidx1 [i-2] {s} p idx w mem)
 12306  	for {
 12307  		i := v.AuxInt
 12308  		s := v.Aux
 12309  		_ = v.Args[3]
 12310  		idx := v.Args[0]
 12311  		p := v.Args[1]
 12312  		v_2 := v.Args[2]
 12313  		if v_2.Op != Op386SHRLconst {
 12314  			break
 12315  		}
 12316  		if v_2.AuxInt != 16 {
 12317  			break
 12318  		}
 12319  		w := v_2.Args[0]
 12320  		x := v.Args[3]
 12321  		if x.Op != Op386MOVWstoreidx1 {
 12322  			break
 12323  		}
 12324  		if x.AuxInt != i-2 {
 12325  			break
 12326  		}
 12327  		if x.Aux != s {
 12328  			break
 12329  		}
 12330  		_ = x.Args[3]
 12331  		if idx != x.Args[0] {
 12332  			break
 12333  		}
 12334  		if p != x.Args[1] {
 12335  			break
 12336  		}
 12337  		if w != x.Args[2] {
 12338  			break
 12339  		}
 12340  		mem := x.Args[3]
 12341  		if !(x.Uses == 1 && clobber(x)) {
 12342  			break
 12343  		}
 12344  		v.reset(Op386MOVLstoreidx1)
 12345  		v.AuxInt = i - 2
 12346  		v.Aux = s
 12347  		v.AddArg(p)
 12348  		v.AddArg(idx)
 12349  		v.AddArg(w)
 12350  		v.AddArg(mem)
 12351  		return true
 12352  	}
 12353  	return false
 12354  }
 12355  func rewriteValue386_Op386MOVWstoreidx1_10(v *Value) bool {
 12356  	// match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem))
 12357  	// cond: x.Uses == 1 && clobber(x)
 12358  	// result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem)
 12359  	for {
 12360  		i := v.AuxInt
 12361  		s := v.Aux
 12362  		_ = v.Args[3]
 12363  		p := v.Args[0]
 12364  		idx := v.Args[1]
 12365  		v_2 := v.Args[2]
 12366  		if v_2.Op != Op386SHRLconst {
 12367  			break
 12368  		}
 12369  		j := v_2.AuxInt
 12370  		w := v_2.Args[0]
 12371  		x := v.Args[3]
 12372  		if x.Op != Op386MOVWstoreidx1 {
 12373  			break
 12374  		}
 12375  		if x.AuxInt != i-2 {
 12376  			break
 12377  		}
 12378  		if x.Aux != s {
 12379  			break
 12380  		}
 12381  		_ = x.Args[3]
 12382  		if p != x.Args[0] {
 12383  			break
 12384  		}
 12385  		if idx != x.Args[1] {
 12386  			break
 12387  		}
 12388  		w0 := x.Args[2]
 12389  		if w0.Op != Op386SHRLconst {
 12390  			break
 12391  		}
 12392  		if w0.AuxInt != j-16 {
 12393  			break
 12394  		}
 12395  		if w != w0.Args[0] {
 12396  			break
 12397  		}
 12398  		mem := x.Args[3]
 12399  		if !(x.Uses == 1 && clobber(x)) {
 12400  			break
 12401  		}
 12402  		v.reset(Op386MOVLstoreidx1)
 12403  		v.AuxInt = i - 2
 12404  		v.Aux = s
 12405  		v.AddArg(p)
 12406  		v.AddArg(idx)
 12407  		v.AddArg(w0)
 12408  		v.AddArg(mem)
 12409  		return true
 12410  	}
 12411  	// match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} idx p w0:(SHRLconst [j-16] w) mem))
 12412  	// cond: x.Uses == 1 && clobber(x)
 12413  	// result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem)
 12414  	for {
 12415  		i := v.AuxInt
 12416  		s := v.Aux
 12417  		_ = v.Args[3]
 12418  		p := v.Args[0]
 12419  		idx := v.Args[1]
 12420  		v_2 := v.Args[2]
 12421  		if v_2.Op != Op386SHRLconst {
 12422  			break
 12423  		}
 12424  		j := v_2.AuxInt
 12425  		w := v_2.Args[0]
 12426  		x := v.Args[3]
 12427  		if x.Op != Op386MOVWstoreidx1 {
 12428  			break
 12429  		}
 12430  		if x.AuxInt != i-2 {
 12431  			break
 12432  		}
 12433  		if x.Aux != s {
 12434  			break
 12435  		}
 12436  		_ = x.Args[3]
 12437  		if idx != x.Args[0] {
 12438  			break
 12439  		}
 12440  		if p != x.Args[1] {
 12441  			break
 12442  		}
 12443  		w0 := x.Args[2]
 12444  		if w0.Op != Op386SHRLconst {
 12445  			break
 12446  		}
 12447  		if w0.AuxInt != j-16 {
 12448  			break
 12449  		}
 12450  		if w != w0.Args[0] {
 12451  			break
 12452  		}
 12453  		mem := x.Args[3]
 12454  		if !(x.Uses == 1 && clobber(x)) {
 12455  			break
 12456  		}
 12457  		v.reset(Op386MOVLstoreidx1)
 12458  		v.AuxInt = i - 2
 12459  		v.Aux = s
 12460  		v.AddArg(p)
 12461  		v.AddArg(idx)
 12462  		v.AddArg(w0)
 12463  		v.AddArg(mem)
 12464  		return true
 12465  	}
 12466  	// match: (MOVWstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem))
 12467  	// cond: x.Uses == 1 && clobber(x)
 12468  	// result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem)
 12469  	for {
 12470  		i := v.AuxInt
 12471  		s := v.Aux
 12472  		_ = v.Args[3]
 12473  		idx := v.Args[0]
 12474  		p := v.Args[1]
 12475  		v_2 := v.Args[2]
 12476  		if v_2.Op != Op386SHRLconst {
 12477  			break
 12478  		}
 12479  		j := v_2.AuxInt
 12480  		w := v_2.Args[0]
 12481  		x := v.Args[3]
 12482  		if x.Op != Op386MOVWstoreidx1 {
 12483  			break
 12484  		}
 12485  		if x.AuxInt != i-2 {
 12486  			break
 12487  		}
 12488  		if x.Aux != s {
 12489  			break
 12490  		}
 12491  		_ = x.Args[3]
 12492  		if p != x.Args[0] {
 12493  			break
 12494  		}
 12495  		if idx != x.Args[1] {
 12496  			break
 12497  		}
 12498  		w0 := x.Args[2]
 12499  		if w0.Op != Op386SHRLconst {
 12500  			break
 12501  		}
 12502  		if w0.AuxInt != j-16 {
 12503  			break
 12504  		}
 12505  		if w != w0.Args[0] {
 12506  			break
 12507  		}
 12508  		mem := x.Args[3]
 12509  		if !(x.Uses == 1 && clobber(x)) {
 12510  			break
 12511  		}
 12512  		v.reset(Op386MOVLstoreidx1)
 12513  		v.AuxInt = i - 2
 12514  		v.Aux = s
 12515  		v.AddArg(p)
 12516  		v.AddArg(idx)
 12517  		v.AddArg(w0)
 12518  		v.AddArg(mem)
 12519  		return true
 12520  	}
 12521  	// match: (MOVWstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} idx p w0:(SHRLconst [j-16] w) mem))
 12522  	// cond: x.Uses == 1 && clobber(x)
 12523  	// result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem)
 12524  	for {
 12525  		i := v.AuxInt
 12526  		s := v.Aux
 12527  		_ = v.Args[3]
 12528  		idx := v.Args[0]
 12529  		p := v.Args[1]
 12530  		v_2 := v.Args[2]
 12531  		if v_2.Op != Op386SHRLconst {
 12532  			break
 12533  		}
 12534  		j := v_2.AuxInt
 12535  		w := v_2.Args[0]
 12536  		x := v.Args[3]
 12537  		if x.Op != Op386MOVWstoreidx1 {
 12538  			break
 12539  		}
 12540  		if x.AuxInt != i-2 {
 12541  			break
 12542  		}
 12543  		if x.Aux != s {
 12544  			break
 12545  		}
 12546  		_ = x.Args[3]
 12547  		if idx != x.Args[0] {
 12548  			break
 12549  		}
 12550  		if p != x.Args[1] {
 12551  			break
 12552  		}
 12553  		w0 := x.Args[2]
 12554  		if w0.Op != Op386SHRLconst {
 12555  			break
 12556  		}
 12557  		if w0.AuxInt != j-16 {
 12558  			break
 12559  		}
 12560  		if w != w0.Args[0] {
 12561  			break
 12562  		}
 12563  		mem := x.Args[3]
 12564  		if !(x.Uses == 1 && clobber(x)) {
 12565  			break
 12566  		}
 12567  		v.reset(Op386MOVLstoreidx1)
 12568  		v.AuxInt = i - 2
 12569  		v.Aux = s
 12570  		v.AddArg(p)
 12571  		v.AddArg(idx)
 12572  		v.AddArg(w0)
 12573  		v.AddArg(mem)
 12574  		return true
 12575  	}
 12576  	return false
 12577  }
 12578  func rewriteValue386_Op386MOVWstoreidx2_0(v *Value) bool {
 12579  	b := v.Block
 12580  	_ = b
 12581  	// match: (MOVWstoreidx2 [c] {sym} (ADDLconst [d] ptr) idx val mem)
 12582  	// cond:
 12583  	// result: (MOVWstoreidx2 [int64(int32(c+d))] {sym} ptr idx val mem)
 12584  	for {
 12585  		c := v.AuxInt
 12586  		sym := v.Aux
 12587  		_ = v.Args[3]
 12588  		v_0 := v.Args[0]
 12589  		if v_0.Op != Op386ADDLconst {
 12590  			break
 12591  		}
 12592  		d := v_0.AuxInt
 12593  		ptr := v_0.Args[0]
 12594  		idx := v.Args[1]
 12595  		val := v.Args[2]
 12596  		mem := v.Args[3]
 12597  		v.reset(Op386MOVWstoreidx2)
 12598  		v.AuxInt = int64(int32(c + d))
 12599  		v.Aux = sym
 12600  		v.AddArg(ptr)
 12601  		v.AddArg(idx)
 12602  		v.AddArg(val)
 12603  		v.AddArg(mem)
 12604  		return true
 12605  	}
 12606  	// match: (MOVWstoreidx2 [c] {sym} ptr (ADDLconst [d] idx) val mem)
 12607  	// cond:
 12608  	// result: (MOVWstoreidx2 [int64(int32(c+2*d))] {sym} ptr idx val mem)
 12609  	for {
 12610  		c := v.AuxInt
 12611  		sym := v.Aux
 12612  		_ = v.Args[3]
 12613  		ptr := v.Args[0]
 12614  		v_1 := v.Args[1]
 12615  		if v_1.Op != Op386ADDLconst {
 12616  			break
 12617  		}
 12618  		d := v_1.AuxInt
 12619  		idx := v_1.Args[0]
 12620  		val := v.Args[2]
 12621  		mem := v.Args[3]
 12622  		v.reset(Op386MOVWstoreidx2)
 12623  		v.AuxInt = int64(int32(c + 2*d))
 12624  		v.Aux = sym
 12625  		v.AddArg(ptr)
 12626  		v.AddArg(idx)
 12627  		v.AddArg(val)
 12628  		v.AddArg(mem)
 12629  		return true
 12630  	}
 12631  	// match: (MOVWstoreidx2 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx2 [i-2] {s} p idx w mem))
 12632  	// cond: x.Uses == 1 && clobber(x)
 12633  	// result: (MOVLstoreidx1 [i-2] {s} p (SHLLconst <idx.Type> [1] idx) w mem)
 12634  	for {
 12635  		i := v.AuxInt
 12636  		s := v.Aux
 12637  		_ = v.Args[3]
 12638  		p := v.Args[0]
 12639  		idx := v.Args[1]
 12640  		v_2 := v.Args[2]
 12641  		if v_2.Op != Op386SHRLconst {
 12642  			break
 12643  		}
 12644  		if v_2.AuxInt != 16 {
 12645  			break
 12646  		}
 12647  		w := v_2.Args[0]
 12648  		x := v.Args[3]
 12649  		if x.Op != Op386MOVWstoreidx2 {
 12650  			break
 12651  		}
 12652  		if x.AuxInt != i-2 {
 12653  			break
 12654  		}
 12655  		if x.Aux != s {
 12656  			break
 12657  		}
 12658  		_ = x.Args[3]
 12659  		if p != x.Args[0] {
 12660  			break
 12661  		}
 12662  		if idx != x.Args[1] {
 12663  			break
 12664  		}
 12665  		if w != x.Args[2] {
 12666  			break
 12667  		}
 12668  		mem := x.Args[3]
 12669  		if !(x.Uses == 1 && clobber(x)) {
 12670  			break
 12671  		}
 12672  		v.reset(Op386MOVLstoreidx1)
 12673  		v.AuxInt = i - 2
 12674  		v.Aux = s
 12675  		v.AddArg(p)
 12676  		v0 := b.NewValue0(v.Pos, Op386SHLLconst, idx.Type)
 12677  		v0.AuxInt = 1
 12678  		v0.AddArg(idx)
 12679  		v.AddArg(v0)
 12680  		v.AddArg(w)
 12681  		v.AddArg(mem)
 12682  		return true
 12683  	}
 12684  	// match: (MOVWstoreidx2 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx2 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem))
 12685  	// cond: x.Uses == 1 && clobber(x)
 12686  	// result: (MOVLstoreidx1 [i-2] {s} p (SHLLconst <idx.Type> [1] idx) w0 mem)
 12687  	for {
 12688  		i := v.AuxInt
 12689  		s := v.Aux
 12690  		_ = v.Args[3]
 12691  		p := v.Args[0]
 12692  		idx := v.Args[1]
 12693  		v_2 := v.Args[2]
 12694  		if v_2.Op != Op386SHRLconst {
 12695  			break
 12696  		}
 12697  		j := v_2.AuxInt
 12698  		w := v_2.Args[0]
 12699  		x := v.Args[3]
 12700  		if x.Op != Op386MOVWstoreidx2 {
 12701  			break
 12702  		}
 12703  		if x.AuxInt != i-2 {
 12704  			break
 12705  		}
 12706  		if x.Aux != s {
 12707  			break
 12708  		}
 12709  		_ = x.Args[3]
 12710  		if p != x.Args[0] {
 12711  			break
 12712  		}
 12713  		if idx != x.Args[1] {
 12714  			break
 12715  		}
 12716  		w0 := x.Args[2]
 12717  		if w0.Op != Op386SHRLconst {
 12718  			break
 12719  		}
 12720  		if w0.AuxInt != j-16 {
 12721  			break
 12722  		}
 12723  		if w != w0.Args[0] {
 12724  			break
 12725  		}
 12726  		mem := x.Args[3]
 12727  		if !(x.Uses == 1 && clobber(x)) {
 12728  			break
 12729  		}
 12730  		v.reset(Op386MOVLstoreidx1)
 12731  		v.AuxInt = i - 2
 12732  		v.Aux = s
 12733  		v.AddArg(p)
 12734  		v0 := b.NewValue0(v.Pos, Op386SHLLconst, idx.Type)
 12735  		v0.AuxInt = 1
 12736  		v0.AddArg(idx)
 12737  		v.AddArg(v0)
 12738  		v.AddArg(w0)
 12739  		v.AddArg(mem)
 12740  		return true
 12741  	}
 12742  	return false
 12743  }
 12744  func rewriteValue386_Op386MULL_0(v *Value) bool {
 12745  	// match: (MULL x (MOVLconst [c]))
 12746  	// cond:
 12747  	// result: (MULLconst [c] x)
 12748  	for {
 12749  		_ = v.Args[1]
 12750  		x := v.Args[0]
 12751  		v_1 := v.Args[1]
 12752  		if v_1.Op != Op386MOVLconst {
 12753  			break
 12754  		}
 12755  		c := v_1.AuxInt
 12756  		v.reset(Op386MULLconst)
 12757  		v.AuxInt = c
 12758  		v.AddArg(x)
 12759  		return true
 12760  	}
 12761  	// match: (MULL (MOVLconst [c]) x)
 12762  	// cond:
 12763  	// result: (MULLconst [c] x)
 12764  	for {
 12765  		_ = v.Args[1]
 12766  		v_0 := v.Args[0]
 12767  		if v_0.Op != Op386MOVLconst {
 12768  			break
 12769  		}
 12770  		c := v_0.AuxInt
 12771  		x := v.Args[1]
 12772  		v.reset(Op386MULLconst)
 12773  		v.AuxInt = c
 12774  		v.AddArg(x)
 12775  		return true
 12776  	}
 12777  	// match: (MULL x l:(MOVLload [off] {sym} ptr mem))
 12778  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
 12779  	// result: (MULLload x [off] {sym} ptr mem)
 12780  	for {
 12781  		_ = v.Args[1]
 12782  		x := v.Args[0]
 12783  		l := v.Args[1]
 12784  		if l.Op != Op386MOVLload {
 12785  			break
 12786  		}
 12787  		off := l.AuxInt
 12788  		sym := l.Aux
 12789  		_ = l.Args[1]
 12790  		ptr := l.Args[0]
 12791  		mem := l.Args[1]
 12792  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
 12793  			break
 12794  		}
 12795  		v.reset(Op386MULLload)
 12796  		v.AuxInt = off
 12797  		v.Aux = sym
 12798  		v.AddArg(x)
 12799  		v.AddArg(ptr)
 12800  		v.AddArg(mem)
 12801  		return true
 12802  	}
 12803  	// match: (MULL l:(MOVLload [off] {sym} ptr mem) x)
 12804  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
 12805  	// result: (MULLload x [off] {sym} ptr mem)
 12806  	for {
 12807  		_ = v.Args[1]
 12808  		l := v.Args[0]
 12809  		if l.Op != Op386MOVLload {
 12810  			break
 12811  		}
 12812  		off := l.AuxInt
 12813  		sym := l.Aux
 12814  		_ = l.Args[1]
 12815  		ptr := l.Args[0]
 12816  		mem := l.Args[1]
 12817  		x := v.Args[1]
 12818  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
 12819  			break
 12820  		}
 12821  		v.reset(Op386MULLload)
 12822  		v.AuxInt = off
 12823  		v.Aux = sym
 12824  		v.AddArg(x)
 12825  		v.AddArg(ptr)
 12826  		v.AddArg(mem)
 12827  		return true
 12828  	}
 12829  	// match: (MULL x l:(MOVLloadidx4 [off] {sym} ptr idx mem))
 12830  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
 12831  	// result: (MULLloadidx4 x [off] {sym} ptr idx mem)
 12832  	for {
 12833  		_ = v.Args[1]
 12834  		x := v.Args[0]
 12835  		l := v.Args[1]
 12836  		if l.Op != Op386MOVLloadidx4 {
 12837  			break
 12838  		}
 12839  		off := l.AuxInt
 12840  		sym := l.Aux
 12841  		_ = l.Args[2]
 12842  		ptr := l.Args[0]
 12843  		idx := l.Args[1]
 12844  		mem := l.Args[2]
 12845  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
 12846  			break
 12847  		}
 12848  		v.reset(Op386MULLloadidx4)
 12849  		v.AuxInt = off
 12850  		v.Aux = sym
 12851  		v.AddArg(x)
 12852  		v.AddArg(ptr)
 12853  		v.AddArg(idx)
 12854  		v.AddArg(mem)
 12855  		return true
 12856  	}
 12857  	// match: (MULL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x)
 12858  	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
 12859  	// result: (MULLloadidx4 x [off] {sym} ptr idx mem)
 12860  	for {
 12861  		_ = v.Args[1]
 12862  		l := v.Args[0]
 12863  		if l.Op != Op386MOVLloadidx4 {
 12864  			break
 12865  		}
 12866  		off := l.AuxInt
 12867  		sym := l.Aux
 12868  		_ = l.Args[2]
 12869  		ptr := l.Args[0]
 12870  		idx := l.Args[1]
 12871  		mem := l.Args[2]
 12872  		x := v.Args[1]
 12873  		if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
 12874  			break
 12875  		}
 12876  		v.reset(Op386MULLloadidx4)
 12877  		v.AuxInt = off
 12878  		v.Aux = sym
 12879  		v.AddArg(x)
 12880  		v.AddArg(ptr)
 12881  		v.AddArg(idx)
 12882  		v.AddArg(mem)
 12883  		return true
 12884  	}
 12885  	return false
 12886  }
 12887  func rewriteValue386_Op386MULLconst_0(v *Value) bool {
 12888  	b := v.Block
 12889  	_ = b
 12890  	// match: (MULLconst [c] (MULLconst [d] x))
 12891  	// cond:
 12892  	// result: (MULLconst [int64(int32(c * d))] x)
 12893  	for {
 12894  		c := v.AuxInt
 12895  		v_0 := v.Args[0]
 12896  		if v_0.Op != Op386MULLconst {
 12897  			break
 12898  		}
 12899  		d := v_0.AuxInt
 12900  		x := v_0.Args[0]
 12901  		v.reset(Op386MULLconst)
 12902  		v.AuxInt = int64(int32(c * d))
 12903  		v.AddArg(x)
 12904  		return true
 12905  	}
 12906  	// match: (MULLconst [-9] x)
 12907  	// cond:
 12908  	// result: (NEGL (LEAL8 <v.Type> x x))
 12909  	for {
 12910  		if v.AuxInt != -9 {
 12911  			break
 12912  		}
 12913  		x := v.Args[0]
 12914  		v.reset(Op386NEGL)
 12915  		v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
 12916  		v0.AddArg(x)
 12917  		v0.AddArg(x)
 12918  		v.AddArg(v0)
 12919  		return true
 12920  	}
 12921  	// match: (MULLconst [-5] x)
 12922  	// cond:
 12923  	// result: (NEGL (LEAL4 <v.Type> x x))
 12924  	for {
 12925  		if v.AuxInt != -5 {
 12926  			break
 12927  		}
 12928  		x := v.Args[0]
 12929  		v.reset(Op386NEGL)
 12930  		v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
 12931  		v0.AddArg(x)
 12932  		v0.AddArg(x)
 12933  		v.AddArg(v0)
 12934  		return true
 12935  	}
 12936  	// match: (MULLconst [-3] x)
 12937  	// cond:
 12938  	// result: (NEGL (LEAL2 <v.Type> x x))
 12939  	for {
 12940  		if v.AuxInt != -3 {
 12941  			break
 12942  		}
 12943  		x := v.Args[0]
 12944  		v.reset(Op386NEGL)
 12945  		v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
 12946  		v0.AddArg(x)
 12947  		v0.AddArg(x)
 12948  		v.AddArg(v0)
 12949  		return true
 12950  	}
 12951  	// match: (MULLconst [-1] x)
 12952  	// cond:
 12953  	// result: (NEGL x)
 12954  	for {
 12955  		if v.AuxInt != -1 {
 12956  			break
 12957  		}
 12958  		x := v.Args[0]
 12959  		v.reset(Op386NEGL)
 12960  		v.AddArg(x)
 12961  		return true
 12962  	}
 12963  	// match: (MULLconst [0] _)
 12964  	// cond:
 12965  	// result: (MOVLconst [0])
 12966  	for {
 12967  		if v.AuxInt != 0 {
 12968  			break
 12969  		}
 12970  		v.reset(Op386MOVLconst)
 12971  		v.AuxInt = 0
 12972  		return true
 12973  	}
 12974  	// match: (MULLconst [1] x)
 12975  	// cond:
 12976  	// result: x
 12977  	for {
 12978  		if v.AuxInt != 1 {
 12979  			break
 12980  		}
 12981  		x := v.Args[0]
 12982  		v.reset(OpCopy)
 12983  		v.Type = x.Type
 12984  		v.AddArg(x)
 12985  		return true
 12986  	}
 12987  	// match: (MULLconst [3] x)
 12988  	// cond:
 12989  	// result: (LEAL2 x x)
 12990  	for {
 12991  		if v.AuxInt != 3 {
 12992  			break
 12993  		}
 12994  		x := v.Args[0]
 12995  		v.reset(Op386LEAL2)
 12996  		v.AddArg(x)
 12997  		v.AddArg(x)
 12998  		return true
 12999  	}
 13000  	// match: (MULLconst [5] x)
 13001  	// cond:
 13002  	// result: (LEAL4 x x)
 13003  	for {
 13004  		if v.AuxInt != 5 {
 13005  			break
 13006  		}
 13007  		x := v.Args[0]
 13008  		v.reset(Op386LEAL4)
 13009  		v.AddArg(x)
 13010  		v.AddArg(x)
 13011  		return true
 13012  	}
 13013  	// match: (MULLconst [7] x)
 13014  	// cond:
 13015  	// result: (LEAL2 x (LEAL2 <v.Type> x x))
 13016  	for {
 13017  		if v.AuxInt != 7 {
 13018  			break
 13019  		}
 13020  		x := v.Args[0]
 13021  		v.reset(Op386LEAL2)
 13022  		v.AddArg(x)
 13023  		v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
 13024  		v0.AddArg(x)
 13025  		v0.AddArg(x)
 13026  		v.AddArg(v0)
 13027  		return true
 13028  	}
 13029  	return false
 13030  }
 13031  func rewriteValue386_Op386MULLconst_10(v *Value) bool {
 13032  	b := v.Block
 13033  	_ = b
 13034  	// match: (MULLconst [9] x)
 13035  	// cond:
 13036  	// result: (LEAL8 x x)
 13037  	for {
 13038  		if v.AuxInt != 9 {
 13039  			break
 13040  		}
 13041  		x := v.Args[0]
 13042  		v.reset(Op386LEAL8)
 13043  		v.AddArg(x)
 13044  		v.AddArg(x)
 13045  		return true
 13046  	}
 13047  	// match: (MULLconst [11] x)
 13048  	// cond:
 13049  	// result: (LEAL2 x (LEAL4 <v.Type> x x))
 13050  	for {
 13051  		if v.AuxInt != 11 {
 13052  			break
 13053  		}
 13054  		x := v.Args[0]
 13055  		v.reset(Op386LEAL2)
 13056  		v.AddArg(x)
 13057  		v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
 13058  		v0.AddArg(x)
 13059  		v0.AddArg(x)
 13060  		v.AddArg(v0)
 13061  		return true
 13062  	}
 13063  	// match: (MULLconst [13] x)
 13064  	// cond:
 13065  	// result: (LEAL4 x (LEAL2 <v.Type> x x))
 13066  	for {
 13067  		if v.AuxInt != 13 {
 13068  			break
 13069  		}
 13070  		x := v.Args[0]
 13071  		v.reset(Op386LEAL4)
 13072  		v.AddArg(x)
 13073  		v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
 13074  		v0.AddArg(x)
 13075  		v0.AddArg(x)
 13076  		v.AddArg(v0)
 13077  		return true
 13078  	}
 13079  	// match: (MULLconst [19] x)
 13080  	// cond:
 13081  	// result: (LEAL2 x (LEAL8 <v.Type> x x))
 13082  	for {
 13083  		if v.AuxInt != 19 {
 13084  			break
 13085  		}
 13086  		x := v.Args[0]
 13087  		v.reset(Op386LEAL2)
 13088  		v.AddArg(x)
 13089  		v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
 13090  		v0.AddArg(x)
 13091  		v0.AddArg(x)
 13092  		v.AddArg(v0)
 13093  		return true
 13094  	}
 13095  	// match: (MULLconst [21] x)
 13096  	// cond:
 13097  	// result: (LEAL4 x (LEAL4 <v.Type> x x))
 13098  	for {
 13099  		if v.AuxInt != 21 {
 13100  			break
 13101  		}
 13102  		x := v.Args[0]
 13103  		v.reset(Op386LEAL4)
 13104  		v.AddArg(x)
 13105  		v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
 13106  		v0.AddArg(x)
 13107  		v0.AddArg(x)
 13108  		v.AddArg(v0)
 13109  		return true
 13110  	}
 13111  	// match: (MULLconst [25] x)
 13112  	// cond:
 13113  	// result: (LEAL8 x (LEAL2 <v.Type> x x))
 13114  	for {
 13115  		if v.AuxInt != 25 {
 13116  			break
 13117  		}
 13118  		x := v.Args[0]
 13119  		v.reset(Op386LEAL8)
 13120  		v.AddArg(x)
 13121  		v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
 13122  		v0.AddArg(x)
 13123  		v0.AddArg(x)
 13124  		v.AddArg(v0)
 13125  		return true
 13126  	}
 13127  	// match: (MULLconst [27] x)
 13128  	// cond:
 13129  	// result: (LEAL8 (LEAL2 <v.Type> x x) (LEAL2 <v.Type> x x))
 13130  	for {
 13131  		if v.AuxInt != 27 {
 13132  			break
 13133  		}
 13134  		x := v.Args[0]
 13135  		v.reset(Op386LEAL8)
 13136  		v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
 13137  		v0.AddArg(x)
 13138  		v0.AddArg(x)
 13139  		v.AddArg(v0)
 13140  		v1 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
 13141  		v1.AddArg(x)
 13142  		v1.AddArg(x)
 13143  		v.AddArg(v1)
 13144  		return true
 13145  	}
 13146  	// match: (MULLconst [37] x)
 13147  	// cond:
 13148  	// result: (LEAL4 x (LEAL8 <v.Type> x x))
 13149  	for {
 13150  		if v.AuxInt != 37 {
 13151  			break
 13152  		}
 13153  		x := v.Args[0]
 13154  		v.reset(Op386LEAL4)
 13155  		v.AddArg(x)
 13156  		v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
 13157  		v0.AddArg(x)
 13158  		v0.AddArg(x)
 13159  		v.AddArg(v0)
 13160  		return true
 13161  	}
 13162  	// match: (MULLconst [41] x)
 13163  	// cond:
 13164  	// result: (LEAL8 x (LEAL4 <v.Type> x x))
 13165  	for {
 13166  		if v.AuxInt != 41 {
 13167  			break
 13168  		}
 13169  		x := v.Args[0]
 13170  		v.reset(Op386LEAL8)
 13171  		v.AddArg(x)
 13172  		v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
 13173  		v0.AddArg(x)
 13174  		v0.AddArg(x)
 13175  		v.AddArg(v0)
 13176  		return true
 13177  	}
 13178  	// match: (MULLconst [45] x)
 13179  	// cond:
 13180  	// result: (LEAL8 (LEAL4 <v.Type> x x) (LEAL4 <v.Type> x x))
 13181  	for {
 13182  		if v.AuxInt != 45 {
 13183  			break
 13184  		}
 13185  		x := v.Args[0]
 13186  		v.reset(Op386LEAL8)
 13187  		v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
 13188  		v0.AddArg(x)
 13189  		v0.AddArg(x)
 13190  		v.AddArg(v0)
 13191  		v1 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
 13192  		v1.AddArg(x)
 13193  		v1.AddArg(x)
 13194  		v.AddArg(v1)
 13195  		return true
 13196  	}
 13197  	return false
 13198  }
 13199  func rewriteValue386_Op386MULLconst_20(v *Value) bool {
 13200  	b := v.Block
 13201  	_ = b
 13202  	// match: (MULLconst [73] x)
 13203  	// cond:
 13204  	// result: (LEAL8 x (LEAL8 <v.Type> x x))
 13205  	for {
 13206  		if v.AuxInt != 73 {
 13207  			break
 13208  		}
 13209  		x := v.Args[0]
 13210  		v.reset(Op386LEAL8)
 13211  		v.AddArg(x)
 13212  		v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
 13213  		v0.AddArg(x)
 13214  		v0.AddArg(x)
 13215  		v.AddArg(v0)
 13216  		return true
 13217  	}
 13218  	// match: (MULLconst [81] x)
 13219  	// cond:
 13220  	// result: (LEAL8 (LEAL8 <v.Type> x x) (LEAL8 <v.Type> x x))
 13221  	for {
 13222  		if v.AuxInt != 81 {
 13223  			break
 13224  		}
 13225  		x := v.Args[0]
 13226  		v.reset(Op386LEAL8)
 13227  		v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
 13228  		v0.AddArg(x)
 13229  		v0.AddArg(x)
 13230  		v.AddArg(v0)
 13231  		v1 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
 13232  		v1.AddArg(x)
 13233  		v1.AddArg(x)
 13234  		v.AddArg(v1)
 13235  		return true
 13236  	}
 13237  	// match: (MULLconst [c] x)
 13238  	// cond: isPowerOfTwo(c+1) && c >= 15
 13239  	// result: (SUBL (SHLLconst <v.Type> [log2(c+1)] x) x)
 13240  	for {
 13241  		c := v.AuxInt
 13242  		x := v.Args[0]
 13243  		if !(isPowerOfTwo(c+1) && c >= 15) {
 13244  			break
 13245  		}
 13246  		v.reset(Op386SUBL)
 13247  		v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type)
 13248  		v0.AuxInt = log2(c + 1)
 13249  		v0.AddArg(x)
 13250  		v.AddArg(v0)
 13251  		v.AddArg(x)
 13252  		return true
 13253  	}
 13254  	// match: (MULLconst [c] x)
 13255  	// cond: isPowerOfTwo(c-1) && c >= 17
 13256  	// result: (LEAL1 (SHLLconst <v.Type> [log2(c-1)] x) x)
 13257  	for {
 13258  		c := v.AuxInt
 13259  		x := v.Args[0]
 13260  		if !(isPowerOfTwo(c-1) && c >= 17) {
 13261  			break
 13262  		}
 13263  		v.reset(Op386LEAL1)
 13264  		v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type)
 13265  		v0.AuxInt = log2(c - 1)
 13266  		v0.AddArg(x)
 13267  		v.AddArg(v0)
 13268  		v.AddArg(x)
 13269  		return true
 13270  	}
 13271  	// match: (MULLconst [c] x)
 13272  	// cond: isPowerOfTwo(c-2) && c >= 34
 13273  	// result: (LEAL2 (SHLLconst <v.Type> [log2(c-2)] x) x)
 13274  	for {
 13275  		c := v.AuxInt
 13276  		x := v.Args[0]
 13277  		if !(isPowerOfTwo(c-2) && c >= 34) {
 13278  			break
 13279  		}
 13280  		v.reset(Op386LEAL2)
 13281  		v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type)
 13282  		v0.AuxInt = log2(c - 2)
 13283  		v0.AddArg(x)
 13284  		v.AddArg(v0)
 13285  		v.AddArg(x)
 13286  		return true
 13287  	}
 13288  	// match: (MULLconst [c] x)
 13289  	// cond: isPowerOfTwo(c-4) && c >= 68
 13290  	// result: (LEAL4 (SHLLconst <v.Type> [log2(c-4)] x) x)
 13291  	for {
 13292  		c := v.AuxInt
 13293  		x := v.Args[0]
 13294  		if !(isPowerOfTwo(c-4) && c >= 68) {
 13295  			break
 13296  		}
 13297  		v.reset(Op386LEAL4)
 13298  		v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type)
 13299  		v0.AuxInt = log2(c - 4)
 13300  		v0.AddArg(x)
 13301  		v.AddArg(v0)
 13302  		v.AddArg(x)
 13303  		return true
 13304  	}
 13305  	// match: (MULLconst [c] x)
 13306  	// cond: isPowerOfTwo(c-8) && c >= 136
 13307  	// result: (LEAL8 (SHLLconst <v.Type> [log2(c-8)] x) x)
 13308  	for {
 13309  		c := v.AuxInt
 13310  		x := v.Args[0]
 13311  		if !(isPowerOfTwo(c-8) && c >= 136) {
 13312  			break
 13313  		}
 13314  		v.reset(Op386LEAL8)
 13315  		v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type)
 13316  		v0.AuxInt = log2(c - 8)
 13317  		v0.AddArg(x)
 13318  		v.AddArg(v0)
 13319  		v.AddArg(x)
 13320  		return true
 13321  	}
 13322  	// match: (MULLconst [c] x)
 13323  	// cond: c%3 == 0 && isPowerOfTwo(c/3)
 13324  	// result: (SHLLconst [log2(c/3)] (LEAL2 <v.Type> x x))
 13325  	for {
 13326  		c := v.AuxInt
 13327  		x := v.Args[0]
 13328  		if !(c%3 == 0 && isPowerOfTwo(c/3)) {
 13329  			break
 13330  		}
 13331  		v.reset(Op386SHLLconst)
 13332  		v.AuxInt = log2(c / 3)
 13333  		v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
 13334  		v0.AddArg(x)
 13335  		v0.AddArg(x)
 13336  		v.AddArg(v0)
 13337  		return true
 13338  	}
 13339  	// match: (MULLconst [c] x)
 13340  	// cond: c%5 == 0 && isPowerOfTwo(c/5)
 13341  	// result: (SHLLconst [log2(c/5)] (LEAL4 <v.Type> x x))
 13342  	for {
 13343  		c := v.AuxInt
 13344  		x := v.Args[0]
 13345  		if !(c%5 == 0 && isPowerOfTwo(c/5)) {
 13346  			break
 13347  		}
 13348  		v.reset(Op386SHLLconst)
 13349  		v.AuxInt = log2(c / 5)
 13350  		v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
 13351  		v0.AddArg(x)
 13352  		v0.AddArg(x)
 13353  		v.AddArg(v0)
 13354  		return true
 13355  	}
 13356  	// match: (MULLconst [c] x)
 13357  	// cond: c%9 == 0 && isPowerOfTwo(c/9)
 13358  	// result: (SHLLconst [log2(c/9)] (LEAL8 <v.Type> x x))
 13359  	for {
 13360  		c := v.AuxInt
 13361  		x := v.Args[0]
 13362  		if !(c%9 == 0 && isPowerOfTwo(c/9)) {
 13363  			break
 13364  		}
 13365  		v.reset(Op386SHLLconst)
 13366  		v.AuxInt = log2(c / 9)
 13367  		v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
 13368  		v0.AddArg(x)
 13369  		v0.AddArg(x)
 13370  		v.AddArg(v0)
 13371  		return true
 13372  	}
 13373  	return false
 13374  }
 13375  func rewriteValue386_Op386MULLconst_30(v *Value) bool {
 13376  	// match: (MULLconst [c] (MOVLconst [d]))
 13377  	// cond:
 13378  	// result: (MOVLconst [int64(int32(c*d))])
 13379  	for {
 13380  		c := v.AuxInt
 13381  		v_0 := v.Args[0]
 13382  		if v_0.Op != Op386MOVLconst {
 13383  			break
 13384  		}
 13385  		d := v_0.AuxInt
 13386  		v.reset(Op386MOVLconst)
 13387  		v.AuxInt = int64(int32(c * d))
 13388  		return true
 13389  	}
 13390  	return false
 13391  }
 13392  func rewriteValue386_Op386MULLload_0(v *Value) bool {
 13393  	b := v.Block
 13394  	_ = b
 13395  	config := b.Func.Config
 13396  	_ = config
 13397  	// match: (MULLload [off1] {sym} val (ADDLconst [off2] base) mem)
 13398  	// cond: is32Bit(off1+off2)
 13399  	// result: (MULLload [off1+off2] {sym} val base mem)
 13400  	for {
 13401  		off1 := v.AuxInt
 13402  		sym := v.Aux
 13403  		_ = v.Args[2]
 13404  		val := v.Args[0]
 13405  		v_1 := v.Args[1]
 13406  		if v_1.Op != Op386ADDLconst {
 13407  			break
 13408  		}
 13409  		off2 := v_1.AuxInt
 13410  		base := v_1.Args[0]
 13411  		mem := v.Args[2]
 13412  		if !(is32Bit(off1 + off2)) {
 13413  			break
 13414  		}
 13415  		v.reset(Op386MULLload)
 13416  		v.AuxInt = off1 + off2
 13417  		v.Aux = sym
 13418  		v.AddArg(val)
 13419  		v.AddArg(base)
 13420  		v.AddArg(mem)
 13421  		return true
 13422  	}
 13423  	// match: (MULLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
 13424  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
 13425  	// result: (MULLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
 13426  	for {
 13427  		off1 := v.AuxInt
 13428  		sym1 := v.Aux
 13429  		_ = v.Args[2]
 13430  		val := v.Args[0]
 13431  		v_1 := v.Args[1]
 13432  		if v_1.Op != Op386LEAL {
 13433  			break
 13434  		}
 13435  		off2 := v_1.AuxInt
 13436  		sym2 := v_1.Aux
 13437  		base := v_1.Args[0]
 13438  		mem := v.Args[2]
 13439  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
 13440  			break
 13441  		}
 13442  		v.reset(Op386MULLload)
 13443  		v.AuxInt = off1 + off2
 13444  		v.Aux = mergeSym(sym1, sym2)
 13445  		v.AddArg(val)
 13446  		v.AddArg(base)
 13447  		v.AddArg(mem)
 13448  		return true
 13449  	}
 13450  	// match: (MULLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem)
 13451  	// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
 13452  	// result: (MULLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem)
 13453  	for {
 13454  		off1 := v.AuxInt
 13455  		sym1 := v.Aux
 13456  		_ = v.Args[2]
 13457  		val := v.Args[0]
 13458  		v_1 := v.Args[1]
 13459  		if v_1.Op != Op386LEAL4 {
 13460  			break
 13461  		}
 13462  		off2 := v_1.AuxInt
 13463  		sym2 := v_1.Aux
 13464  		_ = v_1.Args[1]
 13465  		ptr := v_1.Args[0]
 13466  		idx := v_1.Args[1]
 13467  		mem := v.Args[2]
 13468  		if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
 13469  			break
 13470  		}
 13471  		v.reset(Op386MULLloadidx4)
 13472  		v.AuxInt = off1 + off2
 13473  		v.Aux = mergeSym(sym1, sym2)
 13474  		v.AddArg(val)
 13475  		v.AddArg(ptr)
 13476  		v.AddArg(idx)
 13477  		v.AddArg(mem)
 13478  		return true
 13479  	}
 13480  	return false
 13481  }
 13482  func rewriteValue386_Op386MULLloadidx4_0(v *Value) bool {
 13483  	b := v.Block
 13484  	_ = b
 13485  	config := b.Func.Config
 13486  	_ = config
 13487  	// match: (MULLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem)
 13488  	// cond: is32Bit(off1+off2)
 13489  	// result: (MULLloadidx4 [off1+off2] {sym} val base idx mem)
 13490  	for {
 13491  		off1 := v.AuxInt
 13492  		sym := v.Aux
 13493  		_ = v.Args[3]
 13494  		val := v.Args[0]
 13495  		v_1 := v.Args[1]
 13496  		if v_1.Op != Op386ADDLconst {
 13497  			break
 13498  		}
 13499  		off2 := v_1.AuxInt
 13500  		base := v_1.Args[0]
 13501  		idx := v.Args[2]
 13502  		mem := v.Args[3]
 13503  		if !(is32Bit(off1 + off2)) {
 13504  			break
 13505  		}
 13506  		v.reset(Op386MULLloadidx4)
 13507  		v.AuxInt = off1 + off2
 13508  		v.Aux = sym
 13509&