1 // Copyright 2019 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
4
5 #include "../../../../../runtime/textflag.h"
6
7 TEXT asmtest(SB),DUPOK|NOSPLIT,$0
8 start:
9 // Unprivileged ISA
10
11 // 2.4: Integer Computational Instructions
12
13 ADDI $2047, X5 // 9382f27f
14 ADDI $-2048, X5 // 93820280
15 ADDI $2048, X5 // 9382024093820240
16 ADDI $-2049, X5 // 938202c09382f2bf
17 ADDI $4094, X5 // 9382f27f9382f27f
18 ADDI $-4096, X5 // 9382028093820280
19 ADDI $4095, X5 // b71f00009b8fffffb382f201
20 ADDI $-4097, X5 // b7ffffff9b8fffffb382f201
21 ADDI $2047, X5, X6 // 1383f27f
22 ADDI $-2048, X5, X6 // 13830280
23 ADDI $2048, X5, X6 // 1383024013030340
24 ADDI $-2049, X5, X6 // 138302c01303f3bf
25 ADDI $4094, X5, X6 // 1383f27f1303f37f
26 ADDI $-4096, X5, X6 // 1383028013030380
27 ADDI $4095, X5, X6 // b71f00009b8fffff3383f201
28 ADDI $-4097, X5, X6 // b7ffffff9b8fffff3383f201
29
30 SLTI $55, X5, X7 // 93a37203
31 SLTIU $55, X5, X7 // 93b37203
32
33 ANDI $1, X5, X6 // 13f31200
34 ANDI $1, X5 // 93f21200
35 ANDI $2048, X5 // b71f00009b8f0f80b3f2f201
36 ORI $1, X5, X6 // 13e31200
37 ORI $1, X5 // 93e21200
38 ORI $2048, X5 // b71f00009b8f0f80b3e2f201
39 XORI $1, X5, X6 // 13c31200
40 XORI $1, X5 // 93c21200
41 XORI $2048, X5 // b71f00009b8f0f80b3c2f201
42
43 SLLI $1, X5, X6 // 13931200
44 SLLI $1, X5 // 93921200
45 SRLI $1, X5, X6 // 13d31200
46 SRLI $1, X5 // 93d21200
47 SRAI $1, X5, X6 // 13d31240
48 SRAI $1, X5 // 93d21240
49
50 ADD X6, X5, X7 // b3836200
51 ADD X5, X6 // 33035300
52 ADD $2047, X5, X6 // 1383f27f
53 ADD $-2048, X5, X6 // 13830280
54 ADD $2047, X5 // 9382f27f
55 ADD $-2048, X5 // 93820280
56
57 SLT X6, X5, X7 // b3a36200
58 SLT $55, X5, X7 // 93a37203
59 SLTU X6, X5, X7 // b3b36200
60 SLTU $55, X5, X7 // 93b37203
61
62 AND X6, X5, X7 // b3f36200
63 AND X5, X6 // 33735300
64 AND $1, X5, X6 // 13f31200
65 AND $1, X5 // 93f21200
66 OR X6, X5, X7 // b3e36200
67 OR X5, X6 // 33635300
68 OR $1, X5, X6 // 13e31200
69 OR $1, X5 // 93e21200
70 XOR X6, X5, X7 // b3c36200
71 XOR X5, X6 // 33435300
72 XOR $1, X5, X6 // 13c31200
73 XOR $1, X5 // 93c21200
74
75 AUIPC $0, X10 // 17050000
76 AUIPC $0, X11 // 97050000
77 AUIPC $1, X10 // 17150000
78 AUIPC $-524288, X15 // 97070080
79 AUIPC $524287, X10 // 17f5ff7f
80
81 LUI $0, X15 // b7070000
82 LUI $167, X15 // b7770a00
83 LUI $-524288, X15 // b7070080
84 LUI $524287, X15 // b7f7ff7f
85
86 SLL X6, X5, X7 // b3936200
87 SLL X5, X6 // 33135300
88 SLL $1, X5, X6 // 13931200
89 SLL $1, X5 // 93921200
90 SRL X6, X5, X7 // b3d36200
91 SRL X5, X6 // 33535300
92 SRL $1, X5, X6 // 13d31200
93 SRL $1, X5 // 93d21200
94
95 SUB X6, X5, X7 // b3836240
96 SUB X5, X6 // 33035340
97 SUB $-2047, X5, X6 // 1383f27f
98 SUB $2048, X5, X6 // 13830280
99 SUB $-2047, X5 // 9382f27f
100 SUB $2048, X5 // 93820280
101
102 SRA X6, X5, X7 // b3d36240
103 SRA X5, X6 // 33535340
104 SRA $1, X5, X6 // 13d31240
105 SRA $1, X5 // 93d21240
106
107 // 2.5: Control Transfer Instructions
108 JAL X5, 2(PC) // ef028000
109 JALR X6, (X5) // 67830200
110 JALR X6, 4(X5) // 67834200
111 BEQ X5, X6, 2(PC) // 63846200
112 BNE X5, X6, 2(PC) // 63946200
113 BLT X5, X6, 2(PC) // 63c46200
114 BLTU X5, X6, 2(PC) // 63e46200
115 BGE X5, X6, 2(PC) // 63d46200
116 BGEU X5, X6, 2(PC) // 63f46200
117
118 // 2.6: Load and Store Instructions
119 LW (X5), X6 // 03a30200
120 LW 4(X5), X6 // 03a34200
121 LWU (X5), X6 // 03e30200
122 LWU 4(X5), X6 // 03e34200
123 LH (X5), X6 // 03930200
124 LH 4(X5), X6 // 03934200
125 LHU (X5), X6 // 03d30200
126 LHU 4(X5), X6 // 03d34200
127 LB (X5), X6 // 03830200
128 LB 4(X5), X6 // 03834200
129 LBU (X5), X6 // 03c30200
130 LBU 4(X5), X6 // 03c34200
131
132 SW X5, (X6) // 23205300
133 SW X5, 4(X6) // 23225300
134 SH X5, (X6) // 23105300
135 SH X5, 4(X6) // 23125300
136 SB X5, (X6) // 23005300
137 SB X5, 4(X6) // 23025300
138
139 // 2.7: Memory Ordering Instructions
140 FENCE // 0f00f00f
141
142 // 5.2: Integer Computational Instructions (RV64I)
143 ADDIW $1, X5, X6 // 1b831200
144 SLLIW $1, X5, X6 // 1b931200
145 SRLIW $1, X5, X6 // 1bd31200
146 SRAIW $1, X5, X6 // 1bd31240
147 ADDW X5, X6, X7 // bb035300
148 SLLW X5, X6, X7 // bb135300
149 SRLW X5, X6, X7 // bb535300
150 SUBW X5, X6, X7 // bb035340
151 SRAW X5, X6, X7 // bb535340
152 ADDIW $1, X6 // 1b031300
153 SLLIW $1, X6 // 1b131300
154 SRLIW $1, X6 // 1b531300
155 SRAIW $1, X6 // 1b531340
156 ADDW X5, X7 // bb835300
157 SLLW X5, X7 // bb935300
158 SRLW X5, X7 // bbd35300
159 SUBW X5, X7 // bb835340
160 SRAW X5, X7 // bbd35340
161 ADDW $1, X6 // 1b031300
162 SLLW $1, X6 // 1b131300
163 SRLW $1, X6 // 1b531300
164 SUBW $1, X6 // 1b03f3ff
165 SRAW $1, X6 // 1b531340
166
167 // 5.3: Load and Store Instructions (RV64I)
168 LD (X5), X6 // 03b30200
169 LD 4(X5), X6 // 03b34200
170 SD X5, (X6) // 23305300
171 SD X5, 4(X6) // 23325300
172
173 // 7.1: Multiplication Operations
174 MUL X5, X6, X7 // b3035302
175 MULH X5, X6, X7 // b3135302
176 MULHU X5, X6, X7 // b3335302
177 MULHSU X5, X6, X7 // b3235302
178 MULW X5, X6, X7 // bb035302
179 DIV X5, X6, X7 // b3435302
180 DIVU X5, X6, X7 // b3535302
181 REM X5, X6, X7 // b3635302
182 REMU X5, X6, X7 // b3735302
183 DIVW X5, X6, X7 // bb435302
184 DIVUW X5, X6, X7 // bb535302
185 REMW X5, X6, X7 // bb635302
186 REMUW X5, X6, X7 // bb735302
187
188 // 8.2: Load-Reserved/Store-Conditional
189 LRW (X5), X6 // 2fa30214
190 LRD (X5), X6 // 2fb30214
191 SCW X5, (X6), X7 // af23531a
192 SCD X5, (X6), X7 // af33531a
193
194 // 8.3: Atomic Memory Operations
195 AMOSWAPW X5, (X6), X7 // af23530e
196 AMOSWAPD X5, (X6), X7 // af33530e
197 AMOADDW X5, (X6), X7 // af235306
198 AMOADDD X5, (X6), X7 // af335306
199 AMOANDW X5, (X6), X7 // af235366
200 AMOANDD X5, (X6), X7 // af335366
201 AMOORW X5, (X6), X7 // af235346
202 AMOORD X5, (X6), X7 // af335346
203 AMOXORW X5, (X6), X7 // af235326
204 AMOXORD X5, (X6), X7 // af335326
205 AMOMAXW X5, (X6), X7 // af2353a6
206 AMOMAXD X5, (X6), X7 // af3353a6
207 AMOMAXUW X5, (X6), X7 // af2353e6
208 AMOMAXUD X5, (X6), X7 // af3353e6
209 AMOMINW X5, (X6), X7 // af235386
210 AMOMIND X5, (X6), X7 // af335386
211 AMOMINUW X5, (X6), X7 // af2353c6
212 AMOMINUD X5, (X6), X7 // af3353c6
213
214 // 10.1: Base Counters and Timers
215 RDCYCLE X5 // f32200c0
216 RDTIME X5 // f32210c0
217 RDINSTRET X5 // f32220c0
218
219 // 11.5: Single-Precision Load and Store Instructions
220 FLW (X5), F0 // 07a00200
221 FLW 4(X5), F0 // 07a04200
222 FSW F0, (X5) // 27a00200
223 FSW F0, 4(X5) // 27a20200
224
225 // 11.6: Single-Precision Floating-Point Computational Instructions
226 FADDS F1, F0, F2 // 53011000
227 FSUBS F1, F0, F2 // 53011008
228 FMULS F1, F0, F2 // 53011010
229 FDIVS F1, F0, F2 // 53011018
230 FMINS F1, F0, F2 // 53011028
231 FMAXS F1, F0, F2 // 53111028
232 FSQRTS F0, F1 // d3000058
233
234 // 11.7: Single-Precision Floating-Point Conversion and Move Instructions
235 FCVTWS F0, X5 // d31200c0
236 FCVTLS F0, X5 // d31220c0
237 FCVTSW X5, F0 // 538002d0
238 FCVTSL X5, F0 // 538022d0
239 FCVTWUS F0, X5 // d31210c0
240 FCVTLUS F0, X5 // d31230c0
241 FCVTSWU X5, F0 // 538012d0
242 FCVTSLU X5, F0 // 538032d0
243 FSGNJS F1, F0, F2 // 53011020
244 FSGNJNS F1, F0, F2 // 53111020
245 FSGNJXS F1, F0, F2 // 53211020
246 FMVXS F0, X5 // d30200e0
247 FMVSX X5, F0 // 538002f0
248 FMVXW F0, X5 // d30200e0
249 FMVWX X5, F0 // 538002f0
250 FMADDS F1, F2, F3, F4 // 43822018
251 FMSUBS F1, F2, F3, F4 // 47822018
252 FNMSUBS F1, F2, F3, F4 // 4b822018
253 FNMADDS F1, F2, F3, F4 // 4f822018
254
255 // 11.8: Single-Precision Floating-Point Compare Instructions
256 FEQS F0, F1, X7 // d3a300a0
257 FLTS F0, F1, X7 // d39300a0
258 FLES F0, F1, X7 // d38300a0
259
260 // 11.9: Single-Precision Floating-Point Classify Instruction
261 FCLASSS F0, X5 // d31200e0
262
263 // 12.3: Double-Precision Load and Store Instructions
264 FLD (X5), F0 // 07b00200
265 FLD 4(X5), F0 // 07b04200
266 FSD F0, (X5) // 27b00200
267 FSD F0, 4(X5) // 27b20200
268
269 // 12.4: Double-Precision Floating-Point Computational Instructions
270 FADDD F1, F0, F2 // 53011002
271 FSUBD F1, F0, F2 // 5301100a
272 FMULD F1, F0, F2 // 53011012
273 FDIVD F1, F0, F2 // 5301101a
274 FMIND F1, F0, F2 // 5301102a
275 FMAXD F1, F0, F2 // 5311102a
276 FSQRTD F0, F1 // d300005a
277
278 // 12.5: Double-Precision Floating-Point Conversion and Move Instructions
279 FCVTWD F0, X5 // d31200c2
280 FCVTLD F0, X5 // d31220c2
281 FCVTDW X5, F0 // 538002d2
282 FCVTDL X5, F0 // 538022d2
283 FCVTWUD F0, X5 // d31210c2
284 FCVTLUD F0, X5 // d31230c2
285 FCVTDWU X5, F0 // 538012d2
286 FCVTDLU X5, F0 // 538032d2
287 FCVTSD F0, F1 // d3001040
288 FCVTDS F0, F1 // d3000042
289 FSGNJD F1, F0, F2 // 53011022
290 FSGNJND F1, F0, F2 // 53111022
291 FSGNJXD F1, F0, F2 // 53211022
292 FMVXD F0, X5 // d30200e2
293 FMVDX X5, F0 // 538002f2
294 FMADDD F1, F2, F3, F4 // 4382201a
295 FMSUBD F1, F2, F3, F4 // 4782201a
296 FNMSUBD F1, F2, F3, F4 // 4b82201a
297 FNMADDD F1, F2, F3, F4 // 4f82201a
298
299 // 12.6: Double-Precision Floating-Point Classify Instruction
300 FCLASSD F0, X5 // d31200e2
301
302 // Privileged ISA
303
304 // 3.2.1: Environment Call and Breakpoint
305 ECALL // 73000000
306 SCALL // 73000000
307 EBREAK // 73001000
308 SBREAK // 73001000
309
310 // Arbitrary bytes (entered in little-endian mode)
311 WORD $0x12345678 // WORD $305419896 // 78563412
312 WORD $0x9abcdef0 // WORD $2596069104 // f0debc9a
313
314 // MOV pseudo-instructions
315 MOV X5, X6 // 13830200
316 MOV $2047, X5 // 9302f07f
317 MOV $-2048, X5 // 93020080
318 MOV $2048, X5 // b71200009b820280
319 MOV $-2049, X5 // b7f2ffff9b82f27f
320 MOV $4096, X5 // b7120000
321 MOV $2147479552, X5 // b7f2ff7f
322 MOV $2147483647, X5 // b70200809b82f2ff
323 MOV $-2147483647, X5 // b70200809b821200
324
325 // Converted to load of symbol (AUIPC + LD)
326 MOV $4294967295, X5 // 9702000083b20200
327 // Converted to MOV $1, X5 + SLLI $32, X5
328 MOV $4294967296, X5 // 9302100093920202
329
330 MOV (X5), X6 // 03b30200
331 MOV 4(X5), X6 // 03b34200
332 MOVB (X5), X6 // 03830200
333 MOVB 4(X5), X6 // 03834200
334 MOVH (X5), X6 // 03930200
335 MOVH 4(X5), X6 // 03934200
336 MOVW (X5), X6 // 03a30200
337 MOVW 4(X5), X6 // 03a34200
338 MOV X5, (X6) // 23305300
339 MOV X5, 4(X6) // 23325300
340 MOVB X5, (X6) // 23005300
341 MOVB X5, 4(X6) // 23025300
342 MOVH X5, (X6) // 23105300
343 MOVH X5, 4(X6) // 23125300
344 MOVW X5, (X6) // 23205300
345 MOVW X5, 4(X6) // 23225300
346
347 MOVB X5, X6 // 1393820313538343
348 MOVH X5, X6 // 1393020313530343
349 MOVW X5, X6 // 1b830200
350 MOVBU X5, X6 // 13f3f20f
351 MOVHU X5, X6 // 1393020313530303
352 MOVWU X5, X6 // 1393020213530302
353
354 MOVF 4(X5), F0 // 07a04200
355 MOVF F0, 4(X5) // 27a20200
356 MOVF F0, F1 // d3000020
357
358 MOVD 4(X5), F0 // 07b04200
359 MOVD F0, 4(X5) // 27b20200
360 MOVD F0, F1 // d3000022
361
362 // TLS load with local-exec (LUI + ADDIW + ADD of TP + load)
363 MOV tls(SB), X5 // b70f00009b8f0f00b38f4f0083b20f00
364 MOVB tls(SB), X5 // b70f00009b8f0f00b38f4f0083820f00
365
366 // TLS store with local-exec (LUI + ADDIW + ADD of TP + store)
367 MOV X5, tls(SB) // b70f00009b8f0f00b38f4f0023b05f00
368 MOVB X5, tls(SB) // b70f00009b8f0f00b38f4f0023805f00
369
370 // NOT pseudo-instruction
371 NOT X5 // 93c2f2ff
372 NOT X5, X6 // 13c3f2ff
373
374 // NEG/NEGW pseudo-instructions
375 NEG X5 // b3025040
376 NEG X5, X6 // 33035040
377 NEGW X5 // bb025040
378 NEGW X5, X6 // 3b035040
379
380 // This jumps to the second instruction in the function (the
381 // first instruction is an invisible stack pointer adjustment).
382 JMP start // JMP 2
383
384 JMP 2(PC) // 6f008000
385 JMP (X5) // 67800200
386 JMP 4(X5) // 67804200
387
388 // CALL and JMP to symbol are encoded as JAL (using LR or ZERO
389 // respectively), with a R_RISCV_JAL relocation. The linker resolves
390 // the real address and updates the immediate, using a trampoline in
391 // the case where the address is not directly reachable.
392 CALL asmtest(SB) // ef000000
393 JMP asmtest(SB) // 6f000000
394
395 // Branch pseudo-instructions
396 BEQZ X5, 2(PC) // 63840200
397 BGEZ X5, 2(PC) // 63d40200
398 BGT X5, X6, 2(PC) // 63445300
399 BGTU X5, X6, 2(PC) // 63645300
400 BGTZ X5, 2(PC) // 63445000
401 BLE X5, X6, 2(PC) // 63545300
402 BLEU X5, X6, 2(PC) // 63745300
403 BLEZ X5, 2(PC) // 63545000
404 BLTZ X5, 2(PC) // 63c40200
405 BNEZ X5, 2(PC) // 63940200
406
407 // Set pseudo-instructions
408 SEQZ X15, X15 // 93b71700
409 SNEZ X15, X15 // b337f000
410
411 // F extension
412 FABSS F0, F1 // d3200020
413 FNEGS F0, F1 // d3100020
414 FNES F0, F1, X7 // d3a300a093c31300
415
416 // D extension
417 FABSD F0, F1 // d3200022
418 FNEGD F0, F1 // d3100022
419 FNED F0, F1, X5 // d3a200a293c21200
420 FLTD F0, F1, X5 // d39200a2
421 FLED F0, F1, X5 // d38200a2
422 FEQD F0, F1, X5 // d3a200a2
423
424 GLOBL tls(SB), TLSBSS, $8
425
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