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Source file src/cmd/asm/internal/arch/arm64.go

Documentation: cmd/asm/internal/arch

     1  // Copyright 2015 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  // This file encapsulates some of the odd characteristics of the ARM64
     6  // instruction set, to minimize its interaction with the core of the
     7  // assembler.
     8  
     9  package arch
    10  
    11  import (
    12  	"cmd/internal/obj"
    13  	"cmd/internal/obj/arm64"
    14  	"errors"
    15  )
    16  
    17  var arm64LS = map[string]uint8{
    18  	"P": arm64.C_XPOST,
    19  	"W": arm64.C_XPRE,
    20  }
    21  
    22  var arm64Jump = map[string]bool{
    23  	"B":     true,
    24  	"BL":    true,
    25  	"BEQ":   true,
    26  	"BNE":   true,
    27  	"BCS":   true,
    28  	"BHS":   true,
    29  	"BCC":   true,
    30  	"BLO":   true,
    31  	"BMI":   true,
    32  	"BPL":   true,
    33  	"BVS":   true,
    34  	"BVC":   true,
    35  	"BHI":   true,
    36  	"BLS":   true,
    37  	"BGE":   true,
    38  	"BLT":   true,
    39  	"BGT":   true,
    40  	"BLE":   true,
    41  	"CALL":  true,
    42  	"CBZ":   true,
    43  	"CBZW":  true,
    44  	"CBNZ":  true,
    45  	"CBNZW": true,
    46  	"JMP":   true,
    47  	"TBNZ":  true,
    48  	"TBZ":   true,
    49  }
    50  
    51  func jumpArm64(word string) bool {
    52  	return arm64Jump[word]
    53  }
    54  
    55  // IsARM64CMP reports whether the op (as defined by an arm.A* constant) is
    56  // one of the comparison instructions that require special handling.
    57  func IsARM64CMP(op obj.As) bool {
    58  	switch op {
    59  	case arm64.ACMN, arm64.ACMP, arm64.ATST,
    60  		arm64.ACMNW, arm64.ACMPW, arm64.ATSTW,
    61  		arm64.AFCMPS, arm64.AFCMPD,
    62  		arm64.AFCMPES, arm64.AFCMPED:
    63  		return true
    64  	}
    65  	return false
    66  }
    67  
    68  // IsARM64STLXR reports whether the op (as defined by an arm64.A*
    69  // constant) is one of the STLXR-like instructions that require special
    70  // handling.
    71  func IsARM64STLXR(op obj.As) bool {
    72  	switch op {
    73  	case arm64.ASTLXRB, arm64.ASTLXRH, arm64.ASTLXRW, arm64.ASTLXR,
    74  		arm64.ASTXRB, arm64.ASTXRH, arm64.ASTXRW, arm64.ASTXR,
    75  		arm64.ASTXP, arm64.ASTXPW, arm64.ASTLXP, arm64.ASTLXPW:
    76  		return true
    77  	}
    78  	// LDADDx/SWPx/CASx atomic instructions
    79  	if arm64.IsAtomicInstruction(op) {
    80  		return true
    81  	}
    82  	return false
    83  }
    84  
    85  // IsARM64TBL reports whether the op (as defined by an arm64.A*
    86  // constant) is one of the TBL-like instructions and one of its
    87  // inputs does not fit into prog.Reg, so require special handling.
    88  func IsARM64TBL(op obj.As) bool {
    89  	switch op {
    90  	case arm64.AVTBL, arm64.AVMOVQ:
    91  		return true
    92  	}
    93  	return false
    94  }
    95  
    96  // IsARM64CASP reports whether the op (as defined by an arm64.A*
    97  // constant) is one of the CASP-like instructions, and its 2nd
    98  // destination is a register pair that require special handling.
    99  func IsARM64CASP(op obj.As) bool {
   100  	switch op {
   101  	case arm64.ACASPD, arm64.ACASPW:
   102  		return true
   103  	}
   104  	return false
   105  }
   106  
   107  // ARM64Suffix handles the special suffix for the ARM64.
   108  // It returns a boolean to indicate success; failure means
   109  // cond was unrecognized.
   110  func ARM64Suffix(prog *obj.Prog, cond string) bool {
   111  	if cond == "" {
   112  		return true
   113  	}
   114  	bits, ok := parseARM64Suffix(cond)
   115  	if !ok {
   116  		return false
   117  	}
   118  	prog.Scond = bits
   119  	return true
   120  }
   121  
   122  // parseARM64Suffix parses the suffix attached to an ARM64 instruction.
   123  // The input is a single string consisting of period-separated condition
   124  // codes, such as ".P.W". An initial period is ignored.
   125  func parseARM64Suffix(cond string) (uint8, bool) {
   126  	if cond == "" {
   127  		return 0, true
   128  	}
   129  	return parseARMCondition(cond, arm64LS, nil)
   130  }
   131  
   132  func arm64RegisterNumber(name string, n int16) (int16, bool) {
   133  	switch name {
   134  	case "F":
   135  		if 0 <= n && n <= 31 {
   136  			return arm64.REG_F0 + n, true
   137  		}
   138  	case "R":
   139  		if 0 <= n && n <= 30 { // not 31
   140  			return arm64.REG_R0 + n, true
   141  		}
   142  	case "V":
   143  		if 0 <= n && n <= 31 {
   144  			return arm64.REG_V0 + n, true
   145  		}
   146  	}
   147  	return 0, false
   148  }
   149  
   150  // ARM64RegisterExtension parses an ARM64 register with extension or arrangement.
   151  func ARM64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, isIndex bool) error {
   152  	Rnum := (reg & 31) + int16(num<<5)
   153  	if isAmount {
   154  		if num < 0 || num > 7 {
   155  			return errors.New("index shift amount is out of range")
   156  		}
   157  	}
   158  	switch ext {
   159  	case "UXTB":
   160  		if !isAmount {
   161  			return errors.New("invalid register extension")
   162  		}
   163  		if a.Type == obj.TYPE_MEM {
   164  			return errors.New("invalid shift for the register offset addressing mode")
   165  		}
   166  		a.Reg = arm64.REG_UXTB + Rnum
   167  	case "UXTH":
   168  		if !isAmount {
   169  			return errors.New("invalid register extension")
   170  		}
   171  		if a.Type == obj.TYPE_MEM {
   172  			return errors.New("invalid shift for the register offset addressing mode")
   173  		}
   174  		a.Reg = arm64.REG_UXTH + Rnum
   175  	case "UXTW":
   176  		if !isAmount {
   177  			return errors.New("invalid register extension")
   178  		}
   179  		// effective address of memory is a base register value and an offset register value.
   180  		if a.Type == obj.TYPE_MEM {
   181  			a.Index = arm64.REG_UXTW + Rnum
   182  		} else {
   183  			a.Reg = arm64.REG_UXTW + Rnum
   184  		}
   185  	case "UXTX":
   186  		if !isAmount {
   187  			return errors.New("invalid register extension")
   188  		}
   189  		if a.Type == obj.TYPE_MEM {
   190  			return errors.New("invalid shift for the register offset addressing mode")
   191  		}
   192  		a.Reg = arm64.REG_UXTX + Rnum
   193  	case "SXTB":
   194  		if !isAmount {
   195  			return errors.New("invalid register extension")
   196  		}
   197  		a.Reg = arm64.REG_SXTB + Rnum
   198  	case "SXTH":
   199  		if !isAmount {
   200  			return errors.New("invalid register extension")
   201  		}
   202  		if a.Type == obj.TYPE_MEM {
   203  			return errors.New("invalid shift for the register offset addressing mode")
   204  		}
   205  		a.Reg = arm64.REG_SXTH + Rnum
   206  	case "SXTW":
   207  		if !isAmount {
   208  			return errors.New("invalid register extension")
   209  		}
   210  		if a.Type == obj.TYPE_MEM {
   211  			a.Index = arm64.REG_SXTW + Rnum
   212  		} else {
   213  			a.Reg = arm64.REG_SXTW + Rnum
   214  		}
   215  	case "SXTX":
   216  		if !isAmount {
   217  			return errors.New("invalid register extension")
   218  		}
   219  		if a.Type == obj.TYPE_MEM {
   220  			a.Index = arm64.REG_SXTX + Rnum
   221  		} else {
   222  			a.Reg = arm64.REG_SXTX + Rnum
   223  		}
   224  	case "LSL":
   225  		if !isAmount {
   226  			return errors.New("invalid register extension")
   227  		}
   228  		a.Index = arm64.REG_LSL + Rnum
   229  	case "B8":
   230  		if isIndex {
   231  			return errors.New("invalid register extension")
   232  		}
   233  		a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8B & 15) << 5)
   234  	case "B16":
   235  		if isIndex {
   236  			return errors.New("invalid register extension")
   237  		}
   238  		a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_16B & 15) << 5)
   239  	case "H4":
   240  		if isIndex {
   241  			return errors.New("invalid register extension")
   242  		}
   243  		a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_4H & 15) << 5)
   244  	case "H8":
   245  		if isIndex {
   246  			return errors.New("invalid register extension")
   247  		}
   248  		a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8H & 15) << 5)
   249  	case "S2":
   250  		if isIndex {
   251  			return errors.New("invalid register extension")
   252  		}
   253  		a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2S & 15) << 5)
   254  	case "S4":
   255  		if isIndex {
   256  			return errors.New("invalid register extension")
   257  		}
   258  		a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_4S & 15) << 5)
   259  	case "D1":
   260  		if isIndex {
   261  			return errors.New("invalid register extension")
   262  		}
   263  		a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1D & 15) << 5)
   264  	case "D2":
   265  		if isIndex {
   266  			return errors.New("invalid register extension")
   267  		}
   268  		a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2D & 15) << 5)
   269  	case "Q1":
   270  		if isIndex {
   271  			return errors.New("invalid register extension")
   272  		}
   273  		a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1Q & 15) << 5)
   274  	case "B":
   275  		if !isIndex {
   276  			return nil
   277  		}
   278  		a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_B & 15) << 5)
   279  		a.Index = num
   280  	case "H":
   281  		if !isIndex {
   282  			return nil
   283  		}
   284  		a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_H & 15) << 5)
   285  		a.Index = num
   286  	case "S":
   287  		if !isIndex {
   288  			return nil
   289  		}
   290  		a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_S & 15) << 5)
   291  		a.Index = num
   292  	case "D":
   293  		if !isIndex {
   294  			return nil
   295  		}
   296  		a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_D & 15) << 5)
   297  		a.Index = num
   298  	default:
   299  		return errors.New("unsupported register extension type: " + ext)
   300  	}
   301  
   302  	return nil
   303  }
   304  
   305  // ARM64RegisterArrangement parses an ARM64 vector register arrangement.
   306  func ARM64RegisterArrangement(reg int16, name, arng string) (int64, error) {
   307  	var curQ, curSize uint16
   308  	if name[0] != 'V' {
   309  		return 0, errors.New("expect V0 through V31; found: " + name)
   310  	}
   311  	if reg < 0 {
   312  		return 0, errors.New("invalid register number: " + name)
   313  	}
   314  	switch arng {
   315  	case "B8":
   316  		curSize = 0
   317  		curQ = 0
   318  	case "B16":
   319  		curSize = 0
   320  		curQ = 1
   321  	case "H4":
   322  		curSize = 1
   323  		curQ = 0
   324  	case "H8":
   325  		curSize = 1
   326  		curQ = 1
   327  	case "S2":
   328  		curSize = 2
   329  		curQ = 0
   330  	case "S4":
   331  		curSize = 2
   332  		curQ = 1
   333  	case "D1":
   334  		curSize = 3
   335  		curQ = 0
   336  	case "D2":
   337  		curSize = 3
   338  		curQ = 1
   339  	default:
   340  		return 0, errors.New("invalid arrangement in ARM64 register list")
   341  	}
   342  	return (int64(curQ) & 1 << 30) | (int64(curSize&3) << 10), nil
   343  }
   344  
   345  // ARM64RegisterListOffset generates offset encoding according to AArch64 specification.
   346  func ARM64RegisterListOffset(firstReg, regCnt int, arrangement int64) (int64, error) {
   347  	offset := int64(firstReg)
   348  	switch regCnt {
   349  	case 1:
   350  		offset |= 0x7 << 12
   351  	case 2:
   352  		offset |= 0xa << 12
   353  	case 3:
   354  		offset |= 0x6 << 12
   355  	case 4:
   356  		offset |= 0x2 << 12
   357  	default:
   358  		return 0, errors.New("invalid register numbers in ARM64 register list")
   359  	}
   360  	offset |= arrangement
   361  	// arm64 uses the 60th bit to differentiate from other archs
   362  	// For more details, refer to: obj/arm64/list7.go
   363  	offset |= 1 << 60
   364  	return offset, nil
   365  }
   366  

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