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Run Format

Package arm64

import "cmd/internal/obj/arm64"
Overview
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Package arm64 implements an ARM64 assembler. Go assembly syntax is different from GNU ARM64 syntax, but we can still follow the general rules to map between them.

Instructions mnemonics mapping rules

1. Most instructions use width suffixes of instruction names to indicate operand width rather than using different register names.

Examples:
  ADC R24, R14, R12          <=>     adc x12, x24
  ADDW R26->24, R21, R15     <=>     add w15, w21, w26, asr #24
  FCMPS F2, F3               <=>     fcmp s3, s2
  FCMPD F2, F3               <=>     fcmp d3, d2
  FCVTDH F2, F3              <=>     fcvt h3, d2

2. Go uses .P and .W suffixes to indicate post-increment and pre-increment.

Examples:
  MOVD.P -8(R10), R8         <=>      ldr x8, [x10],#-8
  MOVB.W 16(R16), R10        <=>      ldr x10, [x16,#16]!

3. Go uses a series of MOV instructions as load and store.

64-bit variant ldr, str, stur => MOVD; 32-bit variant str, stur, ldrsw => MOVW; 32-bit variant ldr => MOVWU; ldrb => MOVBU; ldrh => MOVHU; ldrsb, sturb, strb => MOVB; ldrsh, sturh, strh => MOVH.

4. Go moves conditions into opcode suffix, like BLT.

5. Go adds a V prefix for most floating-point and SIMD instrutions except cryptographic extension instructions and floating-point(scalar) instructions.

Examples:
  VADD V5.H8, V18.H8, V9.H8         <=>      add v9.8h, v18.8h, v5.8h
  VLD1.P (R6)(R11), [V31.D1]        <=>      ld1 {v31.1d}, [x6], x11
  VFMLA V29.S2, V20.S2, V14.S2      <=>      fmla v14.2s, v20.2s, v29.2s
  AESD V22.B16, V19.B16             <=>      aesd v19.16b, v22.16b
  SCVTFWS R3, F16                   <=>      scvtf s17, w6

Special Cases.

(1) umov is written as VMOV.

(2) br is renamed JMP, blr is renamed CALL.

(3) No need to add "W" suffix: LDARB, LDARH, LDAXRB, LDAXRH, LDTRH, LDXRB, LDXRH.

Examples:
  VMOV V13.B[1], R20      <=>      mov x20, v13.b[1]
  VMOV V13.H[1], R20      <=>      mov w20, v13.h[1]
  JMP (R3)                <=>      br x3
  CALL (R17)              <=>      blr x17
  LDAXRB (R19), R16       <=>      ldaxrb w16, [x19]

Register mapping rules

1. All basic register names are written as Rn.

2. Go uses ZR as the zero register and RSP as the stack pointer.

3. Bn, Hn, Dn, Sn and Qn instructions are written as Fn in floating-point instructions and as Vn in SIMD instructions.

Argument mapping rules

1. The operands appear in left-to-right assignment order.

Go reverses the arguments of most instructions.

Examples:
  ADD R11.SXTB<<1, RSP, R25      <=>      add x25, sp, w11, sxtb #1
  VADD V16, V19, V14             <=>      add d14, d19, d16

Special Cases.

(1) Argument order is the same as in the GNU ARM64 syntax: cbz, cbnz and some store instructions, such as str, stur, strb, sturb, strh, sturh stlr, stlrb. stlrh, st1.

Examples:
  MOVD R29, 384(R19)    <=>    str x29, [x19,#384]
  MOVB.P R30, 30(R4)    <=>    strb w30, [x4],#30
  STLRH R21, (R18)      <=>    stlrh w21, [x18]

(2) MADD, MADDW, MSUB, MSUBW, SMADDL, SMSUBL, UMADDL, UMSUBL <Rm>, <Ra>, <Rn>, <Rd>

Examples:
  MADD R2, R30, R22, R6       <=>    madd x6, x22, x2, x30
  SMSUBL R10, R3, R17, R27    <=>    smsubl x27, w17, w10, x3

(3) FMADDD, FMADDS, FMSUBD, FMSUBS, FNMADDD, FNMADDS, FNMSUBD, FNMSUBS <Fm>, <Fa>, <Fn>, <Fd>

Examples:
  FMADDD F30, F20, F3, F29    <=>    fmadd d29, d3, d30, d20
  FNMSUBS F7, F25, F7, F22    <=>    fnmsub s22, s7, s7, s25

(4) BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX $<lsb>, <Rn>, $<width>, <Rd>

Examples:
  BFIW $16, R20, $6, R0      <=>    bfi w0, w20, #16, #6
  UBFIZ $34, R26, $5, R20    <=>    ubfiz x20, x26, #34, #5

(5) FCCMPD, FCCMPS, FCCMPED, FCCMPES <cond>, Fm. Fn, $<nzcv>

Examples:
  FCCMPD AL, F8, F26, $0     <=>    fccmp d26, d8, #0x0, al
  FCCMPS VS, F29, F4, $4     <=>    fccmp s4, s29, #0x4, vs
  FCCMPED LE, F20, F5, $13   <=>    fccmpe d5, d20, #0xd, le
  FCCMPES NE, F26, F10, $0   <=>    fccmpe s10, s26, #0x0, ne

(6) CCMN, CCMNW, CCMP, CCMPW <cond>, <Rn>, $<imm>, $<nzcv>

Examples:
  CCMP MI, R22, $12, $13     <=>    ccmp x22, #0xc, #0xd, mi
  CCMNW AL, R1, $11, $8      <=>    ccmn w1, #0xb, #0x8, al

(7) CCMN, CCMNW, CCMP, CCMPW <cond>, <Rn>, <Rm>, $<nzcv>

Examples:
  CCMN VS, R13, R22, $10     <=>    ccmn x13, x22, #0xa, vs
  CCMPW HS, R18, R14, $11    <=>    ccmp w18, w14, #0xb, cs

(9) CSEL, CSELW, CSNEG, CSNEGW, CSINC, CSINCW <cond>, <Rn>, <Rm>, <Rd> ; FCSELD, FCSELS <cond>, <Fn>, <Fm>, <Fd>

Examples:
  CSEL GT, R0, R19, R1        <=>    csel x1, x0, x19, gt
  CSNEGW GT, R7, R17, R8      <=>    csneg w8, w7, w17, gt
  FCSELD EQ, F15, F18, F16    <=>    fcsel d16, d15, d18, eq

(10) TBNZ, TBZ $<imm>, <Rt>, <label>

(11) STLXR, STLXRW, STXR, STXRW, STLXRB, STLXRH, STXRB, STXRH <Rf>, (<Rn|RSP>), <Rs>

Examples:
  STLXR ZR, (R15), R16    <=>    stlxr w16, xzr, [x15]
  STXRB R9, (R21), R18    <=>    stxrb w18, w9, [x21]

(12) STLXP, STLXPW, STXP, STXPW (<Rf1>, <Rf2>), (<Rn|RSP>), <Rs>

Examples:
  STLXP (R17, R18), (R4), R5      <=>    stlxp w5, x17, x18, [x4]
  STXPW (R30, R25), (R22), R13    <=>    stxp w13, w30, w25, [x22]

2. Expressions for special arguments.

#<immediate> is written as $<immediate>.

Optionally-shifted immedate.

Examples:
  ADD $(3151<<12), R14, R20     <=>    add x20, x14, #0xc4f, lsl #12
  ADDW $1864, R25, R6           <=>    add w6, w25, #0x748

Optionally-shifted registers are written as <Rm>{<shift><amount>}. The <shift> can be <<(lsl), >>(lsr), ->(asr), @>(ror).

Examples:
  ADD R19>>30, R10, R24     <=>    add x24, x10, x19, lsr #30
  ADDW R26->24, R21, R15    <=>    add w15, w21, w26, asr #24

Extended registers are written as <Rm>{.<extend>{<<<amount>}}. <extend> can be UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW or SXTX.

Examples:
  ADDS R18.UXTB<<4, R9, R26     <=>    adds x26, x9, w18, uxtb #4
  ADDSW R14.SXTX, R14, R6       <=>    adds w6, w14, w14, sxtx

Memory references: [<Xn|SP>{,#0}] is written as (Rn|RSP), a base register and an immediate offset is written as imm(Rn|RSP), a base register and an offset register is written as (Rn|RSP)(Rm).

Examples:
  LDAR (R22), R9                  <=>    ldar x9, [x22]
  LDP 28(R17), (R15, R23)         <=>    ldp x15, x23, [x17,#28]
  MOVWU (R4)(R12<<2), R8          <=>    ldr w8, [x4, x12, lsl #2]
  MOVD (R7)(R11.UXTW<<3), R25     <=>    ldr x25, [x7,w11,uxtw #3]
  MOVBU (R27)(R23), R14           <=>    ldrb w14, [x27,x23]

Register pairs are written as (Rt1, Rt2).

Examples:
  LDP.P -240(R11), (R12, R26)    <=>    ldp x12, x26, [x11],#-240

Register with arrangement and register with arrangement and index.

Examples:
  VADD V5.H8, V18.H8, V9.H8                     <=>    add v9.8h, v18.8h, v5.8h
  VLD1 (R2), [V21.B16]                          <=>    ld1 {v21.16b}, [x2]
  VST1.P V9.S[1], (R16)(R21)                    <=>    st1 {v9.s}[1], [x16], x28
  VST1.P [V13.H8, V14.H8, V15.H8], (R3)(R14)    <=>    st1 {v13.8h-v15.8h}, [x3], x14
  VST1.P [V14.D1, V15.D1], (R7)(R23)            <=>    st1 {v14.1d, v15.1d}, [x7], x23

Constants

const (
        NSNAME = 8
        NSYM   = 50
        NREG   = 32 /* number of general registers */
        NFREG  = 32 /* number of floating point registers */
)

General purpose registers, kept in the low bits of Prog.Reg.

const (
        // integer
        REG_R0 = obj.RBaseARM64 + iota
        REG_R1
        REG_R2
        REG_R3
        REG_R4
        REG_R5
        REG_R6
        REG_R7
        REG_R8
        REG_R9
        REG_R10
        REG_R11
        REG_R12
        REG_R13
        REG_R14
        REG_R15
        REG_R16
        REG_R17
        REG_R18
        REG_R19
        REG_R20
        REG_R21
        REG_R22
        REG_R23
        REG_R24
        REG_R25
        REG_R26
        REG_R27
        REG_R28
        REG_R29
        REG_R30
        REG_R31

        // scalar floating point
        REG_F0
        REG_F1
        REG_F2
        REG_F3
        REG_F4
        REG_F5
        REG_F6
        REG_F7
        REG_F8
        REG_F9
        REG_F10
        REG_F11
        REG_F12
        REG_F13
        REG_F14
        REG_F15
        REG_F16
        REG_F17
        REG_F18
        REG_F19
        REG_F20
        REG_F21
        REG_F22
        REG_F23
        REG_F24
        REG_F25
        REG_F26
        REG_F27
        REG_F28
        REG_F29
        REG_F30
        REG_F31

        // SIMD
        REG_V0
        REG_V1
        REG_V2
        REG_V3
        REG_V4
        REG_V5
        REG_V6
        REG_V7
        REG_V8
        REG_V9
        REG_V10
        REG_V11
        REG_V12
        REG_V13
        REG_V14
        REG_V15
        REG_V16
        REG_V17
        REG_V18
        REG_V19
        REG_V20
        REG_V21
        REG_V22
        REG_V23
        REG_V24
        REG_V25
        REG_V26
        REG_V27
        REG_V28
        REG_V29
        REG_V30
        REG_V31

        // The EQ in
        // 	CSET	EQ, R0
        // is encoded as TYPE_REG, even though it's not really a register.
        COND_EQ
        COND_NE
        COND_HS
        COND_LO
        COND_MI
        COND_PL
        COND_VS
        COND_VC
        COND_HI
        COND_LS
        COND_GE
        COND_LT
        COND_GT
        COND_LE
        COND_AL
        COND_NV

        REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31
)

bits 0-4 indicates register: Vn bits 5-8 indicates arrangement: <T>

const (
        REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn.<T>
        REG_ELEM                                    // Vn.<T>[index]
        REG_ELEM_END
)
const (
        REG_UXTB = REG_EXT + iota<<8
        REG_UXTH
        REG_UXTW
        REG_UXTX
        REG_SXTB
        REG_SXTH
        REG_SXTW
        REG_SXTX
)

Special registers, after subtracting obj.RBaseARM64, bit 12 indicates a special register and the low bits select the register.

const (
        REG_SPECIAL = obj.RBaseARM64 + 1<<12 + iota
        REG_DAIF
        REG_NZCV
        REG_FPSR
        REG_FPCR
        REG_SPSR_EL1
        REG_ELR_EL1
        REG_SPSR_EL2
        REG_ELR_EL2
        REG_CurrentEL
        REG_SP_EL0
        REG_SPSel
        REG_DAIFSet
        REG_DAIFClr
        REG_DCZID_EL0
        REG_PLDL1KEEP
        REG_PLDL1STRM
        REG_PLDL2KEEP
        REG_PLDL2STRM
        REG_PLDL3KEEP
        REG_PLDL3STRM
        REG_PLIL1KEEP
        REG_PLIL1STRM
        REG_PLIL2KEEP
        REG_PLIL2STRM
        REG_PLIL3KEEP
        REG_PLIL3STRM
        REG_PSTL1KEEP
        REG_PSTL1STRM
        REG_PSTL2KEEP
        REG_PSTL2STRM
        REG_PSTL3KEEP
        REG_PSTL3STRM
)

Register assignments:

compiler allocates R0 up as temps compiler allocates register variables R7-R25 compiler allocates external registers R26 down

compiler allocates register variables F7-F26 compiler allocates external registers F26 down

const (
        REGMIN = REG_R7  // register variables allocated from here to REGMAX
        REGRT1 = REG_R16 // ARM64 IP0, for external linker, runtime, duffzero and duffcopy
        REGRT2 = REG_R17 // ARM64 IP1, for external linker, runtime, duffcopy
        REGPR  = REG_R18 // ARM64 platform register, unused in the Go toolchain
        REGMAX = REG_R25

        REGCTXT = REG_R26 // environment for closures
        REGTMP  = REG_R27 // reserved for liblink
        REGG    = REG_R28 // G
        REGFP   = REG_R29 // frame pointer, unused in the Go toolchain
        REGLINK = REG_R30

        // ARM64 uses R31 as both stack pointer and zero register,
        // depending on the instruction. To differentiate RSP from ZR,
        // we use a different numeric value for REGZERO and REGSP.
        REGZERO = REG_R31
        REGSP   = REG_RSP

        FREGRET = REG_F0
        FREGMIN = REG_F7  // first register variable
        FREGMAX = REG_F26 // last register variable for 7g only
        FREGEXT = REG_F26 // first external register
)
const (
        /* mark flags */
        LABEL = 1 << iota
        LEAF
        FLOAT
        BRANCH
        LOAD
        FCMP
        SYNC
        LIST
        FOLL
        NOSCHED
)
const (
        // optab is sorted based on the order of these constants
        // and the first match is chosen.
        // The more specific class needs to come earlier.
        C_NONE   = iota
        C_REG    // R0..R30
        C_RSP    // R0..R30, RSP
        C_FREG   // F0..F31
        C_VREG   // V0..V31
        C_PAIR   // (Rn, Rm)
        C_SHIFT  // Rn<<2
        C_EXTREG // Rn.UXTB[<<3]
        C_SPR    // REG_NZCV
        C_COND   // EQ, NE, etc
        C_ARNG   // Vn.<T>
        C_ELEM   // Vn.<T>[index]
        C_LIST   // [V1, V2, V3]

        C_ZCON     // $0 or ZR
        C_ABCON0   // could be C_ADDCON0 or C_BITCON
        C_ADDCON0  // 12-bit unsigned, unshifted
        C_ABCON    // could be C_ADDCON or C_BITCON
        C_ADDCON   // 12-bit unsigned, shifted left by 0 or 12
        C_MBCON    // could be C_MOVCON or C_BITCON
        C_MOVCON   // generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16
        C_BITCON   // bitfield and logical immediate masks
        C_LCON     // 32-bit constant
        C_VCON     // 64-bit constant
        C_FCON     // floating-point constant
        C_VCONADDR // 64-bit memory address

        C_AACON // ADDCON offset in auto constant $a(FP)
        C_LACON // 32-bit offset in auto constant $a(FP)
        C_AECON // ADDCON offset in extern constant $e(SB)

        // TODO(aram): only one branch class should be enough
        C_SBRA // for TYPE_BRANCH
        C_LBRA

        C_ZAUTO      // 0(RSP)
        C_NSAUTO_8   // -256 <= x < 0, 0 mod 8
        C_NSAUTO_4   // -256 <= x < 0, 0 mod 4
        C_NSAUTO     // -256 <= x < 0
        C_NPAUTO     // -512 <= x < 0, 0 mod 8
        C_NAUTO4K    // -4095 <= x < 0
        C_PSAUTO_8   // 0 to 255, 0 mod 8
        C_PSAUTO_4   // 0 to 255, 0 mod 4
        C_PSAUTO     // 0 to 255
        C_PPAUTO     // 0 to 504, 0 mod 8
        C_UAUTO4K_8  // 0 to 4095, 0 mod 8
        C_UAUTO4K_4  // 0 to 4095, 0 mod 4
        C_UAUTO4K_2  // 0 to 4095, 0 mod 2
        C_UAUTO4K    // 0 to 4095
        C_UAUTO8K_8  // 0 to 8190, 0 mod 8
        C_UAUTO8K_4  // 0 to 8190, 0 mod 4
        C_UAUTO8K    // 0 to 8190, 0 mod 2
        C_UAUTO16K_8 // 0 to 16380, 0 mod 8
        C_UAUTO16K   // 0 to 16380, 0 mod 4
        C_UAUTO32K   // 0 to 32760, 0 mod 8
        C_LAUTO      // any other 32-bit constant

        C_SEXT1  // 0 to 4095, direct
        C_SEXT2  // 0 to 8190
        C_SEXT4  // 0 to 16380
        C_SEXT8  // 0 to 32760
        C_SEXT16 // 0 to 65520
        C_LEXT

        C_ZOREG    // 0(R)
        C_NSOREG_8 // must mirror C_NSAUTO_8, etc
        C_NSOREG_4
        C_NSOREG
        C_NPOREG
        C_NOREG4K
        C_PSOREG_8
        C_PSOREG_4
        C_PSOREG
        C_PPOREG
        C_UOREG4K_8
        C_UOREG4K_4
        C_UOREG4K_2
        C_UOREG4K
        C_UOREG8K_8
        C_UOREG8K_4
        C_UOREG8K
        C_UOREG16K_8
        C_UOREG16K
        C_UOREG32K
        C_LOREG

        C_ADDR // TODO(aram): explain difference from C_VCONADDR

        // The GOT slot for a symbol in -dynlink mode.
        C_GOTADDR

        // TLS "var" in local exec mode: will become a constant offset from
        // thread local base that is ultimately chosen by the program linker.
        C_TLS_LE

        // TLS "var" in initial exec mode: will become a memory address (chosen
        // by the program linker) that the dynamic linker will fill with the
        // offset from the thread local base.
        C_TLS_IE

        C_ROFF // register offset (including register extended)

        C_GOK
        C_TEXTSIZE
        C_NCLASS // must be last
)
const (
        C_XPRE  = 1 << 6 // match arm.C_WBIT, so Prog.String know how to print it
        C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it
)
const (
        AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota
        AADCS
        AADCSW
        AADCW
        AADD
        AADDS
        AADDSW
        AADDW
        AADR
        AADRP
        AAND
        AANDS
        AANDSW
        AANDW
        AASR
        AASRW
        AAT
        ABFI
        ABFIW
        ABFM
        ABFMW
        ABFXIL
        ABFXILW
        ABIC
        ABICS
        ABICSW
        ABICW
        ABRK
        ACBNZ
        ACBNZW
        ACBZ
        ACBZW
        ACCMN
        ACCMNW
        ACCMP
        ACCMPW
        ACINC
        ACINCW
        ACINV
        ACINVW
        ACLREX
        ACLS
        ACLSW
        ACLZ
        ACLZW
        ACMN
        ACMNW
        ACMP
        ACMPW
        ACNEG
        ACNEGW
        ACRC32B
        ACRC32CB
        ACRC32CH
        ACRC32CW
        ACRC32CX
        ACRC32H
        ACRC32W
        ACRC32X
        ACSEL
        ACSELW
        ACSET
        ACSETM
        ACSETMW
        ACSETW
        ACSINC
        ACSINCW
        ACSINV
        ACSINVW
        ACSNEG
        ACSNEGW
        ADC
        ADCPS1
        ADCPS2
        ADCPS3
        ADMB
        ADRPS
        ADSB
        AEON
        AEONW
        AEOR
        AEORW
        AERET
        AEXTR
        AEXTRW
        AHINT
        AHLT
        AHVC
        AIC
        AISB
        ALDADDALD
        ALDADDALW
        ALDADDB
        ALDADDH
        ALDADDW
        ALDADDD
        ALDANDB
        ALDANDH
        ALDANDW
        ALDANDD
        ALDAR
        ALDARB
        ALDARH
        ALDARW
        ALDAXP
        ALDAXPW
        ALDAXR
        ALDAXRB
        ALDAXRH
        ALDAXRW
        ALDEORB
        ALDEORH
        ALDEORW
        ALDEORD
        ALDORB
        ALDORH
        ALDORW
        ALDORD
        ALDP
        ALDPW
        ALDPSW
        ALDXR
        ALDXRB
        ALDXRH
        ALDXRW
        ALDXP
        ALDXPW
        ALSL
        ALSLW
        ALSR
        ALSRW
        AMADD
        AMADDW
        AMNEG
        AMNEGW
        AMOVK
        AMOVKW
        AMOVN
        AMOVNW
        AMOVZ
        AMOVZW
        AMRS
        AMSR
        AMSUB
        AMSUBW
        AMUL
        AMULW
        AMVN
        AMVNW
        ANEG
        ANEGS
        ANEGSW
        ANEGW
        ANGC
        ANGCS
        ANGCSW
        ANGCW
        AORN
        AORNW
        AORR
        AORRW
        APRFM
        APRFUM
        ARBIT
        ARBITW
        AREM
        AREMW
        AREV
        AREV16
        AREV16W
        AREV32
        AREVW
        AROR
        ARORW
        ASBC
        ASBCS
        ASBCSW
        ASBCW
        ASBFIZ
        ASBFIZW
        ASBFM
        ASBFMW
        ASBFX
        ASBFXW
        ASDIV
        ASDIVW
        ASEV
        ASEVL
        ASMADDL
        ASMC
        ASMNEGL
        ASMSUBL
        ASMULH
        ASMULL
        ASTXR
        ASTXRB
        ASTXRH
        ASTXP
        ASTXPW
        ASTXRW
        ASTLP
        ASTLPW
        ASTLR
        ASTLRB
        ASTLRH
        ASTLRW
        ASTLXP
        ASTLXPW
        ASTLXR
        ASTLXRB
        ASTLXRH
        ASTLXRW
        ASTP
        ASTPW
        ASUB
        ASUBS
        ASUBSW
        ASUBW
        ASVC
        ASXTB
        ASXTBW
        ASXTH
        ASXTHW
        ASXTW
        ASYS
        ASYSL
        ATBNZ
        ATBZ
        ATLBI
        ATST
        ATSTW
        AUBFIZ
        AUBFIZW
        AUBFM
        AUBFMW
        AUBFX
        AUBFXW
        AUDIV
        AUDIVW
        AUMADDL
        AUMNEGL
        AUMSUBL
        AUMULH
        AUMULL
        AUREM
        AUREMW
        AUXTB
        AUXTH
        AUXTW
        AUXTBW
        AUXTHW
        AWFE
        AWFI
        AYIELD
        AMOVB
        AMOVBU
        AMOVH
        AMOVHU
        AMOVW
        AMOVWU
        AMOVD
        AMOVNP
        AMOVNPW
        AMOVP
        AMOVPD
        AMOVPQ
        AMOVPS
        AMOVPSW
        AMOVPW
        ASWPD
        ASWPW
        ASWPH
        ASWPB
        ABEQ
        ABNE
        ABCS
        ABHS
        ABCC
        ABLO
        ABMI
        ABPL
        ABVS
        ABVC
        ABHI
        ABLS
        ABGE
        ABLT
        ABGT
        ABLE
        AFABSD
        AFABSS
        AFADDD
        AFADDS
        AFCCMPD
        AFCCMPED
        AFCCMPS
        AFCCMPES
        AFCMPD
        AFCMPED
        AFCMPES
        AFCMPS
        AFCVTSD
        AFCVTDS
        AFCVTZSD
        AFCVTZSDW
        AFCVTZSS
        AFCVTZSSW
        AFCVTZUD
        AFCVTZUDW
        AFCVTZUS
        AFCVTZUSW
        AFDIVD
        AFDIVS
        AFMOVD
        AFMOVS
        AFMULD
        AFMULS
        AFNEGD
        AFNEGS
        AFSQRTD
        AFSQRTS
        AFSUBD
        AFSUBS
        ASCVTFD
        ASCVTFS
        ASCVTFWD
        ASCVTFWS
        AUCVTFD
        AUCVTFS
        AUCVTFWD
        AUCVTFWS
        AWORD
        ADWORD
        AFCSELS
        AFCSELD
        AFMAXS
        AFMINS
        AFMAXD
        AFMIND
        AFMAXNMS
        AFMAXNMD
        AFNMULS
        AFNMULD
        AFRINTNS
        AFRINTND
        AFRINTPS
        AFRINTPD
        AFRINTMS
        AFRINTMD
        AFRINTZS
        AFRINTZD
        AFRINTAS
        AFRINTAD
        AFRINTXS
        AFRINTXD
        AFRINTIS
        AFRINTID
        AFMADDS
        AFMADDD
        AFMSUBS
        AFMSUBD
        AFNMADDS
        AFNMADDD
        AFNMSUBS
        AFNMSUBD
        AFMINNMS
        AFMINNMD
        AFCVTDH
        AFCVTHS
        AFCVTHD
        AFCVTSH
        AAESD
        AAESE
        AAESIMC
        AAESMC
        ASHA1C
        ASHA1H
        ASHA1M
        ASHA1P
        ASHA1SU0
        ASHA1SU1
        ASHA256H
        ASHA256H2
        ASHA256SU0
        ASHA256SU1
        AVADD
        AVADDP
        AVAND
        AVCMEQ
        AVCNT
        AVEOR
        AVMOV
        AVLD1
        AVORR
        AVREV32
        AVREV64
        AVST1
        AVDUP
        AVADDV
        AVMOVI
        AVUADDLV
        AVSUB
        AVFMLA
        AVFMLS
        AVPMULL
        AVPMULL2
        AVEXT
        AVRBIT
        AVUSHR
        AVSHL
        AVSRI
        AVTBL
        AVZIP1
        AVZIP2
        ALAST
        AB  = obj.AJMP
        ABL = obj.ACALL
)
const (
        // shift types
        SHIFT_LL = 0 << 22
        SHIFT_LR = 1 << 22
        SHIFT_AR = 2 << 22
)

Arrangement for ARM64 SIMD instructions

const (
        // arrangement types
        ARNG_8B = iota
        ARNG_16B
        ARNG_1D
        ARNG_4H
        ARNG_8H
        ARNG_2S
        ARNG_4S
        ARNG_2D
        ARNG_1Q
        ARNG_B
        ARNG_H
        ARNG_S
        ARNG_D
)
const (
        S32     = 0 << 31
        S64     = 1 << 31
        Sbit    = 1 << 29
        LSL0_32 = 2 << 13
        LSL0_64 = 3 << 13
)
const (
        LFROM = 1 << 0
        LTO   = 1 << 1
)
const (
        BIG = 2048 - 8
)
const (
        REGFROM = 1
)
const REG_EXT = obj.RBaseARM64 + 1<<11

Not registers, but flags that can be combined with regular register constants to indicate extended register conversion. When checking, you should subtract obj.RBaseARM64 first. From this difference, bit 11 indicates extended register, bits 8-10 select the conversion mode. REG_LSL is the index shift specifier, bit 9 indicates shifted offset register.

const REG_LSL = obj.RBaseARM64 + 1<<9

Variables

http://infocenter.arm.com/help/topic/com.arm.doc.ecm0665627/abi_sve_aadwarf_100985_0000_00_en.pdf

var ARM64DWARFRegisters = map[int16]int16{
        REG_R0:  0,
        REG_R1:  1,
        REG_R2:  2,
        REG_R3:  3,
        REG_R4:  4,
        REG_R5:  5,
        REG_R6:  6,
        REG_R7:  7,
        REG_R8:  8,
        REG_R9:  9,
        REG_R10: 10,
        REG_R11: 11,
        REG_R12: 12,
        REG_R13: 13,
        REG_R14: 14,
        REG_R15: 15,
        REG_R16: 16,
        REG_R17: 17,
        REG_R18: 18,
        REG_R19: 19,
        REG_R20: 20,
        REG_R21: 21,
        REG_R22: 22,
        REG_R23: 23,
        REG_R24: 24,
        REG_R25: 25,
        REG_R26: 26,
        REG_R27: 27,
        REG_R28: 28,
        REG_R29: 29,
        REG_R30: 30,

        REG_F0:  64,
        REG_F1:  65,
        REG_F2:  66,
        REG_F3:  67,
        REG_F4:  68,
        REG_F5:  69,
        REG_F6:  70,
        REG_F7:  71,
        REG_F8:  72,
        REG_F9:  73,
        REG_F10: 74,
        REG_F11: 75,
        REG_F12: 76,
        REG_F13: 77,
        REG_F14: 78,
        REG_F15: 79,
        REG_F16: 80,
        REG_F17: 81,
        REG_F18: 82,
        REG_F19: 83,
        REG_F20: 84,
        REG_F21: 85,
        REG_F22: 86,
        REG_F23: 87,
        REG_F24: 88,
        REG_F25: 89,
        REG_F26: 90,
        REG_F27: 91,
        REG_F28: 92,
        REG_F29: 93,
        REG_F30: 94,
        REG_F31: 95,

        REG_V0:  64,
        REG_V1:  65,
        REG_V2:  66,
        REG_V3:  67,
        REG_V4:  68,
        REG_V5:  69,
        REG_V6:  70,
        REG_V7:  71,
        REG_V8:  72,
        REG_V9:  73,
        REG_V10: 74,
        REG_V11: 75,
        REG_V12: 76,
        REG_V13: 77,
        REG_V14: 78,
        REG_V15: 79,
        REG_V16: 80,
        REG_V17: 81,
        REG_V18: 82,
        REG_V19: 83,
        REG_V20: 84,
        REG_V21: 85,
        REG_V22: 86,
        REG_V23: 87,
        REG_V24: 88,
        REG_V25: 89,
        REG_V26: 90,
        REG_V27: 91,
        REG_V28: 92,
        REG_V29: 93,
        REG_V30: 94,
        REG_V31: 95,
}
var Anames = []string{
        obj.A_ARCHSPECIFIC: "ADC",
        "ADCS",
        "ADCSW",
        "ADCW",
        "ADD",
        "ADDS",
        "ADDSW",
        "ADDW",
        "ADR",
        "ADRP",
        "AND",
        "ANDS",
        "ANDSW",
        "ANDW",
        "ASR",
        "ASRW",
        "AT",
        "BFI",
        "BFIW",
        "BFM",
        "BFMW",
        "BFXIL",
        "BFXILW",
        "BIC",
        "BICS",
        "BICSW",
        "BICW",
        "BRK",
        "CBNZ",
        "CBNZW",
        "CBZ",
        "CBZW",
        "CCMN",
        "CCMNW",
        "CCMP",
        "CCMPW",
        "CINC",
        "CINCW",
        "CINV",
        "CINVW",
        "CLREX",
        "CLS",
        "CLSW",
        "CLZ",
        "CLZW",
        "CMN",
        "CMNW",
        "CMP",
        "CMPW",
        "CNEG",
        "CNEGW",
        "CRC32B",
        "CRC32CB",
        "CRC32CH",
        "CRC32CW",
        "CRC32CX",
        "CRC32H",
        "CRC32W",
        "CRC32X",
        "CSEL",
        "CSELW",
        "CSET",
        "CSETM",
        "CSETMW",
        "CSETW",
        "CSINC",
        "CSINCW",
        "CSINV",
        "CSINVW",
        "CSNEG",
        "CSNEGW",
        "DC",
        "DCPS1",
        "DCPS2",
        "DCPS3",
        "DMB",
        "DRPS",
        "DSB",
        "EON",
        "EONW",
        "EOR",
        "EORW",
        "ERET",
        "EXTR",
        "EXTRW",
        "HINT",
        "HLT",
        "HVC",
        "IC",
        "ISB",
        "LDADDALD",
        "LDADDALW",
        "LDADDB",
        "LDADDH",
        "LDADDW",
        "LDADDD",
        "LDANDB",
        "LDANDH",
        "LDANDW",
        "LDANDD",
        "LDAR",
        "LDARB",
        "LDARH",
        "LDARW",
        "LDAXP",
        "LDAXPW",
        "LDAXR",
        "LDAXRB",
        "LDAXRH",
        "LDAXRW",
        "LDEORB",
        "LDEORH",
        "LDEORW",
        "LDEORD",
        "LDORB",
        "LDORH",
        "LDORW",
        "LDORD",
        "LDP",
        "LDPW",
        "LDPSW",
        "LDXR",
        "LDXRB",
        "LDXRH",
        "LDXRW",
        "LDXP",
        "LDXPW",
        "LSL",
        "LSLW",
        "LSR",
        "LSRW",
        "MADD",
        "MADDW",
        "MNEG",
        "MNEGW",
        "MOVK",
        "MOVKW",
        "MOVN",
        "MOVNW",
        "MOVZ",
        "MOVZW",
        "MRS",
        "MSR",
        "MSUB",
        "MSUBW",
        "MUL",
        "MULW",
        "MVN",
        "MVNW",
        "NEG",
        "NEGS",
        "NEGSW",
        "NEGW",
        "NGC",
        "NGCS",
        "NGCSW",
        "NGCW",
        "ORN",
        "ORNW",
        "ORR",
        "ORRW",
        "PRFM",
        "PRFUM",
        "RBIT",
        "RBITW",
        "REM",
        "REMW",
        "REV",
        "REV16",
        "REV16W",
        "REV32",
        "REVW",
        "ROR",
        "RORW",
        "SBC",
        "SBCS",
        "SBCSW",
        "SBCW",
        "SBFIZ",
        "SBFIZW",
        "SBFM",
        "SBFMW",
        "SBFX",
        "SBFXW",
        "SDIV",
        "SDIVW",
        "SEV",
        "SEVL",
        "SMADDL",
        "SMC",
        "SMNEGL",
        "SMSUBL",
        "SMULH",
        "SMULL",
        "STXR",
        "STXRB",
        "STXRH",
        "STXP",
        "STXPW",
        "STXRW",
        "STLP",
        "STLPW",
        "STLR",
        "STLRB",
        "STLRH",
        "STLRW",
        "STLXP",
        "STLXPW",
        "STLXR",
        "STLXRB",
        "STLXRH",
        "STLXRW",
        "STP",
        "STPW",
        "SUB",
        "SUBS",
        "SUBSW",
        "SUBW",
        "SVC",
        "SXTB",
        "SXTBW",
        "SXTH",
        "SXTHW",
        "SXTW",
        "SYS",
        "SYSL",
        "TBNZ",
        "TBZ",
        "TLBI",
        "TST",
        "TSTW",
        "UBFIZ",
        "UBFIZW",
        "UBFM",
        "UBFMW",
        "UBFX",
        "UBFXW",
        "UDIV",
        "UDIVW",
        "UMADDL",
        "UMNEGL",
        "UMSUBL",
        "UMULH",
        "UMULL",
        "UREM",
        "UREMW",
        "UXTB",
        "UXTH",
        "UXTW",
        "UXTBW",
        "UXTHW",
        "WFE",
        "WFI",
        "YIELD",
        "MOVB",
        "MOVBU",
        "MOVH",
        "MOVHU",
        "MOVW",
        "MOVWU",
        "MOVD",
        "MOVNP",
        "MOVNPW",
        "MOVP",
        "MOVPD",
        "MOVPQ",
        "MOVPS",
        "MOVPSW",
        "MOVPW",
        "SWPD",
        "SWPW",
        "SWPH",
        "SWPB",
        "BEQ",
        "BNE",
        "BCS",
        "BHS",
        "BCC",
        "BLO",
        "BMI",
        "BPL",
        "BVS",
        "BVC",
        "BHI",
        "BLS",
        "BGE",
        "BLT",
        "BGT",
        "BLE",
        "FABSD",
        "FABSS",
        "FADDD",
        "FADDS",
        "FCCMPD",
        "FCCMPED",
        "FCCMPS",
        "FCCMPES",
        "FCMPD",
        "FCMPED",
        "FCMPES",
        "FCMPS",
        "FCVTSD",
        "FCVTDS",
        "FCVTZSD",
        "FCVTZSDW",
        "FCVTZSS",
        "FCVTZSSW",
        "FCVTZUD",
        "FCVTZUDW",
        "FCVTZUS",
        "FCVTZUSW",
        "FDIVD",
        "FDIVS",
        "FMOVD",
        "FMOVS",
        "FMULD",
        "FMULS",
        "FNEGD",
        "FNEGS",
        "FSQRTD",
        "FSQRTS",
        "FSUBD",
        "FSUBS",
        "SCVTFD",
        "SCVTFS",
        "SCVTFWD",
        "SCVTFWS",
        "UCVTFD",
        "UCVTFS",
        "UCVTFWD",
        "UCVTFWS",
        "WORD",
        "DWORD",
        "FCSELS",
        "FCSELD",
        "FMAXS",
        "FMINS",
        "FMAXD",
        "FMIND",
        "FMAXNMS",
        "FMAXNMD",
        "FNMULS",
        "FNMULD",
        "FRINTNS",
        "FRINTND",
        "FRINTPS",
        "FRINTPD",
        "FRINTMS",
        "FRINTMD",
        "FRINTZS",
        "FRINTZD",
        "FRINTAS",
        "FRINTAD",
        "FRINTXS",
        "FRINTXD",
        "FRINTIS",
        "FRINTID",
        "FMADDS",
        "FMADDD",
        "FMSUBS",
        "FMSUBD",
        "FNMADDS",
        "FNMADDD",
        "FNMSUBS",
        "FNMSUBD",
        "FMINNMS",
        "FMINNMD",
        "FCVTDH",
        "FCVTHS",
        "FCVTHD",
        "FCVTSH",
        "AESD",
        "AESE",
        "AESIMC",
        "AESMC",
        "SHA1C",
        "SHA1H",
        "SHA1M",
        "SHA1P",
        "SHA1SU0",
        "SHA1SU1",
        "SHA256H",
        "SHA256H2",
        "SHA256SU0",
        "SHA256SU1",
        "VADD",
        "VADDP",
        "VAND",
        "VCMEQ",
        "VCNT",
        "VEOR",
        "VMOV",
        "VLD1",
        "VORR",
        "VREV32",
        "VREV64",
        "VST1",
        "VDUP",
        "VADDV",
        "VMOVI",
        "VUADDLV",
        "VSUB",
        "VFMLA",
        "VFMLS",
        "VPMULL",
        "VPMULL2",
        "VEXT",
        "VRBIT",
        "VUSHR",
        "VSHL",
        "VSRI",
        "VTBL",
        "VZIP1",
        "VZIP2",
        "LAST",
}
var Linkarm64 = obj.LinkArch{
        Arch:           sys.ArchARM64,
        Init:           buildop,
        Preprocess:     preprocess,
        Assemble:       span7,
        Progedit:       progedit,
        UnaryDst:       unaryDst,
        DWARFRegisters: ARM64DWARFRegisters,
}

func ADR

func ADR(p uint32, o uint32, rt uint32) uint32

func DRconv

func DRconv(a int) string

func FPCCMP

func FPCCMP(m uint32, s uint32, type_ uint32, op uint32) uint32

func FPCMP

func FPCMP(m uint32, s uint32, type_ uint32, op uint32, op2 uint32) uint32

func FPCVTI

func FPCVTI(sf uint32, s uint32, type_ uint32, rmode uint32, op uint32) uint32

func FPOP1S

func FPOP1S(m uint32, s uint32, type_ uint32, op uint32) uint32

func FPOP2S

func FPOP2S(m uint32, s uint32, type_ uint32, op uint32) uint32

func FPOP3S

func FPOP3S(m uint32, s uint32, type_ uint32, op uint32, op2 uint32) uint32

func LD2STR

func LD2STR(o uint32) uint32

func LDSTR12U

func LDSTR12U(sz uint32, v uint32, opc uint32) uint32

func LDSTR9S

func LDSTR9S(sz uint32, v uint32, opc uint32) uint32

func LDSTX

func LDSTX(sz uint32, o2 uint32, l uint32, o1 uint32, o0 uint32) uint32

func OPBIT

func OPBIT(x uint32) uint32

func OPBLR

func OPBLR(x uint32) uint32

func OPBcc

func OPBcc(x uint32) uint32

func OPDP2

func OPDP2(x uint32) uint32

func OPDP3

func OPDP3(sf uint32, op54 uint32, op31 uint32, o0 uint32) uint32

func SYSARG4

func SYSARG4(op1 int, Cn int, Cm int, op2 int) int

func SYSARG5

func SYSARG5(op0 int, op1 int, Cn int, Cm int, op2 int) int

form offset parameter to SYS; special register number

func SYSHINT

func SYSHINT(x uint32) uint32

func SYSOP

func SYSOP(l uint32, op0 uint32, op1 uint32, crn uint32, crm uint32, op2 uint32, rt uint32) uint32

type Optab

type Optab struct {
        // contains filtered or unexported fields
}