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sync/atomic: "synchronizes-before" ordering is broken on Load/Store. #67203
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sync/atomic uses AArch64's STLR* instructions. go/src/internal/runtime/atomic/atomic_arm64.s Lines 105 to 121 in ac17440
But, arm's hardware memory model allows memory accesses to different addresses to be "Re-order"ed. |
isn't this simply: W1, (the two store ops), W2 |
Sorry, I don't understand. Could you give me some details? |
(I added "R1" and "R2" for convention) |
Sorry, I get it. You meant R1, W1, W2, R2. |
I fixed my code, and confirmed the test works.
Thank you for comments! (Though I'm curious there are correct ordering with arm's STLR/LDAR instructions, I will study it. ) |
In my macOS, TSO mode is enabled. So, If I turn it off or use another arm, fixed test may fail possibly.
|
Go version
go version go1.22.2 darwin/arm64
Output of
go env
in your module/workspace:What did you do?
sample
What did you see happen?
r1 == 0 && r2 == 1 was observed.
https://pkg.go.dev/sync/atomic says,
but, it seems to be false.
What did you expect to see?
If W1 synchronized before W2, r1 == 0 && r2 == 1 should not be observed.
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