runtime/internal/atomic: for arm and mips compare-and-swap does not have a memory barrier on failure #63506
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ianlancetaylor
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gopherbot
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This CL adds a memory barrier on the failure case of the compare-and-swap for arm. For golang#63506
Add a memory barrier on the failure case of the compare-and-swap for mips, this avoids potential race conditions. For golang#63506
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Change https://go.dev/cl/536115 mentions this issue: |
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Change https://go.dev/cl/536116 mentions this issue: |
Add a memory barrier on the failure case of the compare-and-swap for mips, this avoids potential race conditions. For #63506 Change-Id: I3df1479d1438ba72aa72567eb3dea76ff745e98d GitHub-Last-Rev: 2101b9f GitHub-Pull-Request: #63604 Reviewed-on: https://go-review.googlesource.com/c/go/+/536116 Auto-Submit: Keith Randall <khr@golang.org> Reviewed-by: Keith Randall <khr@golang.org> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Keith Randall <khr@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
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@ianlancetaylor I'm not sure how to proceed with the fix for the arm platform, quoting Keith Randall reply on the CL:
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I'm not positive this would work, but ARM does have a model checker for ARM64 memory synchronization code: https://developer.arm.com/herd7 (docs). While ARM64 is pretty different from ARM in general, I think in this particular case the code can be translated to ARM64 without loss of fidelity. |
In the discussion about #63384 we agreed that it would be best if atomic compare-and-swap applied a memory barrier even if the comparison fails. That avoids potential race conditions such as the one described in that issue.
Based on my own inspection, the arm and mips implementation of compare-and-swap do not implement the expected memory barrier. The arm64 and mips64 implementations look OK.
CC @golang/arm @golang/mips @golang/runtime
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