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sync/atomic: arm CompareAndSwap backtraces fail #4422
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the sigsegv happened in kernel provided cas primitive and it doesn't use our standard stack frame so it confused the back tracer. perhaps we can force a read in sync/atomic CompareAndSwapUint32 so the the signal is received earlier. diff -r bbc0024af4a4 src/pkg/sync/atomic/asm_linux_arm.s --- a/src/pkg/sync/atomic/asm_linux_arm.s Sun Nov 18 15:31:26 2012 +1100 +++ b/src/pkg/sync/atomic/asm_linux_arm.s Sun Nov 25 00:20:48 2012 +0000 @@ -30,6 +30,7 @@ // Implement using kernel cas for portability. TEXT ·CompareAndSwapUint32(SB),7,$0 MOVW addr+0(FP), R2 + MOVW (R2), R1 // force a read here MOVW old+4(FP), R0 casagain: MOVW new+8(FP), R1 Labels changed: added priority-later, go1.1, arch-arm, removed priority-triage, go1.1maybe. Status changed to Accepted. |
https://golang.org/cl/6939056 Owner changed to @davecheney. Status changed to Started. |
I've not been able to solve the problem for the CAS64 case, if others want to pick this up, please consider https://golang.org/cl/6939056/ as a starting point. Owner changed to ---. Status changed to Accepted. |
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