We decided to suppress integer alignment diagnostics on architectures that don't require strict alignment, so it seems consistent to only diagnose mixed-size atomics on architectures where that's actually not safe?

I think it's safe on amd64 and probably all 64-bit architectures, since they provide native 64-bit atomic instructions.

It looks safe on 386 and arm too, since they use native 64-bit atomic instructions.

On 32-bit mips, I think the particular test case above is safe, because the 64-bit store is decomposed into two aligned 32-bit stores. But if it was changed to atomically load an unaligned 32-bit value, it could see tearing between the two 32-bit stores. (But maybe mips doesn't allow unaligned 32-bit memory accesses anyway?)

On wasm I think it's safe because there's no real concurrency?

What "safe" do we want to guarantee here? Do we forbid x0 observing new value while x1 observing old value? I think this could happen on 32-bit MIPS and maybe old 32-bit ARM. Do we say this "unsafe"?

@cherrymui Good point. I forgot the Loads themselves should be ordered, so you probably wouldn't expect them to return new and then old, respectively.

Preventing that on 32-bit MIPS seems like it might be prohibitive though. We'd have to add mutex protection to all atomics, not just the 64-bit variants.