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cmd/compile: bugs in mips rules #38648
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For the record, two incorrect rules that were deleted were:
Deletion occurred in CL 229637. They were never triggered when building |
I'm not sure I understand why those rules are incorrect. Maybe I missed something. |
To be clear, I don't think there is an actual code generation bug. The docs for SRAconst, for example, just say "arg0 >> auxInt, signed". But I don't think that's what it actually does, at least if you interpret That's what we do on other archs, e.g. for amd64/SHLQconst: |
Okay, thanks! That makes sense. |
It seems that this PR #42587 had been resloved it . |
I came across some bugs in the mips rules while reviewing the typed aux conversion for those rules.
Constant shifts require 0-31 as the shift amount. Rules like this:
(SLL x (MOVWconst [c])) => (SLLconst x [c])
Might violate that invariant. Might just need
&31
in a few places.We should check all the other uses of constant shifts to make sure they obey the invariant listed in the opcode definition. Maybe even define a new aux type
range0to31
or something to help with enforcement (which thecheck
pass can check).@ALTree
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