I found the TLS stuff I guess. That's too much assembly for today; will try ...
12 years, 11 months ago
(2012-04-10 20:25:06 UTC)
#4
I found the TLS stuff I guess. That's too much assembly for today; will try to
read it again tomorrow.
I'm very glad you're doing this and not me. :-)
Thank you.
Pretty good, just some confusion on my part. http://codereview.appspot.com/5989057/diff/4001/src/pkg/runtime/asm_arm.s File src/pkg/runtime/asm_arm.s (right): http://codereview.appspot.com/5989057/diff/4001/src/pkg/runtime/asm_arm.s#newcode280 src/pkg/runtime/asm_arm.s:280: BIC ...
12 years, 10 months ago
(2012-04-25 02:25:19 UTC)
#5
http://codereview.appspot.com/5989057/diff/4001/src/pkg/runtime/asm_arm.s File src/pkg/runtime/asm_arm.s (right): http://codereview.appspot.com/5989057/diff/4001/src/pkg/runtime/asm_arm.s#newcode280 src/pkg/runtime/asm_arm.s:280: BIC $0x7, R13 // alignment for gcc ABI On ...
12 years, 10 months ago
(2012-04-25 07:45:05 UTC)
#7
http://codereview.appspot.com/5989057/diff/4001/src/pkg/runtime/asm_arm.s
File src/pkg/runtime/asm_arm.s (right):
http://codereview.appspot.com/5989057/diff/4001/src/pkg/runtime/asm_arm.s#new...
src/pkg/runtime/asm_arm.s:280: BIC $0x7, R13 // alignment for gcc ABI
On 2012/04/25 02:25:20, rsc wrote:
> It hardly matters but you might want to look at the disassembly in gdb or 5l
-a.
> I think AND $~0x7 assembles cheaper than BIC $0x7 due to the choices for
> constants on ARM, but I am not 100% sure.
I've checked the output of objdump, and "BIC $0x7, R13" is encoded 0xe3cdd007.
http://codereview.appspot.com/5989057/diff/4001/src/pkg/runtime/asm_arm.s#new...
src/pkg/runtime/asm_arm.s:301: SUB $4, R13 // XXX: how to use "str r4, [sp,
-4]!"?
On 2012/04/25 02:25:20, rsc wrote:
> I believe that is MOVW.P R4, -4(R13)
that will be "str r4, [sp], #-4" as confirmed by objdump.
After some experiments, I finally found out that "str r4, [sp, #-4]!"
should be "MOVW.W R4, -4(SP)".
For the record, these suffixes are defined in ARM instruction
encoding.
http://codereview.appspot.com/5989057/diff/4001/src/pkg/runtime/cgo/gcc_arm.S
File src/pkg/runtime/cgo/gcc_arm.S (right):
http://codereview.appspot.com/5989057/diff/4001/src/pkg/runtime/cgo/gcc_arm.S...
src/pkg/runtime/cgo/gcc_arm.S:28: mov lr, pc
On 2012/04/25 02:25:20, rsc wrote:
> What does this do? My guess would be that it jumps to lr, but I don't know
what
> lr might have in it right now, and I especially don't know how we get to the
> next instruction.
GNU as(1) is somewhat confusing that its operand order is reversed for ARM.
http://codereview.appspot.com/5989057/diff/4001/src/pkg/runtime/cgo/gcc_arm.S...
src/pkg/runtime/cgo/gcc_arm.S:43: push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10,
r11, ip, lr}
On 2012/04/25 02:25:20, rsc wrote:
> Why are more registers saved here than above? And what happened to r3?
we still have to save callee save registers (r4-r10, r11, ip, lr)
and we need to pass two parameter r1, r2 to the procedure,
also at 5a procedure entry, the first argument is at 4(R13) not 0(R13),
so we push r0 for that slot.
Another reason for pushing r0 is that cgo_tls_get_gm will clobber
r0, so we must save r0 somewhere.
Anyway, I've changed the comment to present all the reasoning.
LGTM http://codereview.appspot.com/5989057/diff/4001/src/pkg/runtime/asm_arm.s File src/pkg/runtime/asm_arm.s (right): http://codereview.appspot.com/5989057/diff/4001/src/pkg/runtime/asm_arm.s#newcode301 src/pkg/runtime/asm_arm.s:301: SUB $4, R13 // XXX: how to use ...
12 years, 10 months ago
(2012-05-03 21:56:19 UTC)
#9
LGTM
http://codereview.appspot.com/5989057/diff/4001/src/pkg/runtime/asm_arm.s
File src/pkg/runtime/asm_arm.s (right):
http://codereview.appspot.com/5989057/diff/4001/src/pkg/runtime/asm_arm.s#new...
src/pkg/runtime/asm_arm.s:301: SUB $4, R13 // XXX: how to use "str r4, [sp,
-4]!"?
On 2012/04/25 07:45:05, minux wrote:
> On 2012/04/25 02:25:20, rsc wrote:
> > I believe that is MOVW.P R4, -4(R13)
> that will be "str r4, [sp], #-4" as confirmed by objdump.
> After some experiments, I finally found out that "str r4, [sp, #-4]!"
> should be "MOVW.W R4, -4(SP)".
>
> For the record, these suffixes are defined in ARM instruction
> encoding.
Did you want to use MOVW.W R4, -4(SP) here instead of the MOVW+SUB?
http://codereview.appspot.com/5989057/diff/4001/src/pkg/runtime/cgo/gcc_arm.S
File src/pkg/runtime/cgo/gcc_arm.S (right):
http://codereview.appspot.com/5989057/diff/4001/src/pkg/runtime/cgo/gcc_arm.S...
src/pkg/runtime/cgo/gcc_arm.S:28: mov lr, pc
On 2012/04/25 07:45:05, minux wrote:
> On 2012/04/25 02:25:20, rsc wrote:
> > What does this do? My guess would be that it jumps to lr, but I don't know
> what
> > lr might have in it right now, and I especially don't know how we get to the
> > next instruction.
> GNU as(1) is somewhat confusing that its operand order is reversed for ARM.
Aha! Thanks. That makes a lot more sense now.
Issue 5989057: code review 5989057: runtime: cgo support for Linux/ARM
(Closed)
Created 12 years, 11 months ago by minux1
Modified 12 years, 10 months ago
Reviewers:
Base URL:
Comments: 10